WS57C71C MILITARY HIGH SPEED 32K x 8 CMOS PROM/RPROM KEY FEATURES • Immune to Latch-UP • Ultra-Fast Access Time — Up to 200 mA — 45 ns • Low Power Consumption • Fast Programming • ESD Protection Exceeds 2000V • Available in 300 and 600 Mil DIP and CLLCC GENERAL DESCRIPTION The WS57C71C is a High Performance 256K UV Erasable Electrically Re-Programmable Read Only Memory (RPROM). It is manufactured in an advanced CMOS technology and utilizes WSI's patented self-aligned split gate EPROM cell. The industry standard PROM pin configuration of the WS57C71C provides an easy upgrade path from a 16K x 8 device. This RPROM is capable of operating at speeds as fast as 35 ns address access time, which enables it to be used directly with today's fast microprocessors and DSP processors without introducing any wait states. All inputs and outputs are TTL compatible. The WS57C71C is a low power device even when operated at its fastest speed. The DIP version is packaged in a 300 mil wide DIP package saving board space for the user. CS1/ VPP CS2 CS3 VCC OUTPUTS Read VIL VIH VIL VCC DOUT Output Disable VIH X X VCC High Z MODE Output Disable X VIL X VCC High Z Output Disable X X VIH VCC High Z Program VPP X VIH VCC DIN Program Verify VIL VIH VIL VCC DOUT Program Inhibit VPP X VIL VCC HIGH Z TOP VIEW Chip Carrier CERDIP 4 3 2 A6 A5 A4 A3 A2 A1 A0 NC O0 32 31 30 1 5 29 6 28 7 27 8 26 9 25 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20 O1 O2 GND PINS PIN CONFIGURATION A7 A8 A9 NC VCC A10 A11 MODE SELECTION A12 A13 A14 NC CS3 CS2 CS1/VPP O7 O6 NC O3 O4 O5 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A10 A11 A12 A13 A14 CS3 CS2 CS1/VPP O7 O6 O5 O4 O3 PRODUCT SELECTION GUIDE PARAMETER WS57C71C-45 WS57C71C-55 WS57C71C-70 Address Access Time (Max) 45 ns 55 ns 70 ns CS to Output Valid Time (Max) 20 ns 20 ns 30 ns Return to Main Menu 4-13 WS57C71C ORDERING INFORMATION PART NUMBER WS57C71C-45TMB WS57C71C-55CMB WS57C71C-55DMB WS57C71C-55TMB WS57C71C-70TMB SPEED (ns) 45 55 55 55 70 PACKAGE TYPE 28 Pin CERDIP, 0.3" 32 Pad CLLCC 28 Pin CERDIP, 0.6" 28 Pin CERDIP, 0.3" 28 Pin CERDIP, 0.3" WSI PACKAGE OPERATING TEMPERATURE MANUFACTURING DRAWING RANGE PROCEDURE T2 C2 D2 T2 T2 Military Military Military Military Military MIL-STD-883C MIL-STD-883C MIL-STD-883C MIL-STD-883C MIL-STD-883C NOTE: 9. The actual part marking will not include the initials "WS." PROGRAMMING/ALGORITHMS/ERASURE/PROGRAMMERS REFER TO PAGE 5-1 The WS57C71C is programmed using Algorithm D shown on page 5-9. For complete data sheet and electrical specifications see page 2-55. Return to Main Menu 4-14