K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM Document Title 1Mx36 & 2Mx18-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 1. Initial document. May. 10. 2001 Preliminary 0.1 1. Add 165FBGA package Aug. 29. 2001 Preliminary 0.2 1.Update JTAG scan order 2. Speed bin merge. From K7N3236(18)49M to K7N3236(18)45M 3. AC parameter change. tOH(min)/tLZC(min) from 0.8 to 1.5 at -25 tOH(min)/tLZC(min) from 1.0 to 1.5 at -22 tOH(min)/tLZC(min) from 1.0 to 1.5 at -20 Dec. 31. 2001 Preliminary 0.3 1. Change pin out for 165FBGA - x18/x36 ; 11B => from A to NC , 2R ==> from NC to A Feb. 14. 2002 Preliminary 0.4 1. Insert pin at JTAG scan order of 165FBGA in connection with pin out change - x18/x36 ; insert Pin ID of 2R to BIT number of 69 Apr. 20. 2002 Preliminary 0.5 1. Add Icc, Isb, Isb1 and Isb2 values. May. 10. 2002 Preliminary 1.0 1. Final datasheet release. Sep. 26. 2002 Final 1.1 1. Change the Stand-by current (Isb) Before After Isb - 25 : 120 170 - 22 : 110 160 - 20 : 100 150 - 16 : 90 140 - 15 : 90 140 - 13 : 90 140 Isb1 : 90 110 Isb2 : 80 100 Oct. 17, 2003 Final 2.0 1. Delete the 119BGA package 2. Delete the 225MHz and 150MHz speed bin Nov. 18, 2003 Final Rev. No. The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Nov. 2003 Rev 2.0 K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM 32Mb NtRAM(Flow Through / Pipelined) Ordering Information Org. Part Number K7M321825M-QC75 Mode VDD Speed FT ; Access Time(ns) Pipelined ; Cycle Time(MHz) FlowThrough 3.3 7.5ns 2Mx18 K7N321801M-Q(F)C25/20/16/13 Pipelined 3.3 250/200/167/133MHz K7N321845M-Q(F)C25/20/16/13 Pipelined 2.5 250/200/167/133MHz FlowThrough 3.3 7.5ns 1Mx36 K7N323601M-Q(F)C25/20/16/13 K7M323625M-QC75 Pipelined 3.3 250/200/167/133MHz K7N323645M-Q(F)C25/20/16/13 Pipelined 2.5 250/200/167/133MHz -2- PKG Temp C Q:100TQFP (Commercial F:165FBGA Temperature Range) Nov. 2003 Rev 2.0 K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM 1Mx36 & 2Mx18-Bit Pipelined NtRAMTM FEATURES GENERAL DESCRIPTION • 2.5V ±5% Power Supply. • Byte Writable Function. • Enable clock and suspend operation. • Single READ/WRITE control pin. • Self-Timed Write Cycle. • Three Chip Enable for simple depth expansion with no data contention . • A interleaved burst or a linear burst mode. • Asynchronous output enable control. • Power Down mode. • TTL-Level Three-State Outputs. • 100-TQFP-1420A. • 165FBGA(11x15 ball aray) with body size of 15mmx17mm. The K7N323645M and K7N321845M are 37,748,736-bits Synchronous Static SRAMs. The NtRAM TM, or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock. The K7N323645M and K7N321845M are implemented with SAMSUNG ′s high performance CMOS technology and is available in 100pin TQFP and 165FBGA packages. Multiple power and ground pins minimize ground bounce. FAST ACCESS TIMES PARAMETER Symbol -25 -20 -16 -13 Unit tCYC 4.0 5.0 6.0 7.5 ns Clock Access Time tCD 2.6 3.2 3.5 4.2 ns Output Enable Access Time tOE 2.6 3.2 3.5 4.2 ns Cycle Time LOGIC BLOCK DIAGRAM LBO A [0:19]or A [0:20] CKE ADDRESS REGISTER A 2 ~A 19 or A 2~A 20 CONTROL LOGIC CLK BURST ADDRESS COUNTER A 0~A 1 ADV WE B Wx (x=a,b,c,d or a,b) CONTROL REGISTER CS 1 CS 2 CS 2 WRITE ADDRESS REGISTER K A′ 0~A ′ 1 WRITE ADDRESS REGISTER 1Mx36, 2Mx18 MEMORY ARRAY K DATA-IN REGISTER K DATA-IN REGISTER CONTROL LOGIC K OUTPUT REGISTER BUFFER OE ZZ 36 or 18 DQa0 ~ DQd7 or D Q a0 ~ DQb 8 DQPa ~ DQPd NtRAM TM and No Turnaround Random Access Memory are trademarks of Samsung. -3- Nov. 2003 Rev 2.0 K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM A6 A7 CS 1 CS 2 BWd BWc BWb BWa CS 2 V DD V SS CLK WE CK E OE ADV A 18 A 17 A8 A9 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 Pin TQFP (20mm x 14mm) 38 39 40 41 42 43 44 45 46 47 48 49 50 N.C. N.C. V SS V DD N.C. A 19 A 10 A 11 A 12 A 13 A 14 A 15 A 16 35 A2 37 34 A3 A0 33 A4 36 32 A1 31 K7N323645M(1Mx36) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO DQPc DQc0 DQc1 V DDQ V SSQ DQc2 DQc3 DQc4 DQc5 V SSQ V DDQ DQc6 DQc7 V DD V DD V DD V SS DQd 0 DQd 1 V DDQ V SSQ DQd 2 DQd 3 DQd 4 DQd 5 V SSQ V DDQ DQd 6 DQd 7 DQPd 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb DQb 7 DQb 6 V DDQ V SSQ DQb 5 DQb 4 DQb 3 DQb 2 V SSQ V DDQ DQb 1 DQb 0 V SS V DD V DD ZZ DQa 7 DQa 6 V DDQ V SSQ DQa 5 DQa 4 DQa 3 DQa 2 V SSQ V DDQ DQa 1 DQa 0 DQPa PIN NAME SYMBOL PIN NAME A 0 - A 19 Address Inputs ADV WE CLK CKE CS 1 CS 2 CS 2 B Wx(x=a,b,c,d) OE ZZ LBO Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control TQFP PIN NO. SYMBOL 32,33,34,35,36,37,43, 44,45,46,47,48,49,50, 81,82,83,84,99,100 85 88 89 87 98 97 92 93,94,95,96 86 64 31 PIN NAME TQFP PIN NO. V DD V SS Power Supply(2.5V) Ground 14,15,16,41,65,66,91 17,40,67,90 N.C. No Connect 38,39,42 DQa 0 ~a7 DQb 0 ~b7 DQc 0~c 7 DQd 0 ~d7 DQPa~P d Data Data Data Data Data 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 V DDQ Output Power Supply 4,11,20,27,54,61,70,77 (2.5V) Output Ground 5,10,21,26,55,60,71,76 V SSQ Inputs/Outputs Inputs/Outputs Inputs/Outputs Inputs/Outputs Inputs/Outputs Note : 1. A 0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. -4- Nov. 2003 Rev 2.0 K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM A7 CS 1 CS 2 N.C. N.C. BWb BWa CS 2 V DD V SS CLK WE CK E OE ADV A 19 A 18 A8 A9 98 97 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 96 A6 99 100 Pin TQFP (20mm x 14mm) 39 40 41 42 43 44 45 46 N.C. V SS V DD N.C. A 20 A 11 A 12 A 13 50 38 N.C. A 17 37 A0 49 36 A1 A 16 35 A2 48 34 A3 A 15 33 A4 47 32 A 14 31 K7N321845M(2Mx18) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO N.C. N.C. N.C. V DDQ V SSQ N.C. N.C. DQb 8 DQb 7 V SSQ V DDQ DQb 6 DQb 5 V DD V DD V DD V SS DQb 4 DQb 3 V DDQ V SSQ DQb 2 DQb 1 DQb 0 N.C. V SSQ V DDQ N.C. N.C. N.C. 100 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A 10 N.C. N.C. V DDQ V SSQ N.C. DQa 0 DQa 1 DQa 2 V SSQ V DDQ DQa 3 DQa 4 V SS V DD V DD ZZ DQa 5 DQa 6 V DDQ V SSQ DQa 7 DQa 8 N.C. N.C. V SSQ V DDQ N.C. N.C. N.C. PIN NAME SYMBOL PIN NAME A 0 - A 20 Address Inputs ADV WE CLK CKE CS 1 CS 2 CS 2 BW x(x=a,b) OE ZZ LBO Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control TQFP PIN NO. SYMBOL 32,33,34,35,36,37,43 44,45,46,47,48,49,50, 80,81,82,83,84,99,100 85 88 89 87 98 97 92 93,94 86 64 31 PIN NAME TQFP PIN NO. V DD V SS Power Supply(2.5V) Ground 14,15,16,41,65,66,91 17,40,67,90 N.C. No Connect 1,2,3,6,7,25,28,29,30, 38,39,42,51,52,53, 56,57,75,78,79,95,96 DQa0~a8 DQb0~b8 Data Inputs/Outputs Data Inputs/Outputs 58,59,62,63,68,69,72,73,74 8,9,12,13,18,19,22,23,24 V DDQ Output Power Supply (2.5V) Output Ground 4,11,20,27,54,61,70,77 V SSQ 5,10,21,26,55,60,71,76 N OTE : A 0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. -5- Nov. 2003 Rev 2.0 K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM 165-PIN FBGA PACKAGE CONFIGURATIONS (TOP VIEW) K7N323645M(1Mx36) 1 2 3 4 5 6 7 8 9 10 11 A NC A CS 1 BW c BWb CS2 CKE ADV A A NC B NC A CS2 BWd BWa CLK WE OE A A NC C DQPc NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPb D DQc DQc V DDQ V DD V SS V SS V SS V DD V DDQ DQb DQb E DQc DQc V DDQ V DD V SS V SS V SS V DD V DDQ DQb DQb F DQc DQc V DDQ V DD V SS V SS V SS V DD V DDQ DQb DQb G DQc DQc V DDQ V DD V SS V SS V SS V DD V DDQ DQb DQb H NC V DD NC V DD V SS V SS V SS V DD NC NC ZZ J DQd DQd V DDQ V DD V SS V SS V SS V DD V DDQ DQa DQa K DQd DQd V DDQ V DD V SS V SS V SS V DD V DDQ DQa DQa L DQd DQd V DDQ V DD V SS V SS V SS V DD V DDQ DQa DQa M DQd DQd V DDQ V DD V SS V SS V SS V DD V DDQ DQa DQa N DQPd NC V DDQ V SS NC NC NC V SS V DDQ NC DQPa P NC NC A A TDI A1 * TDO A A A NC R LBO A A A TMS A0 * TCK A A A A Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN NAME SYMBOL PIN NAME A Address Inputs A 0,A1 ADV WE CLK CKE CS1 CS2 CS2 BWx (x=a,b,c,d) Burst Address Inputs Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs OE ZZ LBO Output Enable Power Sleep Mode Burst Mode Control TCK TMS TDI TDO JTAG JTAG JTAG JTAG SYMBOL PIN NAME V DD V SS Power Supply Ground N.C. No Connect DQa DQb DQc DQd DQPa~Pd Data Data Data Data Data V DDQ Output Power Supply Inputs/Outputs Inputs/Outputs Inputs/Outputs Inputs/Outputs Inputs/Outputs Test Clock Test Mode Select Test Data Input Test Data Output -6- Nov. 2003 Rev 2.0 K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM 165-PIN FBGA PACKAGE CONFIGURATIONS (TOP VIEW) K7N321845M(2Mx18) 1 2 3 4 5 6 7 8 9 10 11 A NC A CS 1 BWb NC CS2 CKE ADV A A A B NC A CS2 NC BWa CLK WE OE A A NC C NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPa D NC DQb V DDQ V DD V SS V SS V SS V DD V DDQ NC DQa E NC DQb V DDQ V DD V SS V SS V SS V DD V DDQ NC DQa F NC DQb V DDQ V DD V SS V SS V SS V DD V DDQ NC DQa G NC DQb V DDQ V DD V SS V SS V SS V DD V DDQ NC DQa H NC V DD NC V DD V SS V SS V SS V DD NC NC ZZ J DQb NC V DDQ V DD V SS V SS V SS V DD V DDQ DQa NC K DQb NC V DDQ V DD V SS V SS V SS V DD V DDQ DQa NC L DQb NC V DDQ V DD V SS V SS V SS V DD V DDQ DQa NC M DQb NC V DDQ V DD V SS V SS V SS V DD V DDQ DQa NC N DQPb NC V DDQ V SS NC NC NC V SS V DDQ NC NC P NC NC A A TDI A1 * TDO A A A NC R LBO A A A TMS A0 * TCK A A A A Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN NAME SYMBOL PIN NAME A Address Inputs A 0,A1 ADV WE CLK CKE CS1 CS2 CS2 BWx (x=a,b) Burst Address Inputs Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs OE ZZ LBO Output Enable Power Sleep Mode Burst Mode Control TCK TMS TDI TDO JTAG JTAG JTAG JTAG SYMBOL PIN NAME V DD V SS Power Supply Ground N.C. No Connect DQa DQb DQPa, Pb Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs V DDQ Output Power Supply Test Clock Test Mode Select Test Data Input Test Data Output -7- Nov. 2003 Rev 2.0 K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM FUNCTION DESCRIPTION The K7N323645M and K7N321845M are NtRAM TM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of O E, LBO and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next operation. Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. NtRAM TM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables( CS 1, CS 2, CS 2) are active . Output Enable(OE ) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, CKE is driven low, all three chip enables( CS 1, CS 2 , CS 2) are active, the write enable input signals WE are driven high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must be driven low for the device to drive out the requested data. Write operation occurs when WE is driven low at the rising edge of the clock. B W[d:a] can be used for byte write operation. The pipelined NtRAMTM uses a late-late write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, W E and address are registered, and the data associated with that address is required two cycle later. Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected. And when this pin is high, Interleaved burst sequence is selected. During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up time. BURST SEQUENCE TABLE LBO PIN HIGH First Address Fourth Address (Interleaved Burst, LBO=High) Case 1 A1 0 0 1 1 Case 2 A0 0 1 0 1 A1 0 0 1 1 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 BQ TABLE LBO PIN A1 1 1 0 0 A0 1 0 1 0 (Linear Burst, LBO=Low) LOW First Address Fourth Address Case 1 A1 0 0 1 1 Case 2 A0 0 1 0 1 A1 0 1 1 0 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 0 0 1 A0 1 0 1 0 Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed . -8- Nov. 2003 Rev 2.0 K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM STATE DIAGRAM FOR N tRAMTM WRITE READ READ BEGIN READ BEGIN WRITE DS RE AD W DS AD W R IT E ST BUR TE E R BURST DS BURST READ BURST WRITE COMMAND DS WRI DESELECT DS BURST TE BUR ST D R EA DS RI WRITE BURST ACTION DESELECT READ BEGIN READ WRITE BEGIN WRITE BURST BEGIN READ BEGIN WRITE CONTINUE DESELECT Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock(CLK) -9- Nov. 2003 Rev 2.0 K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM TRUTH TABLES SYNCHRONOUS TRUTH TABLE CS 1 CS 2 CS 2 ADV WE BW x OE CKE CLK ADDRESS ACCESSED OPERATION H X X L X X X L ↑ N/A Not Selected X L X L X X X L ↑ N/A Not Selected X X H L X X X L ↑ N/A Not Selected X X X H X X X L ↑ N/A Not Selected Continue L H L L H X L L ↑ External Address Begin Burst Read Cycle X X X H X X L L ↑ Next Address Continue Burst Read Cycle L H L L H X H L ↑ External Address NOP/Dummy Read X X X H X X H L ↑ Next Address Dummy Read L H L L L L X L ↑ External Address Begin Burst Write Cycle X X X H X L X L ↑ Next Address Continue Burst Write Cycle L H L L L H X L ↑ N/A NOP/Write Abort X X X H X H X L ↑ Next Address Write Abort X X X X X X X H ↑ Current Address Ignore Clock Notes : 1. X means "Don′t Care". 2. The rising edge of clock is symbolized by ( ↑). 3. A continue deselect cycle can only be enterd if a deselect cycle is executed first. 4. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 5. Operation finally depends on status of asynchronous input pins(ZZ and OE). WRITE TRUTH TABLE(x36) WE BW a BW b BWc BW d OPERATION H X X X X READ L L H H H WRITE BYTE a L H L H H WRITE BYTE b L H H L H WRITE BYTE c L H H H L WRITE BYTE d L L L L L WRITE ALL BYTEs L H H H H WRITE ABORT/NOP Notes : 1. X means "Don ′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑). WRITE TRUTH TABLE(x18) WE BWa BW b OPERATION H X X READ L L H WRITE BYTE a L H L WRITE BYTE b L L L WRITE ALL BYTEs L H H WRITE ABORT/NOP Notes : 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑). - 10 - Nov. 2003 Rev 2.0 K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM ASYNCHRONOUS TRUTH TABLE OPERATION ZZ OE I/O STATUS Sleep Mode H X High-Z L L DQ L H High-Z Write L X Din, High-Z Deselected L X High-Z Read Notes 1. X means "Don′t Care". 2. Sleep Mode means power Sleep Mode of which stand-by current does not depend on cycle time. 3. Deselected means power Sleep Mode of which stand-by current depends on cycle time. ABSOLUTE MAXIMUM RATINGS* PARAMETER SYMBOL RATING UNIT Voltage on V DD Supply Relative to V SS V DD -0.3 to 3.6 V Voltage on Any Other Pin Relative to VSS VI N -0.3 to VDD+0.3 V Power Dissipation PD 1.6 W Storage Temperature TSTG -65 to 150 °C Operating Temperature T OPR 0 to 70 °C Storage Temperature Range Under Bias TBIAS -10 to 85 °C *Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING CONDITIONS (0°C ≤ TA ≤ 70°C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. MAX UNIT V DD 2.375 2.5 2.625 V V DDQ 2.375 2.5 2.625 V V SS 0 0 0 V *Note : V DD and VDDQ must be supplied with identical vlotage levels. CAPACITANCE*(TA =25°C, f=1MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL TEST CONDITION TYP MAX UNIT C IN V I N=0V - 5 pF COUT V OUT=0V - 7 pF *Note : Sampled not 100% tested. - 11 - Nov. 2003 Rev 2.0 K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM DC ELECTRICAL CHARACTERISTICS(VDD =2.5V ±5%, T A=0°C to +70°C) PARAMETER SYMBOL Input Leakage Current(except ZZ) IIL V DD=Max ; VIN=VSS to V DD Output Leakage Current IOL Output Disabled, Operating Current ICC TEST CONDITIONS MAX UNIT -2 +2 µA µA -2 +2 -25 - 460 V DD=Max IOUT=0mA -20 - 410 Cycle Time ≥ tCYC Min -16 - 360 -13 - 310 -25 - 170 -20 - 150 -16 - 140 -13 - 140 - 110 mA - 100 mA Device deselected, I OUT=0mA, ISB MIN ZZ ≤ V IL, f=Max, All Inputs ≤0.2V or ≥ V DD-0.2V mA NOTES 1,2 mA Device deselected, I OUT=0mA, Standby Current ISB1 ZZ ≤ 0.2V, f=0, All Inputs=fixed (VDD-0.2V or 0.2V) Device deselected, I OUT=0mA, ISB2 ZZ≥V DD-0.2V, f=Max, All Inputs ≤ V IL or ≥V IH Output Low Voltage V OL IOL =1.0mA - 0.4 V Output High Voltage V OH IOH=-1.0mA 2.0 - V Input Low Voltage V IL -0.3* 0.7 V Input High Voltage V IH 1.7 V DD+0.3** V 3 Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing. 2. Data states are all zero. 3. In Case of I/O Pins, the Max. VIH=VDDQ +0.3V VIH VSS VSS- 0.8V 20% tCYC (MIN) TEST CONDITIONS (T A=0 to 70°C, V DD=2.5V ±5%, unless otherwise specified) Input Pulse Level PARAMETER VALUE 0 to 2.5V Input Rise and Fall Time(Measured at 20% to 80%) Input and Output Timing Reference Levels Output Load 1.0V/ns V DDQ/2 See Fig. 1 - 12 - Nov. 2003 Rev 2.0 K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM Output Load(A) Dout Output Load(B), (for tLZC, tLZOE , tHZOE & tHZC) RL=50Ω +2.5V VL=V DDQ/2 30pF* Zo=50Ω 1667 Ω Dout 1538Ω 5pF* * Including Scope and Jig Capacitance Fig. 1 AC TIMING CHARACTERISTICS (VDD=2.5V ±5%, T A=0 to 70°C) -25 PARAMETER SYMBOL MIN -20 MAX MIN -16 MAX MIN -13 MAX MIN MAX UNIT Cycle Time tCYC 4.0 - 5.0 - 6.0 - 7.5 - ns Clock Access Time tCD - 2.6 - 3.2 - 3.5 - 4.2 ns Output Enable to Data Valid tOE - 2.6 - 3.2 - 3.5 - 4.2 ns Clock High to Output Low-Z tLZC 1.5 - 1.5 - 1.5 - 1.5 - ns Output Hold from Clock High tOH 1.5 - 1.5 - 1.5 - 1.5 - ns Output Enable Low to Output Low-Z tLZOE 0 - 0 - 0 - 0 - ns Output Enable High to Output High-Z tHZOE - 2.6 - 3.0 - 3.0 - 3.5 ns Clock High to Output High-Z tHZC - 2.6 - 3.0 - 3.0 - 3.5 ns Clock High Pulse Width tCH 1.7 - 2.0 - 2.2 - 3.0 - ns Clock Low Pulse Width tCL 1.7 - 2.0 - 2.2 - 3.0 - ns Address Setup to Clock High tAS 1.2 - 1.4 - 1.5 - 1.5 - ns CKE Setup to Clock High tCES 1.2 - 1.4 - 1.5 - 1.5 - ns Data Setup to Clock High tDS 1.2 - 1.4 - 1.5 - 1.5 - ns Write Setup to Clock High (WE, BW X ) tWS 1.2 - 1.4 - 1.5 - 1.5 - ns Address Advance Setup to Clock High tADVS 1.2 - 1.4 - 1.5 - 1.5 - ns Chip Select Setup to Clock High tCSS 1.2 - 1.4 - 1.5 - 1.5 - ns Address Hold from Clock High tAH 0.3 - 0.4 - 0.5 - 0.5 - ns CKE Hold from Clock High tCEH 0.3 - 0.4 - 0.5 - 0.5 - ns Data Hold from Clock High tDH 0.3 - 0.4 - 0.5 - 0.5 - ns Write Hold from Clock High (WE , BW X) tWH 0.3 - 0.4 - 0.5 - 0.5 - ns Address Advance Hold from Clock High tADVH 0.3 - 0.4 - 0.5 - 0.5 - ns Chip Select Hold from Clock High tCSH 0.3 - 0.4 - 0.5 - 0.5 - ns ZZ High to Power Down tPDS 2 - 2 - 2 - 2 - cycle ZZ Low to Power Up tPUS 2 - 2 - 2 - 2 - cycle Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled. 3. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low, Both cases must meet setup and hold times. 4. To avoid bus contention, At a given voltage and temperature t LZC is more than t HZC. The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions ( 0°C,2.625V) than tHZC, which is a Max. parameter(worst case at 70°C,2.375V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature. - 13 - Nov. 2003 Rev 2.0 K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM SLEEP MODE SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to I SB2. The duration of SLEEP MODE is dictated by the length of time the ZZ is in a High state. After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE. When the ZZ pin becomes a logic High, I SB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pending operations are completed. similarly, when exiting SLEEP MODE during t PUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SLEEP MODE. SLEEP MODE ELECTRICAL CHARACTERISTICS DESCRIPTION Current during SLEEP MODE CONDITIONS SYMBOL ZZ ≥ V IH ISB2 MIN MAX 60 UNITS mA ZZ active to input ignored tPDS 2 cycle ZZ inactive to input sampled tPUS 2 cycle ZZ active to SLEEP current tZZI ZZ inactive to exit SLEEP current tRZZI 2 cycle 0 SLEEP MODE WAVEFORM K t PDS ZZ setup cycle tPUS ZZ recovery cycle ZZ t ZZI Isupply ISB2 tRZZI All inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z DON′ T CARE - 14 - Nov. 2003 Rev 2.0 K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left unconnected. JTAG Block Diagram JTAG Instruction Coding IR2 IR1 SRAM CORE TDI BYPASS Reg. TDO Identification Reg. Instruction Reg. Control Signals TMS TCK TAP Controller IR0 Instruction TDO Output Notes 0 0 0 EXTEST Boundary Scan Register 1 0 0 1 IDCODE Identification Register 3 0 1 0 SAMPLE-Z Boundary Scan Register 2 0 1 1 BYPASS Bypass Register 4 1 0 0 SAMPLE Boundary Scan Register 5 1 0 1 RESERVED Do Not Use 6 1 1 0 BYPASS Bypass Register 4 1 1 1 BYPASS Bypass Register 4 NOTE : 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. This instruction is not IEEE 1149.1 compliant. 2. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 3. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 4. Bypass register is initiated to V SS when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 5. SAMPLE instruction dose not places DQs in Hi-Z. 6. This instruction is reserved for future use. TAP Controller State Diagram 1 Test Logic Reset 0 0 Run Test Idle 1 1 Select DR 0 Exit2 DR 1 1 Update DR 0 - 15 - 1 Capture IR 0 0 Shift IR 1 1 Exit1 DR 0 Pause DR 1 Select IR 0 1 Capture DR 0 Shift DR 1 1 1 0 0 0 Exit1 IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 0 Nov. 2003 Rev 2.0 K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM SCAN INFORMATION (165 FBGA ) SCAN REGISTER DEFINITION Part Instruction Register Bypass Register ID Register Boundary Scan 1Mx36 3 bits 1 bits 32 bits 76 bits 2Mx18 3 bits 1 bits 32 bits 76 bits ID REGISTER DEFINITION Part Revision Number (31:28) Part Configuration (27:18) Vendor Definition (17:12) Samsung JEDEC Code (11: 1) Start Bit(0) 1Mx36 0000 01000 00100 XXXXXX 00001001110 1 2Mx18 0000 01001 00011 XXXXXX 00001001110 1 BOUNDARY SCAN EXIT ORDER BIT PIN ID(x18) PIN ID(x36) BIT PIN ID(x18) PIN ID(x36) 1 2 6N 8P 6N 8P 3 4 5 6 7 8 9 10 8R 9R 9P 10P 10R 11R 11P 11H 8R 9R 9P 10P 10R 11R 11P 11H 40 41 42 43 44 45 6A 5B 5A 4A 4B 3B 6A 5B 5A 4A 4B 3B 11 12 13 14 15 16 17 18 19 11N 11M 11L 11K 11J 10M 10L 10K 10J 11N 11M 11L 11K 11J 10M 10L 10K 10J 46 47 48 49 50 51 52 53 54 3A 2A 2B 1B 1A 1C 1D 1E 1F 3A 2A 2B 1B 1A 1C 1D 1E 1F 20 21 22 23 24 25 26 27 11G 11F 11E 11D 11C 10F 10E 10D 11G 11F 11E 11D 10G 10F 10E 10D 55 56 57 58 59 60 61 62 1G 2D 2E 2F 2G 1J 1K 1L 1G 2D 2E 2F 2G 1J 1K 1L 28 29 30 31 32 33 34 35 36 10G 11A 11B 10A 10B 9A 9B 8A 8B 11C 11A 11B 10A 10B 9A 9B 8A 8B 63 64 65 66 67 68 69 70 71 1M 1N 2K 2L 2M 2J 2R 1R 3P 1M 2J 2K 2L 2M 1N 2R 1R 3P 37 38 39 7A 7B 6B 7A 7B 6B 72 73 74 75 76 3R 4R 4P 6P 6R 3R 4R 4P 6P 6R Note : 1. NC and Vss pins included in the scan exit order are read as "X" ( i.e. don ′t care). - 16 - Nov. 2003 Rev 2.0 K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM JTAG DC OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Power Supply Voltage V DD 3.135 3.3 3.465 V Input High Level VI H 1.7 - V DD+0.3 V Input Low Level V IL -0.3 - 0.7 V Output High Voltage VO H 2.0 - - V Output Low Voltage V OL - - 0.4 V Note NOTE : The input level of SRAM pin is to follow the SRAM DC specification. JTAG AC TEST CONDITIONS Symbol Min Unit Input High/Low Level Parameter V IH/VIL 2.5/0 V Input Rise/Fall Time TR/TF 1.0/1.0 ns V DDQ/2 V Input and Output Timing Reference Level Note JTAG AC Characteristics Parameter Symbol Min Max Unit TCK Cycle Time tCHCH 50 - ns TCK High Pulse Width tCHCL 20 - ns TCK Low Pulse Width tCLCH 20 - ns TMS Input Setup Time tMVCH 5 - ns TMS Input Hold Time tCHMX 5 - ns TDI Input Setup Time tDVCH 5 - ns TDI Input Hold Time tCHDX 5 - ns SRAM Input Setup Time tSVCH 5 - ns SRAM Input Hold Time tCHSX 5 - ns Clock Low to Output Valid tCLQV 0 10 ns Note JTAG TIMING DIAGRAM TCK tC H C H tC H C L t MVCH t CHMX t DVCH tC H D X t SVCH t CHSX tC L C H TMS TDI PI (SRAM) t CLQV TDO - 17 - Nov. 2003 Rev 2.0 - 18 - Data Out OE ADV CS WRITE Address CKE Clock A1 tADVH tCSH tWH tAH tLZOE tOE Q 1-1 A2 tHZOE tCEH Q 2-1 tCD tOH tCYC Q2-2 tCL NO TE S : WRITE = L me ans WE = L, an d B Wx = L CS = L mean s CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS 2 = H, or CS 1 = L, and CS 2 = L tADVS tCSS tWS tAS tCES tCH Q 2-3 A3 TIMING WAVEFORM OF READ CYCLE Q2-4 Q 3-1 Q 3-2 Q3-3 Un defined Do n′t Care Q3-4 tHZC K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM Nov. 2003 Rev 2.0 - 19 - Data Out Data In OE ADV CS WRITE Address CKE Clock Q 0-4 tHZOE D1-1 A2 tCYC tCL D2-1 D2-2 NOTES : WRITE = L means WE = L, a nd BWx = L CS = L me ans CS1 = L, CS2 = H a nd CS 2 = L CS = H mean s CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L Q0-3 A1 tCES tCEH tCH D2-3 A3 TIMING WAVEFORM OF WRTE CYCLE D2-4 D3-1 tDS D3-2 tDH D3-3 Undefined Don′t Ca re D3-4 K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM Nov. 2003 Rev 2.0 - 20 - Data In Data Out OE ADV CS WRITE Address CKE Clock tOE tLZOE A2 Q1 A3 tDS D2 tDH Q3 A4 NOTES : WRITE = L means WE = L, a nd BWx = L CS = L me ans CS1 = L, CS2 = H a nd CS 2 = L CS = H mean s CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L A1 tCES tCEH A5 Q4 A6 D5 A7 TIMING WAVEFORM OF SINGLE READ/WRITE tCH Q6 tCYC tCL A8 Q7 A9 Undefined Don′t Car e K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM Nov. 2003 Rev 2.0 - 21 - Data In A1 tCES tCEH tCD tLZC A2 Q1 tHZC A3 NO TE S : WRITE = L me ans WE = L, an d B Wx = L CS = L mean s CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS 2 = H, or CS 1 = L, and CS 2 = L Data Out OE ADV CS WRITE Address CKE Clock tDS D2 A4 TIMING WAVEFORM OF CKE OPERATION tDH tCH Q3 tCYC tCL A5 Q4 A6 Undefined Don′t Care K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM Nov. 2003 Rev 2.0 - 22 - Data In Data Out OE ADV CS WRITE Address CKE Clock A1 tCEH tOE tLZOE A2 Q1 Q2 tHZC A3 NO TE S : WRITE = L me ans WE = L, an d B Wx = L CS = L mean s CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS 2 = H, or CS 1 = L, and CS 2 = L tCES D3 tDS tDH A4 tCD tLZC TIMING WAVEFORM OF CS OPERATION Q4 A5 tCH tCYC tCL D5 Undefined Don′t Care K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM Nov. 2003 Rev 2.0 K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM PACKAGE DIMENSIONS 100-TQFP-1420A Units ; millimeters/Inches 0~8° 22.00 ±0.30 0.127 +- 0.10 0.05 20.00 ±0.20 16.00 ±0.30 14.00 ±0.20 0.10 MAX (0.83) 0.50 ±0.10 #1 0.65 (0.58) 0.30 ±0.10 0.10 MAX 1.40 ±0.10 0.50 ±0.10 - 23 - 1.60 MAX 0.05 MIN Nov. 2003 Rev 2.0 K7N323645M K7N321845M 1Mx36 & 2Mx18 Pipelined NtRAM TM 165 FBGA PACKAGE DIMENSIONS 15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array A B Top View C Side View D A F E G B Bottom View ∅H E Symbol Value Units A 17 ± 0.1 mm B 15 ± 0.1 mm C 1.3 ± 0.1 D 0.35 ± 0.05 Note Symbol Value Units E 1.0 mm F 14.0 mm mm G 10.0 mm mm H 0.5 ± 0.05 mm - 24 - Note Nov. 2003 Rev 2.0