SAMSUNG K7N801801B

K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAMTM
8Mb NtRAMTM Specification
100 TQFP with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 5.0 April 2006
K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAMTM
Document Title
256Kx36 & 512Kx18-Bit Pipelined NtRAMTM
Revision History
Rev. No.
History
Draft Date
Remark
0.0
1. Initial document.
May. 18. 2001
Preliminary
0.1
1. Add x32 org part and industrial temperature part
Aug. 11. 2001
Preliminary
0.2
1. change scan order(1) form 4T to 6T at 119BGA(x18)
Aug. 28 .2001
Preliminary
1.0
1. Final spec release
2. Change ISB2 form 50mA to 60mA
Nov. 16. 2001
Final
2.0
Change ordering information( remove 225MHz at Nt-Pipelined)
April. 01. 2002
Final
2.1
1. Delete 119BGA package
April. 04. 2003
Final
3.0
1. Remove x32 organization
Nov. 17. 2003
Final
4.0
1. Add the overshoot timing
Feb. 16. 2006
Final
5.0
1. Change ordering information
Apr. 03. 2006
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-2-
Rev. 5.0 April 2006
K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAMTM
8Mb NtRAM (Pipelined) Ordering Information
Org.
512Kx18
256Kx36
VDD (V)
Speed (ns)
Access Time (ns)
Part Number
RoHS Avail.
3.3
6.0
3.5
K7N801801B-P(Q)1C(I)216
√
3.3
7.5
4.2
K7N801801B-Q C(I)13
•
3.3
6.0
3.5
K7N803601B-P(Q)1C(I)216
√
3.3
7.5
4.2
K7N803601B-Q C(I)13
•
3
3
Note 1. P(Q) [Package type] : P-Pb Free, Q-Pb
2. C(I) [Operating Temperature] : C-Commercial, I-Industrial
3. Support only Pb package Parts. For Pb-Free package, use faster frequency parts.
-3-
Rev. 5.0 April 2006
K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAMTM
256Kx32 & 256Kx36 & 512Kx18-Bit Pipelined NtRAMTM
FEATURES
GENERAL DESCRIPTION
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention .
• Α interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• 100-TQFP-1420A
• Operating in commercial and industrial temperature range.
The K7N803601B and K7N801801B are
9,437,184 bits Synchronous Static SRAMs.
The NtRAMTM, or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex offchip write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N803601B and K7N801801B are implemented with
SAMSUNG′s high performance CMOS technology and is available in 100pin TQFP and Multiple power and ground pins minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Symbol
-16
-13
Unit
Cycle Time
tCYC
6.0
7.5
ns
Clock Access Time
tCD
3.5
4.2
ns
Output Enable Access Time
tOE
3.5
3.8
ns
LOGIC BLOCK DIAGRAM
LBO
A [0:17] or
A [0:18]
CKE
ADDRESS
REGISTER A2~A17 or A2~A18
CONTROL
LOGIC
CLK
A0~A1
ADV
WE
BWx
(x=a,b,c,d or a,b)
CONTROL
REGISTER
CS1
CS2
CS2
WRITE
ADDRESS
REGISTER
K
BURST
ADDRESS
COUNTER
A′0~A′1
WRITE
ADDRESS
REGISTER
256Kx36 , 512Kx18
MEMORY
ARRAY
K
DATA-IN
REGISTER
K
DATA-IN
REGISTER
CONTROL
LOGIC
K
OUTPUT
REGISTER
BUFFER
OE
ZZ
36 or 18
DQa0 ~ DQd7 or DQa0 ~ DQb8
DQPa ~ DQPd
NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung,
and its architecture and functionalities are supported by NEC and Toshiba.
-4-
Rev. 5.0 April 2006
K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAMTM
CLK
WE
CKE
OE
ADV
N.C.
A17
A8
A9
88
87
86
85
84
83
82
81
BWa
VSS
BWb
93
89
BWc
94
90
BWd
95
CS2
CS2
96
VDD
CS1
97
91
A7
98
92
A6
99
100 Pin TQFP
(20mm x 14mm)
38
39
40
41
42
43
44
45
46
47
48
49
50
N.C.
N.C.
VSS
VDD
N.C.
N.C.
A10
A11
A12
A13
A14
A15
A16
35
A2
37
34
A3
A0
33
A4
36
32
A1
31
K7N803601B(256Kx36)
K7N803201B(256Kx32)
A5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LBO
DQPc
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
VDD
VDD
VDD
VSS
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
DQPd
100
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
VDD
VDD
ZZ
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
32,33,34,35,36,37,44
45,46,47,48,49,50,81
82,83,99,100
85
ADV
Address Advance/Load
WE
Read/Write Control Input 88
89
Clock
CLK
87
Clock Enable
CKE
98
Chip Select
CS1
97
Chip Select
CS2
92
Chip Select
CS2
93,94,95,96
BWx(x=a,b,c,d) Byte Write Inputs
86
Output Enable
OE
64
Power Sleep Mode
ZZ
31
Burst Mode Control
LBO
A0 - A17
Address Inputs
PIN NAME
TQFP PIN NO.
VDD
VSS
N.C.
Power Supply(+3.3V) 14,15,16,41,65,66,91
17,40,67,90
Ground
38,39,42,43,84
No Connect
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
Data Inputs/Outputs
VDDQ
Output Power Supply 4,11,20,27,54,61,70,77
(3.3V or 2.5V)
5,10,21,26,55,60,71,76
Output Ground
VSSQ
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM.
2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-5-
Rev. 5.0 April 2006
K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAMTM
VSS
CLK
WE
CKE
OE
ADV
N.C.
A18
A8
A9
89
88
87
86
85
84
83
82
81
BWa
93
90
BWb
94
CS2
N.C.
95
VDD
CS2
N.C.
91
CS1
97
92
A7
98
96
A6
99
100 Pin TQFP
(20mm x 14mm)
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A0
N.C.
N.C.
VSS
VDD
N.C.
N.C.
A11
A12
A13
A14
A15
A16
A17
34
A3
A1
33
A4
35
32
A2
31
K7N801801B(512Kx18)
A5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LBO
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
N.C.
DQb8
DQb7
VSSQ
VDDQ
DQb6
DQb5
VDD
VDD
VDD
VSS
DQb4
DQb3
VDDQ
VSSQ
DQb2
DQb1
DQb0
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
100
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQa0
DQa1
DQa2
VSSQ
VDDQ
DQa3
DQa4
VSS
VDD
VDD
ZZ
DQa5
DQa6
VDDQ
VSSQ
DQa7
DQa8
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
32,33,34,35,36,37,44
45,46,47,48,49,50,80
81,82,83,99,100
85
Address Advance/Load
ADV
Read/Write Control Input 88
WE
89
Clock
CLK
87
Clock Enable
CKE
98
Chip Select
CS1
97
Chip Select
CS2
92
Chip Select
CS2
93,94
BWx(x=a,b) Byte Write Inputs
86
Output Enable
OE
64
Power Sleep Mode
ZZ
31
Burst Mode Control
LBO
A0 - A18
Address Inputs
SYMBOL
PIN NAME
TQFP PIN NO.
VDD
VSS
N.C.
Power Supply(+3.3V)
Ground
No Connect
14,15,16,41,65,66,91
17,40,67,90
1,2,3,6,7,25,28,29,30,
38,39,42,43,51,52,53,
56,57,75,78,79,84,95,96
DQa0~a8
DQb0~b8
Data Inputs/Outputs
58,59,62,63,68,69,72,73,74
8,9,12,13,18,19,22,23,24
VDDQ
Output Power Supply
(3.3V or 2.5V)
Output Ground
4,11,20,27,54,61,70,77
VSSQ
5,10,21,26,55,60,71,76
Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM.
2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-6-
Rev. 5.0 April 2006
K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAMTM
FUNCTION DESCRIPTION
The K7N803601B and K7N801801B is NtRAMTM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when
there is transition from Read to Write, or vice versa.
All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the
burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next
operation.
Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous
inputs are ignored and the internal device registers will hold their previous values.
NtRAMTM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2)
are active .
Output Enable(OE) can be used to disable the output at any given time.
Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the
address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven
high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data
is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must
be driven low for the device to drive out the requested data.
Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipelined NtRAMTM uses a late-late write cycle to utilize 100% of the bandwidth.
At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle
later.
Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.
And when this pin is high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At
this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up
time.
BURST SEQUENCE TABLE
LBO PIN
HIGH
First Address
Fourth Address
(Interleaved Burst, LBO=High)
Case 1
A1
0
0
1
1
Case 2
A0
0
1
0
1
A1
0
0
1
1
Case 3
A0
1
0
1
0
A1
1
1
0
0
BQ TABLE
LBO PIN
Case 4
A0
0
1
0
1
A1
1
1
0
0
A0
1
0
1
0
(Linear Burst, LBO=Low)
LOW
First Address
Fourth Address
Case 1
A1
0
0
1
1
Case 2
A0
0
1
0
1
A1
0
1
1
0
Case 3
A0
1
0
1
0
A1
1
1
0
0
Case 4
A0
0
1
0
1
A1
1
0
0
1
A0
1
0
1
0
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
-7-
Rev. 5.0 April 2006
K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAMTM
STATE DIAGRAM FOR NtRAMTM
WRITE
READ
READ
BEGIN
READ
BEGIN
WRITE
ITE
WR
DS
RE
A
D
DS
ST
BUR
ST
WRI
TE
DESELECT
DS
D
EA
W
R
IT
E
R
BURST
DS
BURST
READ
BURST
WRITE
COMMAND
DS
BUR
D
REA
DS
BURST
WRITE
BURST
ACTION
DESELECT
READ
BEGIN READ
WRITE
BEGIN WRITE
BURST
BEGIN READ
BEGIN WRITE
CONTINUE DESELECT
Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does
not change the state of the device.
2. States change on the rising edge of the clock(CLK)
-8-
Rev. 5.0 April 2006
K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAMTM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1
CS2
CS2
ADV
WE
BWx
OE
CKE
CLK
ADDRESS ACCESSED
OPERATION
H
X
X
L
X
X
X
L
↑
N/A
Not Selected
X
L
X
L
X
X
X
L
↑
N/A
Not Selected
X
X
H
L
X
X
X
L
↑
N/A
Not Selected
X
X
X
H
X
X
X
L
↑
N/A
Not Selected Continue
L
H
L
L
H
X
L
L
↑
External Address
Begin Burst Read Cycle
X
X
X
H
X
X
L
L
↑
Next Address
Continue Burst Read Cycle
L
H
L
L
H
X
H
L
↑
External Address
NOP/Dummy Read
X
X
X
H
X
X
H
L
↑
Next Address
Dummy Read
L
H
L
L
L
L
X
L
↑
External Address
Begin Burst Write Cycle
X
X
X
H
X
L
X
L
↑
Next Address
Continue Burst Write Cycle
L
H
L
L
L
H
X
L
↑
N/A
NOP/Write Abort
X
X
X
H
X
H
X
L
↑
Next Address
Write Abort
X
X
X
X
X
X
X
H
↑
Current Address
Ignore Clock
Notes : 1. X means "Don′t Care".
2. The rising edge of clock is symbolized by (↑).
3. A continue deselect cycle can only be enterd if a deselect cycle is executed first.
4. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
5. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE(x36)
WE
BWa
BWb
BWc
BWd
OPERATION
H
X
X
X
X
READ
L
L
H
H
H
WRITE BYTE a
L
H
L
H
H
WRITE BYTE b
L
H
H
L
H
WRITE BYTE c
L
H
H
H
L
WRITE BYTE d
L
L
L
L
L
WRITE ALL BYTEs
L
H
H
H
H
WRITE ABORT/NOP
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
-9-
Rev. 5.0 April 2006
K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAMTM
ASYNCHRONOUS TRUTH TABLE
Operation
ZZ
OE
I/O STATUS
Sleep Mode
H
X
High-Z
Read
L
L
DQ
L
H
High-Z
Write
L
X
Din, High-Z
Deselected
L
X
High-Z
Notes
1. X means "Don′t Care".
2. Sleep Mode means power Sleep Mode of which stand-by current does
not depend on cycle time.
3. Deselected means power Sleep Mode of which stand-by current
depends on cycle time.
ABSOLUTE MAXIMUM RATINGS*
SYMBOL
RATING
UNIT
Voltage on VDD Supply Relative to VSS
PARAMETER
VDD
-0.3 to 4.6
V
Voltage on Any Other Pin Relative to VSS
VIN
-0.3 to VDD+0.3
V
Power Dissipation
PD
1.6
W
Storage Temperature
Commercial
Operating Temperature
Industrial
Storage Temperature Range Under Bias
TSTG
-65 to 150
°C
TOPR
0 to 70
°C
TOPR
-40 to 85
°C
TBIAS
-10 to 85
°C
*Notes : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O(0°C ≤ TA ≤ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
MIN
Typ.
MAX
UNIT
VDD
3.135
3.3
3.465
V
VDDQ
3.135
3.3
3.465
V
VSS
0
0
0
V
* The above parameters are also guaranteed at industrial temperature range.
OPERATING CONDITIONS at 2.5V I/O(0°C ≤ TA ≤ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
MIN
Typ.
MAX
UNIT
VDD
3.135
3.3
3.465
V
VDDQ
2.375
2.5
2.9
V
VSS
0
0
0
V
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25°C, f=1MHz)
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
TEST CONDITION
MIN
MAX
UNIT
CIN
VIN=0V
-
5
pF
COUT
VOUT=0V
-
7
pF
*Note : Sampled not 100% tested.
- 10 -
Rev. 5.0 April 2006
K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAMTM
DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
PARAMETER
SYMBOL
Input Leakage Current(except ZZ)
IIL
VDD=Max ; VIN=VSS to VDD
Output Leakage Current
IOL
Output Disabled, Vout=VSS to VDDQ
Operating Current
ICC
ISB
Standby Current
ISB1
ISB2
TEST CONDITIONS
MIN
MAX
-2
+2
µA
µA
UNIT NOTES
-2
+2
Device Selected , IOUT=0mA,
-16
-
350
ZZ≤VIL , Cycle Time ≥ tCYC Min
-13
-
300
Device deselected, IOUT=0mA, ZZ≤VIL,
-16
-
130
f=Max, All Inputs≤0.2V or ≥ VDD-0.2V
-13
-
120
-
100
mA
-
60
mA
Device deselected, IOUT=0mA, ZZ≤0.2V, f=0,
All Inputs=fixed (VDD-0.2V or 0.2V)
Device deselected, IOUT=0mA, ZZ≥VDD-0.2V,
f=Max, All Inputs≤VIL or ≥VIH
mA
1,2
mA
Output Low Voltage(3.3V I/O)
VOL
IOL=8.0mA
-
0.4
V
Output High Voltage(3.3V I/O)
VOH
IOH=-4.0mA
2.4
-
V
Output Low Voltage(2.5V I/O)
VOL
IOL=1.0mA
-
0.4
V
Output High Voltage(2.5V I/O)
VOH
IOH=-1.0mA
2.0
-
V
Input Low Voltage(3.3V I/O)
VIL
-0.3*
0.8
V
Input High Voltage(3.3V I/O)
VIH
2.0
VDD+0.3**
V
Input Low Voltage(2.5V I/O)
VIL
-0.3*
0.7
V
Input High Voltage(2.5V I/O)
VIH
1.7
VDD+0.3**
V
3
3
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. Reference AC Operating Conditions and Characteristics for input and timing.
3. Data states are all zero.
4. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
Overshoot Timing
Undershoot Timing
20% tCYC(MIN)
VIH
VDDQ+1.0V
VDDQ+0.5V
VSS
VDDQ
VSS-0.5V
VSS-1.0V
20% tCYC(MIN)
VIL
TEST CONDITIONS
(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70°C)
Parameter
Value
Input Pulse Level(for 3.3V I/O)
0 to 3.0V
Input Pulse Level(for 2.5V I/O)
0 to 2.5V
Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)
1.0V/ns
Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)
1.0V/ns
Input and Output Timing Reference Levels for 3.3V I/O
1.5V
Input and Output Timing Reference Levels for 2.5V I/O
VDDQ/2
Output Load
See Fig. 1
* The above parameters are also guaranteed at industrial temperature range.
- 11 -
Rev. 5.0 April 2006
K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAMTM
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
Output Load(A)
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
RL=50Ω
Dout
Zo=50Ω
30pF*
VL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
319Ω / 1667Ω
Dout
353Ω / 1538Ω
5pF*
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0 to 70°C)
PARAMETER
SYMBOL
-16
MIN
-13
MAX
MIN
MAX
UNIT
Cycle Time
tCYC
6.0
-
7.5
-
ns
Clock Access Time
tCD
-
3.5
-
4.2
ns
Output Enable to Data Valid
tOE
-
3.5
-
4.2
ns
Clock High to Output Low-Z
tLZC
1.5
-
1.5
-
ns
tOH
1.5
-
1.5
-
ns
Output Enable Low to Output Low-Z
tLZOE
0
-
0
-
ns
Output Hold from Clock High
Output Enable High to Output High-Z
tHZOE
-
3.0
-
3.5
ns
Clock High to Output High-Z
tHZC
-
3.0
-
3.5
ns
Clock High Pulse Width
tCH
2.2
-
3.0
-
ns
Clock Low Pulse Width
tCL
2.2
-
3.0
-
ns
Address Setup to Clock High
tAS
1.5
-
1.5
-
ns
CKE Setup to Clock High
tCES
1.5
-
1.5
-
ns
Data Setup to Clock High
tDS
1.5
-
1.5
-
ns
Write Setup to Clock High (WE, BWX)
tWS
1.5
-
1.5
-
ns
Address Advance Setup to Clock High
tADVS
1.5
-
1.5
-
ns
Chip Select Setup to Clock High
tCSS
1.5
-
1.5
-
ns
Address Hold from Clock High
tAH
0.5
-
0.5
-
ns
CKE Hold from Clock High
tCEH
0.5
-
0.5
-
ns
Data Hold from Clock High
tDH
0.5
-
0.5
-
ns
Write Hold from Clock High (WE, BWEX)
tWH
0.5
-
0.5
-
ns
Address Advance Hold from Clock High
tADVH
0.5
-
0.5
-
ns
Chip Select Hold from Clock High
tCSH
0.5
-
0.5
-
ns
ZZ High to Power Down
tPDS
2
-
2
-
cycle
ZZ Low to Power Up
tPUS
2
-
2
-
cycle
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled
low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
3. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
4. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,
Both cases must meet setup and hold times.
5. To avoid bus contention, At a given voltage and temperature tLZC is more than tHZC.
The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions
(0°C,3.465V) than tHZC, which is a Max. parameter(worst case at 70°C,3.135V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
- 12 -
Rev. 5.0 April 2006
K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAMTM
SLEEP MODE
SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SLEEP MODE is dictated by the length of time the ZZ is in a High state.
After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z
The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP
MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pending operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given
while the SRAM is transitioning out of SLEEP MODE.
SLEEP MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
CONDITIONS
SYMBOL
ZZ ≥ VIH
Current during SLEEP MODE
MIN
ISB2
MAX
60
ZZ active to input ignored
tPDS
2
ZZ inactive to input sampled
tPUS
2
ZZ active to SLEEP current
tZZI
ZZ inactive to exit SLEEP current
tRZZI
UNITS
mA
cycle
cycle
2
cycle
0
SLEEP MODE WAVEFORM
K
tPDS
ZZ setup cycle
tPUS
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All inputs
(except ZZ)
Deselect or Read Only
Deselect or Read Only
Normal
operation
cycle
Outputs
(Q)
High-Z
DON′T CARE
- 13 -
Rev. 5.0 April 2006
- 14 -
Data Out
OE
ADV
CS
WRITE
Address
CKE
Clock
A1
tADVH
tCSH
tWH
tAH
tLZOE
tOE
Q1-1
A2
tHZOE
tCEH
Q2-1
tCD
tOH
tCYC
Q2-2
tCL
NOTES : WRITE = L means WE = L, and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
tADVS
tCSS
tWS
tAS
tCES
tCH
Q2-3
A3
TIMING WAVEFORM OF READ CYCLE
Q2-4
Q3-1
Q3-2
Q3-3
Undefined
Don′t Care
Q3-4
tHZC
K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAMTM
Rev. 5.0 April 2006
- 15 -
Data Out
Data In
OE
ADV
CS
WRITE
Address
CKE
Clock
Q0-4
tHZOE
D1-1
A2
tCYC
tCL
D2-1
D2-2
NOTES : WRITE = L means WE = L, and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
Q0-3
A1
tCES tCEH
tCH
D2-3
A3
TIMING WAVEFORM OF WRTE CYCLE
D2-4
D3-1
tDS
D3-2
tDH
D3-3
Undefined
Don′t Care
D3-4
K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAMTM
Rev. 5.0 April 2006
- 16 -
Data In
Data Out
OE
ADV
CS
WRITE
Address
CKE
Clock
tOE
tLZOE
A2
Q1
A3
tDS
D2
tDH
Q3
A4
NOTES : WRITE = L means WE = L, and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
A1
tCES tCEH
A5
Q4
A6
D5
A7
TIMING WAVEFORM OF SINGLE READ/WRITE
tCH
Q6
tCYC
tCL
A8
Q7
A9
Undefined
Don′t Care
K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAMTM
Rev. 5.0 April 2006
- 17 -
Data In
A1
tCES tCEH
tCD
tLZC
A2
Q1
tHZC
A3
NOTES : WRITE = L means WE = L, and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
Data Out
OE
ADV
CS
WRITE
Address
CKE
Clock
tDS
A4
D2
TIMING WAVEFORM OF CKE OPERATION
tDH
tCH
Q3
tCYC
tCL
A5
Q4
A6
Undefined
Don′t Care
K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAMTM
Rev. 5.0 April 2006
- 18 -
Data In
Data Out
OE
ADV
CS
WRITE
Address
CKE
Clock
A1
tCEH
tOE
tLZOE
A2
Q1
Q2
tHZC
A3
NOTES : WRITE = L means WE = L, and BWx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
tCES
D3
tDS tDH
A4
tCD
tLZC
TIMING WAVEFORM OF CS OPERATION
Q4
A5
tCH
tCYC
tCL
D5
Undefined
Don′t Care
K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAMTM
Rev. 5.0 April 2006
K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAMTM
PACKAGE DIMENSIONS
100-TQFP-1420A
Units ; millimeters/Inches
0~8°
22.00 ±0.30
0.10
0.127 +- 0.05
20.00 ±0.20
16.00 ±0.30
14.00 ±0.20
0.10 MAX
(0.83)
0.50 ±0.10
#1
0.65
(0.58)
0.30 ±0.10
0.10 MAX
1.40 ±0.10 1.60 MAX
0.50 ±0.10
- 19 -
0.05 MIN
Rev. 5.0 April 2006