CENTRAL CTLDM7003T

CTLDM7003T-M563D
SURFACE MOUNT
DUAL, N-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFETS
TLM563D CASE
• Device is Halogen Free by design
APPLICATIONS:
• Load Power Switches
• DC/DC Converters
• Battery powered devices including Cell Phones,
PDAs, Digital Cameras, MP3 Players, etc.
MAXIMUM RATINGS: (TA=25°C)
Drain-Source Voltage
Drain-Gate Voltage
Gate-Source Voltage
Continuous Drain Current
Maximum Pulsed Drain Current
Power Dissipation (Note 1)
Operating and Storage Junction Temperature
Thermal Resistance (Note 1)
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DESCRIPTION:
The CENTRAL SEMICONDUCTOR CTLDM7003TM563D is a Dual N-channel MOSFET packaged in
a space saving 1.6 x 1.6mm TLM™ surface mount
package. This device is a TLM™ equivalent of the
popular CMLDM7003T, SOT-563 device, featuring
enhanced thermal characteristics, a package footprint
compatible with standard SOT-563 mounting pad
geometries, and a height profile of only 0.4mm.
MARKING CODE: CJA
FEATURES:
• ESD protection up to 2kV
• Dual MOSFETs
• Low rDS(ON) (1.6Ω TYP @ VGS=1.8V)
• TLM563D with a package profile of 0.4mm, compatible with
SOT-563 mounting geometries
SYMBOL
VDS
50
UNITS
V
VDG
VGS
50
V
12
V
ID
280
mA
IDM
PD
1.5
A
350
-65 to +150
mW
357
°C/W
TJ, Tstg
ΘJA
°C
ELECTRICAL CHARACTERISTICS PER TRANSISTOR: (TA=25°C unless otherwise noted)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
IGSSF, IGSSR
VGS=5.0V, VDS=0
50
UNITS
nA
IGSSF, IGSSR
IGSSF, IGSSR
VGS=10V, VDS=0
VGS=12V, VDS=0
0.5
1.0
μA
IDSS
VDS=50V, VGS=0
VGS=0, ID=10μA
50
nA
1.2
V
BVDSS
VGS(th)
50
μA
V
VSD
VDS=10V, ID=250μA
VGS=0, IS=115mA
0.75
1.4
V
rDS(ON)
VGS=1.8V, ID=50mA
1.6
2.3
Ω
rDS(ON)
rDS(ON)
1.3
1.9
Ω
1.1
1.5
gFS
VGS=2.5V, ID=50mA
VGS=5.0V, ID=50mA
VDS=10V, ID=200mA
Crss
Ciss
VDS=25V, VGS=0, f=1.0MHz
VDS=25V, VGS=0, f=1.0MHz
Coss
VDS=25V, VGS=0, f=1.0MHz
200
Notes: (1) Mounted on 2 inch square FR4 PCB with copper mounting pad area of
5.0
pF
50
pF
25
1.8mm2.
Ω
mS
pF
R1 (17-February 2010)
CTLDM7003T-M563D
SURFACE MOUNT
DUAL, N-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFETS
TLM563D CASE - MECHANICAL OUTLINE
SUGGESTED MOUNTING PADS
(Dimensions in mm)
PIN CONFIGURATION
LEAD CODE:
1) Gate Q1
2) Source Q1
3) Drain Q2
4) Gate Q2
5) Source Q2
6) Drain Q1
MARKING CODE: CJA
R1 (17-February 2010)
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