AP7217A 3.3V 600mA CMOS LDO General Description Features • • • • • • • • • • • The AP7217A low-dropout linear regulator operates from a 3.3V to 5.5V supply and delivers a guaranteed 600mA (min) continuous load current. Very Low Dropout Voltage Low Current Consumption: Typ. 50µA Output Voltage: 3.3V Guaranteed 600mA (min) Output Input Range up to 5.5V Current Limiting Stability with Low ESR Capacitors Thermal shutdown Protection Low Temperature Coefficient SOP-8L and SOP-8L-EP: Available in “Green” Molding Compound (No Br, Sb) Lead Free Finish/ RoHS Compliant (Note 1) The high-accuracy output voltage is preset to an internally trimmed voltage. An active-low open-drain reset output remains asserted for at least 200ms (TYP) after output voltage reaches regulation. The space-saving SOP-8L and SOP-8L-EP packages are suitable for “pocket” and hand-held application. Applications • • • • • HD/ Blue Ray DVD & MP3/4 Players CD and MP3 Players Cellular and PCS Phones Digital Still Camera Hand-Held Computers Typical Application Circuit U1 4 VIN VIN VOUT 2 VROUT AP7217A 100K ON CIN 1uF VDOUT 6 VDOUT GND EN 8 OFF COUT 1uF 7 AP7217A Rev. 3 DS31423 1 of 10 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217A 3.3V 600mA CMOS LDO Ordering Information AP 7217A - 33 XX G - 13 Output voltage 33 : 3.3V Device AP7217A-33SG-13 AP7217A-33SPG-13 Notes: Package S : SOP-8L SP : SOP-8L-EP Package Code S SP Packaging (Note 2) SOP-8L SOP-8L-EP Green G : Green Packing 13 : Tape & Reel 13” Tape and Reel Quantity Part Number Suffix 2500/Tape & Reel -13 2500/Tape & Reel -13 1. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied. Please visit our website at http://www.diodes.com/products/lead_free.html. 2. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf. Pin Assignments ( Top View ) ( Top View ) 1 8 EN VR OUT 2 7 GND GND GND AP7217A GND 3 1 8 EN VROUT 2 7 GND GND 3 6 VD OUT 6 VDOUT VIN 4 VIN 4 5 5 GND GND SOP-8L-EP SOP-8L Pin Descriptions Pin Name Pin No. GND VROUT VIN VDOUT EN 1, 3, 5, 7 2 4 6 8 AP7217A Rev. 3 DS31423 Description Ground Voltage Output Supply Voltage VD Output (Reset on I/P) Enable (VR On/Off) 2 of 10 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217A 3.3V 600mA CMOS LDO Block Diagram EN Enable VIN On - Off ERROR AMP Bandgap Current Limit + VROUT 1.2V R1 VDOUT + R3 R2 VD Comp. R4 GND Absolute Maximum Ratings Symbol ESD HBM ESD MM VIN IOUT VROUT PD TJ Parameter Human Body Model ESD Protection Machine Model ESD Protection Input Voltage Output Current Output Voltage SOP-8L Power Dissipation SOP-8L-EP Operating Junction Temperature Range Rating 3.5 500 +6 PD/ (VIN-VO) GND - 0.3 ~ VIN+ 0.3 1010 1650 -40 to +125 Unit KV V V mA V mW ºC Recommended Operating Conditions Symbol VIN IOUT TA AP7217A Rev. 3 DS31423 Parameter Input Voltage Output Current Operating Ambient Temperature 3 of 10 www.diodes.com Min 3.3 0 -40 Max 5.5 600 85 Unit V mA ºC OCTOBER 2009 © Diodes Incorporated AP7217A 3.3V 600mA CMOS LDO Electrical Characteristics (TA = 25°C, CIN = 1µF, COUT = 1µF, VEN = VIN, unless otherwise noted) Symbol IQ ISTB VROUT VDROPOUT IOUT ILIMIT Ishort ∆VLINE/∆VIN/VOUT ∆VOUT PSRR VEH VEL IEN VDF VD Hysteresis Range IVDout tRP θJA θJC Notes: Parameter Quiescent Current Standby Current Output Voltage Accuracy VOUT Temperature Coefficient Dropout Voltage Test Conditions IO = 0mA VEN = Off VIN = 5.0V IO = 30mA, VIN = 5V Min - 3.234 Typ. 50 Max 80 Unit µA 15 25 µA 3.300 3.366 V -40°C to 85°C, IOUT = 30mA ±100 IOUT = 300mA IOUT = 600mA 350 800 Maximum Output Current Current Limit Short Circuit Current Line Regulation Load Regulation VIN = 5.3V VIN = 5.3V 4.3V ≤ VIN ≤ 5.5V; IOUT = 30mA 1mA ≤ IOUT ≤ 100mA, VIN = 5.3V Power Supply Rejection VIN = 4.3V+ 0.5Vp-pAC, F = 1KHz IOUT = 50mA EN Input Threshold Output ON Output OFF VIN = 5.3V Enable Pin Current Detect fall voltage VDout = 0.5V VIN = 2.0V 3.0V VDOUT Delay Time VIN = 1.8V to VDF+ 1V Thermal Resistance SOP-8L (Note 3) Junction-to-Ambient SOP-8L-EP (Note 4) Thermal Resistance SOP-8L (Note 3) Junction-to-Case SOP-8L-EP (Note 4) 400 900 600 ±0.2 50 55 180 3.3 VDF x1.05 20 30 200 134 82 28 12 mA mA %/V mV dB 1.6 VD Supply Current mV mA 750 50 0.01 15 -0.1 3.23 VDF x1.02 VHysteresis ppm / oC 0.25 0.1 3.37 VDF x1.08 V V µA V V mA - mSec ºC/W ºC/W 3. Test condition for SOP-8L: Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout. 4. Test condition for SOP-8L-EP: Device mounted on 2oz copper, minimum recommended pad layout on top & bottom layer with thermal vias, double sided FR-4 PCB. AP7217A Rev. 3 DS31423 4 of 10 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217A 3.3V 600mA CMOS LDO Typical Performance Characteristics Input Voltage vs. Max Iout 900 800 800 700 700 600 Max Iout (m A) Dropout Voltage (m V) Output Current vs. Dropout Voltage (Vout=3.3V) 600 500 400 300 500 400 300 200 200 100 100 0 0 30mA 100mA 300mA 3.6V 600mA 4.3V 5.3 5.5V Input Voltage Output Current Quiescent Current vs. Tem perature Quiescent Current vs. Input Voltage 75 80 70 70 Quiescent Current (uA) Quiescent Current (uA) 5.0V 65 60 55 50 45 60 50 40 30 20 10 0 40 -40℃ 0℃ 25℃ 85℃ 100℃ AP7217A Rev. 3 DS31423 3.6V 56V 58V 61V 5.5V Input Voltage Tem perature 5 of 10 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217A 3.3V 600mA CMOS LDO Typical Performance Characteristics (Continued) Short Current vs. Input Voltage 65 64 62 63 Short Current (m A) Short Current (m A) 64 Short Current vs. Tem perature (Vin=5.5V) 62 61 60 59 58 57 60 58 56 54 52 56 55 50 3.6V 4.3V 5V 5.3V 5.5V -40℃ 25℃ Stand-by Current vs. Input Voltage 105℃ Stand-by Current vs. Tem perature 24 35 Stand-by Current (uA) Stand-by Current (uA) 85℃ Tem perature Input Voltage 21 18 15 30 25 20 15 10 5 0 12 3.6V 4V 4.3V Input Voltage 5V 5.5V Load Transient Response AP7217A Rev. 3 DS31423 -40℃ 0℃ 25℃ 85℃ Tem perature 105℃ 125℃ Load Transient Response 6 of 10 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217A 3.3V 600mA CMOS LDO Timing Diagram tRP 200mSec-TYP. VIN 1.6V VDOUT EN VROUT Application Note Input Capacitor A 1µF ceramic capacitor is recommended to connect between IN and GND pins to decouple input power supply glitch and noise. The amount of the capacitance may be increased without limit. A lower ESR (Equivalent Series Resistance) capacitor allows the use of less capacitance, while higher ESR type requires more capacitance. This input capacitor must be located as close as possible to the device to assure input stability and less noise. For PCB layout, a wide copper trace is required for both IN and GND. Output Capacitor The output capacitor is required to stabilize and help the transient response of the LDO. The AP7217A is designed to have excellent transient response for most applications with a small amount of output capacitance. The AP7217 is stable with any small ceramic output capacitors of 1.0µF or higher value, and the temperature coefficients of X7R or X5R type. Additional capacitance helps to reduce undershoot and overshoot during transient. For PCB layout, the output capacitor must be placed as close as possible to OUT and GND pins, and keep the leads as short as possible. ENABLE/SHUTDOWN Operation The AP7217A is turned on by setting the EN pin high, and is turned off by pulling it low. If this feature is not used, the EN pin should be tied to IN pin to keep the regulator output on at all time. To ensure proper operation, the signal source used to drive the EN pin must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH. EN=0 EN=1 VROUT 0V 3.3V VDOUT Φ Φ Thermal Considerations Thermal Shutdown Protection limits power dissipation in AP7217A. When the operation junction temperature exceeds 150°C, the Over Temperature Protection circuit starts the thermal shutdown function and turns the pass element off. The pass element turn on again after the junction temperature cools by 40°C. For continuous operation, do not exceed absolute maximum operation junction temperature 125°C. The power dissipation definition in device is: PD = (VIN − VOUT) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = ( TJ(MAX) - TA ) / θJA Where TJ(MAX) is the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. AP7217A Rev. 3 DS31423 7 of 10 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217A 3.3V 600mA CMOS LDO Application Note Vin (Continued) Iin Iout IN C Short circuit protection When VROUT pin is shorted to GND or VROUT voltage is less than 200mV, short circuit protection will be triggered and clamp the output current to approximately 50mA. Vout OUT AP7217A Co GND ESR Iq Current Limit Protection When output current at OUT pin is higher than current limit threshold, the current limit protection will be triggered and clamp the output current to approximately 750mA to prevent over-current and to protect the regulator from damage due to overheating. VDOUT (reset output) ---Open-Drain Active-Low reset output--In general, VDOUT is pulled up by a resistor (100Kohm) to VIN. The AP7217A microprocess (uP) supervisory circuitry asserts a guaranteed logic-low reset during power-up and power-down. Reset is asserted asserts when VIN is below the reset threshold and remain asserted for at least tRP after VIN rises above the reset threshold. As long as VIN is lower than the reset threshold, VDOUT remains at logic "0". When VIN become higher than VTH, a logic "1" is asserted after a time delay defined by tRP. Marking Information (1) SOP-8L ( Top View ) 8 5 Logo Part Number 7217A-33 YY WW X X 1 YY : Year : 08, 09,10~ WW : Week : 01~52; 52 represents 52 and 53 week X : Internal Code G : Green 4 (2) SOP-8L-EP ( Top View ) 8 5 Logo Part No. 7217A-33 YY WW X X E 1 AP7217A Rev. 3 DS31423 G : Green YY : Year : 08, 09,10~ WW : Week : 01~52; 52 represents 52 and 53 week X : Internal Code SOP-8L-EP 4 8 of 10 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217A 3.3V 600mA CMOS LDO Package Information (All Dimensions in mm) 0.254 0.10/0.20 3.85/3.95 5.90/6.10 (1) Package Type: SOP-8L Gauge Plane Seating Plane 0.62/0.82 Detail "A" 7°~9° 7°~9° 0.15/0.25 1.30/1.50 1.75max. 0.35max. 45° Detail "A" 0°/8° 0.3/0.5 1.27typ 4.85/4.95 5.4 8x-0.60 8x-1.55 6x-1.27 Land Pattern Recommendation (Unit: mm) (2) Package Type: SOP-8L-EP Detail "A" Exposed pad 2.4Ref. 3.70/4.10 45° 0.35max. 3.85/3.95 5.90/6.10 7°~9° 7°~9° 1 1 0.15/0.25 Bottom View 1.75max. 1.30/1.50 3.3Ref. 0/0.13 0.254 0.3/0.5 1.27typ 4.85/4.95 1 Gauge Plane Seating Plane 0.62/0.82 Detail "A" 8x-0.60 5.4 Exposed pad 8x-1.55 6x-1.27 Land Pattem Recommendation (Unit:mm) AP7217A Rev. 3 DS31423 9 of 10 www.diodes.com OCTOBER 2009 © Diodes Incorporated AP7217A 3.3V 600mA CMOS LDO IMPORTANT NOTICE DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDING TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 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