FREESCALE MC68HC705P6ACP

Freescale Semiconductor, Inc.
General Release Specification
R E Q U I R E D
A G R E E M E N T
68HC705P6A
July 23, 1996
CSIC System Design Group
Austin, Texas
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N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
HC705P6AGRS/D
Rev. 1.0
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
General Release Specification
© Motorola, Inc., 1996
MC68HC705P6A — Rev. 1.0
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General Release Specification — MC68HC705P6A
List of Sections
Section 3. Operating Modes ............................................ 31
Section 4. Resets ............................................................. 39
Section 5. Interrupts ........................................................ 43
Section 6. Input/Output Ports ......................................... 49
Section 7. Serial Input/Output Port ................................. 57
A G R E E M E N T
Section 2. Memory ........................................................... 23
Section 8. Capture/Compare Timer ................................ 65
Section 9. Analog Subsystem ......................................... 77
Section 10. EPROM .......................................................... 83
Section 11. Mask Option Register (MOR) ...................... 91
Section 12. CPU Core ...................................................... 95
Section 13. Instruction Set ............................................ 101
Section 14. Electrical Specifications ............................ 119
Section 15. Mechanical Specifications ........................ 129
Section 16. Ordering Information ................................. 131
MC68HC705P6A — Rev. 1.0
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Section 1. General Description ....................................... 15
R E Q U I R E D
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List of Sections
General Release Specification
MC68HC705P6A — Rev. 1.0
List of Sections
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Section 1. General Description
1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.4
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.4.1
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.4.2
OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.4.2.1
Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.4.2.2
Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.4.2.3
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.4.3
1.4.4
PA0–PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.4.5
PB5/SDO, PB6/SDI, and PB7/SCK. . . . . . . . . . . . . . . . . . .21
1.4.6
PC0-PC2, PC3/AD3, PC4/AD2, PC5/AD1,
PC6/AD0, and PC7/VREFH . . . . . . . . . . . . . . . . . . . . . . .21
1.4.7
PD5 and PD7/TCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.4.8
TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.4.9
IRQ/VPP (Maskable Interrupt Request) . . . . . . . . . . . . . . . .22
Section 2. Memory
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
User Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Bootloader Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . .24
Input/Output and Control Registers . . . . . . . . . . . . . . . . . . . . .25
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
EPROM/ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Mask Option Register (MOR) $1EFF–$1F00 . . . . . . . . . . . . . .28
COP Clear Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
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A G R E E M E N T
Table of Contents
N O N - D I S C L O S U R E
General Release Specification — MC68HC705P6A
R E Q U I R E D
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Table of Contents
Section 3. Operating Modes
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.3
User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.4
Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.5
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.5.1
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.5.1.1
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.5.1.2
Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.5.2
WAIT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.6
COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . .37
Section 4. Resets
4.1
4.2
4.3
4.4
4.4.1
4.4.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Computer Operating Properly (COP) Reset . . . . . . . . . . . .40
Section 5. Interrupts
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.3
Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.3.1
Reset Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.3.2
Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.3.3
Hardware Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.3.3.1
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.3.3.2
Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .47
5.3.3.3
Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . .47
5.3.3.4
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .47
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Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
I/O Port Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Section 7. Serial Input/Output Port
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.4
7.4.1
7.4.2
7.4.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Serial Data Output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . .60
SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . .61
SIOP Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . .62
SIOP Data Register (SDR) . . . . . . . . . . . . . . . . . . . . . . . . .63
Section 8. Capture/Compare Timer
8.1
8.2
8.3
8.3.1
8.3.2
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.5
8.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Input Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Timer I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . .68
Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . .70
Timer Registers (TRH and TRL) . . . . . . . . . . . . . . . . . . . . .71
Alternate Timer Registers (ATRH and ATRL) . . . . . . . . . . .72
Input Capture Registers (ICRH and ICRL) . . . . . . . . . . . . .73
Output Compare Registers (OCRH and OCRL) . . . . . . . . .74
Timer During Wait/Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . .75
Timer During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
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6.1
6.2
6.3
6.4
6.5
6.6
6.7
N O N - D I S C L O S U R E
Section 6. Input/Output Ports
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Section 9. Analog Subsystem
9.1
9.2
9.3
9.3.1
9.3.2
9.3.3
9.4
9.5
9.5.1
9.5.2
9.5.3
9.6
9.7
9.8
9.9
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Reference Voltage (VREFH) . . . . . . . . . . . . . . . . . . . . . . . .78
Accuracy and Precision. . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Digital Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Conversion Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Internal versus External Oscillator. . . . . . . . . . . . . . . . . . . .79
Multi-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .79
A/D Status and Control Register (ADSC) . . . . . . . . . . . . . . . . .80
A/D Conversion Data Register (ADC). . . . . . . . . . . . . . . . . . . .82
A/D Subsystem Operation during Halt/Wait Modes . . . . . . . . .82
A/D Subsystem Operation during Stop Mode. . . . . . . . . . . . . .82
Section 10. EPROM
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
EPROM Programming Sequence. . . . . . . . . . . . . . . . . . . . . . .84
EPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
EPROM Programming Register (EPROG) . . . . . . . . . . . . . . . .84
EPROM Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Programming from an External Memory Device. . . . . . . . . . . .87
Section 11. Mask Option Register (MOR)
11.1
11.2
11.3
11.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Mask Option Register (MOR) $1EFF–$1F00 . . . . . . . . . . . . . .92
MOR Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
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Section 13. Instruction Set
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
13.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
13.3.1
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
13.3.2
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
13.3.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
13.3.4
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
13.3.5
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
13.3.6
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
13.3.7
Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
13.3.8
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
13.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
13.4.1
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .106
13.4.2
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .107
13.4.3
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .108
13.4.4
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .110
13.4.5
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
13.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
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12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
12.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
12.3.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
12.3.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
12.3.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
12.3.4
Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
12.3.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .98
N O N - D I S C L O S U R E
Section 12. CPU Core
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Section 14. Electrical Specifications
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
14.10
14.11
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .121
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
DC Electrical Characteristics (VDD = 5.0 V) . . . . . . . . . . . . . .122
DC Electrical Charactertistics (VDD = 3.3 V). . . . . . . . . . . . . .123
A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . .124
EPROM Programming Characteristics . . . . . . . . . . . . . . . . . .124
SIOP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Section 15. Mechanical Specifications
15.1
15.2
15.3
15.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Plastic Dual In-Line Package (Case 710) . . . . . . . . . . . . . . . .130
Small Outline Integrated Circuit Package (Case 751F) . . . . .130
Section 16. Ordering Information
16.1
16.2
16.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
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Figure
Title
Page
1-1
1-2
MC68HC705P6A Block Diagram . . . . . . . . . . . . . . . . . . . . .18
Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2-1
2-2
2-3
2-4
2-5
MC68HC705P6A User Mode Memory Map . . . . . . . . . . . . .24
MC68HC705P6A I/O and Control
Registers Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .25
I/O and Control Register Summary . . . . . . . . . . . . . . . . . . .26
Mask Option Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
COP Watchdog Timer Location . . . . . . . . . . . . . . . . . . . . . .29
3-1
3-2
User Mode Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
STOP/WAIT Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4-1
4-2
Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Unused Vector and COP Watchdog Timer . . . . . . . . . . . . .41
5-1
Interrupt Processing Flowchart. . . . . . . . . . . . . . . . . . . . . . .45
6-1
6-2
6-3
6-4
Port A I/O and Interrupt Circuitry . . . . . . . . . . . . . . . . . . . . .50
Port B I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Port C I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Port D I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
7-1
7-2
7-3
7-4
7-5
SIOP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
SIOP Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . .61
SIOP Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . .62
Serial Port Data Register (SDR). . . . . . . . . . . . . . . . . . . . . .63
8-1
8-2
Capture/Compare Timer Block Diagram . . . . . . . . . . . . . . .66
Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . .68
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Figure
Title
Page
8-3
8-4
8-5
8-6
8-7
Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . .70
Timer Registers (TRH and TRL) . . . . . . . . . . . . . . . . . . . . .71
Alternate Timer Registers (ATRH and ATRL) . . . . . . . . . . .72
Input Capture Registers (ICRH and ICRL) . . . . . . . . . . . . . .73
Output Compare Registers (OCRH and OCRL). . . . . . . . . .74
9-1
9-2
A/D Status and Control Register (ADSC) . . . . . . . . . . . . . . .80
A/D Conversion Value Data Register (ADC) . . . . . . . . . . . .82
10-1
10-2
10-3
EPROM Programming Register (EPROG) . . . . . . . . . . . . . .85
MC68HC705P6A EPROM Programming Flowchart . . . . . .89
MC68HC705P6A EPROM Programming
Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
11-1
Mask Option Register (MOR) . . . . . . . . . . . . . . . . . . . . . . . .92
12-1
MC68HC05 Programming Model . . . . . . . . . . . . . . . . . . . . .96
14-1
14-2
SIOP Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Power-On Reset and External Reset Timing Diagram . . . .127
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Table
Title
Page
3-1
Operating Mode Conditions After Reset.................................32
5-1
Vector Addresses for Interrupts and Reset ............................44
6-1
6-2
6-3
6-4
Port A I/O Functions ...............................................................54
Port B I/O Functions ...............................................................54
Port C I/O Functions ...............................................................55
Port D I/O Functions ...............................................................55
9-1
A/D Multiplexer Input Channel Assignments ..........................81
10-1
10-2
EPROM Programming Routine ..............................................86
Bootloader Control Pins..........................................................87
11-1
11-2
SIOP Clock Rate ....................................................................93
MOR Programming Routine ...................................................94
13-1
13-2
13-3
13-4
13-5
13-6
13-7
Register/Memory Instructions...............................................106
Read-Modify-Write Instructions ............................................107
Jump and Branch Instructions ..............................................109
Bit Manipulation Instructions.................................................110
Control Instructions...............................................................111
Instruction Set Summary ......................................................112
Opcode Map .........................................................................118
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A G R E E M E N T
R E Q U I R E D
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1.1 Contents
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.4
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.4.1
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.4.2
OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.4.2.1
Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.4.2.2
Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.4.2.3
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.4.3
1.4.4
PA0–PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.4.5
PB5/SDO, PB6/SDI, and PB7/SCK. . . . . . . . . . . . . . . . . . .21
1.4.6
PC0-PC2, PC3/AD3, PC4/AD2, PC5/AD1,
PC6/AD0, and PC7/VREFH . . . . . . . . . . . . . . . . . . . . . . .21
1.4.7
PD5 and PD7/TCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.4.8
TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.4.9
IRQ/VPP (Maskable Interrupt Request) . . . . . . . . . . . . . . . .22
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Section 1. General Description
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1.2 Introduction
The Motorola MC68HC705P6A is an EPROM version of the
MC68HC05P6 microcontroller. It is a low-cost combination of an
M68HC05 Family microprocessor with a 4-channel, 8-bit analog-todigital (A/D) converter, a 16-bit timer with output compare and input
capture, a serial communications port (SIOP), and a computer operating
properly (COP) watchdog timer. The HC05 CPU core contains 176 bytes
of RAM, 4672 bytes of user EPROM, 239 bytes of bootloader ROM, and
21 input/output (I/O) pins (20 bidirectional, 1 input-only). This device is
available in a 28-pin SOIC, PDIP, or windowed DIP package. A
functional block diagram of the MC68HC705P6A is shown in Figure 1-1.
1.3 Features
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General Description
•
Low Cost
•
HC05 Core
•
28-Pin SOIC, PDIP, or Windowed DIP Package
•
4672 Bytes of User EPROM (Including 48 Bytes of Page Zero
EPROM and 16 Bytes of User Vectors)
•
239 Bytes of Bootloader ROM
•
176 Bytes of On-Chip RAM
•
4-Channel 8-Bit A/D Converter
•
SIOP Serial Communications Port
•
16-Bit Timer with Output Compare and Input Capture
•
20 Bidirectional I/O Lines and 1 Input-Only line
•
PC0 and PC1 High-Current Outputs
•
Single-Chip, Bootloader, and Test Modes
•
Power-Saving Stop, Halt, and Wait Modes
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Static EPROM Mask Option Register (MOR) Selectable Options:
– COP Watchdog Timer Enable or Disable
– Edge-Sensitive or Edge- and Level-Sensitive External
Interrupt
– SIOP Most Significant Bit (MSB) or Least Significant Bit (LSB)
First
– SIOP Clock Rates: OSC Divided by 8, 16, 32, or 64
– Stop Instruction Mode, STOP or HALT
– EPROM Security External Lockout
N O N - D I S C L O S U R E
– Programmable Keyscan (Pullups/Interrupts) on PA0–PA7
A G R E E M E N T
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•
R E Q U I R E D
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R E Q U I R E D
General Description
INTERNAL
CPU CLOCK
COP
CPU CONTROL
ALU
RESET
68HC05 CPU
IRQ/VPP
÷4
÷2
OSC
16-BIT TIMER
1 INPUT CAPTURE
1 OUTPUT COMPARE
PORT D LOGIC
COND CODE REG
1 1 1H I NZC
PD7/TCAP
TCMP
PD5
PC7/VREFH
PC6/AD0
MUX
A/ D CONVERTER
PROGRAM COUNTER
PORT C
0 0 0 0 0 0 0 0 1 1 STK PNTR
DATA DIRECTION REGISTER
A G R E E M E N T
INDEX REG
PC5/AD1
PC4/AD2
PC3/AD3
PC2
PC1
PC0
SRAM — 176 BYTES
PA7
BOOTLOADER ROM — 239 BYTES
PORT B AND
SIOP
REGISTERS
AND LOGIC
PB5/SDO
PB6/SDI
PB7/SCK
PA6
PA5
PORT A
USER EPROM — 4672 BYTES
DATA DIRECTION REG
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OSC 2
ACCUM
CPU REGISTERS
N O N - D I S C L O S U R E
OSC 1
PA4
PA3
PA2
PA1
PA0
VDD
VSS
Figure 1-1. MC68HC705P6A Block Diagram
NOTE:
A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low.
Any reference to voltage, current, or frequency specified in the following
sections will refer to the nominal values. The exact values and their
tolerances or limits are specified in Section 14. Electrical
Specifications.
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The following paragraphs describe the functionality of each pin on the
MC68HC705P6A package. Pins connected to subsystems described in
other chapters provide a reference to the chapter instead of a detailed
functional description.
Power is supplied to the MCU through VDD and VSS. VDD is connected
to a regulated +5 volt supply and VSS is connected to ground.
Very fast signal transitions occur on the MCU pins. The short rise and
fall times place very high short-duration current demands on the power
supply. To prevent noise problems, take special care to provide good
power supply bypassing at the MCU. Use bypass capacitors with good
high-frequency characteristics and position them as close to the MCU as
possible. Bypassing requirements vary, depending on how heavily the
MCU pins are loaded.
1.4.2 OSC1 and OSC2
The OSC1 and OSC2 pins are the control connections for the on-chip
oscillator. The OSC1 and OSC2 pins can accept the following:
1. A crystal as shown in Figure 1-2(a)
2. A ceramic resonator as shown in Figure 1-2(a)
3. An external clock signal as shown in Figure 1-2(b)
The frequency, fosc, of the oscillator or external clock source is divided
by two to produce the internal bus clock operating frequency, fop. The
oscillator cannot be turned off by software unless the MOR bit, SWAIT,
is clear when a STOP instruction is executed.
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1.4.1 VDD and VSS
A G R E E M E N T
1.4 Functional Pin Description
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To VDD (or STOP)
OSC1
MCU
To VDD (or STOP)
OSC2
OSC1
MCU
OSC2
4.7 MΩ
UNCONNECTED
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EXTERNAL CLOCK
37 pF
(a)
37 pF
Crystal or Ceramic
Resonator Connections
(b)
External Clock Source
Connections
Figure 1-2. Oscillator Connections
1.4.2.1 Crystal
The circuit in Figure 1-2(a) shows a typical oscillator circuit for an ATcut, parallel resonant crystal. Follow the crystal manufacturer’s
recommendations, as the crystal parameters determine the external
component values required to provide maximum stability and reliable
startup. The load capacitance values used in the oscillator circuit design
should include all stray capacitances. Mount the crystal and components
as close as possible to the pins for startup stabilization and to minimize
output distortion.
1.4.2.2 Ceramic Resonator
In cost-sensitive applications, use a ceramic resonator in place of a
crystal. Use the circuit in Figure 1-2(a) for a ceramic resonator and
follow the resonator manufacturer’s recommendations, as the resonator
parameters determine the external component values required for
maximum stability and reliable starting. The load capacitance values
used in the oscillator circuit design should include all stray capacitances.
Mount the resonator and components as close as possible to the pins for
startup stabilization and to minimize output distortion.
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An external clock from another CMOS-compatible device can be
connected to the OSC1 input, with the OSC2 input not connected, as
shown in Figure 1-2(b).
Driving this input low will reset the MCU to a known startup state. The
RESET pin contains an internal Schmitt trigger to improve its noise
immunity. Refer to Section 4. Resets.
1.4.4 PA0–PA7
These eight I/O pins comprise port A. The state of any pin is software
programmable and all port A lines are configured as inputs during
power-on or reset. Port A has mask-option register enabled interrupt
capability with internal pullup devices selectable for any pin. Refer to
Section 6. Input/Output Ports.
1.4.5 PB5/SDO, PB6/SDI, and PB7/SCK
These three I/O pins comprise port B and are shared with the SIOP
communications subsystem. The state of any pin is software
programmable, and all port B lines are configured as inputs during
power-on or reset. Refer to Section 6. Input/Output Ports and Section
7. Serial Input/Output Port.
1.4.6 PC0-PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/VREFH
These eight I/O pins comprise port C and are shared with the A/D
converter subsystem. The state of any pin is software programmable
and all port C lines are configured as inputs during power-on or reset.
Refer to Section 6. Input/Output Ports and Section 9. Analog
Subsystem.
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1.4.3 RESET
A G R E E M E N T
1.4.2.3 External Clock
R E Q U I R E D
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1.4.7 PD5 and PD7/TCAP
These two I/O pins comprise port D and one of them is shared with the
16-bit timer subsystem. The state of PD5 is software programmable and
is configured as an input during power-on or reset. PD7 is always an
input. It may be read at any time, regardless of which mode of operation
the 16-bit timer is in. Refer to Section 6. Input/Output Ports and
Section 8. Capture/Compare Timer.
1.4.8 TCMP
This pin is the output from the 16-bit timer’s output compare function. It
is low after reset. Refer to Section 8. Capture/Compare Timer.
1.4.9 IRQ/VPP (Maskable Interrupt Request)
This input pin drives the asynchronous interrupt function of the MCU in
user mode and provides the VPP programming voltage in bootloader
mode. The MCU will complete the current instruction being executed
before it responds to the IRQ interrupt request. When the IRQ/VPP pin is
driven low, the event is latched internally to signify an interrupt has been
requested. When the MCU completes its current instruction, the interrupt
latch is tested. If the interrupt latch is set and the interrupt mask bit (I bit)
in the condition code register is clear, the MCU will begin the interrupt
sequence.
Depending on the MOR LEVEL bit, the IRQ/VPP pin will trigger an
interrupt on either a negative edge at the IRQ/VPP pin and/or while the
IRQ/VPP pin is held in the low state. In either case, the IRQ/VPP pin must
be held low for at least one tILIH time period. If the edge- and levelsensitive mode is selected (LEVEL bit set), the IRQ/VPP input pin
requires an external resistor connected to VDD for wired-OR operation.
If the IRQ/VPP pin is not used, it must be tied to the VDD supply. The
IRQ/VPP pin input circuitry contains an internal Schmitt trigger to improve
noise immunity. Refer to Section 5. Interrupts.
NOTE:
If the voltage level applied to the IRQ/VPP pin exceeds VDD, it may affect
the MCU’s mode of operation. See Section 3. Operating Modes.
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2.1 Contents
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.3
User Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.4
Bootloader Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . .24
2.5
Input/Output and Control Registers . . . . . . . . . . . . . . . . . . . . .25
2.6
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.7
EPROM/ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.8
Mask Option Register (MOR) $1EFF–$1F00 . . . . . . . . . . . . . .28
2.9
COP Clear Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.2 Introduction
The MC68HC705P6A utilizes 13 address lines to access an internal
memory space covering 8 Kbytes. This memory space is divided into
I/O, RAM, ROM, and EPROM areas.
2.3 User Mode Memory Map
When the MC68HC705P6A is in the user mode, the 32 bytes of I/O, 176
bytes of RAM, 4608 bytes of user EPROM, 48 bytes of user page zero
EPROM, 239 bytes of bootloader ROM, and 16 bytes of user vectors
EPROM are all active as shown in Figure 2-1.
MC68HC705P6A — Rev. 1.0
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Section 2. Memory
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R E Q U I R E D
Memory
$0000
$001F
$0020
$004F
$0050
$00BF
$00C0
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A G R E E M E N T
$00FF
$0100
0000
I/O
32 Bytes
$0000
0031
0032
User EPROM
48 Bytes
I/O Registers
See Figure 2-2
0079
0080
Internal RAM
176 Bytes
Stack
64 Bytes
0191
0192
$001F
0255
0256
User EPROM
4608 Bytes
$12FF
$1300
COP Clear Register*
$1FF0
Unused
$1FF1
Unused
$1FF2
Unused
$1FF3
Unused
$1FF4
Unused
$1FF5
Unused
$1FF6
Unused
$1FF7
Timer Vector (High Byte)
$1FF8
4863
4864
Unimplemented
3071 Bytes
$1EFE
$1EFF
$1F00
$1F01
$1FEF
$1FF0
$1FFF
7934
7935
7936
7937
Mask Option Registers
Bootloader ROM
and Vectors 239 Bytes
User Vectors EPROM
16 Bytes
Timer Vector (Low Byte)
$1FF9
8175
8176
IRQ Vector (High Byte)
$1FFA
IRQ Vector (Low Byte)
$1FFB
8191
SWI Vector (High Byte)
$1FFC
SWI Vector (Low Byte)
$1FFD
Reset Vector (High Byte)
$1FFE
Reset Vector (Low Byte)
$1FFF
*Writing zero to bit 0 of $1FF0 clears the COP watchdog timer. Reading $1FF0 returns user EPROM data
Figure 2-1. MC68HC705P6A User Mode Memory Map
2.4 Bootloader Mode Memory Map
Memory space is identical to the user mode. See Figure 2-1.
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Port A Data Register
$0000
Port B Data Register
$0001
Port C Data Register
$0002
Port D Data Register
$0003
Port A Data Direction Register
$0004
Port B Data Direction Register
$0005
Port C Data Direction Register
$0006
Port D Data Direction Register
$0007
Unimplemented
$0008
Unimplemented
$0009
SIOP Control Register
$000A
SIOP Status Register
$000B
SIOP Data Register
$000C
Reserved
$000D
Unimplemented
$000E
Unimplemented
$000F
Unimplemented
$0010
Unimplemented
$0011
Timer Control Register
$0012
Timer Status Register
$0013
Input Capture MSB
$0014
Input Capture LSB
$0015
Output Compare MSB
$0016
Output Compare LSB
$0017
Timer MSB
$0018
Timer LSB
$0019
Alternate Counter MSB
$001A
Alternate Counter LSB
$001B
EPROM Programming Register
$001C
A/D Converter Data Register
$001D
A/D Converter Control & Status Reg
$001E
Reserved
$001F
Figure 2-2. MC68HC705P6A I/O and Control Registers Memory Map
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Figure 2-2 and Figure 2-3 briefly describe the I/O and control registers
at locations $0000–$001F. Reading unimplemented bits will return
unknown states, and writing unimplemented bits will be ignored.
N O N - D I S C L O S U R E
2.5 Input/Output and Control Registers
R E Q U I R E D
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Input/Output and Control Registers
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A G R E E M E N T
R E Q U I R E D
Memory
Addr.
Name
R/W
Read:
$0000
Port A Data, PORTA
$0001
Port B Data, PORTB
$0002
Port C Data, PORTC
$0003
Port D Data, PORTD
$0004
Port A Data Direction,
DDRA
Read:
$0005
Port B Data Direction,
DDRB
Read:
$0006
Port C Data Direction,
DDRC
Read:
$0007
Port D Data Direction,
DDRD
Read:
$0008
Unimplemented
$0009
Unimplemented
$000A
SIOP Control Register,
SCR
Read:
$000B
SIOP Status Register,
SSR
Read:
$000C
SIOP Data Register,
SDR
Read:
$000D
Reserved for Test
$000E
Unimplemented
$000F
Unimplemented
Write:
Read:
Write:
Read:
Write:
Read:
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB7
PB6
PB5
0
0
0
0
0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PD7
0
1
0
0
0
0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
DDRB7
DDRB6
DDRB5
1
1
1
1
1
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
0
0
0
0
Write:
Write:
Write:
Write:
Write:
PD5
DDRD5
Read:
Write:
Read:
Write:
0
Write:
SPE
0
MSTR
SPIF
DCOL
0
0
0
0
0
0
SDR7
SDR6
SDR5
SDR4
SDR3
SSDR2
SDR1
SDR0
R
R
R
R
R
R
R
R
Write:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
= Unimplemented
R
= Reserved
Figure 2-3. I/O and Control Register Summary
General Release Specification
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R/W
Bit 7
6
5
4
3
2
1
Bit 0
ICIE
OCIE
TOIE
0
0
0
IEDG
OLVL
ICF
OCF
TOF
0
0
0
0
0
ICRH7
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
ICRL7
ICRL6
ICRL5
ICRL4
ICRL3
ICRL2
ICRL1
ICRL0
OCRH7
OCRH6
OCRH5
OCRH4
OCRH3
OCRH2
OCRH1
OCRH0
OCRL7
OCRL6
OCRL5
OCRL4
OCRL3
OCRL2
OCRL1
OCRL0
TMRH7
TMRH6
TMRH5
TMRH4
TMRH3
TMRH2
TMRH1
TMRH0
TMRL7
TMRL6
TMRL5
TMRL4
TMRL3
TMRL2
TMRL1
TMRL0
ACRH7
ACRH6
ACRH5
ACRH4
ACRH3
ACRH2
ACRH1
ACRH0
ACRL7
ACRL6
ACRL5
ACRL4
ACRL3
ACRL2
ACRL1
ACRL0
0
0
0
0
0
AD7
AD6
AD5
AD4
AD3
ADRC
ADON
0
0
R
R
R
R
Read:
$0010
Unimplemented
$0011
Unimplemented
$0012
Timer Control Register,
TCR
Read:
$0013
Timer Status Register,
TSR
Read:
$0014
Input Capture MSB,
ICRH
Read:
$0015
Input Capture LSB,
ICRL
Read:
$0016
Output Compare MSB,
OCRH
Read:
$0017
Output Compare LSB,
OCRL
Read:
$0018
Timer MSB, TRH
$0019
Timer LSB, TRL
$001A
Alternate Counter MSB,
ATRH
Read:
$001B
Alternate Counter LSB,
ATRL
Read:
$001C
EPROM Programming,
EPROG
Read:
$001D
A/D Conversion Data,
ADC
Read:
$001E
A/D Status and Control,
ADSC
Read:
$001F
Reserved for Test
Write:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Read:
Write:
Read:
Write:
Write:
Write:
Write:
ELAT
0
EPGM
AD2
AD1
AD0
CH2
CH1
CH0
R
R
R
Write:
CC
Write:
Read:
Write:
R
= Unimplemented
R
= Reserved
Figure 2-3. I/O and Control Register Summary (Continued)
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Name
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Addr.
R E Q U I R E D
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Input/Output and Control Registers
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A G R E E M E N T
R E Q U I R E D
Memory
2.6 RAM
The user RAM consists of 176 bytes (including the stack) at locations
$0050 through $00FF. The stack begins at address $00FF. The stack
pointer can access 64 bytes of RAM from $00FF to $00C0.
NOTE:
Using the stack area for data storage or temporary work locations
requires care to prevent it from being overwritten due to stacking from an
interrupt or subroutine call.
2.7 EPROM/ROM
There are 4608 bytes of user EPROM at locations $0100 through
$12FF, plus 48 bytes in user page zero locations $0020 through $004F,
and 16 additional bytes for user vectors at locations $1FF0 through
$1FFF. The bootloader ROM and vectors are at locations $1F01 through
$1FEF.
2.8 Mask Option Register (MOR) $1EFF–$1F00
The MOR is a pair of EPROM bytes located at $1EFF and $1F00. It
controls the programmable options on the MC68HC705P6A. See
Section 11. Mask Option Register (MOR) for additional information.
$1EFF
Bit 7
6
5
4
3
2
1
Bit 0
PA7PU
PA6PU
PA5PU
PA4PU
PA3PU
PA2PU
PA1PU
PA0PU
Erased
State:
0
0
0
0
0
0
0
0
$1F00
Bit 7
6
5
4
3
2
1
Bit 0
SWAIT
SPR1
SPR0
LSBF
LEVEL
COP
0
0
0
0
0
0
Read:
Write:
Read:
Write:
Erased
State:
SECURE
0
0
= Unimplemented
Figure 2-4. Mask Option Register
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2.9 COP Clear Register
The computer operating properly (COP) watchdog timer is located at
address $1FF0. Writing a logical zero to bit zero of this location will clear
the COP watchdog counter as described in 4.4.2 Computer Operating
Properly (COP) Reset.
$1FF0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
0
0
COPR
Reset:
Unimplemented
N O N - D I S C L O S U R E
Figure 2-5. COP Watchdog Timer Location
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Write:
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COP Clear Register
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General Release Specification
MC68HC705P6A — Rev. 1.0
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Section 3. Operating Modes
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.3
User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.4
Bootloader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.5
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.5.1
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.5.1.1
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.5.1.2
Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.5.2
WAIT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.6
COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . .37
3.2 Introduction
The MC68HC705P6A has two modes of operation that affect the pinout
and architecture of the MCU: user mode and bootloader mode. The user
mode is normally used for the application and the bootloader mode is
used for programming the EPROM. The conditions required to enter
each mode are shown in Table 3-1. The mode of operation is
determined by the voltages on the IRQ/VPP and PD7/TCAP pins on the
rising edge of the external RESET pin.
The mode of operation is also determined whenever the internal COP
watchdog timer resets the MCU. When the COP timer expires, the
voltage applied to the IRQ/VPP pin controls the mode of operation while
the voltage applied to PD7/TCAP is ignored. The voltage applied to
PD7/TCAP during the last rising edge on RESET is stored in a latch and
used to determine the mode of operation when the COP watchdog timer
resets the MCU.
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3.1 Contents
A G R E E M E N T
General Release Specification — MC68HC705P6A
R E Q U I R E D
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A G R E E M E N T
R E Q U I R E D
Operating Modes
Table 3-1. Operating Mode Conditions After Reset
RESET Pin
IRQ/VPP
PD7/TCAP
Mode
VSS to VDD
VSS to VDD
Single-Chip
VPP
VDD
Bootloader
3.3 User Mode
The user mode allows the MCU to function as a self-contained
microcontroller, with maximum use of the pins for on-chip peripheral
functions. All address and data activity occurs within the MCU and are
not available externally. User mode is entered on the rising edge of
RESET if the IRQ/VPP pin is within the normal operating voltage range.
The pinout for the user mode is shown in Figure 3-1.
RESET
1
28
VDD
IRQ/VPP
2
27
OSC1
PA7
3
26
OSC2
PA6
4
25
PD7/TCAP
PA5
5
24
TCMP
PA4
6
23
PD5
PA3
7
22
PC0
PA2
8
21
PC1
PA1
9
20
PC2
PA0
10
19
PC3/AD3
SDO/PB5
11
18
PC4/AD2
SDI/PB6
12
17
PC5/AD1
SCK/PB7
13
16
PC6/AD0
VSS
14
15
PC7/VREFH
Figure 3-1. User Mode Pinout
In the user mode, there is an 8-bit I/O port, a second 8-bit I/O port shared
with the A/D subsystem, one 3-bit I/O port shared with the SIOP, and a
3-bit port shared with the 16-bit timer subsystem, which includes one
general-purpose I/O pin.
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3.5 Low-Power Modes
The MC68HC705P6A is capable of running in a low-power mode in each
of its configurations. The WAIT and STOP instructions provide three
modes that reduce the power required for the MCU by stopping various
internal clocks and/or the on-chip oscillator. The SWAIT bit in the MOR
is used to modify the behavior of the STOP instruction from stop mode
to halt mode. The flow of the stop, halt, and wait modes is shown in
Figure 3-2.
3.5.1 STOP Instruction
The STOP instruction can result in one of two modes of operation
depending on the state of the SWAIT bit in the MOR. If the SWAIT bit is
clear, the STOP instruction will behave like a normal STOP instruction in
the M68HC05 Family and place the MCU in stop mode. If the SWAIT bit
in the MOR is set, the STOP instruction will behave like a WAIT
instruction (with the exception of a brief delay at startup) and place the
MCU in halt mode.
3.5.1.1 Stop Mode
Execution of the STOP instruction when the SWAIT bit in the MOR is
clear places the MCU in its lowest power consumption mode. In stop
mode, the internal oscillator is turned off, halting all internal processing,
including the COP watchdog timer. Execution of the STOP instruction
automatically clears the I bit in the condition code register so that the
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The bootloader mode provides a means to program the user EPROM
from an external memory device or host computer. This mode is entered
on the rising edge of RESET if VPP is applied to the IRQ/VPP pin and VDD
is applied to the PD7/TCAP pin. The user code in the external memory
device must have data located in the same address space it will occupy
in the internal MCU EPROM, including the mask option register (MOR)
at $1EFF and $1F00.
A G R E E M E N T
3.4 Bootloader Mode
R E Q U I R E D
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Bootloader Mode
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Operating Modes
IRQ external interrupt is enabled. All other registers and memory remain
unaltered. All input/output lines remain unchanged.
The MCU can be brought out of stop mode only by an IRQ external
interrupt or an externally generated RESET. When exiting stop mode,
the internal oscillator will resume after a 4064 internal clock cycle
oscillator stabilization delay.
NOTE:
Execution of the STOP instruction when the SWAIT bit in the MOR is
clear will cause the oscillator to stop, and, therefore, disable the COP
watchdog timer. To avoid turning off the COP watchdog timer, stop
mode should be changed to halt mode by setting the SWAIT bit in the
MOR. See 3.6 COP Watchdog Timer Considerations for additional
information.
3.5.1.2 Halt Mode
NOTE:
Halt mode is NOT designed for intentional use. Halt mode is only
provided to keep the COP watchdog timer active in the event a STOP
instruction is executed inadvertantly. This mode of operation is usually
achieved by invoking wait mode.
Execution of the STOP instruction when the SWAIT bit in the MOR is set
places the MCU in this low-power mode. Halt mode consumes the same
amount of power as wait mode (both halt and wait modes consume more
power than stop mode).
In halt mode, the internal clock is halted, suspending all processor and
internal bus activity. Internal timer clocks remain active, permitting
interrupts to be generated from the 16-bit timer or a reset to be
generated from the COP watchdog timer. Execution of the STOP
instruction automatically clears the I bit in the condition code register,
enabling the IRQ external interrupt. All other registers, memory, and
input/output lines remain in their previous states.
If the 16-bit timer interrupt is enabled, it will cause the processor to exit
the halt mode and resume normal operation. The halt mode also can be
exited when an IRQ external interrupt or external RESET occurs. When
exiting the halt mode, the internal clock will resume after a delay of one
to 4064 internal clock cycles. This varied delay time is the result of the
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The WAIT instruction places the MCU in a low-power mode which
consumes more power than stop mode. In wait mode, the internal clock
is halted, suspending all processor and internal bus activity. Internal
timer clocks remain active, permitting interrupts to be generated from the
16-bit timer and reset to be generated from the COP watchdog timer.
Execution of the WAIT instruction automatically clears the I bit in the
condition code register, enabling the IRQ external interrupt. All other
registers, memory, and input/output lines remain in their previous state.
If the 16-bit timer interrupt is enabled, it will cause the processor to exit
wait mode and resume normal operation. The 16-bit timer may be used
to generate a periodic exit from wait mode. Wait mode may also be
exited when an IRQ external interrupt or RESET occurs.
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3.5.2 WAIT Instruction
A G R E E M E N T
halt mode exit circuitry testing the oscillator stabilization delay timer (a
feature of the stop mode), which has been free-running (a feature of the
wait mode).
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Operating Modes
HALT
STOP
MOR
SWAIT
BIT SET?
WAIT
EXTERNAL OSCILLATOR ACTIVE
AND
INTERNAL TIMER CLOCK ACTIVE
Y
N
STOP EXTERNAL OSCILLATOR,
STOP INTERNAL TIMER CLOCK,
RESET STARTUP DELAY
Y
STOP INTERNAL
PROCESSOR CLOCK,
CLEAR I BIT IN CCR
STOP INTERNAL
PROCESSOR CLOCK,
CLEAR I BIT IN CCR
EXTERNAL OSCILLATOR ACTIVE
AND
INTERNAL TIMER CLOCK ACTIVE
EXTERNAL
RESET?
STOP INTERNAL
PROCESSOR CLOCK,
CLEAR I BIT IN CCR
N
EXTERNAL
RESET?
Y
Y
IRQ
EXTERNAL
INTERRUPT?
N
IRQ
EXTERNAL
INTERRUPT?
N
Y
N
N
Y
Y
TIMER
INTERNAL
INTERRUPT?
RESTART EXTERNAL OSCILLATOR,
START STABILIZATION DELAY
END
OF STABILIZATION
DELAY?
COP
INTERNAL
RESET?
Y
RESTART
INTERNAL PROCESSOR CLOCK
2.
IRQ
EXTERNAL
INTERRUPT?
N
Y
TIMER
INTERNAL
INTERRUPT?
N
N
N
1.
Y
N
Y
EXTERNAL
RESET?
Y
COP
INTERNAL
RESET?
N
FETCH RESET VECTOR
OR
SERVICE INTERRUPT
A. STACK
B. SET I BIT
C. VECTOR TO INTERRUPT ROUTINE
Figure 3-2. STOP/WAIT Flowcharts
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Furthermore, it is recommended that the COP watchdog timer be
disabled for applications that will use the wait mode for time periods that
will exceed the COP timeout period.
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The COP watchdog timer is active in user mode of operation when the
COP bit in the MOR is set. Executing the STOP instruction when the
SWAIT bit in the MOR is clear will cause the COP to be disabled.
Therefore, it is recommended that the STOP instruction be modified to
produce halt mode (set bit SWAIT in the MOR) if the COP watchdog
timer is required to function at all times.
A G R E E M E N T
3.6 COP Watchdog Timer Considerations
R E Q U I R E D
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COP Watchdog Timer Considerations
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4.1 Contents
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.3
External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.4
Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.4.1
Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.4.2
Computer Operating Properly (COP) Reset . . . . . . . . . . . .40
4.2 Introduction
The MCU can be reset from three sources: one external input and two
internal reset conditions. The RESET pin is a Schmitt trigger input as
shown in Figure 4-1. The CPU and all peripheral modules will be reset
by the RST signal which is the logical OR of internal reset functions and
is clocked by PH1.
RESET
VDD
OSC
DATA
ADDRESS
POWER-ON
RESET
(POR)
COP
WATCHDOG
(COPR)
D
RST
RES
DFF
TO CPU AND
PERIPHERALS
PH1
Figure 4-1. Reset Block Diagram
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Section 4. Resets
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Resets
4.3 External Reset (RESET)
The RESET input is the only external reset and is connected to an
internal Schmitt trigger. The external reset occurs whenever the RESET
input is driven below the lower threshold and remains in reset until the
RESET pin rises above the upper threshold. The upper and lower
thresholds are given in Section 14. Electrical Specifications.
4.4 Internal Resets
The two internally generated resets are the initial power-on reset (POR)
function and the COP watchdog timer function.
4.4.1 Power-On Reset (POR)
The internal POR is generated at power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and should
not be used to detect a drop in the power supply voltage. There is a 4064
internal clock cycle oscillator stabilization delay after the oscillator
becomes active.
The POR will generate the RST signal and reset the MCU. If any other
reset function is active at the end of this 4064 internal clock cycle delay,
the RST signal will remain active until the other reset condition(s) end.
4.4.2 Computer Operating Properly (COP) Reset
When the COP watchdog timer is enabled (COP bit in the MOR is set),
the internal COP reset is generated automatically by a timeout of the
COP watchdog timer. This timer is implemented with an 18-stage ripple
counter that provides a timeout period of 65.5 ms when a 4-MHz
oscillator is used. The COP watchdog counter is cleared by writing a
logical zero to bit zero at location $1FF0.
The COP watchdog timer can be disabled by clearing the COP bit in the
MOR or by applying 2 x VDD to the IRQ/VPP pin (for example, during
bootloader). When the IRQ/VPP pin is returned to its normal operating
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$1FF0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
0
0
Write:
COPR
= Unimplemented
Figure 4-2. Unused Vector and COP Watchdog Timer
When the COP watchdog timer expires, it will generate the RST signal
and reset the MCU. If any other reset function is active at the end of the
COP reset signal, the RST signal will remain in the reset condition until
the other reset condition(s) end. When the reset condition ends, the
MCU’s operating mode will be selected (see Table 3-1).
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The COP register is shared with the LSB of an unused vector address
as shown in Figure 4-2. Reading this location will return the
programmed value of the unused user interrupt vector, usually zero.
Writing to this location will clear the COP watchdog timer.
A G R E E M E N T
voltage range (between VSS–VDD), the COP watchdog timer’s output will
be restored if the COP bit in the MOR is set.
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Section 5. Interrupts
5.1 Contents
5.3
Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.3.1
Reset Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.3.2
Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.3.3
Hardware Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.3.3.1
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.3.3.2
Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .47
5.3.3.3
Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . .47
5.3.3.4
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .47
5.2 Introduction
A G R E E M E N T
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
The MCU can be interrupted six different ways:
1. Non-maskable software interrupt instruction (SWI)
2. External asynchronous interrupt (IRQ)
3. Input capture interrupt (TIMER)
4. Output compare interrupt (TIMER)
5. Timer overflow interrupt (TIMER)
6. Port A interrupt (if selected via mask option register)
Interrupts cause the processor to save the register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike
RESET, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is completed.
When the current instruction is completed, the processor checks all
pending hardware interrupts. If interrupts are not masked (I bit in the
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5.2
R E Q U I R E D
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A G R E E M E N T
R E Q U I R E D
Interrupts
condition code register is clear) and the corresponding interrupt enable
bit is set, the processor proceeds with interrupt processing. Otherwise,
the next instruction is fetched and executed. The SWI is executed the
same as any other instruction, regardless of the I-bit state.
When an interrupt is to be processed, the CPU puts the register contents
on the stack, sets the I bit in the CCR, and fetches the address of the
corresponding interrupt service routine from the vector table at locations
$1FF8 through $1FFF. If more than one interrupt is pending when the
interrupt vector is fetched, the interrupt with the highest vector location
shown in Table 5-1 will be serviced first.
Table 5-1. Vector Addresses for Interrupts and Reset
Register
Flag
Name
CPU
Interrupt
Vector
Address
N/A
N/A
Reset
RESET
$1FFE–$1FFF
N/A
N/A
Software
SWI
$1FFC–$1FFD
N/A
N/A
External Interrupt
IRQ
$1FFA-$1FFB
TSR
ICF
Timer Input Capture
TIMER
$1FF8–$1FF9
TSR
OCF
Timer Output Compare
TIMER
$1FF8–$1FF9
TSR
TOF
Timer Overflow
TIMER
$1FF8–$1FF9
Interrupts
An RTI instruction is used to signify when the interrupt software service
routine is completed. The RTI instruction causes the CPU state to be
recovered from the stack and normal processing to resume at the next
instruction that was to be executed when the interrupt took place.
Figure 5-1 shows the sequence of events that occurs during interrupt
processing.
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R E Q U I R E D
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Introduction
FROM RESET
IS I BIT
SET?
N
IRQ
INTERRUPT?
Y
CLEAR IRQ
REQUEST
LATCH
N
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TIMER
INTERRUPT?
Y
N
STACK
PC, X, A, CC
SET
I BIT IN CCR
LOAD PC FROM:
SWI: $1FFC, $1FFD
IRQ: $1FFA-$1FFB
TIMER: $1FF8-$1FF9
A G R E E M E N T
Y
SWI
INSTRUCTION?
Y
N
RTI
INSTRUCTION?
Y
RESTORE RESISTERS
FROM STACK
CC, A, X, PC
N
EXECUTE INSTRUCTION
Figure 5-1. Interrupt Processing Flowchart
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FETCH NEXT
INSTRUCTION
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R E Q U I R E D
Interrupts
5.3 Interrupt Types
The interrupts fall into three categories: reset, software, and hardware.
5.3.1 Reset Interrupt Sequence
The RESET function is not in the strictest sense an interrupt; however,
it is acted upon in a similar manner as shown in Figure 5-1. A low-level
input on the RESET pin or internally generated RST signal causes the
program to vector to its starting address which is specified by the
contents of memory locations $1FFE and $1FFF. The I bit in the
condition code register is also set. The MCU is configured to a known
state during this type of reset as previously described in Section 4.
Resets.
5.3.2 Software Interrupt (SWI)
The SWI is an executable instruction. It is also a non-maskable interrupt
since it is executed regardless of the state of the I bit in the CCR. As with
any instruction, interrupts pending during the previous instruction will be
serviced before the SWI opcode is fetched. The interrupt service routine
address for the SWI instruction is specified by the contents of memory
locations $1FFC and $1FFD.
5.3.3 Hardware Interrupts
All hardware interrupts are maskable by the I bit in the CCR. If the I bit
is set, all hardware interrupts (internal and external) are disabled.
Clearing the I bit enables the hardware interrupts. Four hardware
interrupts are explained in the following subsections.
5.3.3.1 External Interrupt (IRQ)
The IRQ/VPP pin drives an asynchronous interrupt to the CPU. An edge
detector flip-flop is latched on the falling edge of IRQ/VPP. If either the
output from the internal edge detector flip-flop or the level on the
IRQ/VPP pin is low, a request is synchronized to the CPU to generate the
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The internal interrupt latch is cleared nine internal clock cycles after the
interrupt is recognized (immediately after location $1FFA is read).
Therefore, another external interrupt pulse could be latched during the
IRQ service routine.
Another interrupt will be serviced if the IRQ pin is still in a low state when
the RTI in the service routine is executed.
5.3.3.2 Input Capture Interrupt
The input capture interrupt is generated by the 16-bit timer as described
in Section 8. Capture/Compare Timer. The input capture interrupt flag
is located in register TSR and its corresponding enable bit can be found
in register TCR. The I bit in the CCR must be clear for the input capture
interrupt to be enabled. The interrupt service routine address is specified
by the contents of memory locations $1FF8 and $1FF9.
5.3.3.3 Output Compare Interrupt
The output compare interrupt is generated by a 16-bit timer as described
in Section 8. Capture/Compare Timer. The output compare interrupt
flag is located in register TSR and its corresponding enable bit can be
found in register TCR. The I bit in the CCR must be clear for the output
compare interrupt to be enabled. The interrupt service routine address
is specified by the contents of memory locations $1FF8 and $1FF9.
5.3.3.4 Timer Overflow Interrupt
The timer overflow interrupt is generated by the 16-bit timer as described
in Section 8. Capture/Compare Timer. The timer overflow interrupt flag
is located in register TSR and its corresponding enable bit can be found
in register TCR. The I bit in the CCR must be clear for the timer overflow
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IRQ interrupt. If the LEVEL bit in the mask option register is clear (edgesensitive only), the output of the internal edge detector flip-flop is
sampled and the input level on the IRQ/VPP pin is ignored. The interrupt
service routine address is specified by the contents of memory locations
$1FFA and $1FFB. If the port A interrupts are enabled by the MOR, they
generate external interrupts identically to the IRQ/Vpp pin.
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interrupt to be enabled. This internal interrupt will vector to the interrupt
service routine located at the address specified by the contents of
memory locations $1FF8 and $1FF9.
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6.1 Contents
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
6.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
6.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
6.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6.7
I/O Port Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
6.2 Introduction
In the user mode, 20 bidirectional I/O lines are arranged as two 8-bit I/O
ports (ports A and C), one 3-bit I/O port (port B), and one 1-bit I/O port
(port D). These ports are programmable as either inputs or outputs
under software control of the data direction registers (DDRs). Port D also
contains one input-only pin.
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A G R E E M E N T
Section 6. Input/Output Ports
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R E Q U I R E D
Input/Output Ports
6.3 Port A
Port A is an 8-bit bidirectional port, which does not share any of its pins
with other subsystems (see Figure 6-1). The port A data register is
located at address $0000 and its data direction register (DDR) is located
at address $0004. The contents of the port A data register are
indeterminate at initial power up and must be initialized by user software.
Reset does not affect the data registers, but does clear the DDRs,
thereby setting all of the port pins to input mode. Writing a one to a DDR
bit sets the corresponding port pin to output mode. Port A has mask
option register enabled interrupt capability with an internal pullup device
NOTE:
The keyscan (pullup/interrupt) feature available on port A is NOT
available in the ROM device, MC68HC05P6.
VDD
PULLUP MASK
OPTION REGISTER
READ $0004
WRITE $0004
RESET
(RST)
WRITE $0000
DATA DIRECTION
REGISTER BIT
DATA
REGISTER BIT
OUTPUT
I/O
PIN
READ $0000
INTERNAL HC05
DATA BUS
TO IRQ
INTERRUPT SYSTEM
Figure 6-1. Port A I/O and Interrupt Circuitry
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Port B may be used for general I/O applications when the SIOP
subsystem is disabled. The SPE bit in register SPCR is used to
enable/disable the SIOP subsystem. When the SIOP subsystem is
enabled, port B registers are still accessible to software. Writing to either
of the port B registers while a data transfer is under way could corrupt
the data. See Section 7. Serial Input/Output Port for a discussion of
the SIOP subsystem.
READ $0005
WRITE $0005
RESET
(RST)
WRITE $0001
DATA DIRECTION
REGISTER BIT
DATA
REGISTER BIT
OUTPUT
I/O
PIN
READ $0001
INTERNAL HC05
DATA BUS
Figure 6-2. Port B I/O Circuitry
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Port B is a 3-bit bidirectional port which can share pins PB5–PB7 with
the SIOP communications subsystem. The port B data register is located
at address $0001 and its data direction register (DDR) is located at
address $0005. The contents of the port B data register are
indeterminate at initial powerup and must be initialized by user software.
Reset does not affect the data registers, but clears the DDRs, thereby
setting all of the port pins to input mode. Writing a one to a DDR bit sets
the corresponding port pin to output mode (see Figure 6-2).
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Input/Output Ports
6.5 Port C
Port C is an 8-bit bidirectional port which can share pins PC3–PC7 with
the A/D subsystem. The port C data register is located at address $0002
and its data direction register (DDR) is located at address $0006. The
contents of the port C data register are indeterminate at initial powerup
and must be initialized by user software. Reset does not affect the data
registers, but clears the DDRs, thereby setting all of the port pins to input
mode. Writing a one to a DDR bit sets the corresponding port pin to
output mode (see Figure 6-3).
Port C may be used for general I/O applications when the A/D
subsystem is disabled. The ADON bit in register ADSC is used to
enable/disable the A/D subsystem. Care must be exercised when using
pins PC0–PC2 while the A/D subsystem is enabled. Accidental changes
to bits that affect pins PC3–PC7 in the data or DDR registers will produce
unpredictable results in the A/D subsystem. See Section 9. Analog
Subsystem.
READ $0006
WRITE $0006
RESET
(RST)
WRITE $0002
DATA DIRECTION
REGISTER BIT
DATA
REGISTER BIT
OUTPUT
I/O
PIN
READ $0002
INTERNAL HC05
DATA BUS
Figure 6-3. Port C I/O Circuitry
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Port D may be used for general I/O applications regardless of the state
of the 16-bit timer. Since PD7 is an input-only line, its state can be read
from the port D data register at any time.
READ $0007
WRITE $0007
RESET
(RST)
DATA DIRECTION
REGISTER BIT
WRITE $0003
DATA
REGISTER BIT
OUTPUT
I/O
PIN
READ $0003
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Port D is a 2-bit port with one bidirectional pin (PD5) and one input-only
pin (PD7). Pin PD7 is shared with the 16-bit timer. The port D data
register is located at address $0003 and its data direction register (DDR)
is located at address $0007. The contents of the port D data register are
indeterminate at initial powerup and must be initialized by user software.
Reset does not affect the data registers, but clears the DDRs, thereby
setting PD5 to input mode. Writing a one to DDR bit 5 sets PD5 to output
mode (see Figure 6-4).
INTERNAL HC05
DATA BUS
Figure 6-4. Port D I/O Circuitry
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A G R E E M E N T
6.6 Port D
R E Q U I R E D
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A G R E E M E N T
R E Q U I R E D
Input/Output Ports
6.7 I/O Port Programming
Each pin on port A through port D (except pin 7 of port D) can be
programmed as an input or an output under software control as shown
in Table 6-1, Table 6-2, Table 6-3, and Table 6-4. The direction of a pin
is determined by the state of its corresponding bit in the associated port
data direction register (DDR). A pin is configured as an output if its
corresponding DDR bit is set to a logic one. A pin is configured as an
input if its corresponding DDR bit is cleared to a logic zero.
Table 6-1. Port A I/O Functions
DDRA
I/O Pin Mode
Accesses to
DDRA @ $0004
Accesses to Data
Register @ $0000
Read/Write
Read
Write
0
IN, Hi-Z
DDRA0–DDRA7
I/O Pin
See Note
1
OUT
DDRA0–DDRA7
PA0–PA7
PA0–PA7
NOTE: Does not affect input, but stored to data register
Table 6-2. Port B I/O Functions
DDRB
I/O Pin Mode
Accesses to
DDRB @ $0005
Accesses to Data
Register @ $0001
Read/Write
Read
Write
0
IN, Hi-Z
DDRB5–DDRB7
I/O Pin
See Note
1
OUT
DDRB5–DDRB7
PB5–PB7
PB5–PB7
NOTE: Does not affect input, but stored to data register
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I/O Pin Mode
Accesses to
DDRC @ $0006
Accesses to Data
Register @ $0002
Read/Write
Read
Write
0
IN, Hi-Z
DDRC0–DDRC7
I/O Pin
See Note
1
OUT
DDRC0–DDRC7
PC0–PC7
PC0–PC7
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NOTE: Does not affect input, but stored to data register
Table 6-4. Port D I/O Functions
DDRD
I/O Pin Mode
Accesses to
DDRD @ $0007
Accesses to Data
Register @ $0003
Read/Write
Read
Write
0
IN, Hi-Z
DDRD5
I/O Pin
See Note 1
1
OUT
DDRD5
PD5
PD5
NOTES:
1. Does not affect input, but stored to data register
2. PD7 is input only
NOTE:
To avoid generating a glitch on an I/O port pin, data should be written to
the I/O port data register before writing a logic one to the corresponding
data direction register.
At power-on or reset, all DDRs are cleared, which configures all port pins
as inputs. The DDRs are capable of being written to or read by the
processor. During the programmed output state, a read of the data
register will actually read the value of the output data latch and not the
level on the I/O port pin.
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A G R E E M E N T
DDRC
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Table 6-3. Port C I/O Functions
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Section 7. Serial Input/Output Port
7.1 Contents
7.3
SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
7.3.1
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
7.3.2
Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
7.3.3
Serial Data Output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . .60
7.4
SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
7.4.1
SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . .61
7.4.2
SIOP Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . .62
7.4.3
SIOP Data Register (SDR) . . . . . . . . . . . . . . . . . . . . . . . . .63
A G R E E M E N T
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
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7.2
R E Q U I R E D
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7.2 Introduction
The simple synchronous serial I/O port (SIOP) subsystem is designed to
provide efficient serial communications between peripheral devices or
other MCUs. The SIOP is implemented as a 3-wire master/slave system
with serial clock (SCK), serial data input (SDI), and serial data output
(SDO). A block diagram of the SIOP is shown in Figure 7-1. A mask
programmable option determines whether the SIOP is MSB or LSB first.
The SIOP subsystem shares its input/output pins with port B. When the
SIOP is enabled (SPE bit set in register SCR), port B DDR and data
registers are modified by the SIOP. Although port B DDR and data
registers can be altered by application software, these actions could
affect the transmitted or received data.
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Serial Input/Output Port
HCO5 INTERNAL BUS
SPE
76 54 3210
76543210
BAUD
CONTROL
STATUS
RATE
8-BIT
SDO
SHIFT
REGISTER
$0A
76543210
GENERATOR
REGISTER
$0B
REGISTER
$0C
SDO/PB5
I/O
CONTROL
SDI
LOGIC
SCK
SDI/PB6
SCK/PB7
INTERNAL
CPU CLOCK
Figure 7-1. SIOP Block Diagram
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7.3.1 Serial Clock (SCK)
The state of the SCK output normally remains a logic one during idle
periods between data transfers. The first falling edge of SCK signals the
beginning of a data transfer. At this time, the first bit of received data may
be presented at the SDI pin and the first bit of transmitted data is
presented at the SDO pin (see Figure 7-2). Data is captured at the SDI
pin on the rising edge of SCK. The transfer is terminated upon the eighth
rising edge of SCK.
The master and slave modes of operation differ only by the sourcing of
SCK. In master mode, SCK is driven from an internal source within the
MCU. In slave mode, SCK is driven from a source external to the MCU.
The SCK frequency is dependent upon the SPR0 and SPR1 bits located
in the mask option register. Refer to 11.3 Mask Option Register (MOR)
$1EFF–$1F00 for a description of available SCK frequencies.
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 6
BIT 7
SDO
SCK
100 ns
100 ns
SDI
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
Figure 7-2. SIOP Timing Diagram
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A G R E E M E N T
The SIOP subsystem is software configurable for master or slave
operation. No external mode selection inputs are available (for instance,
slave select pin).
N O N - D I S C L O S U R E
7.3 SIOP Signal Format
R E Q U I R E D
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SIOP Signal Format
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R E Q U I R E D
Serial Input/Output Port
7.3.2 Serial Data Input (SDI)
The SDI pin becomes an input as soon as the SIOP subsystem is
enabled. New data may be presented to the SDI pin on the falling edge
of SCK.However, valid data must be present at least 100 nanoseconds
before the rising edge of SCK and remain valid for 100 nanoseconds
after the rising edge of SCK. See Figure 7-2.
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A G R E E M E N T
7.3.3 Serial Data Output (SDO)
The SDO pin becomes an output as soon as the SIOP subsystem is
enabled. Prior to enabling the SIOP, PB5 can be initialized to determine
the beginning state. While the SIOP is enabled, PB5 cannot be used as
a standard output since that pin is connected to the last stage of the
SIOP serial shift register. Mask option register bit LSBF permits data to
be transmitted in either the MSB first format or the LSB first format. Refer
to 11.3 Mask Option Register (MOR) $1EFF–$1F00 for MOR LSBF
programming information.
On the first falling edge of SCK, the first data bit will be shifted out to the
SDO pin. The remaining data bits will be shifted out to the SDO pin on
subsequent falling edges of SCK. The SDO pin will present valid data at
least 100 nanoseconds before the rising edge of the SCK and remain
valid for 100 nanoseconds after the rising edge of SCK. See Figure 7-2.
7.4 SIOP Registers
The SIOP is programmed and controlled by the SIOP control register
(SCR) located at address $000A, the SIOP status register (SSR) located
at address $000B, and the SIOP data register (SDR) located at address
$000C.
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$000A
Bit 7
Read:
0
6
5
4
0
SPE
3
2
1
Bit 0
0
0
0
0
0
0
0
0
MSTR
Freescale Semiconductor, Inc...
Write:
Reset:
0
0
0
0
= Unimplemented
Figure 7-3. SIOP Control Register (SCR)
SPE — Serial Peripheral Enable
When set, the SPE bit enables the SIOP subsystem such that
SDO/PB5 is the serial data output, SDI/PB6 is the serial data input,
and SCK/PB7 is a serial clock input in the slave mode or a serial clock
output in the master mode. Port B DDR and data registers can be
manipulated as usual (except for PB5); however, these actions could
affect the transmitted or received data.
The SPE bit is readable at any time. However, writing to the SIOP
control register while a transmission is in progress will cause the SPIF
and DCOL bits in the SIOP status register (see below) to operate
incorrectly. Therefore, the SIOP control register should be written
once to enable the SIOP and then not written to until the SIOP is to
be disabled. Clearing the SPE bit while a transmission is in progress
will 1) abort the transmission, 2) reset the serial bit counter, and 3)
convert the port B/SIOP port to a general-purpose I/O port. Reset
clears the SPE bit.
MSTR — Master Mode Select
When set, the MSTR bit configures the serial I/O port for master
mode. A transfer is initiated by writing to the SDR. Also, the SCK pin
becomes an output providing a synchronous data clock dependent
upon the oscillator frequency. When the device is in slave mode, the
SDO and SDI pins do not change function. These pins behave exactly
the same in both the master and slave modes.
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This register is located at address $000A and contains two bits.
Figure 7-3 shows the position of each bit in the register and indicates
the value of each bit after reset.
N O N - D I S C L O S U R E
7.4.1 SIOP Control Register (SCR)
R E Q U I R E D
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SIOP Registers
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A G R E E M E N T
R E Q U I R E D
Serial Input/Output Port
The MSTR bit is readable and writeable at any time regardless of the
state of the SPE bit. Clearing the MSTR bit will abort any transfers that
may have been in progress. Reset clears the MSTR bit as well as the
SPE bit, disabling the SIOP subsystem.
7.4.2 SIOP Status Register (SSR)
This register is located at address $000B and contains two bits.
Figure 7-4 shows the position of each bit in the register and indicates
the value of each bit after reset.
$000B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SPIF
DCOL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 7-4. SIOP Status Register (SSR)
SPIF — Serial Port Interface Flag
SPIF is a read-only status bit that is set on the last rising edge of SCK
and indicates that a data transfer has been completed. It has no effect
on any future data transfers and can be ignored. The SPIF bit is
cleared by reading the SSR followed by a read or write of the SDR. If
the SPIF is cleared before the last rising edge of SCK, it will be set
again on the last rising edge of SCK. Reset clears the SPIF bit.
DCOL — Data Collision
DCOL is a read-only status bit which indicates that an illegal access
of the SDR has occurred. The DCOL bit will be set when reading or
writing the SDR after the first falling edge of SCK and before SPIF is
set. Reading or writing the SDR during this time will result in invalid
data being transmitted or received.
The DCOL bit is cleared by reading the SSR (when the SPIF bit is set)
followed by a read or write of the SDR. If the last part of the clearing
sequence is done after another transfer has started, the DCOL bit will
be set again. Reset clears the DCOL bit.
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$000C
Bit 7
6
5
4
3
2
1
Bit 0
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
Read:
Write:
Reset:
Unaffected by reset
Figure 7-5. Serial Port Data Register (SDR)
A G R E E M E N T
This register is located at address $000C and serves as both the
transmit and receive data register. Writing to this register will initiate a
message transmission if the SIOP is in master mode. The SIOP
subsystem is not double buffered and any write to this register will
destroy the previous contents. The SDR can be read at any time;
however, if a transfer is in progress, the results may be ambiguous and
the DCOL bit will be set. Writing to the SDR while a transfer is in
progress can cause invalid data to be transmitted and/or received.
Figure 7-5 shows the position of each bit in the register. This register is
not affected by reset.
N O N - D I S C L O S U R E
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7.4.3 SIOP Data Register (SDR)
R E Q U I R E D
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A G R E E M E N T
R E Q U I R E D
Serial Input/Output Port
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General Release Specification — MC68HC705P6A
Section 8. Capture/Compare Timer
8.1 Contents
8.3
Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
8.3.1
Input Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
8.3.2
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
8.4
Timer I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
8.4.1
Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . .68
8.4.2
Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . .70
8.4.3
Timer Registers (TRH and TRL) . . . . . . . . . . . . . . . . . . . . .71
8.4.4
Alternate Timer Registers (ATRH and ATRL) . . . . . . . . . . .72
8.4.5
Input Capture Registers (ICRH and ICRL) . . . . . . . . . . . . .73
8.4.6
Output Compare Registers (OCRH and OCRL) . . . . . . . . .74
8.5
Timer During Wait/Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . .75
8.6
Timer During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
8.2 Introduction
This section describes the operation of the 16-bit capture/compare timer.
Figure 8-1 shows the structure of the capture/compare subsystem.
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A G R E E M E N T
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
N O N - D I S C L O S U R E
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8.2
R E Q U I R E D
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R E Q U I R E D
Capture/Compare Timer
INTERNAL BUS
HIGH LOW
BYTE BYTE
$16
$17
INTERNAL
PROCESSOR
CLOCK
OUTPUT
COMPARE
REGISTER
8-BIT
BUFFER
÷4
HIGH
BYTE
16-BIT FREE
RUNNING
COUNTER
LOW
BYTE
HIGH LOW
BYTE BYTE
$18
$19
INPUT
$14
CAPTURE $15
REGISTER
N O N - D I S C L O S U R E
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A G R E E M E N T
COUNTER $1A
ALTERNATE $1B
REGISTER
OUTPUT
COMPARE
CIRCUIT
OVERFLOW
DETECT
CIRCUIT
EDGE
DETECT
CIRCUIT
OUTPUT
LEVEL
REG.
TIMER
STATUS ICF OCF TOF $13
REG.
D Q
CLK
C
TIMER
RESET
ICIE OCIE TOIE IEDG OLVL CONTROL
REG.
$12
INTERRUPT CIRCUIT
OUTPUT
LEVEL
(TCMP)
EDGE
INPUT
(TCAP)
Figure 8-1. Capture/Compare Timer Block Diagram
8.3 Timer Operation
The core of the capture/compare timer is a 16-bit free-running counter.
The counter provides the timing reference for the input capture and
output compare functions. The input capture and output compare
functions provide a means to latch the times at which external events
occur, to measure input waveforms, and to generate output waveforms
and timing delays. Software can read the value in the 16-bit free-running
counter at any time without affecting the counter sequence.
Because of the 16-bit timer architecture, the I/O registers for the input
capture and output compare functions are pairs of 8-bit registers.
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The input capture function is a means to record the time at which an
external event occurs. When the input capture circuitry detects an active
edge on the TCAP pin, it latches the contents of the timer registers into
the input capture registers. The polarity of the active edge is
programmable.
Latching values into the input capture registers at successive edges of
the same polarity measures the period of the input signal on the TCAP
pin. Latching values into the input capture registers at successive edges
of opposite polarity measures the pulse width of the signal.
8.3.2 Output Compare
The output compare function is a means of generating an output signal
when the 16-bit counter reaches a selected value. Software writes the
selected value into the output compare registers. On every fourth
internal clock cycle the output compare circuitry compares the value of
the counter to the value written in the output compare registers. When a
match occurs, the timer transfers the programmable output level bit
(OLVL) from the timer control register to the TCMP pin.
The programmer can use the output compare register to measure time
periods, to generate timing delays, or to generate a pulse of specific
duration or a pulse train of specific frequency and duty cycle on the
TCMP pin.
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8.3.1 Input Capture
N O N - D I S C L O S U R E
Because the counter is 16 bits long and preceded by a fixed divide-by-4
prescaler, the counter rolls over every 262,144 internal clock cycles.
Timer resolution with a 4-MHz crystal is 2 µs.
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A G R E E M E N T
R E Q U I R E D
Capture/Compare Timer
8.4 Timer I/O Registers
The following I/O registers control and monitor timer operation:
•
Timer control register (TCR)
•
Timer status register (TSR)
•
Timer registers (TRH and TRL)
•
Alternate timer registers (ATRH and ATRL)
•
Input capture registers (ICRH and ICRL)
•
Output compare registers (OCRH and OCRL)
8.4.1 Timer Control Register (TCR)
The timer control register, shown in Figure 8-2, performs these
functions:
•
Enables input capture interrupts
•
Enables output compare interrupts
•
Enables timer overflow interrupts
•
Controls the active edge polarity of the TCAP signal
•
Controls the active level of the TCMP output
$0012
Bit 7
6
5
ICIE
OCIE
TOIE
0
0
0
Read:
4
3
2
0
0
0
1
Bit 0
IEDG
OLVL
U
0
Write:
Reset:
= Unimplemented
0
0
0
U = Undetermined
Figure 8-2. Timer Control Register (TCR)
ICIE — Input Capture Interrupt Enable
This read/write bit enables interrupts caused by an active signal on
the TCAP pin. Resets clear the ICIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
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TOIE — Timer Overflow Interrupt Enable
This read/write bit enables interrupts caused by a timer overflow.
Reset clear the TOIE bit.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
IEDG — Input Edge
The state of this read/write bit determines whether a positive or
negative transition on the TCAP pin triggers a transfer of the contents
of the timer register to the input capture register. Resets have no
effect on the IEDG bit.
1 = Positive edge (low to high transition) triggers input capture
0 = Negative edge (high to low transition) triggers input capture
OLVL — Output Level
The state of this read/write bit determines whether a logic one or logic
zero appears on the TCMP pin when a successful output compare
occurs. Resets clear the OLVL bit.
1 = TCMP goes high on output compare
0 = TCMP goes low on output compare
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A G R E E M E N T
This read/write bit enables interrupts caused by an active signal on
the TCMP pin. Resets clear the OCIE bit.
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
N O N - D I S C L O S U R E
OCIE — Output Compare Interrupt Enable
R E Q U I R E D
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Timer I/O Registers
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R E Q U I R E D
Capture/Compare Timer
8.4.2 Timer Status Register (TSR)
The timer status register, shown in Figure 8-3, contains flags to signal
the following conditions:
•
An active signal on the TCAP pin, transferring the contents of the
timer registers to the input capture registers
•
A match between the 16-bit counter and the output compare
registers, transferring the OLVL bit to the TCMP pin
•
A timer roll over from $FFFF to $0000
$0013
Bit 7
6
5
4
3
2
1
Bit 0
Read:
ICF
OCF
TOF
0
0
0
0
0
Reset:
U
U
U
0
0
0
0
0
U = Undetermined
Figure 8-3. Timer Status Register (TSR)
ICF — Input Capture Flag
The ICF bit is set automatically when an edge of the selected polarity
occurs on the TCAP pin. Clear the ICF bit by reading the timer status
register with ICF set and then reading the low byte ($0015) of the
input capture registers. Resets have no effect on ICF.
OCF — Output Compare Flag
The OCF bit is set automatically when the value of the timer registers
matches the contents of the output compare registers. Clear the OCF
bit by reading the timer status register with OCF set and then reading
the low byte ($0017) of the output compare registers. Resets have no
effect on OCF.
TOF — Timer Overflow Flag
The TOF bit is set automatically when the 16-bit counter rolls over
from $FFFF to $0000. Clear the TOF bit by reading the timer status
register with TOF set, and then reading the low byte ($0019) of the
timer registers. Resets have no effect on TOF.
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TRH
$0018
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
Reset:
1
1
1
1
1
1
1
1
TRL
$0019
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
1
1
1
1
1
1
0
0
Write
Write:
Reset:
= Unimplemented
Figure 8-4. Timer Registers (TRH and TRL)
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The timer registers, shown in Figure 8-4, contains the current high and
low bytes of the 16-bit counter. Reading TRH before reading TRL
causes TRL to be latched until TRL is read. Reading TRL after reading
the timer status register clears the timer overflow flag (TOF). Writing to
the timer registers has no effect.
N O N - D I S C L O S U R E
8.4.3 Timer Registers (TRH and TRL)
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8.4.4 Alternate Timer Registers (ATRH and ATRL)
The alternate timer registers, shown in Figure 8-5, contain the current
high and low bytes of the 16-bit counter. Reading ATRH before reading
ATRL causes ATRL to be latched until ATRL is read. Reading ATRL has
no effect on the timer overflow flag (TOF). Writing to the alternate timer
registers has no effect.
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R E Q U I R E D
Capture/Compare Timer
ATRH
$001A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
Reset:
1
1
1
1
1
1
1
1
ATRL
$001B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
1
1
1
1
1
1
0
0
Write:
Write:
Reset:
= Unimplemented
Figure 8-5. Alternate Timer Registers (ATRH and ATRL)
NOTE:
To prevent interrupts from occurring between readings of ATRH and
ATRL, set the interrupt flag in the condition code register before reading
ATRH, and clear the flag after reading ATRL.
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ICRH
$0014
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
ICRL
$0015
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
Write:
Write:
RESET DOES NOT AFFECT THE INPUT CAPTURE REGISTERS
= Unimplemented
Figure 8-6. Input Capture Registers (ICRH and ICRL)
NOTE:
To prevent interrupts from occurring between readings of ICRH and
ICRL, set the interrupt flag in the condition code register before reading
ICRH, and clear the flag after reading ICRL.
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When a selected edge occurs on the TCAP pin, the current high and low
bytes of the 16-bit counter are latched into the input capture registers.
Reading ICRH before reading ICRL inhibits further capture until ICRL is
read. Reading ICRL after reading the status register clears the input
capture flag (ICF). Writing to the input capture registers has no effect.
A G R E E M E N T
8.4.5 Input Capture Registers (ICRH and ICRL)
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R E Q U I R E D
Capture/Compare Timer
8.4.6 Output Compare Registers (OCRH and OCRL)
When the value of the 16-bit counter matches the value in the output
compare registers, the planned TCMP pin action takes place. Writing to
OCRH before writing to OCRL inhibits timer compares until OCRL is
written. Reading or writing to OCRL after the timer status register clears
the output compare flag (OCF).
N O N - D I S C L O S U R E
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A G R E E M E N T
OCRH
$0016
Bit 7
6
5
4
3
2
1
Bit 0
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
Write:
Read:
Unaffected by Reset
OCRL
$0017
Bit 7
6
5
4
3
2
1
Bit 0
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
Write:
Read:
Unaffected by Reset
Figure 8-7. Output Compare Registers (OCRH and OCRL)
To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use this procedure:
7. Disable interrupts by setting the I bit in the condition code register.
8. Write to OCRH. Compares are now inhibited until OCRL is written.
9. Clear bit OCF by reading timer status register (TSR).
10. Enable the output compare function by writing to OCRL.
11. Enable interrupts by clearing the I bit in the condition code
register.
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The CPU clock halts during the wait (or halt) mode, but the timer remains
active. If interrupts are enabled, a timer interrupt will cause the processor
to exit the wait mode.
In the stop mode, the timer stops counting and holds the last count value
if STOP is exited by an interrupt. If STOP is exited by RESET, the
counters are forced to $FFFC. During STOP, if at least one valid input
capture edge occurs at the TCAP pins, the input capture detect circuit is
armed. This does not set any timer flags or wake up the MCU, but if an
interrupt is used to exit stop mode, there is an active input capture flag
and data from the first valid edge that occurred during the stop mode. If
RESET is used to exit stop mode, then no input capture flag or data
remains, even if a valid input capture edge occurred.
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8.6 Timer During Stop Mode
A G R E E M E N T
8.5 Timer During Wait/Halt Mode
R E Q U I R E D
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Timer During Wait/Halt Mode
MC68HC705P6A — Rev. 1.0
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Capture/Compare Timer
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A G R E E M E N T
R E Q U I R E D
Capture/Compare Timer
General Release Specification
MC68HC705P6A — Rev. 1.0
Capture/Compare Timer
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General Release Specification — MC68HC705P6A
Section 9. Analog Subsystem
9.1 Contents
9.3
Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
9.3.1
Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
9.3.2
Reference Voltage (VREFH) . . . . . . . . . . . . . . . . . . . . . . . . .78
9.3.3
Accuracy and Precision. . . . . . . . . . . . . . . . . . . . . . . . . . . .78
9.4
Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
9.5
Digital Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.5.1
Conversion Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.5.2
Internal versus External Oscillator. . . . . . . . . . . . . . . . . . . .79
9.5.3
Multi-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.6
A/D Status and Control Register (ADSC) . . . . . . . . . . . . . . . . .80
9.7
A/D Conversion Data Register (ADC). . . . . . . . . . . . . . . . . . . .82
9.8
A/D Subsystem Operation during Halt/Wait Modes . . . . . . . . .82
9.9
A/D Subsystem Operation during Stop Mode. . . . . . . . . . . . . .82
9.2 Introduction
The MC68HC705P6A includes a 4-channel, multiplexed input, 8-bit,
successive approximation A/D converter. The A/D subsystem shares its
inputs with port C pins PC3–PC7.
MC68HC705P6A — Rev. 1.0
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Analog Subsystem
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A G R E E M E N T
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
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9.2
R E Q U I R E D
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A G R E E M E N T
R E Q U I R E D
Analog Subsystem
9.3 Analog Section
The following paragraphs describe the operation and performance of
analog modules within the analog subsystem.
9.3.1 Ratiometric Conversion
The A/D converter is ratiometric, with pin VREFH supplying the high
reference voltage. Applying an input voltage equal to VREFH produces a
conversion result of $FF (full scale). Applying an input voltage equal to
VSS produces a conversion result of $00. An input voltage greater than
VREFH will convert to $FF with no overflow indication. For ratiometric
conversions, VREFH should be at the same potential as the supply
voltage being used by the analog signal being measured and referenced
to VSS.
9.3.2 Reference Voltage (VREFH)
The reference supply for the A/D converter shares pin PC7 with port C.
The low reference is tied to the VSS pin internally. VREFH can be any
voltage between VSS and VDD; however, the accuracy of conversions is
tested and guaranteed only for VREFH = VDD.
9.3.3 Accuracy and Precision
The 8-bit conversion result is accurate to within ±1 1/2 LSB, including
quantization; however, the accuracy of conversions is tested and
guaranteed only with external oscillator operation.
9.4 Conversion Process
The A/D reference inputs are applied to a precision digital-to-analog
converter. Control logic drives the D/A and the analog output is
successively compared to the selected analog input which was sampled
at the beginning of the conversion cycle. The conversion process is
monotonic and has no missing codes.
General Release Specification
MC68HC705P6A — Rev. 1.0
Analog Subsystem
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The following paragraphs describe the operation and performance of
digital modules within the analog subsystem.
9.5.1 Conversion Times
9.5.2 Internal versus External Oscillator
If the internal clock is 1 MHz or greater (i.e., external oscillator 2 MHz or
greater), the internal RC oscillator must be turned off and the external
oscillator used as the conversion clock.
If the MCU internal clock frequency is less than 1 MHz (2 MHz external
oscillator), the internal RC oscillator (approximately 1.5 MHz) must be
used for the A/D converter clock. The internal RC clock is selected by
setting the ADRC bit in the ADSC register.
When the internal RC oscillator is being used, these limitations apply:
1. Since the internal RC oscillator is running asynchronously with
respect to the internal clock, the conversion complete bit (CC) in
register ADSC must be used to determine when a conversion
sequence has been completed.
2. Electrical noise will slightly degrade the accuracy of the A/D
converter. The A/D converter is synchronized to read voltages
during the quiet period of the clock driving it. Since the internal and
external clocks are not synchronized, the A/D converter will
occasionally measure an input when the external clock is making
a transition.
9.5.3 Multi-Channel Operation
An input multiplexer allows the A/D converter to select from one of four
external analog signals. Port C pins PC3 through PC6 are shared with
the inputs to the multiplexer.
MC68HC705P6A — Rev. 1.0
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Analog Subsystem
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Each input conversion requires 32 internal clock cycles, which must be
at a frequency equal to or greater than 1 MHz.
A G R E E M E N T
9.5 Digital Section
R E Q U I R E D
General Release Specification
Digital Section
Freescale Semiconductor, Inc.
R E Q U I R E D
Analog Subsystem
9.6 A/D Status and Control Register (ADSC)
The ADSC register reports the completion of A/D conversion and
provides control over oscillator selection, analog subsystem power, and
input channel selection. See Figure 9-1.
$001E
Bit 7
Read:
CC
6
5
ADRC
ADON
0
0
4
3
0
0
2
1
Bit 0
CH2
CH1
CH0
0
0
0
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A G R E E M E N T
Write:
Reset:
0
0
0
= Unimplemented
Figure 9-1. A/D Status and Control Register (ADSC)
CC — Conversion Complete
This read-only status bit is set when a conversion sequence has
completed and data is ready to be read from the ADC register. CC is
cleared when the ADSC is written to or when data is read from the
ADC register. Once a conversion has been started, conversions of
the selected channel will continue every 32 internal clock cycles until
the ADSC register is written to again. During continuous conversion
operation, the ADC register will be updated with new data, and the CC
bit set every 32 internal clock cycles. Also, data from the previous
conversion will be overwritten regardless of the state of the CC bit.
ADRC — RC Oscillator Control
When ADRC is set, the A/D subsystem operates from the internal RC
oscillator instead of the internal clock. The RC oscillator requires a
time, tRCON, to stabilize before accurate conversion results can be
obtained. See 9.3.2 Reference Voltage (VREFH) for more
information.
ADON — A/D Subsystem On
When the A/D subsystem is turned on (ADON = 1), it requires a time,
tADON, to stabilize before accurate conversion results can be attained.
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MC68HC705P6A — Rev. 1.0
Analog Subsystem
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If the ADON bit is set and an input from channels 0–4 is selected, the
corresponding port C pin’s DDR bit will be cleared (making that port
C pin an input). If the port C data register is read while the A/D is on
and one of the shared input channels is selected using bit CH0–CH2,
the corresponding port C pin will read as a logic zero. The remaining
port C pins will read normally. To digitally read a port C pin, the A/D
subsystem must be disabled (ADON = 0), or input channels 5–7 must
be selected.
Table 9-1. A/D Multiplexer Input
Channel Assignments
Channel
Signal
0
AD0 — Port C, Bit 6
1
AD1 — Port C, Bit 5
2
AD2 — Port C, Bit 4
3
AD3 — Port C, Bit 3
4
VREFH — Port C, Bit 7
5
(VREFH + VSS)/2
6
VSS
7
Reserved for Factory Test
MC68HC705P6A — Rev. 1.0
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Analog Subsystem
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A G R E E M E N T
CH2, CH1, and CH0 form a 3-bit field which is used to select an input
to the A/D converter. Channels 0–3 correspond to port C input pins
PC6–PC3. Channels 4–6 are used for reference measurements.
Channel 7 is reserved. If a conversion is attempted with channel 7
selected, the result will be $00. Table 9-1 lists the inputs selected by
bits CH0-CH3.
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CH2–CH0 — Channel Select Bits
R E Q U I R E D
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A/D Status and Control Register (ADSC)
Freescale Semiconductor, Inc.
R E Q U I R E D
Analog Subsystem
9.7 A/D Conversion Data Register (ADC)
This register contains the output of the A/D converter. See Figure 9-2.
$001D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:
Unaffected by reset
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A G R E E M E N T
= Unimplemented
Figure 9-2. A/D Conversion Value Data Register (ADC)
9.8 A/D Subsystem Operation during Halt/Wait Modes
The A/D subsystem continues normal operation during wait and halt
modes. To decrease power consumption during wait or halt mode, the
ADON and ADRC bits in the A/D status and control register should be
cleared if the A/D subsystem is not being used.
9.9 A/D Subsystem Operation during Stop Mode
When stop mode is enabled, execution of the STOP instruction will
terminate all A/D subsystem functions. Any pending conversion is
aborted. When the oscillator resumes operation upon leaving stop
mode, a finite amount of time passes before the A/D subsystem
stabilizes sufficiently to provide conversions at its rated accuracy. The
delays built into the MC68HC705P6A when coming out of stop mode are
sufficient for this purpose. No explicit delays need to be added to the
application software.
General Release Specification
MC68HC705P6A — Rev. 1.0
Analog Subsystem
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Section 10. EPROM
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
10.3
EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
10.4
EPROM Programming Sequence. . . . . . . . . . . . . . . . . . . . . . .84
10.5
EPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
10.6
EPROM Programming Register (EPROG) . . . . . . . . . . . . . . . .84
10.7
EPROM Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
10.8
Programming from an External Memory Device. . . . . . . . . . . .87
10.2 Introduction
The user EPROM consists of 48 bytes of user page zero EPROM from
$0020 to $004F, 4608 bytes of user EPROM from $0100 to $12FF, the
two MOR reset values located at $1EFF and $1F00, and 16 bytes of
user vectors EPROM from $1FF0 to $1FFF. The bootloader ROM and
vectors are located from $1F01 to $1FEF.
MC68HC705P6A — Rev. 1.0
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EPROM
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10.1 Contents
A G R E E M E N T
General Release Specification — MC68HC705P6A
R E Q U I R E D
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A G R E E M E N T
R E Q U I R E D
EPROM
10.3 EPROM Erasing
NOTE:
Only parts packaged in a windowed package may be erased. Others are
one-tme programmable and may not be erased by UV exposure.
The MC68HC705P6A can be erased by exposure to a high-intensity
ultraviolet (UV) light with a wavelength of 2537 angstroms. The
recommended dose (UV intensity multiplied by exposure time) is 15
Ws/cm2. UV lamps without shortwave filters should be used, and the
EPROM device should be positioned about one inch from the UV lamp.
An erased EPROM byte will read as $00.
10.4 EPROM Programming Sequence
The bootloader software goes through a complete write cycle of the
EPROM including the MOR. This is followed by a verify cycle which
continually branches in a loop if an error is found. A sample routine to
program a byte of EPROM is shown in Table 10-1.
NOTE:
To avoid damage to the MCU, VDD must be applied to the MCU before
VPP.
10.5 EPROM Registers
Three registers are associated with the EPROM: the EPROM
programming register (EPROG) and the two mask option registers
(MOR). The EPROG register controls the actual programming of the
EPROM bytes and the MOR. The MOR registers control the six mask
options found on the ROM version of this MCU (MC68HC05P6), the
EPROM security feature, and eight additional port A interrupt options.
10.6 EPROM Programming Register (EPROG)
This register is used to program the EPROM array. Only the ELAT and
EPGM bits are available. Table 10-1 shows the location of each bit in the
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EPROG register and the state of these bits coming out of reset. All the
bits in the EPROG register are cleared by reset.
$1C
Read:
Bit 7
6
5
4
3
0
0
0
0
0
2
1
Bit 0
0
ELAT
EPGM
Write:
Reset:
0
0
0
0
0
0
0
0
EPGM — EPROM Program Control
If the EPGM bit is set, programming power is applied to the EPROM
array. If the EPGM bit is cleared, programming power is removed
from the EPROM array. The EPGM bit cannot be set unless the ELAT
bit is set already.
Whenever the ELAT bit is cleared, the EPGM bit is cleared also. Both
the EPGM and the ELAT bit cannot be set using the same write
instruction. Any attempt to set both the EPGM and ELAT bit on the
same write instruction cycle will result in the ELAT bit being set and
the EPGM bit being cleared. The EPGM bit is a read-write bit and can
be read at any time. The EPGM bit is cleared by reset.
ELAT— EPROM Latch Control
If the ELAT bit is set, the EPROM address and data bus are
configured for programming to the array. If the ELAT bit is cleared, the
EPROM address and data bus are configured for normal reading of
data from the array. When the ELAT bit is set, the address and data
bus are latched in the EPROM array when a subsequent write to the
array is made. Data in the EPROM array cannot be read if the ELAT
bit is set.
Whenever the ELAT bit is cleared, the EPGM bit is cleared also. Both
the EPGM and the ELAT bit cannot be set using the same write
instruction. Any attempt to set both the EPGM and ELAT bit on the
same write instruction cycle will result in the ELAT bit being set and
the EPGM bit being cleared. The ELAT bit is a read-write bit and can
be read at any time. The ELAT bit is cleared by reset.
MC68HC705P6A — Rev. 1.0
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EPROM
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A G R E E M E N T
Figure 10-1. EPROM Programming Register (EPROG)
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= Unimplemented
R E Q U I R E D
General Release Specification
EPROM Programming Register (EPROG)
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A G R E E M E N T
R E Q U I R E D
EPROM
To program a byte of EPROM, manipulate the EPROG register as
follows:
1. Set the ELAT bit in the EPROG register.
2. Write the desired data to the desired EPROM address.
3. Set the EPGM bit in the EPROG register for the specified
programming time, tEPGM.
4. Clear the ELAT and EPGM bits in the EPROG register.
This sequence is also shown in the sample program listing in
Table 10-1.
Table 10-1. EPROM Programming Routine
001C
0055
0700
0000
EPROG
DATA
EPROM
EPGM
EQU
EQU
EQU
EQU
00D0
ORG
$D0
00D0
00D2
00D4
00D6
00D9
00DB
00DD
00DF
A6
B7
A6
C7
10
AD
3F
81
02
1C
55
07 00
1C
03
1C
LDA
STA
LDA
STA
BSET
BSR
CLR
RTS
$1C
$55
$700
$00
PROGRAMMING REG
DATA VALUE
A SAMPLE EPROM ADX
EPGM BIT IN EPROG REG
#$04
SET LAT BIT IN EPROG
EPROG
#DATA
DATA BYTE
EPROM
WRITE IT TO EPROM LOC
EPGM, EPROG TURN ON PGM VOLTAGE
DELAY
WAIT 4 ms MINIMUM
EPROG
CLR LAT AND PGM BITS
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EPROM
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Table 10-2. Bootloader Control Pins
PC6
PC4
PC3
Mode
1
1
1
Program/Verify
1
1
0
Verify Only
1
0
0
Dump MCU EPROM to Port A
10.8 Programming from an External Memory Device
In this programming mode, PC5 must be connected to VSS. PC4 and
PC3 are used to select the programming mode. The programming circuit
shown in Figure 10-2 uses an external 12-bit counter to address the
memory device containing the code to be copied. This counter requires
a clock and a reset function. The 12-bit counter can address up to
4 Kbytes of memory, which means that a port pin has to be used to
address the remaining 4 K of the 8-K memory space.
The following procedure explains how to use the programming circuit
shown in Figure 10-2 to copy a user program from an external memory
device into the MCU’s EPROM:
1. Program a 2764-type EPROM device with the desired instructions
and data. Code programmed into the 2764 must appear at the
same addresses desired in the MC68HC705P6A. Therefore, the
page zero code must start at $0020 and end at $004F, the main
body of code must start at $0100 and end at $12FF, and the user
vectors must start at $1FF0 and end at $1FFF.
NOTE:
The MOR data must appear at $1EFF and $1F00.
2. Install the programmed 2764 device into the programming circuit.
3. Install the MC68HC705P6A to be programmed into the
programming circuit.
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A G R E E M E N T
Three port pins are associated with bootloader control functions: PC3,
PC4, and PC6. Table 10-2 summarizes their functionality.
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10.7 EPROM Bootloader
R E Q U I R E D
General Release Specification
EPROM Bootloader
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4. Set the PROGRAM and/or VERIFY switches for the desired
operation (an open switch is the active state) and close the
RESET switch to hold the MCU in reset.
5. Make sure that the VPP source is OFF.
6. Apply the VDD source to the programming circuit.
7. Apply the VPP source to the programming circuit.
8. Open the RESET switch to allow the MCU to come out of reset
and begin execution of the software in its internal bootloader
ROM.
9. Wait for programming and/or verification to complete (about 40
seconds). The PROGRAM LED will light during programming and
the VERIFY LED will light if verification was requested and was
successful.
10. When complete, close the RESET switch to force the MCU into
the reset state.
11. Turn off the VPP source.
12. Turn off the VDD source.
13. Remove device(s).
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EPROM
General Release Specification
MC68HC705P6A — Rev. 1.0
EPROM
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INSTALL EPROM INTO PROGRAMMER
PROGRAMMING?
INSTALL MC68HC705P6A INTO PROGRAMMER
N
Y
Y
OPEN PROGRAM SWITCH
CLOSE PROGRAM SWITCH
VERIFYING?
N
Y
WAIT FOR 30 SECONDS
N
VERIFYING?
Y
OPEN VERIFY SWITCH
CLOSE VERIFY SWITCH
N
IS VERIFY
LED LIT?
CLOSE RESET SWITCH
Y
MAKE SURE VPP IS OFF
VERIFICATION FAILED
VERIFICATION COMPLETE
TURN VDD ON
CLOSE RESET SWITCH
TURN VPP ON
TURN OFF VPP
OPEN RESET SWITCH
TURN OFF VDD
REMOVE DEVICES
Figure 10-2. MC68HC705P6A EPROM Programming Flowchart
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EPROM
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WAIT FOR PROGRAMMING LED TO
TURN ON AND OFF.
N
PROGRAMMING?
A G R E E M E N T
PROGRAM 2764 TYPE EPROM
R E Q U I R E D
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Programming from an External Memory Device
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R E Q U I R E D
EPROM
VDD
MC68HC705P6A
VPP
A G R E E M E N T
Freescale Semiconductor, Inc...
10 kΩ
2764
PD7/TCAP
MC74HC4040
VDD
OSC1
PGM
2 MHz
OSC2
20 pF
N O N - D I S C L O S U R E
IRQ/VPP
10 MΩ
20 pF
VDD
10 kΩ
RESET
RESET
PB5
A12
PA7
D7
PA6
D6
PA5
D5
PA4
D4
PA3
D3
PA2
D2
PA1
D1
PA0
D0
1 µF
VDD
CE
A11
Q12
A10
Q11
A9
Q10
A8
Q9
A7
Q8
A6
Q7
A5
Q6
A4
Q5
A3
Q4
A2
Q3
A1
Q2
A0
Q1
OE
RST
VDD
CLK
10 kΩ
PC6
PC1
PROG
PB7
PC2
330 Ω
VDD
10 kΩ
VERF
PB6
330 Ω
PC5
VDD
10 kΩ
PGM
PC3
VFY
PC4
VDD = 5.0 V
VPP = 16.5 V
Figure 10-3. MC68HC705P6A EPROM Programming Schematic Diagram
General Release Specification
MC68HC705P6A — Rev. 1.0
EPROM
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Section 11. Mask Option Register (MOR)
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
11.3
Mask Option Register (MOR) $1EFF–$1F00 . . . . . . . . . . . . . .92
11.4
MOR Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
11.2 Introduction
The mask option register (MOR) contains two bytes of EPROM used to
enable or disable each of the features controlled by mask options on the
MC68HC05P6 (a ROM version of the MC68HC705P6A). The seven
programmable options on the MC68HC705P6A are:
1. COP watchdog timer (enable or disable)
2. IRQ triggering (edge- or edge- and level-sensitive)
3. SIOP data bit order (most significant bit or least significant bit first)
4. SIOP clock rate (OSC divided by 8, 16, 32, or 64)
5. Stop instruction mode (stop mode or halt mode)
6. Secure EPROM from external reading
7. Keyscan interrupt/pullups on PA0–PA7
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Mask Option Register (MOR)
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11.1 Contents
A G R E E M E N T
General Release Specification — MC68HC705P6A
R E Q U I R E D
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Mask Option Register (MOR)
11.3 Mask Option Register (MOR) $1EFF–$1F00
Mask options are programmed into the mask option register (MOR) by
the firmware in the bootloader ROM.
$1EFF
Bit 7
6
5
4
3
2
1
Bit 0
PA7PU
PA6PU
PA5PU
PA4PU
PA3PU
PA2PU
PA1PU
PA0PU
Erased
State:
0
0
0
0
0
0
0
0
$1F00
Bit 7
6
5
4
3
2
1
Bit 0
SECURE
RCOSC
SWAIT
SPR1
SPR0
LSBF
LEVEL
COP
0
0
0
0
0
0
0
0
Read:
Write:
Read:
Write:
Erased
State:
Figure 11-1. Mask Option Register (MOR)
COP — COP Watchdog Enable
Setting the COP bit will enable the COP watchdog timer. The COP will
reset the MCU if the timeout period is reached before the COP
watchdog timer is cleared by the application software and the voltage
applied to the IRQ/VPP pin is between VSS and VDD. Clearing the
COP bit will disable the COP watchdog timer regardless of the voltage
applied to the IRQ/VPP pin.
LEVEL — IRQ Edge Sensitivity
If the LEVEL bit is clear, the IRQ/VPP pin will only be sensitive to the
falling edge of the signal applied to the IRQ/VPP pin. If the LEVEL bit
is set, the IRQ/VPP pin will be sensitive to both the falling edge of the
input signal and the logic low level of the input signal on the IRQ/VPP
pin.
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SPR0 and SPR1 — SIOP Clock Rate
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The SPR0 and SPR1 bits determine the clock rate used to transfer the
serial data to and from the SIOP. The various clock rates available are
given in Table 11-1.
Table 11-1. SIOP Clock Rate
SPR1
SPR0
SIOP Master Clock
0
0
fosc ÷ 64
0
1
fosc ÷ 32
1
0
fosc ÷ 16
1
1
fosc ÷ 8
SWAIT — STOP Instruction Mode
Setting the SWAIT bit will prevent the STOP instruction from stopping
the on-board oscillator. Clearing the SWAIT bit will permit the STOP
instruction to stop the on-board oscillator and place the MCU in stop
mode. Executing the STOP instruction when SWAIT is set will place
the MCU in halt mode. See 3.5.1 STOP Instruction for additional
information.
SECURE — Security State1
If SECURE bit is set, the EPROM is locked.
PA(0:7)PU — Port A Pullups/Interrupt Enable/Disable
If any PA(0:7)PU is selected, that pullup/interrupt is enabled. The
interrupt sensitivity will be selected via the LEVEL bit in the same way
as the IRQ pin.
NOTE:
The port A pullup/interrupt function is NOT available on the ROM device,
MC68HC05P6.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the EPROM/OTPROM difficult for unauthorized users.
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If the LSBF bit is set, the serial data to and from the SIOP will be
transferred least significant bit first. If the LSBF bit is clear, the serial
data to and from the SIOP will be transferred most significant bit first.
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LSBF — SIOP Least Significant Bit First
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Mask Option Register (MOR) $1EFF–$1F00
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R E Q U I R E D
Mask Option Register (MOR)
11.4 MOR Programming
The contents of the MOR should be programmed in bootloader mode
using the hardware shown in Figure 10-2. In order to allow
programming, all the implemented bits in the MOR are essentially readwrite bits in bootloader mode as shown in Figure 11-1.
The programming of the MOR is the same as user EPROM.
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1. Set the ELAT bit in the EPROG register.
2. Write the desired data to the desired MOR address.
3. Set the EPGM bit in the EPROG.
4. Wait for the programming time (tEPGM).
5. Clear the ELAT and EPGM bits in the EPROG.
6. Remove the programming voltage from the IRQ/VPP pin.
A sample routine to program a byte of EPROM is shown in Table 11-2.
Once the MOR bits have been programmed, the options are not loaded
into the MOR registers until the part is reset.
Table 11-2. MOR Programming Routine
001C
00FF
0023
1EFF
1F00
0000
EPROG
DATA2
DATA1
MOR2
MOR1
EPGM
00E0
00E0
00E2
00E4
00E6
00E9
00EB
00ED
00EF
A6
B7
A6
C7
12
AD
3F
81
04
1C
FF
1E FF
1C
03
1C
EQU
EQU
EQU
EQU
EQU
EQU
$1C
$FF
#23
$1EFF
$1F00
$00
ORG
$E0
LDA
STA
LDA
STA
BSET
BSR
CLR
RTS
#$04
EPROG
#DATA2
MOR2
EPGM,EPROG
DELAY
EPROG
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PROGRAMMING REG
SAMPLE MOR VALUES
MOPR ADDRESSES
EPGM BIT IN EPROG REG
SET ELAT BIT
IN EPGM REG AT $1C
DATA BYTE
WRITE IT TO MOR LOC
TURN ON PGM VOLTAGE
WAIT 4 ms MINIMUM
CLR EPGM REGISTER
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Section 12. CPU Core
12.1 Contents
12.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
12.3.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
12.3.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
12.3.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
12.3.4
Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
12.3.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .98
12.2 Introduction
The MC68HC705P6A has an 8-K memory map. Therefore, it uses only
the lower 13 bits of the address bus. In the following discussion, the
upper three bits of the address bus can be ignored. Also, the STOP
instruction can be modified to place the MCU in either the normal stop
mode or the halt mode by means of a MOR bit. All other instructions and
registers behave as described in this section.
12.3 Registers
The MCU contains five registers which are hard-wired within the CPU
and are not part of the memory map. These five registers are shown in
Figure 12-1 and are described in the following paragraphs.
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
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12.2
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R E Q U I R E D
CPU Core
7
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
A G R E E M E N T
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1
5
4
3
2
1
0
ACCUMULATOR
A
INDEX REGISTER
X
1
STACK POINTER
SP
PROGRAM COUNTER
CONDITION CODE REGISTER
N O N - D I S C L O S U R E
6
1
1
PC
1
H
I
N
Z
C
CC
HALF-CARRY BIT (FROM BIT 3)
INTERRUPT MASK
NEGATIVE BIT
ZERO BIT
CARRY BIT
Figure 12-1. MC68HC05 Programming Model
12.3.1 Accumulator
The accumulator is a general-purpose 8-bit register as shown in
Figure 12-1. The CPU uses the accumulator to hold operands and
results of arithmetic calculations or non-arithmetic operations. The
accumulator is unaffected by a reset of the device.
12.3.2 Index Register
The index register shown in Figure 12-1 is an 8-bit register that can
perform two functions:
•
Indexed addressing
•
Temporary storage
In indexed addressing with no offset, the index register contains the low
byte of the operand address, and the high byte is assumed to be $00. In
indexed addressing with an 8-bit offset, the CPU finds the operand
address by adding the index register contents to an 8-bit immediate
value. In indexed addressing with a 16-bit offset, the CPU finds the
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12.3.3 Stack Pointer
The stack pointer shown in Figure 12-1 is a 16-bit register internally. In
devices with memory maps less than 64 Kbytes, the unimplemented
upper address lines are ignored. The stack pointer contains the address
of the next free location on the stack. During a reset or the reset stack
pointer (RSP) instruction, the stack pointer is set to $00FF. The stack
pointer is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
When accessing memory, the 10 most significant bits are permanently
set to 0000000011. The six least significant register bits are appended
to these 10 fixed bits to produce an address within the range of $00FF
to $00C0. Subroutines and interrupts may use up to 64 ($40) locations.
If 64 locations are exceeded, the stack pointer wraps around and writes
over the previously stored information. A subroutine call occupies two
locations on the stack and an interrupt uses five locations.
12.3.4 Program Counter
The program counter shown in Figure 12-1 is a 16-bit register internally.
In devices with memory maps less than 64 Kbytes, the unimplemented
upper address lines are ignored. The program counter contains the
address of the next instruction or operand to be fetched.
Normally, the address in the program counter increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
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The index register can also serve as an auxiliary accumulator for
temporary storage. The index register is unaffected by a reset of the
device.
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operand address by adding the index register contents to a 16-bit
immediate value.
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CPU Core
12.3.5 Condition Code Register
The CCR shown in Figure 12-1 is a 5-bit register in which four bits are
used to indicate the results of the instruction just executed. The fifth bit
is the interrupt mask. These bits can be individually tested by a program,
and specific actions can be taken as a result of their state. The condition
code register should be thought of as having three additional upper bits
that are always ones. Only the interrupt mask is affected by a reset of
the device. The following paragraphs explain the functions of the lower
five bits of the condition code register.
H — Half Carry Bit
When the half-carry bit is set, it means that a carry occurred between
bits 3 and 4 of the accumulator during the last ADD or ADC (add with
carry) operation. The half-carry bit is required for binary-coded
decimal (BCD) arithmetic operations.
I — Interrupt Mask Bit
When the interrupt mask is set, the internal and external interrupts are
disabled. Interrupts are enabled when the interrupt mask is cleared.
When an interrupt occurs, the interrupt mask is automatically set after
the CPU registers are saved on the stack, but before the interrupt
vector is fetched. If an interrupt request occurs while the interrupt
mask is set, the interrupt request is latched. Normally, the interrupt is
processed as soon as the interrupt mask is cleared.
A return from interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its state before the interrupt
was encountered. After any reset, the interrupt mask is set and can
only be cleared by the clear I bit (CLI), STOP, or WAIT instructions.
N — Negative Bit
The negative bit is set when the result of the last arithmetic operation,
logical operation, or data manipulation was negative. (Bit 7 of the
result was a logic one.)
The negative bit can also be used to check an often-tested flag by
assigning the flag to bit 7 of a register or memory location. Loading
the accumulator with the contents of that register or location then sets
or clears the negative bit according to the state of the flag.
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The zero bit is set when the result of the last arithmetic operation,
logical operation, data manipulation, or data load operation was zero.
C — Carry/Borrow Bit
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The carry/borrow bit is set when a carry out of bit 7 of the accumulator
occurred during the last arithmetic operation, logical operation, or
data manipulation. The carry/borrow bit is also set or cleared during
bit test and branch instructions and during shifts and rotates. This bit
is not set by an INC or DEC instruction.
A G R E E M E N T
Z — Zero Bit
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R E Q U I R E D
CPU Core
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Section 13. Instruction Set
13.1 Contents
13.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
13.3.1
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
13.3.2
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
13.3.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
13.3.4
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
13.3.5
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
13.3.6
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
13.3.7
Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
13.3.8
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
13.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
13.4.1
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .106
13.4.2
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .107
13.4.3
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .108
13.4.4
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .110
13.4.5
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
13.5
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
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13.2
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13.2 Introduction
The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
13.3 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing modes
are:
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Instruction Set
•
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, no offset
•
Indexed, 8-bit offset
•
Indexed, 16-bit offset
•
Relative
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13.3.1 Inherent
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
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Addressing Modes
13.3.3 Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
13.3.4 Extended
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
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Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
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13.3.2 Immediate
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Instruction Set
13.3.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
13.3.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
13.3.7 Indexed,16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
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When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
13.4 Instruction Types
The MCU instructions fall into the following five categories:
•
Register/Memory Instructions
•
Read-Modify-Write Instructions
•
Jump/Branch Instructions
•
Bit Manipulation Instructions
•
Control Instructions
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Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
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13.3.8 Relative
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Instruction Set
13.4.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 13-1. Register/Memory Instructions
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A G R E E M E N T
Instruction
Mnemonic
Add Memory Byte and Carry Bit to Accumulator
ADC
Add Memory Byte to Accumulator
ADD
AND Memory Byte with Accumulator
AND
Bit Test Accumulator
BIT
Compare Accumulator
CMP
Compare Index Register with Memory Byte
CPX
EXCLUSIVE OR Accumulator with Memory Byte
EOR
Load Accumulator with Memory Byte
LDA
Load Index Register with Memory Byte
LDX
Multiply
MUL
OR Accumulator with Memory Byte
ORA
Subtract Memory Byte and Carry Bit from Accumulator
SBC
Store Accumulator in Memory
STA
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
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13.4.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
Do not use read-modify-write operations on write-only registers.
Table 13-2. Read-Modify-Write Instructions
Mnemonic
Arithmetic Shift Left (Same as LSL)
ASL
Arithmetic Shift Right
ASR
Bit Clear
BCLR(1)
Bit Set
BSET(1)
Clear Register
CLR
Complement (One’s Complement)
COM
Decrement
DEC
Increment
INC
Logical Shift Left (Same as ASL)
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
NEG
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
Test for Negative or Zero
TST(2)
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence because it does not write a replacement value.
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Instruction
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Instruction Types
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13.4.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Instruction Set
General Release Specification
MC68HC705P6A — Rev. 1.0
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Mnemonic
Branch if Carry Bit Clear
BCC
Branch if Carry Bit Set
BCS
Branch if Equal
BEQ
Branch if Half-Carry Bit Clear
BHCC
Branch if Half-Carry Bit Set
BHCS
Branch if Higher
BHI
Branch if Higher or Same
BHS
Branch if IRQ Pin High
BIH
Branch if IRQ Pin Low
BIL
Branch if Lower
BLO
Branch if Lower or Same
BLS
Branch if Interrupt Mask Clear
BMC
Branch if Minus
BMI
Branch if Interrupt Mask Set
BMS
Branch if Not Equal
BNE
Branch if Plus
BPL
Branch Always
BRA
Branch if Bit Clear
Branch Never
Branch if Bit Set
BRCLR
BRN
BRSET
Branch to Subroutine
BSR
Unconditional Jump
JMP
Jump to Subroutine
JSR
MC68HC705P6A — Rev. 1.0
General Release Specification
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
Freescale Semiconductor, Inc...
Instruction
N O N - D I S C L O S U R E
Table 13-3. Jump and Branch Instructions
R E Q U I R E D
General Release Specification
Instruction Types
Freescale Semiconductor, Inc.
R E Q U I R E D
Instruction Set
13.4.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 13-4. Bit Manipulation Instructions
A G R E E M E N T
Instruction
Freescale Semiconductor, Inc...
Bit Clear
Mnemonic
BCLR
Branch if Bit Clear
BRCLR
Branch if Bit Set
BRSET
BSET
N O N - D I S C L O S U R E
Bit Set
General Release Specification
MC68HC705P6A — Rev. 1.0
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Table 13-5. Control Instructions
Freescale Semiconductor, Inc...
Instruction
Mnemonic
Clear Carry Bit
CLC
Clear Interrupt Mask
CLI
No Operation
NOP
Reset Stack Pointer
RSP
Return from Interrupt
RTI
Return from Subroutine
RTS
Set Carry Bit
SEC
Set Interrupt Mask
SEI
Stop Oscillator and Enable IRQ Pin
STOP
Software Interrupt
SWI
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
Stop CPU Clock and Enable Interrupts
WAIT
MC68HC705P6A — Rev. 1.0
General Release Specification
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
These instructions act on CPU registers and control CPU operation
during program execution.
N O N - D I S C L O S U R E
13.4.5 Control Instructions
R E Q U I R E D
General Release Specification
Instruction Types
Freescale Semiconductor, Inc.
13.5 Instruction Set Summary
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
Description
↕
IMM
DIR
EXT
IX2
IX1
IX
A9 ii
2
B9 dd 3
C9 hh ll 4
D9 ee ff 5
E9 ff
4
F9
3
↕
IMM
DIR
EXT
IX2
IX1
IX
AB ii
2
BB dd 3
CB hh ll 4
DB ee ff 5
EB ff
4
FB
3
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A4 ii
2
B4 dd 3
C4 hh ll 4
D4 ee ff 5
E4 ff
4
F4
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
REL
24
rr
3
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
H I N Z C
A ← (A) + (M) + (C)
Add with Carry
A ← (A) + (M)
Add without Carry
Arithmetic Shift Left (Same as LSL)
C
BCC rel
Branch if Carry Bit Clear
↕
↕
— — ↕
0
b7
Arithmetic Shift Right
↕ —
A ← (A) ∧ (M)
Logical AND
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
↕ —
— — ↕
↕
↕
↕
b0
C
b7
— — ↕
↕
↕
b0
PC ← (PC) + 2 + rel ? C = 0
Mn ← 0
— — — — —
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
ff
ff
Cycles
Operation
Effect on
CCR
Opcode
Source
Form
Operand
Table 13-6. Instruction Set Summary
Address
Mode
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Instruction Set
5
3
3
6
5
5
3
3
6
5
BCLR n opr
Clear Bit n
BCS rel
Branch if Carry Bit Set (Same as BLO)
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
BHCC rel
Branch if Half-Carry Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
BHCS rel
Branch if Half-Carry Bit Set
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
BHI rel
Branch if Higher
BHS rel
Branch if Higher or Same
PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — —
PC ← (PC) + 2 + rel ? C = 0
General Release Specification
— — — — —
REL
22
rr
3
REL
24
rr
3
MC68HC705P6A — Rev. 1.0
Instruction Set
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Freescale Semiconductor, Inc.
Operand
Cycles
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
— — ↕
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A5 ii
2
B5 dd 3
C5 hh ll 4
D5 ee ff 5
E5 ff
4
F5
3
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — —
REL
23
rr
3
Freescale Semiconductor, Inc...
Operation
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test Accumulator with Memory Byte
BLO rel
Branch if Lower (Same as BCS)
BLS rel
Branch if Lower or Same
Description
(A) ∧ (M)
PC ← (PC) + 2 + rel ? C = 1
Effect on
CCR
H I N Z C
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? I = 0
— — — — —
REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
— — — — —
REL
2B
rr
3
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? I = 1
— — — — —
REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? Z = 0
— — — — —
REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? N = 0
— — — — —
REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
REL
20
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
— — — — —
BRCLR n opr rel Branch if Bit n Clear
BRN rel
Branch Never
BRSET n opr rel Branch if Bit n Set
BSET n opr
Set Bit n
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? 1 = 0
21
rr
3
PC ← (PC) + 2 + rel ? Mn = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn ← 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
BSR rel
Branch to Subroutine
CLC
Clear Carry Bit
C←0
— — — — 0
INH
98
2
CLI
Clear Interrupt Mask
I←0
— 0 — — —
INH
9A
2
MC68HC705P6A — Rev. 1.0
General Release Specification
Instruction Set
For More Information On This Product,
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A G R E E M E N T
Opcode
BIH rel
Source
Form
N O N - D I S C L O S U R E
Address
Mode
Table 13-6. Instruction Set Summary (Continued)
R E Q U I R E D
General Release Specification
Instruction Set Summary
Freescale Semiconductor, Inc.
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
INC opr
INCA
INCX
INC opr,X
INC ,X
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Description
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
dd
↕
IMM
DIR
EXT
IX2
IX1
IX
A1 ii
2
B1 dd 3
C1 hh ll 4
D1 ee ff 5
E1 ff
4
F1
3
1
DIR
INH
INH
IX1
IX
33
43
53
63
73
↕
IMM
DIR
EXT
IX2
IX1
IX
A3 ii
2
B3 dd 3
C3 hh ll 4
D3 ee ff 5
E3 ff
4
F3
3
↕ —
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A8 ii
2
B8 dd 3
C8 hh ll 4
D8 ee ff 5
E8 ff
4
F8
3
↕ —
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
DIR
EXT
IX2
IX1
IX
BC dd 2
CC hh ll 3
DC ee ff 4
EC ff
3
FC
2
Effect on
CCR
H I N Z C
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
Clear Byte
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
EXCLUSIVE OR Accumulator with Memory
Byte
Unconditional Jump
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
(X) – (M)
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
Decrement Byte
Increment Byte
(A) – (M)
A ← (A) ⊕ (M)
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
PC ← Jump Address
General Release Specification
— — 0 1 —
— — ↕
— — ↕
— — ↕
— — ↕
— — ↕
— — ↕
↕
↕
↕
— — — — —
ff
dd
ff
dd
ff
dd
ff
Cycles
Operation
Operand
Source
Form
Opcode
Table 13-6. Instruction Set Summary (Continued)
Address
Mode
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Instruction Set
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
MC68HC705P6A — Rev. 1.0
Instruction Set
For More Information On This Product,
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Freescale Semiconductor, Inc.
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
Jump to Subroutine
X ← (M)
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
↕ —
A6 ii
2
B6 dd 3
C6 hh ll 4
D6 ee ff 5
E6 ff
4
F6
3
↕ —
IMM
DIR
EXT
IX2
IX1
IX
AE ii
2
BE dd 3
CE hh ll 4
DE ee ff 5
EE ff
4
FE
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
0
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
MUL
Unsigned Multiply
0
C
b7
0 — — — 0
INH
42
— — ↕
DIR
INH
INH
IX1
IX
30
40
50
60
70
Negate Byte (Two’s Complement)
NOP
No Operation
— — — — —
INH
9D
— — ↕
↕ —
IMM
DIR
EXT
IX2
IX1
IX
AA ii
2
BA dd 3
CA hh ll 4
DA ee ff 5
EA ff
4
FA
3
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
A ← (A) ∨ (M)
Logical OR Accumulator with Memory
↕
DIR
INH
INH
IX1
IX
39
49
59
69
79
Rotate Byte Left through Carry Bit
C
— — 0 ↕
— — ↕
b7
↕
↕
b0
X : A ← (X) × (A)
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
— — ↕
b0
b0
MC68HC705P6A — Rev. 1.0
↕
↕
↕
ff
ff
Cycles
— — ↕
IMM
DIR
EXT
IX2
IX1
IX
— — ↕
C
b7
Logical Shift Right
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
A ← (M)
Load Accumulator with Memory Byte
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
BD dd 5
CD hh ll 6
DD ee ff 7
ED ff
6
FD
5
5
3
3
6
5
5
3
3
6
5
1
1
dd
ff
5
3
3
6
5
2
dd
ff
5
3
3
6
5
General Release Specification
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
— — — — —
DIR
EXT
IX2
IX1
IX
H I N Z C
N O N - D I S C L O S U R E
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
Description
Opcode
Freescale Semiconductor, Inc...
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Operation
Effect on
CCR
Address
Mode
Source
Form
Operand
Table 13-6. Instruction Set Summary (Continued)
R E Q U I R E D
General Release Specification
Instruction Set Summary
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Operand
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
— — — — —
INH
9C
2
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕
↕
INH
80
9
Return from Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
— — — — —
INH
81
6
— — ↕
↕
IMM
DIR
EXT
IX2
IX1
IX
A2 ii
2
B2 dd 3
C2 hh ll 4
D2 ee ff 5
E2 ff
4
F2
3
Source
Form
Operation
Effect on
CCR
Description
H I N Z C
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right through Carry Bit
RSP
Reset Stack Pointer
SP ← $00FF
RTI
RTS
C
b7
— — ↕
↕
↕
b0
↕
↕
↕
ff
Cycles
Opcode
Table 13-6. Instruction Set Summary (Continued)
Address
Mode
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Instruction Set
5
3
3
6
5
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract Memory Byte and Carry Bit from
Accumulator
SEC
Set Carry Bit
C←1
— — — — 1
INH
99
2
SEI
Set Interrupt Mask
I←1
— 1 — — —
INH
9B
2
— — ↕
↕ —
DIR
EXT
IX2
IX1
IX
B7 dd 4
C7 hh ll 5
D7 ee ff 6
E7 ff
5
F7
4
— 0 — — —
INH
8E
— — ↕
↕ —
DIR
EXT
IX2
IX1
IX
BF dd 4
CF hh ll 5
DF ee ff 6
EF ff
5
FF
4
↕
↕
IMM
DIR
EXT
IX2
IX1
IX
A0 ii
2
B0 dd 3
C0 hh ll 4
D0 ee ff 5
E0 ff
4
F0
3
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
INH
83
1
0
INH
97
2
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in Memory
STOP
Stop Oscillator and Enable IRQ Pin
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
Store Index Register In Memory
Subtract Memory Byte from Accumulator
SWI
Software Interrupt
TAX
Transfer Accumulator to Index Register
A ← (A) – (M) – (C)
M ← (A)
M ← (X)
A ← (A) – (M)
X ← (A)
General Release Specification
— — ↕
↕
— — — — —
2
MC68HC705P6A — Rev. 1.0
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
3D
4D
5D
6D
7D
dd
Test Memory Byte for Negative or Zero
TXA
Transfer Index Register to Accumulator
— — — — —
INH
9F
2
WAIT
Stop CPU Clock and Enable Interrupts
— 0 — — —
INH
8F
2
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
— — ↕
(M) – $00
A ← (X)
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
↕
—
↕ —
ff
4
3
3
5
4
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
MC68HC705P6A — Rev. 1.0
General Release Specification
Instruction Set
For More Information On This Product,
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A G R E E M E N T
DIR
INH
INH
IX1
IX
Cycles
Operand
Description
H I N Z C
TST opr
TSTA
TSTX
TST opr,X
TST ,X
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
Opcode
Operation
Effect on
CCR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
Source
Form
Address
Mode
Table 13-6. Instruction Set Summary (Continued)
R E Q U I R E D
General Release Specification
Instruction Set Summary
General Release Specification
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
1
DIR
2
REL
Branch
3
DIR
4
5
INH
6
IX1
Read-Modify-Write
INH
7
IX
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
EOR
IMM 2
2
ADC
IMM 2
2
ORA
IMM 2
2
ADD
IMM 2
2
2
SUB
IMM 2
2
CMP
IMM 2
2
SBC
IMM 2
2
CPX
IMM 2
2
AND
IMM 2
2
BIT
IMM 2
2
LDA
IMM 2
A
IMM
MSB
0
LSB
0
5
SUB
IX2 2
5
CMP
IX2 2
5
SBC
IX2 2
5
CPX
IX2 2
5
AND
IX2 2
5
BIT
IX2 2
5
LDA
IX2 2
6
STA
IX2 2
5
EOR
IX2 2
5
ADC
IX2 2
5
ORA
IX2 2
5
ADD
IX2 2
4
JMP
IX2 2
7
JSR
IX2 2
5
LDX
IX2 2
6
STX
IX2 2
D
IX2
4
SUB
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
AND
IX1 1
4
BIT
IX1 1
4
LDA
IX1 1
5
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
JMP
IX1 1
6
JSR
IX1 1
4
LDX
IX1 1
5
STX
IX1 1
E
IX1
MSB of Opcode in Hexadecimal
4
SUB
EXT 3
4
CMP
EXT 3
4
SBC
EXT 3
4
CPX
EXT 3
4
AND
EXT 3
4
BIT
EXT 3
4
LDA
EXT 3
5
STA
EXT 3
4
EOR
EXT 3
4
ADC
EXT 3
4
ORA
EXT 3
4
ADD
EXT 3
3
JMP
EXT 3
6
JSR
EXT 3
4
LDX
EXT 3
5
STX
EXT 3
C
EXT
Register/Memory
3
SUB
DIR 3
3
CMP
DIR 3
3
SBC
DIR 3
3
CPX
DIR 3
3
AND
DIR 3
3
BIT
DIR 3
3
LDA
DIR 3
4
STA
DIR 3
3
EOR
DIR 3
3
ADC
DIR 3
3
ORA
DIR 3
3
ADD
DIR 3
2
JMP
DIR 3
5
JSR
DIR 3
3
LDX
DIR 3
4
STX
DIR 3
B
DIR
5 Number of Cycles
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode
2
6
BSR
REL 2
2
LDX
2
IMM 2
2
TAX
INH
2
CLC
INH 2
2
SEC
INH 2
2
CLI
INH 2
2
SEI
INH 2
2
RSP
INH
2
NOP
INH 2
9
2
STOP
INH
2
2
TXA
WAIT
INH 1
INH
10
SWI
INH
9
RTI
INH
6
RTS
INH
8
INH
Control
INH
LSB of Opcode in Hexadecimal
5
5
3
5
3
3
6
5
BRSET0
BRA
BSET0
NEG
NEGA
NEGX
NEG
NEG
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
BRCLR0
BRN
BCLR0
3
1
DIR 2
DIR 2
REL
5
11
5
3
BRSET1
MUL
BHI
BSET1
3
1
DIR 2
INH
DIR 2
REL
5
5
3
5
3
3
6
5
BRCLR1
BLS
BCLR1
COM
COMA
COMX
COM
COM
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
5
3
3
6
5
BRSET2
BCC
BSET2
LSR
LSRA
LSRX
LSR
LSR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR2
BCLR2 BCS/BLO
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET3
BNE
BSET3
ROR
RORA
RORX
ROR
ROR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR3
BEQ
BCLR3
ASR
ASRA
ASRX
ASR
ASR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET4
BHCC
BSET4
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR4
BHCS
BCLR4
ROL
ROLA
ROLX
ROL
ROL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET5
BPL
BSET5
DEC
DECA
DECX
DEC
DEC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR5
BMI
BCLR5
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET6
BMC
BSET6
INC
INCA
INCX
INC
INC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
4
3
3
5
4
BRCLR6
BMS
BCLR6
TST
TSTA
TSTX
TST
TST
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRSET7
BIL
BSET7
1
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRCLR7
BIH
BCLR7
CLR
CLRA
CLRX
CLR
CLR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
0
DIR
Bit Manipulation
Table 13-7. Opcode Map
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
F
IX
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
3
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
nc...
N O N - D I S C LFreescale
O S U R E Semiconductor,
A G R E E M E IN
T
R E Q U I R E D
Freescale Semiconductor, Inc.
Instruction Set
MC68HC705P6A — Rev. 1.0
Section 14. Electrical Specifications
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
14.3
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
14.4
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .121
14.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
14.6
DC Electrical Characteristics (VDD = 5.0 V) . . . . . . . . . . . . . .122
14.7
DC Electrical Charactertistics (VDD = 3.3 V). . . . . . . . . . . . . .123
14.8
A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . .124
14.9
EPROM Programming Characteristics . . . . . . . . . . . . . . . . . .124
14.10 SIOP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
14.11 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
14.2 Introduction
This section contains the electrical and timing specifications.
MC68HC705P6A — Rev. 1.0
General Release Specification
Electrical Specifications
For More Information On This Product,
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N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
14.1 Contents
A G R E E M E N T
General Release Specification — MC68HC705P6A
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
14.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table below. Keep VIN and VOUT within the range
VSS ≤ (VIN or VOUT) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
Rating
Symbol
Value
Unit
Supply Voltage
VDD
–0.3 to +7.0
V
Input Voltage
VIN
VSS –0.3 to
VDD +0.3
V
Bootloader Mode (IRQ/VPP Pin Only)
VIN
VSS –0.3 to
2 x VDD +0.3
V
I
25
mA
Tstg
–65 to +150
°C
Current Drain Per Pin Excluding VDD and VSS
Storage Temperature Range
NOTE: Voltages are referenced to VSS.
NOTE:
This device is not guaranteed to operate properly at the maximum
ratings. Refer to 14.6 DC Electrical Characteristics (VDD = 5.0 V) and
14.7 DC Electrical Charactertistics (VDD = 3.3 V) for guaranteed
operating conditions.
General Release Specification
MC68HC705P6A — Rev. 1.0
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
Characteristic
Operating Temperature Range
MC68HC705P6A (Standard)
MC68HC705P6AC (Extended)
Symbol
Value
Unit
TA
TL to TH
0 to +70
–40 to +85
°C
Symbol
Value
Unit
θJA
60
60
°C/W
Freescale Semiconductor, Inc...
14.5 Thermal Characteristics
Characteristic
N O N - D I S C L O S U R E
Thermal Resistance
PDIP
SOIC
A G R E E M E N T
14.4 Operating Temperature Range
R E Q U I R E D
General Release Specification
Operating Temperature Range
MC68HC705P6A — Rev. 1.0
General Release Specification
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
14.6 DC Electrical Characteristics (VDD = 5.0 V)
Characteristic
Output Voltage
Iload = 10.0 µA
Iload = –10.0 µA
Output High Voltage
(Iload = –0.8 mA) PA0:7, PB5:7, PC2:7, PD5, TCMP
(Iload = –5.0 mA) PC0:1
Output Low Voltage
(Iload = 1.6 mA) PA0:7, PB5:7, PC2:7, PD5, TCMP
(Iload = 10 mA) PC0:1
Input High Voltage
PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7, IRQ/VPP,
RESET, OSC1
Input Low Voltage
PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7, IRQ/VPP,
RESET, OSC1
Symbol
Min
Typ
Max
Unit
VOL
VOH
—
VDD –0.1
—
—
0.1
—
V
VOH
VDD –0.8
VDD –0.8
—
—
—
—
V
VOL
—
—
—
—
0.4
0.4
V
VIH
0.7 x VDD
—
VDD
V
VIL
VSS
—
0.2 x VDD
V
—
—
—
4.0
2.0
1.3
7.0
4.0
2.0
mA
mA
mA
—
—
—
2
—
—
30
50
100
µA
µA
µA
Supply Current
Run
Wait (A/D Converter On)
Wait (A/D Converter Off)
Stop
25 °C
0 °C to +70 °C (Standard)
–40 °C to +85 °C (Extended)
IDD
I/O Ports High-Z Leakage Current
PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7
IIL
—
—
±10.0
µA
A/D Ports H4i-Z Leakage Current
PC3:7
IOZ
—
—
±1.0
µA
Input Current
RESET, IRQ/VPP, OSC1, PD7/TCAP
IIN
—
—
±1.0
µA
Input Pullup Current
PA0:7 (With Pullup Enabled)
IIN
175
385
750
µA
COUT
CIN
—
—
—
—
12
8
pF
Capaitance
Ports (As Input or Output)
RESET, IRQ/VPP
NOTES:
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted.
2. All values shown reflect pre-silicon estimates.
3. Typical values at midpoint of voltage range, 25 °C only.
4. Run (Operating) IDD, Wait IDD: To be measured using external square wave clock source (fosc = 4.2 MHz), all inputs
0.2 V from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
5. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD –0.2 V.
6. Stop IDD to be measured with OSC1 = VSS.
7. Wait IDD will be affected linearly by the OSC2 capacitance.
General Release Specification
MC68HC705P6A — Rev. 1.0
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
Output Voltage
Iload = 10.0 µA
Iload = –10.0 µA
Output High Voltage
(Iload = –0.2 mA) PA0:7, PB5:7, PC2:7, PD5, TCMP
(Iload = –1.2 mA) PC0:1
Output Low Voltage
(Iload = 0.4 mA) PA0:7, PB5:7, PC2:7, PD5, TCMP
(Iload = 2.5 mA) PC0:1
Input High Voltage
PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7, IRQ/VPP,
RESET, OSC1
Input Low Voltage
PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7, IRQ/VPP,
RESET, OSC1
Symbol
Min
Typ
Max
Unit
VOL
VOH
—
VDD –0.1
—
—
0.1
—
V
VOH
VDD –0.3
VDD –0.3
—
—
—
—
V
VOL
—
—
—
—
0.3
0.3
V
VIH
0.7 x VDD
—
VDD
V
VIL
VSS
—
0.2 x VDD
V
—
—
—
1.8
1.0
0.6
2.5
1.4
1.0
mA
mA
mA
—
—
—
2
—
—
20
40
50
µA
µA
µA
Supply Current
Run
Wait (A/D Converter On)
Wait (A/D Converter Off)
Stop
25 °C
0 °C to +70 °C (Standard)
–40 °C to +85 °C (Extended)
IDD
I/O Ports High-Z Leakage Current
PA0:7, PB5:7, PC0:7, PD5, TCAP/PD7
IIL
—
—
±10.0
µA
A/D Ports H4i-Z Leakage Current
PC3:7
IOZ
—
—
±1.0
µA
Input Current
RESET, IRQ/VPP, OSC1, PD7/TCAP
IIN
—
—
±1.0
µA
Input Pullup Current
PA0:7 (With Pullup Enabled)
IIN
75
175
350
µA
COUT
CIN
—
—
—
—
12
8
pF
Capaitance
Ports (as Input or Output)
RESET, IRQ/VPP
NOTES:
1. VDD = 3.3 Vdc ± 0.3 Vdc, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted.
2. All values shown reflect pre-silicon estimates.
3. Typical values at midpoint of voltage range, 25 °C only.
4. Run (Operating) IDD, Wait IDD: To be measured using external square wave clock source (fosc = 4.2 MHz), all inputs
0.2 V from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
5. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD –0.2 V.
6. Stop IDD to be measured with OSC1 = VSS.
7. Wait IDD will be affected linearly by the OSC2 capacitance.
MC68HC705P6A — Rev. 1.0
General Release Specification
Electrical Specifications
For More Information On This Product,
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A G R E E M E N T
Freescale Semiconductor, Inc...
Characteristic
N O N - D I S C L O S U R E
14.7 DC Electrical Charactertistics (VDD = 3.3 V)
R E Q U I R E D
General Release Specification
DC Electrical Charactertistics (VDD = 3.3 V)
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
14.8 A/D Converter Characteristics
Characteristic
Min
Max
Unit
Resolution
8
8
Bits
Absolute Accuacy
(VDD ≥ VREFH > 4.0)
—
± 1 1/2
LSB
VSS
VSS
VREFH
VDD
V
Input Leakage
AD0, AD1, AD2, AD3
VREFH
—
—
±1
±1
µA
Conversion Time
MCU External Oscillator
Internal RC Oscillator
—
—
32
32
tcyc
µs
Conversion Range
VREFH
Monotonicity
Comments
Including quanitization
A/D accuracy may decrease
proportionately as VREFH is
reduced below 4.0
Includes Sampling Time
Inherent (Within Total Error)
Zero Input Reading
00
01
Hex
Vin = 0 V
Full-Scale Reading
FE
FF
Hex
Vin = VREFH
Sample Time
MCU External Oscillator
Internal RC Oscillator
—
—
12
12
tcyc
µs
Input Capacitance
—
12
pF
VSS
VREFH
V
A/D On Current Stabilization Time
—
100
µs
tADON
A/D Ports Hi-Z Leakage Current (PC3:7)
—
±1
µA
IOZ
Analog Input Voltage
NOTES:
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted.
14.9 EPROM Programming Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
Programming Voltage
IRQ/VPP
VPP
16.25
16.5
16.75
V
Programming Current
IRQ/VPP
IPP
—
5.0
10
mA
tEPGM
4
—
—
ms
Programming Time Per Byte
General Release Specification
MC68HC705P6A — Rev. 1.0
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
Characteristic
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
fop(m)
fop(s)
0.25
dc
0.25
0.25
fop
1
Cycle Time
Master
Slave
tcyc(m)
tcyc(s)
4.0
—
4.0
4.0
tcyc
2
SCK Low Time
tcyc
932
—
ns
3
SDO Data Valid Time
tv
—
200
ns
4
SDO Hold Time
tho
0
—
ns
5
SDI Setup Time
ts
100
—
ns
6
SDI Hold Time
th
100
—
ns
t2
t1
SCK
t5
SDI
BIT 0
t3
SDO
BIT 1 ... 6
t6
BIT 7
t4
BIT 0
BIT 1 ... 6
BIT 7
Figure 14-1. SIOP Timing Diagram
MC68HC705P6A — Rev. 1.0
General Release Specification
Electrical Specifications
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Number
N O N - D I S C L O S U R E
14.10 SIOP Timing
R E Q U I R E D
General Release Specification
SIOP Timing
Freescale Semiconductor, Inc.
14.11 Control Timing
Characteristic
Symbol
Min
Max
Unit
Frequency of Operation
Crystal Option
External Clock Option
fOSC
—
DC
4.2
4.2
MHz
Internal Operating Frequency
Crystal (fOSC ÷ 2)
External Clock (fOSC ÷ 2)
fOP
—
DC
2.1
2.1
MHz
Cycle Time
tCYC
476
—
ns
Crystal Oscillator Startup Time
tOXOV
—
100
ms
Stop Mode Recovery Startup Time (Crystal Oscillator)
tILCH
—
100
ms
RESET Pulse Width
tRL
1.5
—
tCYC
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
125
—
ns
Interrupt Pulse Period
tILIL
Note 2
—
tCYC
tOH, tOL
200
—
ns
tADON
Q
100
µs
OSC1 Pulse Width
A/D On Current Stabilization Time
NOTES:
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +125 °C, unless otherwise noted
2. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt
service routine plus 19 tCYC.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
General Release Specification
MC68HC705P6A — Rev. 1.0
Electrical Specifications
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DD
t
NEW
PCL
1FFF
cyc
NEW PC
OP
CODE
NEW PC
NOTE 3
tRL
1FFE
1FFE
1FFE
MC68HC705P6A — Rev. 1.0
Electrical Specifications
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PCH
1FFE
PCL
1FFF
General Release Specification
N O N - D I S C L O S U R E
A G R E E M E N T
NEW PC
OP
CODE
NEW PC
R E Q U I R E D
Figure 14-2. Power-On Reset and External Reset Timing Diagram
NOTES:
1. Internal timing signal and bus information are not available externally.
2. OSC1 line is not meant to represent frequency. It is only used to represent time.
3. The next rising edge of the internal clock following the rising edge of RESET initiates the reset sequence.
RESET
NEW
PCH
INTERNAL
DATA
1
BUS
4064 tcyc
DD THRESHOLD (1-2 V TYPICAL)
1FFE
V
VDDR
INTERNAL
ADDRESS
BUS 1
INTERNAL
PROCESSOR
1
CLOCK
OSC12
V
t
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General Release Specification
Control Timing
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
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A G R E E M E N T
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Electrical Specifications
General Release Specification
MC68HC705P6A — Rev. 1.0
Electrical Specifications
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15.1 Contents
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
15.3
Plastic Dual In-Line Package (Case 710) . . . . . . . . . . . . . . . .130
15.4
Small Outline Integrated Circuit Package (Case 751F) . . . . .130
15.2 Introduction
The MC68HC705P6A is available in either a 28-pin plastic dual in-line
(PDIP) or a 28-pin small outline integrated circuit (SOIC) package.
The following figures show the latest packages at the time of this
publication. To make sure that you have the latest package
specifications, contact one of the following:
•
Local Motorola Sales Office
•
Motorola Mfax
– Phone 602-244-6609
– EMAIL [email protected]
•
Worldwide Web (wwweb) at http://design-net.com
Follow Mfax or wwweb on-line instructions to retrieve the current
mechanical specifications.
MC68HC705P6A — Rev. 1.0
General Release Specification
Mechanical Specifications
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A G R E E M E N T
Section 15. Mechanical Specifications
N O N - D I S C L O S U R E
General Release Specification — MC68HC705P6A
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
R E Q U I R E D
Mechanical Specifications
15.3 Plastic Dual In-Line Package (Case 710)
28
15
B
Freescale Semiconductor, Inc...
A G R E E M E N T
1
N O N - D I S C L O S U R E
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! ! # ! "
14
A
L
C
N
H
G
M
K
D
F
J
°
°
°
°
15.4 Small Outline Integrated Circuit Package (Case 751F)
-A28
! ! %
! !
! " !" $" !" ! "
!" #
!" !! $ ! $" !
!
15
14X
-B1
P
14
28X D
!
M
R X 45°
C
-T26X
-T-
G
K
F
J
General Release Specification
°
°
°
°
MC68HC705P6A — Rev. 1.0
Mechanical Specifications
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Freescale Semiconductor, Inc...
16.1 Contents
16.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
16.3
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
16.2 Introduction
This section contains ordering information for the available package
types.
16.3 MC Order Numbers
The following table shows the MC order numbers for the available
package types.
MC Order Number
Operating
Temperature Range
MC68HC705P6ACP (Extended)
–40 °C to 85 °C
MC68HC705P6ACDW (Extended)
–40 °C to 85 °C
NOTE:
P = Plastic Dual In-Line Package
DW = Small Outline Integrated Circuit (SOIC) Package
MC68HC705P6A — Rev. 1.0
General Release Specification
Ordering Information
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A G R E E M E N T
Section 16. Ordering Information
N O N - D I S C L O S U R E
General Release Specification — MC68HC705P6A
R E Q U I R E D
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Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Ordering Information
General Release Specification
MC68HC705P6A — Rev. 1.0
Ordering Information
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HC705P6AGRS/D