FREESCALE MC68HC05CT4FB

Freescale Semiconductor, Inc.
General Release Specification
September 15, 1997
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
68HC05CT4
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
R E Q U I R E D
HC05CT4GRS/D
REV. 2.0
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
General Release Specification
General Release Specification
MC68HC05CT4 — Rev. 2.0
For More Information On This Product,
Go to: www.freescale.com
General Release Specification — MC68HC05CT4
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . 15
R E Q U I R E D
Freescale Semiconductor, Inc.
Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Section 6. Operating Modes. . . . . . . . . . . . . . . . . . . . . . 49
Section 7. Parallel Input/Output (I/O) . . . . . . . . . . . . . . 55
Section 8. 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Section 9. Synchronous Serial Interface (SSI) . . . . . . . . 69
Section 10. Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Section 11. Dual Phase-Locked Loop (PLL) . . . . . . . . . . 85
Section 12. Pulse Width Modulator (PWM) . . . . . . . . . . 93
Section 13. Comparators . . . . . . . . . . . . . . . . . . . . . . . . 99
Section 14. Miscellaneous Register . . . . . . . . . . . . . . . 105
Section 15. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . 107
Section 16. Electrical Specifications . . . . . . . . . . . . . . 125
Section 17. Mechanical Specifications . . . . . . . . . . . . 133
Section 18. Ordering Information . . . . . . . . . . . . . . . . . 137
MC68HC05CT4 — Rev. 2.0
General Release Specification
List of Sections
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A G R E E M E N T
Section 3. Central Processing Unit . . . . . . . . . . . . . . . . . 31
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
List of Sections
General Release Specification
MC68HC05CT4 — Rev. 2.0
List of Sections
For More Information On This Product,
Go to: www.freescale.com
Section 1. General Description
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
VDD2 and VSS2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Maskable Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . .21
OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Port A (PA0–PA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Port B (PB0–PB7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Port C (PC0–PC7/PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Port D (PD0/CMP3+, PD1/CMP1–, PD2/CMP12+,
PD3/CMP2–, PD4/SDIO, PD5/SCK,
and PD6/TCMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.4.10
TCAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.4.11
FinT and FinR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.4.12
PDoutT and PDoutR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Freescale Semiconductor, Inc...
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.4.9
Section 2. Memory
2.1
2.2
2.3
2.4
2.5
2.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Read-Only Memory (ROM). . . . . . . . . . . . . . . . . . . . . . . . . . . .25
ROM Security Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . .26
MC68HC05CT4 — Rev. 2.0
General Release Specification
Table of Contents
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A G R E E M E N T
Table of Contents
N O N - D I S C L O S U R E
General Release Specification — MC68HC05CT4
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Table of Contents
Section 3. Central Processing Unit
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Section 4. Interrupts
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
16-Bit Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
SSI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Core Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Comparator 3 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Section 5. Resets
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.3
External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.4
Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.4.1
Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.4.2
Computer Operating Properly Reset (COPR) . . . . . . . . . . .46
5.4.2.1
Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.4.2.2
COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .47
5.4.2.3
COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .47
5.4.2.4
COP Watchdog Timer Considerations . . . . . . . . . . . . . . .47
5.4.2.5
COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
5.4.3
Illegal Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
General Release Specification
MC68HC05CT4 — Rev. 2.0
Table of Contents
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Freescale Semiconductor, Inc.
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Stop Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Low-Power Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Section 7. Parallel Input/Output (I/O)
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Input/Output Port Pin Programming . . . . . . . . . . . . . . . . . . . . .57
Section 8. 16-Bit Timer
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Output Compare Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Input Capture Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Timer During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Timer Power Supply Source . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Section 9. Synchronous Serial Interface (SSI)
9.1
9.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
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Freescale Semiconductor, Inc...
6.1
6.2
6.3
6.4
6.4.1
6.4.2
6.4.3
6.4.4
N O N - D I S C L O S U R E
Section 6. Operating Modes
R E Q U I R E D
Table of Contents
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N O N - D I S C L O S U R E
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9.3
9.3.1
9.3.2
9.4
9.4.1
9.4.2
9.4.3
9.5
9.6
9.7
Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Serial Data In/Out (SDIO) . . . . . . . . . . . . . . . . . . . . . . . . . .71
SSI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
SSI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
SSI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
SSI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Operation During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .76
Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .76
SSI Power Supply Source . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Section 10. Core Timer
10.1
10.2
10.3
10.4
10.5
10.6
10.7
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Core Timer Control and Status Register. . . . . . . . . . . . . . . . . .81
Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . .83
Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .84
Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Core Timer Power Supply Source . . . . . . . . . . . . . . . . . . . . . .84
Section 11. Dual Phase-Locked Loop (PLL)
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
11.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
11.3.1
Dual Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
11.3.2
12-Bit Reference Counter Modulus Register. . . . . . . . . . . .89
11.3.3
16-Bit Transmit Counter Modulus Register . . . . . . . . . . . . .90
11.3.4
16-Bit Receive Counter Modulus Register . . . . . . . . . . . . .91
11.4 PLL Power Supply Source . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Section 12. Pulse Width Modulator (PWM)
12.1
12.2
12.3
12.4
12.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
PWM Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
PWM During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
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Section 13. Comparators
Freescale Semiconductor, Inc...
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Comparator Control/Status Register. . . . . . . . . . . . . . . . . . . .101
Reading Comparator Outputs. . . . . . . . . . . . . . . . . . . . . . . . .103
Comparator During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . .103
Comparator During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . .103
Comparator Power Supply Source . . . . . . . . . . . . . . . . . . . . .103
Section 14. Miscellaneous Register
14.1
14.2
14.3
14.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Miscellaneous Control Register . . . . . . . . . . . . . . . . . . . . . . .105
Miscellaneous Register Power Supply Source . . . . . . . . . . . .106
Section 15. Instruction Set
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
15.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
15.3.1
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
15.3.2
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
15.3.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
15.3.4
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
15.3.5
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
15.3.6
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
15.3.7
Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
15.3.8
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
15.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
15.4.1
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .112
15.4.2
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .113
15.4.3
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .114
15.4.4
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .116
15.4.5
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
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PWM During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
PWM During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
PWM Power Supply Source . . . . . . . . . . . . . . . . . . . . . . . . . . .97
N O N - D I S C L O S U R E
12.6
12.7
12.8
R E Q U I R E D
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15.5
15.6
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Section 16. Electrical Specifications
16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8
16.9
16.10
16.11
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
5.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .128
3.3 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .129
3.3 V and 5.0 V Control Timing. . . . . . . . . . . . . . . . . . . . . . . .130
Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
PWM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
PLL Signal Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Section 17. Mechanical Specifications
17.1
17.2
17.3
17.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
44-Lead Plastic-Leaded Chip Carrier (Case 777-02) . . . . . . .134
44-Lead Quad Flat Pack (Case 824A-01) . . . . . . . . . . . . . . .135
Section 18. Ordering Information
18.1
18.2
18.3
18.4
18.5
18.6
18.7
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .138
ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .139
ROM Verification Units (RVUs) . . . . . . . . . . . . . . . . . . . . . . .140
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
General Release Specification
MC68HC05CT4 — Rev. 2.0
Table of Contents
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Figure
Title
Page
1-1
1-2
1-3
1-4
MC68HC05CT4 Block Diagram . . . . . . . . . . . . . . . . . . . . . .18
44-Lead PLCC Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
44-Lead QFP Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2-1
2-2
MC68HC05CT4 8-K Memory Map . . . . . . . . . . . . . . . . . . . .27
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3-1
3-2
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4-1
4-2
Interrupt Processing Flowchart. . . . . . . . . . . . . . . . . . . . . . .38
IRQ Function Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .39
5-1
5-2
5-3
Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
RESET and POR Timing Diagram . . . . . . . . . . . . . . . . . . . .45
COP Watchdog Timer Location . . . . . . . . . . . . . . . . . . . . . .48
6-1
6-2
6-3
Single-Chip Mode Pinout of the MC68HC05CT4 . . . . . . . . .51
Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .52
STOP/WAIT Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
7-1
7-2
Port C Pullup Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
8-1
8-2
8-3
16-Bit Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .61
Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . .64
Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . .65
MC68HC05CT4 — Rev. 2.0
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List of Figures
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A G R E E M E N T
List of Figures
N O N - D I S C L O S U R E
General Release Specification — MC68HC05CT4
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
Page
9-1
9-2
9-3
9-4
9-5
SSI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Serial I/O Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
SSI Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . .73
SSI Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . . .75
SSI Data Register (SDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .76
10-1
10-2
10-3
Core Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .80
Core Timer Control and Status Register (CTCSR) . . . . . . .81
Core Counter Register (CTCR) . . . . . . . . . . . . . . . . . . . . . .83
11-1
11-2
11-3
11-4
11-5
11-6
Dual PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Dual PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .87
12-Bit Reference Counter (PLLRC) . . . . . . . . . . . . . . . . . . .89
16-Bit Transmit Counter (PLLTX) . . . . . . . . . . . . . . . . . . . . .90
16-Bit Receive Counter (PLLRX) . . . . . . . . . . . . . . . . . . . . .91
Counter Structure Block Diagram. . . . . . . . . . . . . . . . . . . . .92
12-1
12-2
12-3
PWM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
PWM Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
PWM Data Register (PWMDR) . . . . . . . . . . . . . . . . . . . . . .96
13-1
13-2
Comparator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .100
Comparator Control/Status Register (CMPCSR) . . . . . . . .101
14-1
Miscellaneous Control Register (MISCR). . . . . . . . . . . . . .105
16-1
Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . .132
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List of Figures
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A G R E E M E N T
Title
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
Figure
R E Q U I R E D
List of Figures
List of Tables
Freescale Semiconductor, Inc...
Table
Title
Page
4-1
Vector Address for Interrupts and Reset . . . . . . . . . . . . . . . . .36
5-1
COP Watchdog Timer Recommendations . . . . . . . . . . . . . . . .48
6-1
Operating Mode Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .49
7-1
I/O PIn Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
9-1
SSI Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
10-1 RTI and COP Rates at 2.048 MHz . . . . . . . . . . . . . . . . . . . . . .82
A G R E E M E N T
General Release Specification — MC68HC05CT4
R E Q U I R E D
Freescale Semiconductor, Inc.
15-1
15-2
15-3
15-4
15-5
15-6
15-7
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . .112
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .113
Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .115
Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .116
Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
18-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
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N O N - D I S C L O S U R E
11-1 PLL Reference Counter Select . . . . . . . . . . . . . . . . . . . . . . . . .87
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
List of Tables
General Release Specification
MC68HC05CT4 — Rev. 2.0
List of Tables
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1.1 Contents
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.3
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.4
Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.4.1
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.4.2
VDD2 and VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.4.3
Maskable Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . .21
1.4.4
OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.4.5
Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.4.6
Port A (PA0–PA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.4.7
Port B (PB0–PB7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.4.8
Port C (PC0–PC7/PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.4.9
Port D (PD0/CMP3+, PD1/CMP1–, PD2/CMP12+,
PD3/CMP2–, PD4/SDIO, PD5/SCK,
and PD6/TCMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.4.10
TCAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.4.11
FinT and FinR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.4.12
PDoutT and PDoutR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.2 Introduction
The MC68HC05CT4 is a 44-pin member of the MC68HC05 Family of
microcontrollers (MCUs), which supports cordless telephone
applications. The memory map includes 5376 bytes of on-chip ROM and
256 bytes of RAM. The microcontroller unit has three 8-bit input/output
(I/O) ports: A, B, and C; and one 7-bit I/O port: D. Port C has pullup
options and keyscan capability. The MC68HC05CT4 includes a bird
core, a bird timer, a synchronous serial interface (SSI), 16-bit timer, a
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A G R E E M E N T
Section 1. General Description
N O N - D I S C L O S U R E
General Release Specification — MC68HC05CT4
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
dual 60-MHz phase-locked loop (PLL), pulse width modulator (PWM),
and an on-chip computer operating properly (COP) watchdog circuit.
Features of the MC68HC05CT4 include:
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
General Description
•
Low Cost
•
HC05 Core
•
44-Pin Plastic Leaded Chip Carrier (PLCC) Package
•
10.24-MHz On-Chip Crystal Oscillator
•
2.048-MHz Internal CPU Speed
•
5136 Bytes of User ROM
•
240 Bytes of Self-Check ROM
•
256 Bytes of On-Chip RAM
•
16-Bit Timer
•
31 Bidirectional I/O Lines
•
Power-Saving Stop and Wait Modes
•
Core Timer
•
Dual 60-MHz PLL
•
Simple Serial with Bidirectional Data (SSI)
•
Keyscan Interrupt with Pullups on Port C
•
Mask Selectable Options:
– COP Watchdog Timer
– Edge-Sensitive or Edge- and Level-Sensitive Interrupt Trigger
– Port C Pullups for Keyscan
– 1-Channel, 6-Bit Pulse Width Modulator (PWM)
•
Three Comparators
•
ROM Security Feature
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•
Six port C pullups
•
The IRQ sensitivity
•
COP enable/disable
Freescale Semiconductor, Inc...
These are nonprogrammable options in that they are selected at the time
of code submission when masks are made. These options are:
PC7PU — Port C7 Pullup
This bit enables or disables the pullup on port C bit 7.
1 = Enables the pullup
0 = Disables the pullup
NOTE:
Since port C bit 7 also is shared with the PWM output, PC7PU cannot be
selected if PWM output is needed.
PC6PU — Port C6 Pullup
This option enables or disables the pullup on port C bit 6.
1 = Enables pullup
0 = Disables pullup
PC5PU — Port C5 Pullup
This option enables or disables the pullup on port C bit 5.
1 = Enables pullup
0 = Disables pullup
PC4PU — Port C4 Pullup
This option enables or disables the pullup on port C bit 4.
1 = Enables pullup
0 = Disables pullup
PC23PU — Port C Bits 2 and 3 Pullups
When PC23PU = 1, the pullups on port C bits 2 and 3 are enabled
simultaneously.
When PC23PU = 0, the pullups on port C bits 2 and 3 are disabled
simultaneously.
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A G R E E M E N T
The MC68HC05CT4 has eight mask options:
N O N - D I S C L O S U R E
1.3 Mask Options
R E Q U I R E D
General Description
Mask Options
Freescale Semiconductor, Inc.
60-MHz DUAL PLL
PD1/CMP1–
PD0/CMP3+
÷5
÷ 40
SSI
PWM
TX PLL
SYNTH
INTERNAL
PROCESSOR
CLOCK
CORE TIMER
SYSTEM
PC3
PC2
PC1
PA1
PA2
PA4
PA5
PA6
PB0
PC0
COP
SYSTEM
PB1
PB2
RESET
IRQ
PA3
PA7
DATA DIRECTION REGISTER
PC4
KEYBOARD SYSTEM
PC5
FinT
PA0
PC7/PWM
PC6
TxPDout
PORT A
PD2/CMP12+
DATA DIRECTION REGISTER
A G R E E M E N T
Freescale Semiconductor, Inc...
PD3/CMP2–
PORT D
PD5/SCK
FinR
VDD2
VSS2
COMPARATORS
PD6/TCMP
RxPDout
PORT B
16-BIT TIMER
SYSTEM
RX PLL
SYNTH
DATA DIRECTION REGISTER
TCAP
DATA DIRECTION REGISTER
OSCILLATOR
PD4/SDIO
N O N - D I S C L O S U R E
10.24 MHz
OSC1
OSC2
PORT C
R E Q U I R E D
General Description
PB3
PB4
PB5
PB6
PB7
CPU
CONTROL
ALU
M68HC05 CPU
CPU REGISTERS
SRAM — 256 BYTES
ACCUMULATOR
INDEX REGISTER
ROM — 5378 BYTES
STACK POINTER
VDD
VSS
PROGRAM COUNTER
CONDITION CODE REG
Figure 1-1. MC68HC05CT4 Block Diagram
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When PC01PU = 1, the pullups on port C bits 0 and 1 are enabled
simultaneously.
When PC01PU = 0, the pullups on port C bits 0 and 1 are disabled
simultaneously.
COP — COP Enable
When the COP option is deselected, the COP watchdog timer is
disabled.
IRQ — IRQ Sensitivity
When the IRQ option is selected (IRQEN = 1), edge- and levelsensitive IRQ is enabled.
When the IRQ option is deselected (IRQEN = 0), edge-only sensitive
IRQ is enabled.
NOTE:
A line over a signal name indicates an active-low signal. For example,
RESET is active low.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
When the COP option is selected, the COP watchdog timer is
enabled.
A G R E E M E N T
PC01PU — Port C Bits 0 and 1 Pullups
R E Q U I R E D
General Description
Mask Options
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PC2
PC1
VDD
PC0
VSS
RESET
IRQ
PA6
PA7
PA5
PA4
6
PA3
7
PC3
PC4
PA1
PC5
PA0
PC6
PB0
PC7/PWM
12
34
TCAP
PB2
PD6/TCMP
PB3
PD5/SCK
PB4
PD4/SDIO
PB5
PD3/CMP2–
17
29
PD2/CMP12+
PD0/CMP3+
OSC2
28
OSC1
PDoutR
FinT
PDouT
PB7
23
VDD2
18
VSS2
PB6
FinR
A G R E E M E N T
39
PA2
PB1
Freescale Semiconductor, Inc...
40
1
PD1/CMP1–
R E Q U I R E D
General Description
PA4
PA5
PA6
PA7
IRQ
RESET
VSS
VDD
PC0
PC1
PC2
44
43
42
41
40
39
38
37
36
35
34
PA3
1
33
PC3
PA2
2
32
PC4
PA1
3
31
PC5
23
PD2/CMP12+
22
11
PD1/CMP1–
PB6
PD0/CMP3+
PD3/CMP2–
21
PD4/SDIO
24
20
25
10
OSC2
9
PB5
19
PB4
18
PD5/SCK
OSC1
PD6/TCMP
26
VSS2
27
8
17
7
PB3
FinR
PB2
16
TCAP
PDoutR
28
15
6
PDoutT
PB1
14
PC7
FinT
PC6
29
13
30
5
12
4
PB7
PA0
PB0
VDD2
N O N - D I S C L O S U R E
Figure 1-2. 44-Lead PLCC Pinout
Figure 1-3. 44-Lead QFP Pinout
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1.4.1 VDD and VSS
Freescale Semiconductor, Inc...
Power is supplied to the microcontroller’s digital circuits using these two
pins. VDD is the positive supply and VSS is ground.
1.4.2 VDD2 and VSS2
Power is supplied to noise-susceptible circuitry such as the phaselocked loop (PLL), comparators, and oscillators that require “cleaner”
supplies using these two pins. VDD2 is the positive supply and VSS2 is
ground.
1.4.3 Maskable Interrupt Request (IRQ)
This pin has a mask option as specified by the user that provides one of
two different choices of interrupt triggering sensitivity. The options are:
1. Negative edge-sensitive triggering only
2. Both negative edge-sensitive and level-sensitive triggering
The microcontroller unit (MCU) completes the current instruction before
it responds to the interrupt request. When IRQ goes low for at least one
tILIH, a logic 1 is latched internally to signify that an interrupt has been
requested. When the MCU completes its current instruction, the interrupt
latch is tested. If the interrupt latch contains a logic 1 and the interrupt
mask bit (I bit) in the condition code register is clear, the MCU then
begins the interrupt sequence.
If the option is selected to include level-sensitive triggering, the IRQ input
requires an external resistor to VDD for wire-OR operation.
The IRQ pin contains an internal Schmitt trigger as part of its input to
improve noise immunity.
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A G R E E M E N T
The following paragraphs describe the signals.
N O N - D I S C L O S U R E
1.4 Signal Description
R E Q U I R E D
General Description
Signal Description
Freescale Semiconductor, Inc.
NOTE:
These pins provide control input for an on-chip clock oscillator circuit that
drives the PLL reference source. A crystal resonator, a ceramic
resonator, or an external signal connects to these pins providing a
system clock. The oscillator frequency is selectable between 5 or 40
times the internal bus rate. Typical oscillator configurations and
component values are shown in Figure 1-4. The manufacturer of the
crystal should be consulted, since actual component values are
dependent on the type of crystal used.
Freescale Semiconductor, Inc...
N O N - D I S C L O S U R E
The voltage on the IRQ pin affects the mode of operation. See Section
6. Operating Modes.
1.4.4 OSC1 and OSC2
A G R E E M E N T
R E Q U I R E D
General Description
MCU
OSC1
MCU
OSC2
OSC1
OSC2
10 MΩ
UNCONNECTED
< EXTERNAL CLOCK
15 pF
10.24 MHz
15 pF
(a) Crystal/Ceramic Resonator
Oscillator Connections
(b) External Clock Source
Connections
Figure 1-4. Oscillator Connections
1.4.5 Reset (RESET)
This active-low pin is used to reset the MCU to a known startup state by
pulling RESET low. The RESET pin contains an internal Schmitt trigger
as part of its input to improve noise immunity. See Section 5. Resets.
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1.4.7 Port B (PB0–PB7)
These eight I/O lines comprise port B. The state of any pin is software
programmable and all port B lines are configured as input during poweron or reset.
1.4.8 Port C (PC0–PC7/PWM)
These eight I/O lines comprise port C. All port C lines are configured as
input during power-on or reset. Port C has pullup devices and interrupt
capability by pin; however, the state of any pin is determined by the user
at the time of code submission. For a detailed description of I/O
programming, refer to 7.7 Input/Output Port Pin Programming. PC7 is
shared with the output of the pulse-width modulation (PWM) function.
1.4.9 Port D (PD0/CMP3+, PD1/CMP1–, PD2/CMP12+, PD3/CMP2–, PD4/SDIO,
PD5/SCK, and PD6/TCMP)
These seven port lines comprise port D. The state of any pin is software
programmable and the lines are configured as input during power-on or
reset. PD4 and PD5 are shared with the SSI subsystem, PD6 is shared
with the 16-bit timer subsystem, and PD0–PD3 are shared with the
comparators. For a detailed description on I/O programming, refer to
7.7 Input/Output Port Pin Programming.
1.4.10 TCAP
This pin is used for the16-bit timer input capture operation. Depending
on the value of the IEDG bit in the timer control register (TCR), the
appropriate level of transition on TCAP will be monitored. When the
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These eight I/O lines comprise port A. The state of any pin is software
programmable, and all port A lines are configured as input during poweron or reset.
N O N - D I S C L O S U R E
1.4.6 Port A (PA0–PA7)
R E Q U I R E D
General Description
Signal Description
Freescale Semiconductor, Inc.
correct level of transition has occurred, the free-running counter will be
transferred to the input capture register.
1.4.11 FinT and FinR
These pins are inputs to the PLL transmit and the receive counters,
respectively. They typically are driven by the loop VCO and are also
AC-coupled. The minimum input signal level is 200 mV peak to peak
@ 60.0 MHz.
1.4.12 PDoutT and PDoutR
These PLL pins are 3-state outputs of the transmit and receive phase
detectors, respectively, for use as either loop error signals or phase
detector signals.
N O N - D I S C L O S U R E
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2.1 Contents
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.4
Read-Only Memory (ROM). . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.5
ROM Security Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.6
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . .26
2.2 Introduction
This section describes the organization of the on-chip memory. The
MC68HC05CT4 8-Kbyte memory map is shown in Figure 2-1 and the
input/output (I/O) registers in Figure 2-2.
2.3 Memory Map
The MC68HC05CT4 has an 8-Kbyte memory map consisting of user
read-only memory (ROM), random-access memory (RAM), self-check
ROM, and I/O.
2.4 Read-Only Memory (ROM)
The user ROM consists of 5120 bytes of ROM located from $0B00 to
$1EFF and 16 bytes of user vectors located from $1FF0 to $1FFF.
The self-check ROM is located from $1F00 to $1FEF.
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Section 2. Memory
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Memory
Twelve of the user vectors, $1FF4–$1FFF, are dedicated to reset and
interrupt vectors. The four remaining locations — $1FF0, $1FF1, $1FF2,
and $1FF3 — are general-purpose user ROM locations.
2.5 ROM Security Feature
A security feature has been incorporated into the MC68HC05CT4 to
help prevent external viewing of the ROM contents. This feature aids in
maintaining the security of proprietary information in customerdeveloped software.1
2.6 Random-Access Memory (RAM)
The user RAM consists of 256 bytes of a shared stack area. The RAM
starts at address $0030 and ends at address $012F. The stack begins
at address $00FF. The stack pointer can access 64 bytes of RAM in the
range $00FF to $00C0.
NOTE:
Using the stack area for data storage or temporary work locations
requires care to prevent it from being overwritten due to stacking from an
interrupt or subroutine call.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the ROM difficult for unauthorized users.
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$0000
Reserved
13 Bytes
RAM
208 Bytes
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$00C0
$00FF
$0100
$012F
$0130
User ROM
5120 Bytes
$1FEF
$1FF0
$1FFF
Self-Check ROM
240 Bytes
ROM User Vectors
16 Bytes
$0022
$00
Port B Data Register
$01
Port C Data Register
$02
Port D Data Register
$03
PLL
8 Bytes
Port A Data Direction Register
$04
Port B Data Direction Register
$05
Timer
10 Bytes
$0AFF
$0B00
Port A Data Register
Core Timer
2 Bytes
Reserved
1 Byte
Stack
64 Bytes
RAM
48 Bytes
Unused
2512 Bytes
$1EFF
$1F00
$1F01
Ports
8 Bytes
Port C Data Direction Register
$06
Port D Data Direction Register
$07
Core Timer Control/Status Register
Core Timer Counter Register
$08
$09
SSI
3 Bytes
PLL Control Register
$0A
PLL Ref. Counter MSB
$0B
Reserved
PLL Ref. Counter LSB
$0C
PWM
1 Byte
Transmit PLL MSB
$0D
Transmit PLL LSB
$0E
Miscellaneous
1 Byte
Receive PLL MSB
$0F
Receive PLL LSB
$10
Reserved
$11
Timer Control Register
$12
Timer Status Register
$13
Input Capture MSB
$14
Input Capture LSB
$15
Output Compare MSB
$16
Output Compare LSB
$17
Counter MSB
$18
Counter LSB
$19
Alternate Counter MSB
$1A
Alternate Counter LSB
$1B
SSI Status Register
$1C
SSI Data Register
$1D
SSI Control Register
$1E
Comparators
1 Byte
Reserved
$1F
PWM Data Register
$20
Miscellaneous Register
$21
Comparator Control/Status Register
$22
Figure 2-1. MC68HC05CT4 8-K Memory Map
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$0022
$0023
$002F
$0030
I/O
35 Bytes
N O N - D I S C L O S U R E
$0000
R E Q U I R E D
Memory
Random-Access Memory (RAM)
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A G R E E M E N T
R E Q U I R E D
Memory
Addr
Register Name
Bit 7
$00
Port A Data Register
$01
Port B Data Register
$02
Port C Data Register
$03
Port D Data Register
$04
Port A Data Direction Register
$05
Port B Data Direction Register
$06
Port C Data Direction Register
$07
Port D Data Direction Register
$08
6
5
4
3
2
1
0
RTIF
TOFE
RTIE
TOFC
RTFC
RT1
RT0
TXON
RXON
PLS1
PLS0
0
0
Timer Control and Status Register CTOF
$09
Timer Counter Register
$0A
PLL Control Register
0
$0B
PLL Reference Counter — MSB
0
0
0
0
$0C
PLL Reference Counter — LSB
$0D
PLL Transmit Counter — MSB
$0E
PLL Transmit Counter — LSB
$0F
PLL Receive Counter — MSB
$10
PLL Receive Counter — LSB
$11
Reserved
R
R
R
R
R
R
R
R
$12
Timer Control Register
ICIE
OCIE
TOIE
0
0
TON
IEDGE
OLVL
$13
Timer Status Register
ICF
OCF
0
0
0
0
0
0
$14
Timer Input Capture — MSB
$15
Timer Input Capture — LSB
$16
Timer Output Compare — MSB
$17
TImer Output Compare — LSB
$18
Timer Counter — MSB
$19
Timer Counter — LSB
R
TLOCK RLOCK REFON
= Reserved
Figure 2-2. I/O Registers
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Bit 7
6
5
4
3
2
1
0
SF
DCOL
0
0
0
0
0
0
SIE
SE
LSBF
MSTR
CPOL
T/R
SR1
SR0
R
R
R
R
R
R
$1A
Timer Alternate Counter — MSB
$1B
TImer Alternate Counter — LSB
$1C
SSI Status Register
$1D
SSI Data Register
$1E
SSI Control Register
$1F
Reserved
R
R
$20
PWM Data Register
0
0
$21
Miscellaneous Register
0
0
0
0
SPEED
COE
PWME
0
CMP2
CMP1
CM3IE
CM3IC
CEN3
CEN2
CEN1
$22
Comparator Control/Status Register CMP3
R
= Reserved
Figure 2-2. I/O Registers (Continued)
A G R E E M E N T
Register Name
N O N - D I S C L O S U R E
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Addr
R E Q U I R E D
Memory
Random-Access Memory (RAM)
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Memory
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3.1 Contents
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.3
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.4
Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.5
Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.6
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.7
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.2 Introduction
The MCU contains five registers as shown in Figure 3-1. The interrupt
stacking order is shown in Figure 3-2.
7
0
A
ACCUMULATOR
7
0
X
INDEX REGISTER
12
0
PC
7
12
0
PROGRAM COUNTER
0
0
0
0
1
0
1
SP
STACK POINTER
CCR
H
I
N
Z
C
CONDITION CODE REGISTER
Figure 3-1. Programming Model
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Section 3. Central Processing Unit
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R E Q U I R E D
Central Processing Unit
7
0
1
INCREASING
MEMORY
ADDRESSES
1
R
E
T
U
R
N
1
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
PCH
PCL
STACK
I
N
T
E
R
R
U
P
T
DECREASING
MEMORY
ADDRESSES
UNSTACK
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A G R E E M E N T
NOTE: Since the stack pointer decrements during pushes, the PCL is stacked
first, followed by PCH, etc. Pulling from the stack is in the reverse order.
Figure 3-2. Stacking Order
3.3 Accumulator
The accumulator (A) is a general-purpose 8-bit register used to hold
operands and results of arithmetic calculations or data manipulations.
7
0
A
3.4 Index Register
The index register (X) is an 8-bit register used for the indexed
addressing value to create an effective address. The index register may
also be used as a temporary storage area.
7
0
X
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3.5 Condition Code Register
The condition code register (CCR) is a 5-bit register in which the H, N,
Z, and C bits are used to indicate the results of the instruction just
executed, and the I bit is used to enable interrupts. These bits can be
tested individually by a program, and specific actions can be taken as a
result of their state. Each bit is explained in the following paragraphs.
CCR
N
Z
C
Half Carry (H)
This bit is set during ADD and ADC operations to indicate that a carry
occurred between bits 3 and 4.
Interrupt (I)
When this bit is set, the timer and external interrupt are masked
(disabled). If an interrupt occurs while this bit is set, the interrupt is
latched and processed as soon as the I bit is cleared.
Negative (N)
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was negative.
Zero (Z)
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was zero.
Carry/Borrow (C)
When set, this bit indicates that a carry or borrow out of the arithmetic
logical unit (ALU) occurred during the last arithmetic operation. This
bit also is affected during bit test and branch instructions and during
shifts and rotates.
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I
N O N - D I S C L O S U R E
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H
R E Q U I R E D
Central Processing Unit
Condition Code Register
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A G R E E M E N T
R E Q U I R E D
Central Processing Unit
3.6 Stack Pointer
The stack pointer contains the address of the next free location on the
stack. During an MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set to location $00FF. The stack pointer then is
decremented as data is pushed onto the stack and incremented as data
is pulled from the stack.
When accessing memory, the seven most significant bits (MSB) are
permanently set to 0000011. These seven bits are appended to the six
least significant register bits to produce an address within the range of
$00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal)
locations. If 64 locations are exceeded, the stack pointer wraps around
and loses the previously stored information. A subroutine call occupies
two locations on the stack; an interrupt uses five locations.
12
0
0
0
0
0
7
1
0
1
SP
3.7 Program Counter
The program counter (PC) is a 13-bit register that contains the address
of the next byte to be fetched. .
12
0
PC
NOTE:
The HC05 CPU core is capable of addressing 16-bit locations. For this
implementation, however, the addressing registers are limited to
an 8-Kbyte memory map
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4.1 Contents
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.3
CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4.4
Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
4.5
Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
4.6
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.7
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.8
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.9
16-Bit Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.10
SSI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.11
Core Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.12
Comparator 3 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.2 Introduction
The MCU can be interrupted seven different ways:
1. Nonmaskable software interrupt instruction (SWI)
2. External asynchronous interrupt (IRQ)
3. External interrupt via IRQ on PC0–PC7
4. Internal 16-bit timer interrupt (TIMER)
5. Internal synchronous serial interface (SSI) interrupt
6. Internal core timer interrupt
7. Comparator 3
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Section 4. Interrupts
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A G R E E M E N T
R E Q U I R E D
Interrupts
4.3 CPU Interrupt Processing
Interrupts cause the processor to save register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike
RESET, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is complete.
If interrupts are not masked (I bit in the CCR is clear) and the
corresponding interrupt enable bit is set, the processor will proceed with
interrupt processing. Otherwise, the next instruction is fetched and
executed. If an interrupt occurs, the processor completes the current
instruction, stacks the current CPU register states, sets the I bit to inhibit
further interrupts, and finally checks the pending hardware interrupts. If
more than one interrupt is pending after the stacking operation, the
interrupt with the highest vector location shown in Table 4-1 will be
serviced first. The SWI is executed the same as any other instruction,
regardless of the I-bit state.
When an interrupt is to be processed, the CPU fetches the address of
the appropriate interrupt software service routine from the vector table at
locations $1FF4–$1FFF as defined in Table 4-1.
Table 4-1. Vector Address for Interrupts and Reset
Register
Flag
Name
N/A
N/A
Reset
N/A
N/A
Software
CMCSR
CMP3
TSR
OCF, ICF, TOF
SSSR
SSIF
CTCSR
TOFE, RTIE
Interrupt
CMP3, External Interrupts*
16-bit Timer Interrupts
SSI Interrupt
Core Timer Interrupts
CPU
Interrupt
Vector
Address
RESET
$1FFE–$1FFF
SWI
$1FFC–$1FFD
CMP3/IRQ
$1FFA–$1FFB
TIMER
$1FF8–$1FF9
SSI
$1FF6–$1FF7
TIMER, RTI
$1FF4–$1FF5
* External interrupts include IRQ and PORTC sources.
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A return-to-interrupt (RTI) instruction is used to signify when the interrupt
software service routine is completed. The RTI instruction causes the
register contents to be recovered from the stack and normal processing
to resume at the next instruction that was to be executed when the
interrupt took place. Figure 4-1 shows the sequence of events that
occurs during interrupt processing.
4.4 Reset Interrupt Sequence
The reset function is not in the strictest sense an interrupt; however, it is
acted upon in a similar manner as shown in Figure 4-1. A low-level input
on the RESET pin or an internally generated RST signal causes the
program to vector to its starting address, which is specified by the
contents of memory locations $1FFE and $1FFF. The I bit in the
condition code register is also set. The MCU is configured to a known
state during this type of reset as described in 4.3 CPU Interrupt
Processing.
4.5 Software Interrupt (SWI)
The SWI is an executable instruction and a nonmaskable interrupt since
it is executed regardless of the state of the I bit in the CCR. If the I bit is
zero (interrupts enabled), the SWI instruction executes after interrupts
that were pending before the SWI was fetched or before interrupts
generated after the SWI was fetched. The interrupt service routine
address is specified by the contents of memory locations $1FFC
and $1FFD.
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Latency = (Longest instruction execution time + 10) x tcyc seconds
N O N - D I S C L O S U R E
The M68HC05 CPU does not support interruptible instructions. The
maximum latency to the first instruction of the interrupt service routine
must include the longest instruction execution time plus stacking
overhead.
R E Q U I R E D
Interrupts
Reset Interrupt Sequence
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R E Q U I R E D
Interrupts
FROM
RESET
Y
A G R E E M E N T
N
IRQ
EXTERNAL
INTERRUPT
CMP3
Y
CLEAR IRQ
REQUEST
LATCH
N
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N O N - D I S C L O S U R E
I BIT
IN CCR
SET?
INTERNAL
16-BIT TIMER
INTERRUPT
Y
N
INTERNAL
SSI
INTERRUPT
N
INTERNAL
CORE TIMER
INTERRUPT
Y
Y
N
STACK
PC, X, A, CCR
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION
?
SET I BIT IN
CC REGISTER
Y
LOAD PC FROM
APPROPRIATE
VECTOR
N
Y
RTI
INSTRUCTION
?
N
EXECUTE
INSTRUCTION
RESTORE REGISTERS
FROM STACK:
CCR, A, X, PC
Figure 4-1. Interrupt Processing Flowchart
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4.7 External Interrupt (IRQ)
The IRQ pin provides an asynchronous interrupt to the CPU. A block
diagram of the IRQ function is shown in Figure 4-2.
NOTE:
The BIH and BIL instructions will apply only to the level on the IRQ pin
itself, and not to the output of the logic OR function with the port C IRQ
interrupts. The state of the individual port C pins can be checked by
reading the appropriate port C pins as inputs.
IRQ PIN
TO BIH & BIL
INSTRUCTION
SENSING
VDD
IRQ
LATCH
PORT C
IRQ VECTOR FETCH
R
TO IRQ
PROCESSING
IN CPU
RST
LEVEL
(MASK OPTION)
Figure 4-2. IRQ Function Block Diagram
The IRQ pin is one source of an external interrupt. All port C pins
(PC0–PC7) act as other external interrupt sources if the keyscan feature
is enabled as specified by the user.
When edge sensitivity is selected for the IRQ interrupt, it is sensitive to:
•
Falling edge on the IRQ pin
•
Falling edge on any port C pin with keyscan enabled
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All hardware interrupts except RESET are maskable by the I bit in the
CCR. If the I bit is set, all hardware interrupts (internal and external) are
disabled. Clearing the I bit enables the hardware interrupts. The two
types of hardware interrupts are explained in the following sections.
N O N - D I S C L O S U R E
4.6 Hardware Interrupts
R E Q U I R E D
Interrupts
Hardware Interrupts
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R E Q U I R E D
Interrupts
When edge and level sensitivity is selected for the IRQ interrupt, it is
sensitive to the following cases:
•
Low level on the IRQ pin
•
Falling edge on the IRQ pin
•
Falling edge or low level on any port C pin with keyscan enabled
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A G R E E M E N T
4.8 External Interrupt Timing
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts
(internal and external) are disabled. Clearing the I bit enables interrupts.
The interrupt request is latched immediately following the falling edge of
the IRQ source. The interrupt request is then synchronized internally and
serviced as specified by the contents of $1FFA and $1FFB.
Either a level-sensitive and edge-sensitive trigger or an edge-sensitiveonly trigger is available via the mask programmable option for
the IRQ pin.
4.9 16-Bit Timer Interrupt
Three different timer interrupt flags cause a timer interrupt whenever
they are set and enabled. The interrupt flags are in the timer status
register (TSR), and the enable bits are in the timer control register
(TCR). Any of these interrupts vector to the same interrupt service
routine, located at the address specified by the contents of memory
locations $1FF8 and $1FF9.
4.10 SSI Interrupt
Two different synchronous serial interrupt (SSI) flags cause an SSI
interrupt whenever they are set and enabled. The interrupt flags are in
the SSI status register (SSSR), and the enable bits are in the SSI control
register (SSCR). Either of these interrupts vector to the same interrupt
service routine, located at the address specified by the contents of
memory locations $1FF6 and $1FF7.
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4.12 Comparator 3 Interrupt
Comparator 3 can create an interrupt when its output (CMP3) gets set
and the enable bit CM3IE is set. The interrupt service routine is located
at the address specified by the contents of memory locations $1FFA and
$1FFB.
N O N - D I S C L O S U R E
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This timer can create two types of interrupts. A timer overflow interrupt
occurs whenever the 8-bit timer rolls over from $FF to $00 and the
enable bit TOFE is set. A real-time interrupt occurs whenever the
programmed time elapses and the enable bit RTIE is set. Either of
these interrupts vector to the same interrupt service routine, located at
the address specified by the contents of memory locations $1FF4 and
$1FF5.
A G R E E M E N T
4.11 Core Timer Interrupt
R E Q U I R E D
Interrupts
Core Timer Interrupt
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R E Q U I R E D
Interrupts
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5.1 Contents
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.3
External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.4
Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.4.1
Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.4.2
Computer Operating Properly Reset (COPR) . . . . . . . . . . .46
5.4.2.1
Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.4.2.2
COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .47
5.4.2.3
COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .47
5.4.2.4
COP Watchdog Timer Considerations . . . . . . . . . . . . . . .47
5.4.2.5
COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
5.4.3
Illegal Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
5.2 Introduction
The MCU can be reset from four sources: one external input and three
internal restart conditions. The RESET pin is an input with a Schmitt
trigger as shown in Figure 5-1. All the internal peripheral modules will be
reset by the internal reset signal (RST). Refer to Figure 5-2 for reset
timing detail.
5.3 External Reset (RESET)
The RESET pin is the only external source of a reset. This pin is
connected to a Schmitt trigger input gate to provide an upper and lower
threshold voltage separated by a minimum amount of hysteresis. This
external reset occurs whenever the RESET pin is pulled below the lower
threshold and remains in reset until the RESET pin rises above the
upper threshold. This active-low input will generate the RST signal and
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Section 5. Resets
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Resets
reset the CPU and peripherals. Termination of the external RESET input
or the internal COP watchdog reset are the only reset sources that can
alter the operating mode of the MCU.
NOTE:
Activation of the RST signal is generally referred to as reset of the
device, unless otherwise specified.
TO IRQ
LOGIC
IRQ/VTST
D
LATCH
MODE
SELECT
RESET
R
CLOCKED
OSC
DATA
ADDRESS
COP WATCHDOG
(COPR)
CPU
VDD
POWER-ON RESET
(POR)
ADDRESS
ILLEGAL ADDRESS
(ILLADDR)
S
D
LATCH
RST
TO OTHER
PERIPHERALS
PH2
Figure 5-1. Reset Block Diagram
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DD
0V
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NEW
PCL
1FFF
tCYC
NEW
PC
OP
CODE
NEW
PC
3
RL
t
1FFE
1FFE
1FFE
PCH
1FFE
PCL
1FFF
NEW
PC
General Release Specification
N O N - D I S C L O S U R E
A G R E E M E N T
Figure 5-2. RESET and POR Timing Diagram
> VPOR 4
R E Q U I R E D
OP
CODE
NEW
PC
NOTES:
1. Internal timing signal and bus information not available externally
2. OSC1 line is not meant to represent frequency. It is only used to represent time.
3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
4. VDD must fall to a level lower than VPOR to be recognized as a power-on reset.
NEW
PCH
INTERNAL
DATA
BUS1
RESET
1FFE
4064 tCYC
INTERNAL
ADDRESS
BUS1
INTERNAL
PROCESSOR
CLOCK1
OSC12
V
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Resets
External Reset (RESET)
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A G R E E M E N T
R E Q U I R E D
Resets
5.4 Internal Resets
The three internally generated resets are the initial power-on reset
function, the COP watchdog timer reset, and the illegal address detector.
Termination of the external RESET input or the internal COP watchdog
timer are the only reset sources that can alter the operating mode of the
MCU. The other internal resets do not have any effect on the mode of
operation when their reset state ends.
5.4.1 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and is not
able to detect a drop in the power supply voltage (brown-out). There is
an oscillator stabilization delay of 4064 internal processor bus clock
cycles (PH2) after the oscillator becomes active.
The POR generates the RST signal that resets the CPU. If any other
reset function is active at the end of this 4064-cycle delay, the RST
signal remains in the reset condition until the other reset condition(s)
end. During the POR, the RESET pin is forced low.
5.4.2 Computer Operating Properly Reset (COPR)
The MCU contains a watchdog timer that automatically times out if not
reset (cleared) within a specific time by a program reset sequence. If the
COP watchdog timer is allowed to time out, an internal reset is
generated to reset the MCU. Regardless of an internal or external
RESET, the MCU comes out of a COP reset according to the standard
rules of mode selection.
The COP reset function is enabled or disabled by a mask option and is
verified during production testing.
5.4.2.1 Resetting the COP
Writing a zero to the COPF bit prevents a COP reset. This action resets
the counter and begins the timeout period again. The COPF bit is bit 0
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5.4.2.2 COP During Wait Mode
5.4.2.3 COP During Stop Mode
When the stop enable mask option is selected, stop mode disables the
oscillator circuit and thereby turns the clock off for the entire device.
When STOP is executed, the COP counter will hold its current state. If a
reset is used to exit stop mode, the COP counter is reset and held until
4064 POR cycles are completed, at that time, counting will begin. If an
external IRQ is used to exit stop mode, the COP counter does not wait
for the completion of the 4064 POR cycles but it does count these
cycles. It is recommended, therefore, that the COP is fed before
executing the STOP instruction.
5.4.2.4 COP Watchdog Timer Considerations
The COP watchdog timer is active in all modes of operation if enabled
by a mask option. If the COP watchdog timer is selected by a mask
option, any execution of the STOP instruction (either intentional or
inadvertent due to the CPU being disturbed) causes the oscillator to halt
and prevent the COP watchdog timer from timing out. If the COP
watchdog timer is selected by a mask option, the COP resets the MCU
when it times out. Therefore, it is recommended that the COP watchdog
is disabled for a system that must have intentional uses of the wait
mode for periods longer than the COP timeout period.
The recommended interactions and considerations for the COP
watchdog timer, STOP instruction, and WAIT instruction are
summarized in Table 5-1.
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The COP continues to operate normally during wait mode. The software
should pull the device out of wait mode periodically and reset the COP
by writing to the COPF bit to prevent a COP reset.
A G R E E M E N T
of address $1FF0. A read of address $1FF0 returns user data
programmed at that location.
R E Q U I R E D
Resets
Internal Resets
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R E Q U I R E D
Resets
Table 5-1. COP Watchdog Timer Recommendations
IF the following conditions exist:
THEN the COP Watchdog Timer should be:
WAIT Time
WAIT Time less than COP Timeout
Enable or Disable COP by Mask Option
WAIT Time More than COP Timeout
Disable COP by Mask Option
Any length WAIT Time
Disable COP by Mask Option
5.4.2.5 COP Register
The COP register is shared with the MSB of an unimplemented user
interrupt vector as shown in Figure 5-3. Reading this location returns
whatever user data has been programmed at this location. Writing a zero
to the COPR bit in this location clears the COP watchdog timer.
Addr
$1FF0
Register Name
Unimplemented Vector Read:
and COP Watchdog Timer Write:
Bit 7
6
5
4
3
2
1
Bit 0
X
X
X
X
X
X
X
X
COPR
= Unimplemented
Figure 5-3. COP Watchdog Timer Location
5.4.3 Illegal Address
An illegal address reset is generated when the CPU attempts to fetch an
instruction from either unimplemented address space ($0130 to $0AFF)
or I/O address space ($0000 to $002F).
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6.1 Contents
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
6.3
Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
6.4
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
6.4.1
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
6.4.2
Stop Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
6.4.3
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
6.4.4
Low-Power Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6.2 Introduction
The MCU has two modes of operation: single-chip mode and self-check
mode with two oscillator options. Table 6-1 shows the conditions
required to go into each mode.
Table 6-1. Operating Mode Conditions
RESET
IRQ
PB1
PD5
MODE
VSS–VDD
VSS–VDD
VSS–VDD
Single-Chip
VTST
VDD
VSS
Self-Check
VTST = 2 x VDD
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Section 6. Operating Modes
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Operating Modes
6.3 Single-Chip Mode
In single-chip mode, the address and data buses are not available
externally, but there are three 8-bit input/output (I/O) ports and one 7-bit
I/O port. This mode allows the MCU to function as a self-contained
microcontroller, with maximum use of the pins for on-chip peripheral
functions. All address and data activity occurs within the MCU. Singlechip mode is entered on the rising edge of RESET if the IRQ pin is within
normal operating range.
6.4 Low-Power Modes
The following paragraphs describe the low-power modes.
6.4.1 Stop Mode
The STOP instruction places the MCU in its lowest power-consumption
mode. In stop mode, the internal oscillator is turned off, halting all
internal processing, including timer operation.
During stop mode, the CTCSR ($08) bits are altered to remove any
pending timer interrupt request and to disable any further timer
interrupts. The timer prescaler is cleared. The I bit in the CCR is cleared
to enable external interrupts. All other registers and memory remain
unaltered. All input/output lines remain unchanged. The processor can
be brought out of stop mode only by an external interrupt or reset.
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39
PC3
PA2
PC4
PA1
PC5
PA0
PC6
PB0
PC7/PWM
PB1
12
34
TCAP
PB2
PD6/TCMP
PB3
PD5/SCK
PB4
PD4/SDIO
PB5
PD3/CMP2–
17
29
PD2/CMP12+
PD1/CMP1–
PD0/CMP3+
OSC2
OSC1
28
VSS2
PDoutR
23
FinT
PDouT
PB7
18
FinR
PB6
VDD2
Figure 6-1. Single-Chip Mode Pinout of the MC68HC05CT4
6.4.2 Stop Recovery
The processor can be brought out of the stop mode only by an external
interrupt or RESET. See Figure 6-2.
6.4.3 Wait Mode
The WAIT instruction places the MCU in a low power-consumption
mode, but the wait mode consumes more power than the stop mode. All
CPU action is suspended, but the core timer, the oscillator, and any
enabled module remain active. Any interrupt or reset will cause the MCU
to exit the wait mode. The user must shut off subsystems to reduce
power consumption. WAIT current specifications assume CPU
operation only and do not include current consumption by any other
subsystems.
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7
R E Q U I R E D
PA3
40
1
A G R E E M E N T
6
PC2
PC1
VDD
PC0
VSS
RESET
IRQ
PA6
PA7
PA5
PA4
Operating Modes
Low-Power Modes
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Operating Modes
OSC11
tRL
RESET
tLIH
IRQ2
tILCH
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A G R E E M E N T
IRQ3
4064 tcyc
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
1FFE
1FFE
1FFE
NOTES:
1. Represents the internal gating of the OSC1 pin
2. IRQ pin edge-sensitive mask option
3. IRQ pin level- and edge-sensitive mask option
1FFE
1FFF
RESET OR INTERRUPT
VECTOR FETCH
Figure 6-2. Stop Recovery Timing Diagram
During wait mode, the I bit in the CCR is cleared to enable interrupts. All
other registers, memory, and input/output lines remain in their previous
state. The timer may be enabled to allow a periodic exit from wait mode.
6.4.4 Low-Power Wait
When the wait mode is entered by executing the WAIT instruction, the
oscillator divider changes from a divide-by-5 to a divide-by-40 (additional
divide-by-8) to lower the wait current. As a result, this gives a CPU clock
rate of 256 kHz if the oscillator is running with a 10.24-MHz crystal. The
oscillator divide-by-5 or divide-by-40 option is also controlled by the
speed bit located in the miscellaneous control register ($21).
Section 14. Miscellaneous Register. When returning from wait mode
via an interrupt, the OSC rate prior to entering wait mode is restored.
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CLEAR I BIT
N
N
EXTERNAL
INTERRUPT
(IRQ)
OSCILLATOR ACTIVE
TIMER CLOCK ACTIVE
PROCESSOR CLOCKS STOPPED
CLEAR I BIT
RESET
RESET
Y
Y
N
EXTERNAL
INTERRUPT
(IRQ)
Y
Y
Y
TURN ON OSCILLATOR
WAIT FOR TIME
DELAY TO STABILIZE
1. FETCH
RESET
VECTOR OR
2 SERVICE
INTERRUPT
A. STACK
B. SET I BIT
C. VECTOR TO
INTERRUPT
ROUTINE
A G R E E M E N T
STOP OSCILLATOR
AND ALL CLOCKS
WAIT
TIMER
INTERRUPT
N
RESTART
PROCESSOR CLOCK
Y
1. FETCH
RESET
VECTOR OR
2. SERVICE INTERRUPT
A. STACK
B. SET I BIT
C. VECTOR TO
INTERRUPT
ROUTINE
N
SSI
INTERRUPT
N
Y
CORE TIMER
INTERRUPTS
N
Figure 6-3. STOP/WAIT Flowchart
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STOP
R E Q U I R E D
Operating Modes
Low-Power Modes
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R E Q U I R E D
Operating Modes
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7.1 Contents
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
7.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
7.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
7.7
Input/Output Port Pin Programming . . . . . . . . . . . . . . . . . . . . .57
7.2 Introduction
In user mode 31 lines are arranged as one 7-bit and three 8-bit ports.
Most of these port pins are programmable as either inputs or outputs
under software control of the data direction registers, though some are
input only.
NOTE:
To avoid a glitch on the output pins, write data to the I/O port data
register before writing a logic 1 to the corresponding data direction
register.
7.3 Port A
Port A is an 8-bit bidirectional port that does not share any of its pins with
other subsystems. The port A data register is at $0000 and the data
direction register (DDR) is at $0004. Reset does not affect the data
registers, but clears the data direction registers, thereby returning the
ports to inputs. Writing a logic 1 to a DDR bit sets the corresponding port
bit to output mode.
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A G R E E M E N T
Section 7. Parallel Input/Output (I/O)
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Parallel Input/Output (I/O)
7.4 Port B
Port B is an 8-bit bidirectional port. The port B data register is at $0001
and the data direction register (DDR) is at $0005. Reset does not affect
the data registers, but clears the data direction registers, thereby
returning the ports to inputs. Writing a logic 1 to a DDR bit sets the
corresponding port bit to output mode.
7.5 Port C
Port C is an 8-bit bidirectional port. The port C data register is at $0002
and the data direction register (DDR) is at $0006. Reset does not affect
the data registers, but clears the data direction registers, thereby
returning the ports to inputs. Writing a logic 1 to a DDR bit sets the
corresponding port pin to output mode. Each of the port C pins has an
optional pullup device. When the DDR bit is cleared and the pullup
device is enabled, the pin will be a pullup and an interrupt pin. The edgeor edge- and level-sensitivity of the IRQ pin also pertains to the enabled
port C pins. Care needs to be taken when using port C pins that have the
pullup enabled. Before switching from an output to an input, the data
should be preconditioned to a logic 1 to prevent an interrupt from
occurring. Port C bit 7 is also shared with the PWM output. When PC7
is used as the PWM output, its pullup option should not be selected
(see Figure 7-1).
VDD
VDD
DISABLED
MASK OPTION (PC7PU)
DDR BIT
ENABLED
IRQ
SCHMITT
TRIGGER
PC7
NORMAL PORT CIRCUITRY
AS SHOWN IN FIGURE 7-2
(PC7 ADDS PWM)
TO INTERRUPT
LOGIC
FROM ALL OTHER PORT C PINS
Figure 7-1. Port C Pullup Option
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7.6 Port D
Port D is a 7-bit bidirectional port. Two of its pins are shared with the SSI
subsystem, four are shared with the comparators, and one is shared with
the timer. During reset, all seven bits become valid input ports because
all special function output drivers associated with the timer and SSI
subsystems are disabled.
R E Q U I R E D
Parallel Input/Output (I/O)
Port D
At power-on or reset, all DDRs are cleared, which configures all pins as
inputs. The data direction registers are capable of being written to or
read by the processor. During the programmed output state, a read of
the data register actually reads the value of the output data latch and not
the I/O pin.
Refer to Table 7-1 and to Figure 7-2 for additional information.
Table 7-1. I/O PIn Functions
R/W
DDR
I/O Pin Functions
0
0
The I/O pin is in input mode. Data is written into the output
data latch.
0
1
Data is written into the output data latch and output to the
I/O pin.
1
0
The state of the I/O pin is read.
1
1
The I/O pin is in an output mode. The output data latch is
read.
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A G R E E M E N T
Port pins may be programmed as inputs or outputs under software
control. The direction of the pins is determined by the state of the
corresponding bit in the port data direction register (DDR). Each I/O port
has an associated DDR. Any I/O port pin is configured as an output if its
corresponding DDR bit is set to a logic one. A pin is configured as an
input if its corresponding DDR bit is cleared to a logic 0.
N O N - D I S C L O S U R E
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7.7 Input/Output Port Pin Programming
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R E Q U I R E D
Parallel Input/Output (I/O)
DATA DIRECTION
REGISTER BIT
INTERNAL
HC05
CONNECTIONS
LATCHED OUTPUT
DATA BIT
OUTPUT
I/O
PIN
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A G R E E M E N T
INPUT
REG
BIT
INPUT
I/O
N O N - D I S C L O S U R E
Figure 7-2. I/O Circuitry
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8.1 Contents
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
8.3
Counter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
8.4
Output Compare Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
8.5
Input Capture Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
8.6
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
8.7
Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
8.8
Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
8.9
Timer During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
8.10
Timer Power Supply Source . . . . . . . . . . . . . . . . . . . . . . . . . . .67
8.2 Introduction
The timer consists of a 16-bit, free-running counter driven by a fixed
divide-by-four prescaler. This timer can be used for many purposes,
including input waveform measurements, while simultaneously
generating an output waveform. Pulse widths can vary from several
microseconds to many seconds.
Because the timer has a 16-bit architecture, each specific functional
segment (capability) is represented by two registers. These registers
contain the high and low byte of that functional segment. Access to the
high byte inhibits that specific timer function until the low byte is also
accessed.
NOTE:
The I bit in the CCR should be set while manipulating both the high and
low byte registers of a specific timer function to ensure that an interrupt
does not occur.
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A G R E E M E N T
Section 8. 16-Bit Timer
N O N - D I S C L O S U R E
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R E Q U I R E D
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A G R E E M E N T
R E Q U I R E D
16-Bit Timer
8.3 Counter Register
The key element in the programmable timer is a 16-bit, free-running
counter or counter register, preceded by a prescaler that divides the
internal processor clock by four. The prescaler gives the timer a
resolution of 2.0 microseconds if the internal bus clock is 2.0 MHz. The
counter is incremented during the low portion of the internal bus clock.
Software can read the counter at any time without affecting its value.
The double-byte, free-running counter can be read from either of two
locations, $18–$19 (counter register) or $1A–$1B (counter alternate
register). If a read of the free-running counter or counter alternate
register is from the least significant byte (LSB) ($19, $1B), the LSB
receives the count value at the time of the read. If a read of the freerunning counter or counter alternate register first addresses the most
significant byte (MSB) ($18, $1A), the LSB ($19, $1B) is transferred to a
buffer. This buffer value remains fixed after the first MSB read, even if
the user reads the MSB several times. This buffer is accessed when
reading the free-running counter or counter alternate register LSB ($19
or $1B) and, thus, completes a read sequence of the total counter value.
In reading either the free-running counter or counter alternate register, if
the MSB is read, the LSB also must be read to complete the sequence.
The counter alternate register differs from the counter register in one
respect: a read of the counter register MSB can clear the timer overflow
flag (TOF). The counter alternate register can be read at any time
without the possibility of missing timer overflow interrupts due to clearing
of the TOF.
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HIGH LOW
BYTE BYTE
INTERNAL
PROCESSOR
CLOCK
8-BIT
BUFFER
÷4
$16 OUTPUT
$17 COMPARE
REGISTER
HIGH
BYTE
LOW
BYTE
16-BIT FREE $18
RUNNING
COUNTER $19
HIGH LOW
BYTE BYTE
$14
INPUT
CAPTURE
REGISTER $15
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COUNTER $1A
ALTERNATE
REGISTER $1B
OVERFLOW
DETECT
CIRCUIT
OUTPUT
COMPARE
CIRCUIT
EDGE
DETECT
CIRCUIT
D
TIMER
STATUS ICF OCF TOF $13
REG.
FOLVL
OUTPUT
LEVEL
REG.
Q
CLK
C
TIMER RESET
ICIE OCIE TOIE IEDG OLVL CONTROL
REG.
$12
INTERRUPT CIRCUIT
OUTPUT
LEVEL
(TCMP)
PD6
EDGE
INPUT
(TCAP)
Figure 8-1. 16-Bit Timer Block Diagram
The free-running counter is configured to $FFFC during reset and is a
read-only register but only when the timer is enabled. During a power-on
reset, the counter is also preset to $FFFC and begins running only after
the TON bit in the TIMER control register is set. Because the freerunning counter is 16 bits preceded by a fixed divided-by-four prescaler,
the value in the free-running counter repeats every 262,144 internal bus
clock cycles. When the counter rolls over from $FFFF to $0000, the TOF
bit is set. An interrupt can also be enabled when counter roll-over occurs
by setting its interrupt enable bit (TOIE).
NOTE:
The I bit in the CCR should be set while manipulating both the high and
low byte registers of a specific timer function to ensure that an interrupt
does not occur.
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N O N - D I S C L O S U R E
INTERNAL BUS
A G R E E M E N T
R E Q U I R E D
16-Bit Timer
Counter Register
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A G R E E M E N T
R E Q U I R E D
16-Bit Timer
8.4 Output Compare Register
The 16-bit output compare register is made up of two 8-bit registers at
locations $16 (MSB) and $17 (LSB). The output compare register is
used for several purposes, such as indicating when a period of time has
elapsed. All bits are readable and writable and are not altered by the
timer hardware or reset. If the compare function is not needed, the two
bytes of the output compare register can be used as storage locations.
The output compare register contents are continually compared with the
contents of the free-running counter. If a match is found, the
corresponding output compare flag (OCF) bit is set and the
corresponding output level (OLVL) bit is clocked to an output level
register. The output compare register values and the output level bit
should be changed after each successful comparison to establish a new
elapsed time-out. An interrupt can also accompany a successful output
compare provided the corresponding interrupt enable bit (OCIE) is set.
After a processor write cycle to the output compare register containing
the MSB ($16), the output compare function is inhibited until the LSB
($17) is also written. The user must write both bytes (locations) if the
MSB is written first. A write made only to the LSB ($17) will not inhibit the
compare function. The free-running counter is updated every four
internal bus clock cycles. The minimum time required to update the
output compare register is a function of the program rather than the
internal hardware.
The processor can write to either byte of the output compare register
without affecting the other byte. The output level (OLVL) bit is clocked to
the output level register regardless of whether the output compare flag
(OCF) is set or clear.
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The result obtained by an input capture is one more than the value of the
free-running counter on the rising edge of the internal bus clock
preceding the external transition. This delay is required for internal
synchronization. Resolution is one count of the free-running counter,
which is four internal bus clock cycles.
The free-running counter contents are transferred to the input capture
register on each proper signal transition regardless of whether the input
capture flag (ICF) is set or clear. The input capture register always
contains the free-running counter value that corresponds to the most
recent input capture.
After a read of the input capture register MSB ($14), the counter transfer
is inhibited until the LSB ($15) is also read. This characteristic causes
the time used in the input capture software routine and its interaction
with the main program to determine the minimum pulse period. A read
of the input capture register LSB ($15) does not inhibit the free-running
counter transfer since they occur on opposite edges of the internal bus
clock.
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A G R E E M E N T
Two 8-bit registers, which make up the 16-bit input capture register, are
read-only and are used to latch the value of the free-running counter
after the corresponding input capture edge detector senses a defined
transition. The level transition that triggers the counter transfer is defined
by the corresponding input edge bit (IEDG). Reset does not affect the
contents of the input capture register.
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8.5 Input Capture Register
R E Q U I R E D
16-Bit Timer
Input Capture Register
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R E Q U I R E D
16-Bit Timer
8.6 Timer Control Register
The TCR is a read/write register containing six control bits. Three bits
control interrupts associated with the timer status register flags ICF,
OCF, and TOF.
Address:
$0012
Bit 7
6
5
4
3
2
1
Bit 0
ICIE
OCIE
TOIE
0
0
TON
IEDG
OLVL
0
0
0
0
0
0
0
0
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A G R E E M E N T
Read:
Write:
Reset:
Figure 8-2. Timer Control Register (TCR)
ICIE — Input Capture Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
OCIE — Output Compare Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
TOIE — Timer Overflow Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
TON — Timer On
When disabled, the timer is initialized to the reset condition.
1 = Timer enabled
0 = Timer disabled
IEDG — Input Edge
Value of input edge determines which level transition on the TCAP pin
will trigger a free-running counter transfer to the input capture
register. Reset clears this bit.
1 = Positive edge
0 = Negative edge
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OLVL — Output Level
Value of output level is clocked into the output level register by the
next successful output compare and will appear on the TCMP pin.
1 = High output
0 = Low output
8.7 Timer Status Register
R E Q U I R E D
16-Bit Timer
Timer Status Register
Read:
$0013
Bit 7
6
5
4
3
2
1
Bit 0
ICF
OCF
TOF
0
0
0
0
0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 8-3. Timer Status Register (TSR)
ICF — Input Capture Flag
1 = Flag set when selected polarity edge is sensed by input capture
edge detector
0 = Flag cleared when TSR and input capture low register ($15) are
accessed
Reset clears this bit.
OCF — Output Compare Flag
1 = Flag set when output compare register contents match the freerunning counter contents
0 = Flag cleared when TSR and output compare low register ($17)
are accessed
Reset clears this bit.
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Address:
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The TSR is a read-only register containing three status flag bits.
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R E Q U I R E D
16-Bit Timer
TOF — Timer Overflow Flag
1 = Flag set when free-running counter transitions from $FFFF to
$0000 occurs
0 = Flag cleared when TSR and counter low register ($19) are
accessed
Reset clears this bit.
Bits 0–4 — Not Used
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A G R E E M E N T
Always read zero.
Accessing the timer status register satisfies the first condition required
to clear status bits. The remaining step is to access the register
corresponding to the status bit.
A problem can occur when using the timer overflow function and reading
the free-running counter at random times to measure an elapsed time.
Without incorporating the proper precautions into software, the timer
overflow flag could unintentionally be cleared if:
•
The timer status register is read or written when TOF is set.
•
The MSB of the free-running counter is read but not for the
purpose of servicing the flag.
The counter alternate register at address $1A and $1B contains the
same value as the free-running counter at address $18 and $19; this
alternate register can be read at any time without affecting the timer
overflow flag in the timer status register.
8.8 Timer During Wait Mode
The CPU clock halts during wait mode, but the timer remains active if
turned on prior to entering wait mode. If interrupts are enabled, a timer
interrupt will cause the processor to exit wait mode.
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8.10 Timer Power Supply Source
The timer’s power is supplied by VDD and VSS. VDD2 and VSS2 will not
be needed since this module is not susceptible to supply noise.
A G R E E M E N T
In stop mode, the timer stops counting and holds the last count value if
stop is exited by an interrupt. If reset is used, the counter is forced to
$FFFC. During stop, if the timer is on and at least one valid input capture
edge occurs at the TCAP pin, the input capture detect circuit is armed.
This does not set any timer flags or wake up the MCU. When the MCU
does wake up, however, there is an active input capture flag and data
from the first valid edge that occurred during the stop mode. If reset is
used to exit stop mode, no input capture flag or data remains, even if a
valid input capture edge occurred.
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8.9 Timer During Stop Mode
R E Q U I R E D
16-Bit Timer
Timer During Stop Mode
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A G R E E M E N T
R E Q U I R E D
16-Bit Timer
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Section 9. Synchronous Serial Interface (SSI)
9.1 Contents
9.3
Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
9.3.1
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
9.3.2
Serial Data In/Out (SDIO) . . . . . . . . . . . . . . . . . . . . . . . . . .71
9.4
SSI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
9.4.1
SSI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
9.4.2
SSI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
9.4.3
SSI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
9.5
Operation During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .76
9.6
Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .76
9.7
SSI Power Supply Source . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
9.2 Introduction
The synchronous serial interface (SSI) is a 2-wire master/slave system
including serial clock (SCK) and serial data input/output (SDIO). Data is
transferred eight bits at a time. A software programmable option
determines whether the SSI transfers data most significant bit (MSB) or
least significant bit (LSB) first and an interrupt may be generated at the
completion of each transfer. When operating as a master device, the
serial clock speed is selectable from a choice of four rates.
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A G R E E M E N T
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
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9.2
R E Q U I R E D
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R E Q U I R E D
Synchronous Serial Interface (SSI)
INTERRUPT
MCU INTERNAL BUS
DATA BUS
CONTROLS/ADDRESS BUS
INTERRUPT CIRCUIT
CONTROL LOGIC
TO INTERRUPT LOGIC
0 0 0 0 0 0
SSI DATA REG.
HFF
SDIO
LSBF
SR
MSTR
CPOL
T/R
SE
SSI CONTROL REG.
START
SSI STATUS REG.
SF
DCOL
N O N - D I S C L O S U R E
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A G R E E M E N T
Transmission in master mode is initiated by a write to the SSI data
register (SDR). A transfer cannot be initiated in slave mode; the external
master initiates the transfer. The programmer must choose between
master or slave mode before the SSI is enabled. The programmer must
ensure that only one master exists in the system at any one time. All
devices in the system must operate with the same clock polarity and
data rates. Slaves should always be disabled before the master is
disabled.
SE
CLOCK GENERATOR
SCK
MSTR
&
Figure 9-1. SSI Block Diagram
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9.3.1 Serial Clock (SCK)
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When SE = 0, this pin is a port D bit 5 pin, which follows the port D DDR
assignment.
In master mode (MSTR = 1), the serial clock (SCK) pin is an output with
four selectable frequencies. This pin will be high (CPOL = 1) or low
(CPOL = 0) between transmissions.
In slave mode (MSTR = 0), the SCK pin is an input and the clock must
be supplied by an external master with a maximum frequency of fOP/2.
There is no minimum SCK frequency. This pin should be driven high
(CPOL = 1) or low (CPOL = 0) between transmissions by the external
master and must be stable before the SSI is first enabled (SE = 1).
Data is always captured at the serial data in/out (SDIO) pin on the rising
edge of SCK.
Data is always shifted out and presented at the serial data in/out (SDIO)
pin on the falling edge of SCK.
9.3.2 Serial Data In/Out (SDIO)
Prior to enabling the SSI (SE = 0), the serial data in/out (SDIO) pin is a
port D bit 4 pin, which follows the port D DDR assignment. When the SSI
is enabled (SE = 1) the SDIO pin becomes a high-impedance input pin
if the T/R bit is low or it idles high if the T/R bit is high.
The data can be sent or received in either MSB first format (LSBF = 0)
or LSB first format (LSBF = 1).
If (CPOL = 1), the first falling edge of SCK will shift the first data bit out
to the SDIO pin. Subsequent falling edges of SCK will shift the remaining
data bits out.
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A G R E E M E N T
The SSI is comprised of two main input/output (I/O) signals that interface
with port D serial clock and serial data.
N O N - D I S C L O S U R E
9.3 Signal Format
R E Q U I R E D
Synchronous Serial Interface (SSI)
Signal Format
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R E Q U I R E D
Synchronous Serial Interface (SSI)
If (CPOL = 0), the first data bit will be driven out to the SDIO pin before
the first rising edge of SCK. Subsequent falling edges of SCK will shift
the remaining data bits out.
When receiving data in master mode, the T/R bit must be low and data
must be written to the data register to initiate clock generation.
When transmitting data in master mode, the T/R bit must be high.
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A G R E E M E N T
When receiving data in slave mode, T/R bit must be low and the clock
and data must be supplied by external device.
When transmitting data in slave mode, T/R bit must be high, and data
must be written to the data register before the SSI is enabled to ensure
that proper data is transferred.
SCK
(CPOL = 1)
SDIO
BIT 1
BIT 2
BIT 3
BIT 7
BIT 8
SCK
(CPOL = 0)
SE
Figure 9-2. Serial I/O Port Timing
9.4 SSI Registers
The SSI has three registers: control, status, and data.
9.4.1 SSI Control Register
This register is located at address $001E and contains seven bits. A
reset clears all of these bits, except bit 3 which is set. Writes to this
register during a transfer should be avoided, with the exception of
clearing the SE bit to disable the SSI.
In addition, the clock polarity, rate, data format and master/slave
selection should not be changed while the SSI is enabled (SE = 1) or
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$001E
Bit 7
6
5
4
3
2
1
Bit 0
SIE
SE
LSBF
MSTR
CPOL
T/R
SR1
SR0
0
0
0
0
1
0
0
0
Read:
Write:
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Reset:
Figure 9-3. SSI Control Register (SCR)
SIE — SSI Interrupt Enable
This bit determines whether an interrupt request should be generated
when a transfer is complete.
When set, an interrupt request is made if the CPU is in the run or wait
mode of operation and status flag bit SF is set.
When cleared, no interrupt requests are made by the SSI.
SE — SSI Enable
When set, this bit enables the SSI, makes PD5 the SCK pin, and
makes PD4 the SDIO pin.
When SE is cleared, any transmission in progress is aborted, the bit
counter is reset, and pins SCK and SDIO revert to being PD5 and
PD4.
LSBF — Least Significant Bit (LSB)First
When set, data is sent and received in a least significant bit (LSB) first
format.
When cleared, data is sent and received in a most significant bit
(MSB) first format.
MSTR — Master Mode
When set, this bit configures the SSI to the master mode. This means
that the transmission is initiated by a write to the data register and the
SCK pin becomes an output providing a synchronous data clock at a
rate determined by the SR bits.
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A G R E E M E N T
Address:
N O N - D I S C L O S U R E
being enabled. Always disable the SSI first, by clearing the SE bit, before
altering these control bits within the SSI control register (SCR).
R E Q U I R E D
Synchronous Serial Interface (SSI)
SSI Registers
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R E Q U I R E D
Synchronous Serial Interface (SSI)
When cleared, this bit configures the SSI to the slave mode and
aborts any transmission in progress. Transfers are initiated by an
external master, which should supply the clock to the SCK pin.
CPOL — Clock Polarity
The clock polarity bit controls the state of the SCK pin between
transmissions.
When this bit is set, pin SCK is high between transmissions.
N O N - D I S C L O S U R E
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A G R E E M E N T
When this bit is cleared, pin SCK is low between transmissions.
In both cases the data is latched on the rising edge of SCK for serial
input and is valid on the rising edge of SCK for serial output. A reset
sets this bit.
NOTE:
If the SSI is used as a slave, the SCK input pin must be active before
enabling the SSI. For example, if CPOL = 0, SCK must be low; if
CPOL = 1, SCK must be high.
T/R — Transmit/Receive
This bit must be set to allow data to be driven on the SDIO pin
(transmitting). It must be cleared to disable the SDIO drivers when
receiving data. It is cleared by a reset.
SR1 and SR0 — SSI Rate
These bits determine the frequency of SCK when in master mode
(MSTR = 1). They have no effect in slave mode (MSTR = 0).
Table 9-1. SSI Rates
SR1 and SR0
SCK Rates (Hz) at fosc Frequency
00
32 kHz
01
64 kHz
10
128 kHz
11
256 kHz
General Release Specification
MC68HC05CT4 — Rev. 2.0
Synchronous Serial Interface (SSI)
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9.4.2 SSI Status Register
This register is located at address $001C and contains two bits. Reset
clears both of these bits.
Address:
Read:
$001C
Bit 7
6
SF
DCOL
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
R E Q U I R E D
Synchronous Serial Interface (SSI)
SSI Registers
0
0
Figure 9-4. SSI Status Register (SSR)
SF — SSI Flag
This bit is set upon occurrence of the last rising clock edge and
indicates that a data transfer has taken place. If MSTR = 0 and
SIE = 0, this bit has no effect on any further transmissions and can be
ignored without problem. However, the SF flag must be clear to write
the data register, or if SIE = 1 to clear the interrupt. If MSTR = 1, the
SF flag must be cleared between transfers. The SF flag can be
cleared three different ways: (1) by reading the SSR with SF set,
followed by a read or write of the serial data register, (2) by a system
reset, or, (3) by disabling the SSI. If the SF flag is cleared before the
last edge of the next byte, it will be set again.
DCOL — Data Collision
This is a read-only status bit, which indicates that an invalid access to
the data register was made. An invalid access can be one of the
following conditions:
•
An access of the SDR register in the middle of a transfer (after the
first falling edge of SCK and before SF is set)
•
An access of the SDR register made before an access of the SSR
register (after SF is set)
DCOL is cleared by reading the status register with SF set followed
by a read or write of the data register. A reset also clears this bit.
MC68HC05CT4 — Rev. 2.0
General Release Specification
Synchronous Serial Interface (SSI)
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A G R E E M E N T
Reset:
N O N - D I S C L O S U R E
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Write:
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Synchronous Serial Interface (SSI)
9.4.3 SSI Data Register
This register is located at address $001D and is both the transmit and
receive data register. This system is not double buffered, but any writes
to this register during transfers are masked and will not destroy the
previous contents. The SDR can be read at any time, but, if a transfer is
in progress the results may be ambiguous. The contents of this register
could be altered whenever the CPOL bit is altered. This register should
be written to only upon completion of a transfer, after the SF flag has
been cleared. Otherwise, the new data will not be stored.
For an SSI configured as a master, to initiate a transfer, the data register
write must occur after the SSI is enabled.
Address:
$001D
Bit 7
6
5
4
3
2
1
Bit 0
U
U
U
U
U
U
U
U
Read:
Write:
Reset:
Figure 9-5. SSI Data Register (SDR)
9.5 Operation During Wait Mode
The CPU clock halts during wait mode, but the SSI remains active. If
interrupts are enabled, an SSI interrupt will cause the processor to exit
wait mode.
9.6 Operation During Stop Mode
In stop mode, the SSI halts operation. The SDIO and SCK pins will
maintain their states.
If the SSI is nearing completion of a transfer when the stop mode is
entered, it might be possible for the SSI to generate an interrupt request
and thus cause the processor immediately to exit stop mode. To prevent
General Release Specification
MC68HC05CT4 — Rev. 2.0
Synchronous Serial Interface (SSI)
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To avoid these potential problems, it is safer to disable the SSI
completely (SE = 0) before entering stop mode.
The synchronous serial interface (SSI) is a 2-wire master/slave system
including serial clock (SCK) and serial data input/output (SDIO). When
operating as a master device, the serial clock speed is selectable
between four rates.
9.7 SSI Power Supply Source
The power supplied to the SSI is VDD and VSS, thus keeping the VDD2
and VSS2 free for the noise susceptible modules.
MC68HC05CT4 — Rev. 2.0
General Release Specification
Synchronous Serial Interface (SSI)
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A G R E E M E N T
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If the SSI is configured to slave mode, further care should be taken in
entering stop mode. The SCK pin will still accept a clock from an external
master, allowing potentially unwanted transfers to take place and power
consumption to be increased. The SSI will not generate interrupt
requests in this situation but, on exiting stop mode through some other
means, the SF flag may be found to be set and an interrupt request will
be generated if SIE is also set at this point.
N O N - D I S C L O S U R E
this occurrence, the programmer should ensure that all transfers are
complete before entering the stop mode.
R E Q U I R E D
Synchronous Serial Interface (SSI)
SSI Power Supply Source
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Synchronous Serial Interface (SSI)
General Release Specification
MC68HC05CT4 — Rev. 2.0
Synchronous Serial Interface (SSI)
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10.1 Contents
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
10.3
Core Timer Control and Status Register. . . . . . . . . . . . . . . . . .81
10.4
Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . .83
10.5
Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .84
10.6
Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
10.7
Core Timer Power Supply Source . . . . . . . . . . . . . . . . . . . . . .84
10.2 Introduction
The core timer for this device is a 12-stage multifunctional ripple counter.
Features include timer overflow, power-on reset (POR), real-time
interrupt (RTI), and COP watchdog timer.
As seen in Figure 10-1, the internal peripheral clock is divided by four,
and then drives an 8-bit ripple counter. The value of this 8-bit ripple
counter can be read by the CPU at any time by accessing the core timer
counter register (CTCR) at address $09. A timer overflow function is
implemented on the last stage of this counter, giving a possible interrupt
rate of the internal peripheral clock(E)/1024. This point is then followed
by three more stages, with the resulting clock (E/16384) driving the realtime interrupt circuit (RTI). The RTI circuit consists of three divider
stages with a one-of-four selector. The output of the RTI circuit is further
divided by eight to drive the mask optional COP watchdog timer circuit.
The RTI rate selector bits and the RTI and CTOF enable bits and flags
are located in the timer control and status register at location $08.
MC68HC05CT4 — Rev. 2.0
General Release Specification
Core Timer
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A G R E E M E N T
Section 10. Core Timer
N O N - D I S C L O S U R E
General Release Specification — MC68HC05CT4
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
INTERNAL BUS
8
Freescale Semiconductor, Inc...
N O N - D I S C L O S U R E
COP
CLEAR
INTERNAL PERIPHERAL CLOCK (E)
8
CTCR
E/22
$09 CORE TIMER COUNTER REGISTER (CTCR)
E/210
A G R E E M E N T
R E Q U I R E D
Core Timer
DIV
÷4
E / 212
POR
5-BIT COUNTER
E / 217
E / 216
E / 215
TCBP
E / 214
RTI SELECT CIRCUIT
OVERFLOW
DETECT
CIRCUIT
RTIOUT
CTCSR
CTOF
RTIF
TOFE
RTIE
TOFC
RTFC
RT1
RT0
$08
TIMER CONTROL &
STATUS REGISTER
INTERRUPT CIRCUIT
TO INTERRUPT
LOGIC
COP WATCHDOG
TIMER (÷ 8)
23
TO RESET
LOGIC
Figure 10-1. Core Timer Block Diagram
General Release Specification
MC68HC05CT4 — Rev. 2.0
Core Timer
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The CTCSR contains the timer interrupt flag, the timer interrupt enable
bits, and the real time interrupt rate select bits. Figure 10-2 shows the
value of each bit in the CTCSR when coming out of reset.
Address
Freescale Semiconductor, Inc...
Read:
$0008
Bit 7
6
CTOF
RTIF
5
4
TOFE
RTIE
Write:
Reset:
0
0
0
0
3
2
0
0
TOFC
RTRC
0
0
1
Bit 0
RT1
RT0
1
1
= Unimplemented
Figure 10-2. Core Timer Control and Status Register (CTCSR)
CTOF — Core Timer Overflow
CTOF is a read-only status bit set when the 8-bit ripple counter rolls
over from $FF to $00. Clearing CTOF is done by writing a logic 1 to
TOFC. Writing to CTOF has no effect. Reset clears CTOF.
A G R E E M E N T
10.3 Core Timer Control and Status Register
R E Q U I R E D
Core Timer
Core Timer Control and Status Register
The real-time interrupt circuit consists of a 3-stage divider and a oneof-four selector. The clock frequency that drives the RTI circuit is
E/2**14 (or E/16,384) with three additional divider stages, giving a
maximum interrupt period of 64 milliseconds at a bus rate of 2.048
MHz. RTIF is a clearable, read-only status bit and is set when the
output of the chosen (one-of-four selection) stage goes active.
Clearing RTIF is done by writing a logic 1 to RTFC. Writing to RTIF
has no effect. Reset clears RTIF.
TOFE — Timer Overflow Enable
When this bit is set, a CPU interrupt request is generated when the
CTOF bit is set. Reset clears this bit.
RTIE — Real-Time Interrupt Enable
When this bit is set, a CPU interrupt request is generated when the
RTIF bit is set. Reset clears this bit.
MC68HC05CT4 — Rev. 2.0
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Core Timer
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N O N - D I S C L O S U R E
RTIF — Real Time Interrupt Flag
Freescale Semiconductor, Inc.
R E Q U I R E D
Core Timer
TOFC — Timer Overflow Flag Clear
When a logic 1 is written to this bit, CTOF is cleared. Writing a logic 0
has no effect on the CTOF bit. This bit always reads as zero.
RTFC — Real-Time Interrupt Flag Clear
When a logic 1 is written to this bit, RTIF is cleared. Writing a logic 0
has no effect on the RTIF bit. This bit always reads as zero.
RT1 and RT0 — Real-Time Interrupt Rate Select
Freescale Semiconductor, Inc...
A G R E E M E N T
These two bits select one of four taps from the real-time interrupt
circuit. See Table 10-1. Reset sets these two bits, which selects the
slowest periodic rate and gives the maximum time in which to alter
these bits if necessary. Care should be taken when altering RT0 and
RT1 if the timeout period is imminent or uncertain. If the selected tap
is modified during a cycle in which the counter is switching, an RTIF
could be missed or an additional one could be generated. To avoid
problems, the COP should be cleared before changing RTI taps.
Table 10-1. RTI and COP Rates at 2.048 MHz
N O N - D I S C L O S U R E
RTI Rate
2.048 MHz
RT1
and RT0
Minimum COP Rates
2.048 MHz
8 ms
214/E
00
(217–214)/E
56 ms
16 ms
215/E
01
(218–215)/E
112 ms
32 ms
216/E
10
(219–216)/E
224 ms
64 ms
217/E
11
(220–217)/E
448 ms
General Release Specification
MC68HC05CT4 — Rev. 2.0
Core Timer
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Address
Read:
$0009
Bit 7
6
5
4
3
2
1
Bit 0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
1
1
Write:
Reset:
= Unimplemented
Figure 10-3. Core Counter Register (CTCR)
The power-on cycle clears the entire counter chain and begins clocking
the counter. After 4064 cycles, the power-on reset circuit is released,
which again clears the counter chain and allows the device to come out
of reset. At this point, if RESET is not asserted, the timer starts counting
up from zero and normal device operation begins. When RESET is
asserted any time during operation (other than POR), the counter chain
is cleared.
MC68HC05CT4 — Rev. 2.0
General Release Specification
Core Timer
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A G R E E M E N T
The timer counter register is a read-only register that contains the
current value of the 8-bit ripple counter at the beginning of the timer
chain. This counter is clocked by the CPU clock (E/4) and can be used
for various functions including a software input capture. Extended time
periods can be attained using the TOF function to increment a temporary
RAM storage location, thereby simulating a 16-bit (or more) counter.
N O N - D I S C L O S U R E
10.4 Core Timer Counter Register
R E Q U I R E D
Core Timer
Core Timer Counter Register
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N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Core Timer
10.5 Computer Operating Properly (COP) Reset
The COP watchdog timer function is implemented on this device by
using the output of the RTI circuit and further dividing it by eight. The
minimum COP reset rates are listed in Table 10-1. If the COP circuit
times out, an internal reset is generated and the normal reset vector is
fetched. Preventing a COP timeout or clearing the COP is accomplished
by writing a logic 0 to bit 0 of address $1FF0. When the COP is cleared,
only the final divide-by-eight stage (output of the RTI) is cleared.
If the COP watchdog timer is allowed to time out, an internal reset is
generated to reset the MCU. In addition, the RESET pin is pulled low for
a minimum of one E-clock cycle for emulation purposes.
The COP remains enabled after execution of the WAIT instruction and
all associated operations apply. If the STOP instruction is disabled,
execution of STOP instruction causes the CPU to execute a NOP
instruction. In addition, the COP is prohibited from being held in RESET.
This prevents a device lock-up condition.
This COP’s objective is to make it impossible for this device to become
stuck or locked-up and to be sure the COP is able to rescue the part from
any situation where it might entrap itself in abnormal or unintended
behavior. This function is a mask option.
10.6 Timer During Wait Mode
The CPU clock halts during wait mode, but the timer remains active. If
interrupts are enabled, a timer interrupt will cause the processor to exit
wait mode. The COP is always enabled while in user mode.
10.7 Core Timer Power Supply Source
The core timer is supplied by VDD and VSS. VDD2 and VSS2 are not
needed here because this module is not susceptible to supply noise.
General Release Specification
MC68HC05CT4 — Rev. 2.0
Core Timer
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General Release Specification — MC68HC05CT4
Section 11. Dual Phase-Locked Loop (PLL)
11.1 Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
11.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
11.3.1
Dual Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
11.3.2
12-Bit Reference Counter Modulus Register. . . . . . . . . . . .89
11.3.3
16-Bit Transmit Counter Modulus Register . . . . . . . . . . . . .90
11.3.4
16-Bit Receive Counter Modulus Register . . . . . . . . . . . . .91
PLL Power Supply Source . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
N O N - D I S C L O S U R E
11.4
A G R E E M E N T
Freescale Semiconductor, Inc...
11.2
R E Q U I R E D
Freescale Semiconductor, Inc.
MC68HC05CT4 — Rev. 2.0
General Release Specification
Dual Phase-Locked Loop (PLL)
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N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Dual Phase-Locked Loop (PLL)
11.2 Introduction
This dual PLL is similar to that of the MC145162 60-MHz universal
programmable dual PLL frequency synthesizer. It is especially designed
for CT-1 cordless phone applications.
The PLL features fully programmable 16-bit receive, 16-bit transmit, and
12-bit reference ripple down counters. It also has two independent
phase detectors for transmit and receive loops.
The FinTx and FinRx signals are input to the PLL transmit and receive
counters, respectively. They are typically driven by the loop VCO and
AC-coupled. The minimum input signal level is 200 mVp-p @ 60.0 MHz.
OSC
(10.24 MHz)
12-BIT PROGRAMMABLE
REFERENCE COUNTER
÷4
÷ 25
÷5
PLS1
PLS0
TX
PHASE
DETECTOR
TxPDOUT
RX
PHASE
DETECTOR
RxPDOUT
MCU BUS
FinT
16-BIT PROGRAMMABLE
TX COUNTER
FinR
16-BIT PROGRAMMABLE
RX COUNTER
Figure 11-1. Dual PLL Block Diagram
General Release Specification
MC68HC05CT4 — Rev. 2.0
Dual Phase-Locked Loop (PLL)
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The PLL has one 12-bit programmable counter, two 16-bit
programmable counters, and one control register.
11.3.1 Dual Control Register
Freescale Semiconductor, Inc...
The PLLCR contains bits that affect the operation of the PLL.
Address:
$000A
Bit 7
Read:
6
5
TLOCK
RLOCK
4
3
2
1
Bit 0
REFON
TXON
RXON
PLS1
PLS0
0
0
0
0
0
Write:
Reset:
0
0
0
= Unimplemented
Figure 11-2. Dual PLL Control Register
PLS1 and PLS0 — PLL Reference Counter Select
These bits select between the PLL reference counter MUX outputs.
This output signal then drives the phase detectors.
Table 11-1. PLL Reference Counter Select
PLS1 and PLS0
PLL Reference Counter Output
00
÷12-Bit Counter
01
÷4 After 12-Bit Counter
10
÷5 After 12-Bit Counter
11
÷25 After 12-Bit Counter
RXON — RX Counter Enable
When set, this bit enables the PLL receive counter.
When clear, it stops the receive counter in a reset state to save power.
RXON also shuts off the associated phase detector and holds it in
three-state. Initializing the receive counter before it is enabled is
recommended.
MC68HC05CT4 — Rev. 2.0
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Dual Phase-Locked Loop (PLL)
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N O N - D I S C L O S U R E
11.3 Registers
A G R E E M E N T
R E Q U I R E D
Dual Phase-Locked Loop (PLL)
Registers
Freescale Semiconductor, Inc.
R E Q U I R E D
Dual Phase-Locked Loop (PLL)
TXON — TX Counter Enable
When set, this bit enables the PLL transmit counter.
When clear, it stops the counter in a reset state to save power. TXON
also shuts off the associated phase detector and holds it in threestate. Initializing the transmit counter before it is enabled is
recommended.
REFON — Reference Counter Enable
When clear, REFON stops the reference counter in a reset state to
save power. Initializing the reference counter before it is enabled is
recommended.
RLOCK — Receive Lock Detect
This bit is read only and is not latched. When set, this bit is a real-time
indication of an active correction pulse from the phase detect in
progress. When clear, no correction is made and the output from the
phase detect is three-stated. Using multiple reads at known intervals
will allow the user to filter and judge a LOCK condition.
TLOCK — Transmit Lock Detect
This bit is read only and is not latched.When set, this bit is a real-time
indication of an active correction pulse from the phase detect in
progress. When clear, no correction is made and the output from the
phase detect is three-stated. Using multiple reads at known intervals
will allow the user to filter and judge a LOCK condition.
N O N - D I S C L O S U R E
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A G R E E M E N T
When set, this bit enables the PLL reference counter.
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MC68HC05CT4 — Rev. 2.0
Dual Phase-Locked Loop (PLL)
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11.3.2 12-Bit Reference Counter Modulus Register
This 2-byte register holds the count for the 12-bit reference counter. The
reference counter is shut off and held in reset when the REFON bit is
cleared. For proper operation, this register must not be loaded with a
value less than $000F.
$000B
6
5
4
3
2
1
Bit 0
Read:
PLLRC11 PLLRC10 PLLRC9
PLLRC8
Write:
Reset:
Address:
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
PLLRC7
PLLRC6
PLLRC5
PLLRC4
PLLRC3
PLLRC2
PLLRC1
PLLRC0
0
0
0
0
0
0
0
0
$000C
Read:
Write:
Reset:
= Unimplemented
Figure 11-3. 12-Bit Reference Counter (PLLRC)
NOTE:
Bit 4 to bit 7 of $000B are not used but they are physically present. The
user may use these four bits for scratch memory.
MC68HC05CT4 — Rev. 2.0
General Release Specification
Dual Phase-Locked Loop (PLL)
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Bit 7
A G R E E M E N T
Address:
R E Q U I R E D
Dual Phase-Locked Loop (PLL)
Registers
Freescale Semiconductor, Inc.
R E Q U I R E D
Dual Phase-Locked Loop (PLL)
11.3.3 16-Bit Transmit Counter Modulus Register
This 2-byte register holds the count for the 16-bit transmit counter. The
transmit counter is shut off and held in reset when the TXON bit is
cleared. For proper operation, this register must not be loaded with a
value less than $000F.
Address:
$000D
6
5
4
3
2
1
Bit 0
PLLTX9
PLLTX8
Read:
PLLTX15 PLLTX14 PLLTX13 PLLTX12 PLLTX11 PLLTX10
Write:
Reset:
Address:
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
PLLTX7
PLLTX6
PLLTX5
PLLTX4
PLLTX3
PLLTX2
PLLTX1
PLLTX0
0
0
0
0
0
0
0
0
$000E
Read:
Write:
Reset:
Figure 11-4. 16-Bit Transmit Counter (PLLTX)
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
Bit 7
General Release Specification
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Dual Phase-Locked Loop (PLL)
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This 2-byte register holds the count for the 16-bit receive counter. The
receive counter is shut off and held in reset when the RXON bit is
cleared. For proper operation, this register must not be loaded with a
value less than $000F.
Address:
$000F
Freescale Semiconductor, Inc...
Bit 7
6
5
4
3
2
1
Bit 0
PLLRX9
PLLRX8
Read:
PLLRX15 PLLRX14 PLLRX13 PLLRX12 PLLRX11 PLLRX10
Write:
Reset:
Address:
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
PLLRX7
PLLRX6
PLLRX5
PLLRX4
PLLRX3
PLLRX2
PLLRX1
PLLRX0
0
0
0
0
0
0
0
0
$0010
Read:
Write:
Reset:
A G R E E M E N T
11.3.4 16-Bit Receive Counter Modulus Register
R E Q U I R E D
Dual Phase-Locked Loop (PLL)
Registers
The modulus registers mentioned above have specific read/write logic.
When the user updates the contents of the modulus registers, the MSB
must be written first and is temporarily stored in a temporary buffer. This
inhibits the transfer of data from this level to the next level, which is the
modulus register. When the LSB is written, all 12 or 16 bits (data from
the temporary buffer and the MCU internal bus) are transferred to the
modulus register simultaneously. This prevents the loading of bad data
from the modulus register. A read of the data registers is the reverse of
a write operation. A read of the LSB buffers the MSB. A subsequent read
of the MSB reflects this buffered value. Since only one temporary buffer
exists, two sequential MSB writes of different registers will result in only
the last data value stored in the temporary buffer. The first value will be
lost.
MC68HC05CT4 — Rev. 2.0
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Dual Phase-Locked Loop (PLL)
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N O N - D I S C L O S U R E
Figure 11-5. 16-Bit Receive Counter (PLLRX)
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MCU INTERNAL BUS
MSB
LSB
MODULUS
COUNTER
NOTE: Not available for the 12-bit reference counter.
Figure 11-6. Counter Structure Block Diagram
11.4 PLL Power Supply Source
The PLL is supplied by VDD, VDD2, VSS, and VSS2. VDD and VSS are
reserved for the digital circuitry, while VDD2 and VSS2 are reserved for
the analog circuitry such as the phase detect and the amplifiers which
are sensitive to supply noise.
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Dual Phase-Locked Loop (PLL)
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Dual Phase-Locked Loop (PLL)
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Section 12. Pulse Width Modulator (PWM)
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
12.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
12.4
PWM Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
12.5
PWM During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
12.6
PWM During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
12.7
PWM During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
12.8
PWM Power Supply Source . . . . . . . . . . . . . . . . . . . . . . . . . . .97
N O N - D I S C L O S U R E
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12.1 Contents
A G R E E M E N T
General Release Specification — MC68HC05CT4
R E Q U I R E D
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MC68HC05CT4 — Rev. 2.0
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Pulse Width Modulator (PWM)
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12.2 Introduction
The pulse width modulator (PWM) system has one 6-bit channel to
enable the correct pulse output. The PWM has a fixed frequency of E/64,
where E is the internal bus frequency. For a PWM output frequency of
32 kHz, E must be 2.048 MHz. This corresponds to a 10.24-MHz crystal
with the divide-by-five crystal option.
A G R E E M E N T
R E Q U I R E D
Pulse Width Modulator (PWM)
MODULUS &
COMPARATOR
PWM
PIN LOGIC
PC7/PWM
6-BIT COUNTER
E
PWME
HC05 DATA BUS
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BUFFER
N O N - D I S C L O S U R E
MISCELLANEOUS CONTROL REGISTER
Figure 12-1. PWM Block Diagram
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MC68HC05CT4 — Rev. 2.0
Pulse Width Modulator (PWM)
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A $00 in the PWM data register yields an off output (0%), but a $3F
yields a duty of 63/64 (98.4%).
When not in use, the PWM system can be shut off to save power by
clearing the PWME bit in MISCR.
Freescale Semiconductor, Inc...
Writes to the PWM data register can be performed at any time without
affecting the current PWM output signal. Updates on the PWM output
occur at the end of the PWM period (E x 64). At this time, the new value
is loaded into the PWM data register. If a write to the registers is
performed while the PWM is disabled, data is transferred directly to the
PWM register. A read of the data register reads the active count in
progress, not the buffered value.
After the PWM is enabled (PWM = 1) the PWM output remains low for
one E cycle. This allows synchronization and will not occur again until
the next time the PWM is enabled.
A G R E E M E N T
12.3 Functional Description
R E Q U I R E D
Pulse Width Modulator (PWM)
Functional Description
N O N - D I S C L O S U R E
64 x E
10
3F
20
0
Figure 12-2. PWM Waveforms
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Pulse Width Modulator (PWM)
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A G R E E M E N T
R E Q U I R E D
Pulse Width Modulator (PWM)
12.4 PWM Data Register
One PWM data register (PWMDR), located at $0020, is associated with
the PWM system. This 8-bit data register holds the duty cycle for the
PWM output; however, only six of these bits are used. PWMDR can be
written to and read at any time. Writes to the PWMDR are buffered and
are not transferred to the active register until the end of the PWM cycle
during which the write was executed.
Address:
$0020
Bit 7
6
0
0
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by Reset
Figure 12-3. PWM Data Register (PWMDR)
Upon RESET the user should write to the data register prior to enabling
the PWM system (for example, prior to setting the PWME bit in the
miscellaneous control register). This avoids an erroneous duty cycle
from being driven.
PWME — Miscellaneous Control Register PWM Enable Bit
When set, this bit enables the PWM subsystem. Its main function is to
allow the user to save power when not using the PWM. When
enabled, the clocks are active to the module. When clear, this bit
shuts off the clocks to the module and relinquishes control of PC7 to
the port C logic (the PC7 pullup option should not be selected if the
PWM is used). Reset clears this bit. This bit is located in the
miscellaneous control register found in Section 13. Comparators.
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Pulse Width Modulator (PWM)
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12.6 PWM During Stop Mode
In stop mode, the oscillator is stopped, causing the PWM to cease
function. Any signal in process is halted in whatever phase the signal
happens to be in. Disabling the PWM before executing the STOP
instruction is recommended.
12.7 PWM During Reset
Upon reset the PWME bit is cleared. In effect, this disables the PWM
system and configures the PC7/PWM pin as a high impedance port C
input pin. The user should write to the data register prior to enabling the
PWM system (for instance, prior to setting PWME). This avoids an
erroneous duty cycle from being driven.
12.8 PWM Power Supply Source
The PWM is supplied by VDD and VSS, due to the noise generated by the
digital circuitry, since this module is not affected by supply noise.
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A G R E E M E N T
The PWM continues normal operation during wait mode. To decrease
power consumption during WAIT, it is recommended that the PWME bit
in the miscellaneous control register be cleared if the PWM D/A
converter is not being used.
N O N - D I S C L O S U R E
12.5 PWM During Wait Mode
R E Q U I R E D
Pulse Width Modulator (PWM)
PWM During Wait Mode
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N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Pulse Width Modulator (PWM)
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MC68HC05CT4 — Rev. 2.0
Pulse Width Modulator (PWM)
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13.1 Contents
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
13.3
Comparator Control/Status Register. . . . . . . . . . . . . . . . . . . .101
13.4
Reading Comparator Outputs. . . . . . . . . . . . . . . . . . . . . . . . .103
13.5
Comparator During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . .103
13.6
Comparator During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . .103
13.7
Comparator Power Supply Source . . . . . . . . . . . . . . . . . . . . .103
13.2 Introduction
Port D shares its pins with CMP3+/PD0, CMP1–/PD1 and
CMP12+/PD2, CMP2–/PD3 of the comparators. The output of the
comparators is a status bit internal to the MCU. This circuitry is used for
the comparison of analog signals, with a digital output. The comparator
circuitry may be powered up by setting the CEN1, CEN2, and the CEN3
bits in the comparator control/status register. This register is located at
$0022 and is cleared by reset. The state of the comparator output bit
upon RESET is logic 0. For further electrical information see Section 16.
Electrical Specifications.
MC68HC05CT4 — Rev. 2.0
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Comparators
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A G R E E M E N T
Section 13. Comparators
N O N - D I S C L O S U R E
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R E Q U I R E D
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R E Q U I R E D
Comparators
+
CMP1
–
PD1/
CMP1–
VOLTAGE
COMPARATOR 1
CEN1
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A G R E E M E N T
PORT D
CEN2
PD3/
CMP2–
VOLTAGE
COMPARATOR 2
–
CMP2
PD2/
CMP12+
+
CEN3
INTERNAL
REF
VOLTAGE
COMPARATOR 3
–
PD0/
CMP3+
CM3IE
CMP3
CMP3 INT
+
Figure 13-1. Comparator Block Diagram
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Comparators
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13.3 Comparator Control/Status Register
Address:
Read:
$0022
Bit 7
6
5
CMP3
CMP2
CMP1
4
3
2
1
Bit 0
CM3IE
0
CEN3
CEN2
CEN1
0
0
0
0
0
Write:
Reset:
0
0
0
R E Q U I R E D
Comparators
Comparator Control/Status Register
CMP3 — Comparator 3 Output
This bit is implemented in two ways: as a real-time comparator output
or as a latched interrupt source. The state of CM3IE determines which
implementation is selected.
CM3IE = 0 (nonlatched mode) — This status bit is cleared only by two
means:
1. Clearing CM3IE while the voltage at CMP3+ is less than CMP3–
2. By an external reset
CM3IE = 1 (latched mode) — This latched status bit is set when the
voltage at CMP3+ (PD0) is larger than that of CMP3– (internal voltage
reference ~ 2 VDD/3). An interrupt is then initiated ($1FFA–$1FFB).
CMP2 — Comparator 2 Output
This status bit is set when the voltage at CMP12+ is larger than that
of CMP2–, otherwise, it is cleared. Reset clears this bit because the
comparator is disabled.
CMP1 — Comparator 1 Output
This status bit is set when the voltage at CMP12+ is larger than that
of CMP1–, otherwise, it is cleared. Reset clears this bit because the
comparator is disabled.
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Comparators
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A G R E E M E N T
Figure 13-2. Comparator Control/Status Register (CMPCSR)
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= Unimplemented
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N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Comparators
CM3IE — Comparator 3 Interrupt Enable
This control bit, when set, allows CMP3 to generate an interrupt when
it goes high.
CEN3 — Comparator 3 Enable
This control bit, when set, powers up the voltage comparator 3 on
PD0. The user must set this bit to allow any functionality of the
comparator. After enabling the comparator, the user should delay for
tCEN before reading the state of the output or enabling the interrupt.
Reset clears this bit.
PD0 remains under control of its DDR bit to enable the user to drive
CMP3+ to a desired level. When CEN3 is cleared, the comparator is
disabled and consumes negligible power.
CEN2 — Comparator 2 Enable
This control bit, when set, powers up the voltage comparator 2 on
PD2 and PD3. The user must set this bit to allow any functionality of
the comparator. After enabling the comparator, the user should delay
for tCEN before reading the state of the output. Reset clears this bit.
PD2 and PD3 remain under control of their DDR bits to enable the
user to drive CMP2– and CMP12+ to desired levels. When CEN2 is
cleared, the comparator is disabled and consumes negligible power.
CEN1 — Comparator 1 Enable
This control bit, when set, powers up voltage comparator 1 on PD1
and PD2. The user must set this bit to allow any functionality of the
comparator. After enabling the comparator, the user should delay for
tCEN before reading the state of the output. Reset clears this bit.
PD1 and PD2 remain under control of their DDR bits to enable the
user to drive CMP1– and CMP12+ to desired levels. When CEN1 is
cleared, the comparator is disabled and consumes negligible power.
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Comparators
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13.5 Comparator During Wait Mode
The comparator operates normally in wait mode. If the user wishes to
save power during the wait mode, the CEN1, CEN2, and CEN3 bits
should be cleared before the WAIT instruction.
13.6 Comparator During Stop Mode
Stop mode does not affect the comparator circuit. If the user needs to
save power, the CEN1, CEN2, and CEN3 bits should be cleared before
the STOP instruction.
13.7 Comparator Power Supply Source
The comparators are supplied by VDD2 and VSS2. These power lines are
reserved for noise-susceptible circuitry, such as the circuitry found in the
comparators.
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A G R E E M E N T
The state of each comparator output bit is internally readable from the
CMPCSR.
N O N - D I S C L O S U R E
13.4 Reading Comparator Outputs
R E Q U I R E D
Comparators
Reading Comparator Outputs
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N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Comparators
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MC68HC05CT4 — Rev. 2.0
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14.1 Contents
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
14.3
Miscellaneous Control Register . . . . . . . . . . . . . . . . . . . . . . .105
14.4
Miscellaneous Register Power Supply Source . . . . . . . . . . . .106
14.2 Introduction
The miscellaneous register exists to hold various system control bits. It
is located at address $0021.
14.3 Miscellaneous Control Register
Address:
$0021
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
SPEED
COE
PWME
0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 14-1. Miscellaneous Control Register (MISCR)
SPEED — CPU Speed Select
This control bit, when set, selects an additional divide-by-eight after
the already divide-by-five from the oscillator clock to the internal bus
clock. This makes the internal CPU clock a divide-by-40 from the
oscillator input.
When clear, the internal bus clock is a divide-by-five from the
oscillator input. Reset clears this bit.
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Section 14. Miscellaneous Register
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COE — 16-Bit Timer Output Compare Enable
This control bit, when set, enables the 16-bit output compare function
to come out on PD6/TCMP. When clear, PD6 returns to a generalpurpose I/O pin.
PWME — PWM Enable
This control bit, when set, enables the PWM function to come out on
PC7/PWM. When clear, PC7 returns to a general-purpose I/O pin.
14.4 Miscellaneous Register Power Supply Source
The miscellaneous control register is supplied by VDD and VSS. VDD2
and VSS2 are reserved for noise-susceptible circuitry.
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A G R E E M E N T
R E Q U I R E D
Miscellaneous Register
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Section 15. Instruction Set
15.1 Contents
15.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
15.3.1
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
15.3.2
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
15.3.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
15.3.4
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
15.3.5
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
15.3.6
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
15.3.7
Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
15.3.8
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
15.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
15.4.1
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .112
15.4.2
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .113
15.4.3
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .114
15.4.4
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .116
15.4.5
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
15.5
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
15.6
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
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A G R E E M E N T
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
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15.2
R E Q U I R E D
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15.2 Introduction
The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
15.3 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing modes
are:
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A G R E E M E N T
R E Q U I R E D
Instruction Set
•
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, no offset
•
Indexed, 8-bit offset
•
Indexed, 16-bit offset
•
Relative
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15.3.1 Inherent
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
R E Q U I R E D
Instruction Set
Addressing Modes
15.3.3 Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
15.3.4 Extended
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
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A G R E E M E N T
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
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15.3.2 Immediate
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A G R E E M E N T
R E Q U I R E D
Instruction Set
15.3.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
15.3.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
15.3.7 Indexed,16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
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When using the Motorola assembler, the programmer does not need to
calculate the offset because the assembler determines the proper offset
and verifies that it is within the span of the branch.
15.4 Instruction Types
The MCU instructions fall into the following five categories:
•
Register/Memory Instructions
•
Read-Modify-Write Instructions
•
Jump/Branch Instructions
•
Bit Manipulation Instructions
•
Control Instructions
MC68HC05CT4 — Rev. 2.0
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
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Instruction Set
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A G R E E M E N T
15.3.8 Relative
R E Q U I R E D
Instruction Set
Instruction Types
Freescale Semiconductor, Inc.
R E Q U I R E D
Instruction Set
15.4.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 15-1. Register/Memory Instructions
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
Instruction
Mnemonic
Add Memory Byte and Carry Bit to Accumulator
ADC
Add Memory Byte to Accumulator
ADD
AND Memory Byte with Accumulator
AND
Bit Test Accumulator
BIT
Compare Accumulator
CMP
Compare Index Register with Memory Byte
CPX
EXCLUSIVE OR Accumulator with Memory Byte
EOR
Load Accumulator with Memory Byte
LDA
Load Index Register with Memory Byte
LDX
Multiply
MUL
OR Accumulator with Memory Byte
ORA
Subtract Memory Byte and Carry Bit from Accumulator
SBC
Store Accumulator in Memory
STA
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
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MC68HC05CT4 — Rev. 2.0
Instruction Set
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15.4.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
Do not use read-modify-write operations on write-only registers.
Table 15-2. Read-Modify-Write Instructions
Mnemonic
Arithmetic Shift Left (Same as LSL)
ASL
Arithmetic Shift Right
ASR
Bit Clear
BCLR(1)
Bit Set
BSET(1)
Clear Register
CLR
Complement (One’s Complement)
COM
Decrement
DEC
Increment
INC
Logical Shift Left (Same as ASL)
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
NEG
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
Test for Negative or Zero
TST(2)
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence
because it does not write a replacement value.
MC68HC05CT4 — Rev. 2.0
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A G R E E M E N T
Freescale Semiconductor, Inc...
Instruction
N O N - D I S C L O S U R E
NOTE:
R E Q U I R E D
Instruction Set
Instruction Types
Freescale Semiconductor, Inc.
15.4.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Instruction Set
General Release Specification
MC68HC05CT4 — Rev. 2.0
Instruction Set
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Mnemonic
Branch if Carry Bit Clear
BCC
Branch if Carry Bit Set
BCS
Branch if Equal
BEQ
Branch if Half-Carry Bit Clear
BHCC
Branch if Half-Carry Bit Set
BHCS
Branch if Higher
BHI
Branch if Higher or Same
BHS
Branch if IRQ Pin High
BIH
Branch if IRQ Pin Low
BIL
Branch if Lower
BLO
Branch if Lower or Same
BLS
Branch if Interrupt Mask Clear
BMC
Branch if Minus
BMI
Branch if Interrupt Mask Set
BMS
Branch if Not Equal
BNE
Branch if Plus
BPL
Branch Always
BRA
Branch if Bit Clear
Branch Never
Branch if Bit Set
BRCLR
BRN
BRSET
Branch to Subroutine
BSR
Unconditional Jump
JMP
Jump to Subroutine
JSR
MC68HC05CT4 — Rev. 2.0
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A G R E E M E N T
Freescale Semiconductor, Inc...
Instruction
N O N - D I S C L O S U R E
Table 15-3. Jump and Branch Instructions
R E Q U I R E D
Instruction Set
Instruction Types
Freescale Semiconductor, Inc.
R E Q U I R E D
Instruction Set
15.4.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 15-4. Bit Manipulation Instructions
A G R E E M E N T
Instruction
Freescale Semiconductor, Inc...
Bit Clear
Mnemonic
BCLR
Branch if Bit Clear
BRCLR
Branch if Bit Set
BRSET
BSET
N O N - D I S C L O S U R E
Bit Set
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Table 15-5. Control Instructions
Freescale Semiconductor, Inc...
Instruction
Mnemonic
Clear Carry Bit
CLC
Clear Interrupt Mask
CLI
No Operation
NOP
Reset Stack Pointer
RSP
Return from Interrupt
RTI
Return from Subroutine
RTS
Set Carry Bit
SEC
Set Interrupt Mask
SEI
Stop Oscillator and Enable IRQ Pin
STOP
Software Interrupt
SWI
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
Stop CPU Clock and Enable Interrupts
WAIT
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A G R E E M E N T
These instructions act on CPU registers and control CPU operation
during program execution.
N O N - D I S C L O S U R E
15.4.5 Control Instructions
R E Q U I R E D
Instruction Set
Instruction Types
Freescale Semiconductor, Inc.
15.5 Instruction Set Summary
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
↕
IMM
DIR
EXT
IX2
IX1
IX
ii
A9
2
B9 dd 3
C9 hh ll 4
D9 ee ff 5
E9 ff
4
F9
3
↕
IMM
DIR
EXT
IX2
IX1
IX
AB ii
2
BB dd 3
CB hh ll 4
DB ee ff 5
EB ff
4
FB
3
↕ —
IMM
DIR
EXT
IX2
IX1
IX
ii
A4
2
B4 dd 3
C4 hh ll 4
D4 ee ff 5
E4 ff
4
F4
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
REL
Effect on
CCR
Description
H I N Z C
A ← (A) + (M) + (C)
Add with Carry
A ← (A) + (M)
Add without Carry
Arithmetic Shift Left (Same as LSL)
C
BCC rel
Branch if Carry Bit Clear
↕
↕
— — ↕
0
b7
Arithmetic Shift Right
↕ —
A ← (A) ∧ (M)
Logical AND
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
↕ —
— — ↕
↕
↕
↕
b0
C
b7
— — ↕
↕
↕
b0
PC ← (PC) + 2 + rel ? C = 0
Mn ← 0
— — — — —
ff
ff
Cycles
Operation
Opcode
Source
Form
Operand
Table 15-6. Instruction Set Summary
Address
Mode
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Instruction Set
5
3
3
6
5
5
3
3
6
5
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
— — — — —
25
rr
3
BCLR n opr
Clear Bit n
BCS rel
Branch if Carry Bit Set (Same as BLO)
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
BHCC rel
Branch if Half-Carry Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
BHCS rel
Branch if Half-Carry Bit Set
BHI rel
Branch if Higher
BHS rel
Branch if Higher or Same
PC ← (PC) + 2 + rel ? C = 1
REL
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 0
— — — — —
REL
22
rr
3
PC ← (PC) + 2 + rel ? C = 0
— — — — —
REL
24
rr
3
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MC68HC05CT4 — Rev. 2.0
Instruction Set
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Operand
Cycles
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
A5
B5
C5
D5
E5
F5
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
Freescale Semiconductor, Inc...
Operation
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test Accumulator with Memory Byte
Description
(A) ∧ (M)
— — — — —
REL
25
rr
3
REL
23
rr
3
— — — — —
REL
2C
rr
3
— — — — —
REL
2B
rr
3
— — — — —
REL
2D
rr
3
— — — — —
REL
26
rr
3
— — — — —
REL
2A
rr
3
— — — — —
REL
20
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
— — — — —
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? I = 0
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? I = 1
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? Z = 0
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? N = 0
BRA rel
Branch Always
PC ← (PC) + 2 + rel ? 1 = 1
BRSET n opr rel Branch if Bit n Set
BSET n opr
Set Bit n
↕ —
— — — — —
Branch if Lower or Same
Branch Never
— — ↕
IMM
DIR
EXT
IX2
IX1
IX
PC ← (PC) + 2 + rel ? C = 1
Branch if Lower (Same as BCS)
BRN rel
H I N Z C
PC ← (PC) + 2 + rel ? C ∨ Z = 1
BLO rel
BLS rel
BRCLR n opr rel Branch if Bit n Clear
Effect on
CCR
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? 1 = 0
21
rr
3
PC ← (PC) + 2 + rel ? Mn = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn ← 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
BSR rel
Branch to Subroutine
CLC
Clear Carry Bit
C←0
— — — — 0
INH
98
2
CLI
Clear Interrupt Mask
I←0
— 0 — — —
INH
9A
2
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Instruction Set
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A G R E E M E N T
Opcode
BIH rel
Source
Form
N O N - D I S C L O S U R E
Address
Mode
Table 15-6. Instruction Set Summary (Continued)
R E Q U I R E D
Instruction Set
Instruction Set Summary
Freescale Semiconductor, Inc.
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
INC opr
INCA
INCX
INC opr,X
INC ,X
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
dd
↕
IMM
DIR
EXT
IX2
IX1
IX
ii
A1
2
B1 dd 3
C1 hh ll 4
D1 ee ff 5
E1 ff
4
F1
3
↕ 1
DIR
INH
INH
IX1
IX
33
43
53
63
73
↕
IMM
DIR
EXT
IX2
IX1
IX
ii
A3
2
B3 dd 3
C3 hh ll 4
D3 ee ff 5
E3 ff
4
F3
3
↕ —
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
↕ —
IMM
DIR
EXT
IX2
IX1
IX
ii
A8
2
B8 dd 3
C8 hh ll 4
D8 ee ff 5
E8 ff
4
F8
3
↕ —
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
DIR
EXT
IX2
IX1
IX
BC dd 2
CC hh ll 3
DC ee ff 4
EC ff
3
FC
2
Effect on
CCR
Description
H I N Z C
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
Clear Byte
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
EXCLUSIVE OR Accumulator with Memory
Byte
Unconditional Jump
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
(X) – (M)
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
Decrement Byte
Increment Byte
(A) – (M)
A ← (A) ⊕ (M)
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
PC ← Jump Address
— — 0 1 —
— — ↕
— — ↕
— — ↕
— — ↕
— — ↕
— — ↕
↕
↕
— — — — —
General Release Specification
ff
dd
ff
dd
ff
dd
ff
Cycles
Operation
Operand
Source
Form
Opcode
Table 15-6. Instruction Set Summary (Continued)
Address
Mode
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Instruction Set
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
MC68HC05CT4 — Rev. 2.0
Instruction Set
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LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
Jump to Subroutine
A ← (M)
Load Accumulator with Memory Byte
X ← (M)
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
↕ —
IMM
DIR
EXT
IX2
IX1
IX
AE ii
2
BE dd 3
CE hh ll 4
DE ee ff 5
EE ff
4
FE
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
0
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
MUL
Unsigned Multiply
0
C
b7
INH
42
Negate Byte (Two’s Complement)
NOP
No Operation
↕
— — 0
↕
↕
b0
X : A ← (X) × (A)
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
— — ↕
b0
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
0 — — — 0
— — ↕
↕
↕
— — — — —
A ← (A) ∨ (M)
Logical OR Accumulator with Memory
Rotate Byte Left through Carry Bit
— — ↕
C
— — ↕
b7
b0
MC68HC05CT4 — Rev. 2.0
DIR
INH
INH
IX1
IX
30
40
50
60
70
INH
9D
ff
ff
5
3
3
6
5
5
3
3
6
5
11
dd
ff
5
3
3
6
5
2
↕ —
IMM
DIR
EXT
IX2
IX1
IX
AA
BA
CA
DA
EA
FA
ii
dd
hh ll
ee ff
ff
39
49
59
69
79
dd
↕
DIR
INH
INH
IX1
IX
↕
Cycles
↕ —
ii
A6
2
B6 dd 3
C6 hh ll 4
D6 ee ff 5
E6 ff
4
F6
3
— — ↕
C
b7
Logical Shift Right
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
— — ↕
IMM
DIR
EXT
IX2
IX1
IX
H I N Z C
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
BD dd 5
CD hh ll 6
DD ee ff 7
ED ff
6
FD
5
Description
ff
2
3
4
5
4
3
5
3
3
6
5
General Release Specification
Instruction Set
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A G R E E M E N T
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
— — — — —
DIR
EXT
IX2
IX1
IX
Effect on
CCR
N O N - D I S C L O S U R E
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
Opcode
Freescale Semiconductor, Inc...
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Operation
Address
Mode
Source
Form
Operand
Table 15-6. Instruction Set Summary (Continued)
R E Q U I R E D
Instruction Set
Instruction Set Summary
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
— — — — —
INH
9C
2
↕
↕
INH
80
9
— — — — —
INH
81
6
— — ↕
↕
IMM
DIR
EXT
IX2
IX1
IX
ii
A2
2
B2 dd 3
C2 hh ll 4
D2 ee ff 5
E2 ff
4
F2
3
Effect on
CCR
Description
H I N Z C
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right through Carry Bit
RSP
Reset Stack Pointer
SP ← $00FF
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
Return from Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
C
b7
— — ↕
↕
↕
b0
↕
↕
↕
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract Memory Byte and Carry Bit from
Accumulator
SEC
Set Carry Bit
C←1
— — — — 1
INH
99
SEI
Set Interrupt Mask
I←1
— 1 — — —
INH
9B
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in Memory
STOP
Stop Oscillator and Enable IRQ Pin
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
Store Index Register In Memory
Subtract Memory Byte from Accumulator
SWI
Software Interrupt
TAX
Transfer Accumulator to Index Register
A ← (A) – (M) – (C)
M ← (A)
↕
↕ —
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
— 0 — — —
INH
8E
— — ↕
ff
Cycles
Operation
Operand
Source
Form
Opcode
Table 15-6. Instruction Set Summary (Continued)
Address
Mode
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Instruction Set
5
3
3
6
5
2
2
dd
hh ll
ee ff
ff
4
5
6
5
4
2
dd
hh ll
ee ff
ff
↕ —
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
↕
↕
IMM
DIR
EXT
IX2
IX1
IX
ii
A0
2
B0 dd 3
C0 hh ll 4
D0 ee ff 5
E0 ff
4
F0
3
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
INH
83
10
INH
97
2
M ← (X)
A ← (A) – (M)
X ← (A)
— — ↕
— — ↕
— — — — —
General Release Specification
4
5
6
5
4
MC68HC05CT4 — Rev. 2.0
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
TXA
Transfer Index Register to Accumulator
— — — — —
INH
9F
2
— 0 — — —
INH
8F
2
— — ↕
(M) – $00
A ← (X)
Stop CPU Clock and Enable Interrupts
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
↕
—
↕ —
ff
4
3
3
5
4
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
15.6 Opcode Map
See Table 15-7.
MC68HC05CT4 — Rev. 2.0
General Release Specification
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
dd
Cycles
3D
4D
5D
6D
7D
Description
N O N - D I S C L O S U R E
Test Memory Byte for Negative or Zero
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
DIR
INH
INH
IX1
IX
Effect on
CCR
H I N Z C
TST opr
TSTA
TSTX
TST opr,X
TST ,X
WAIT
Operand
Operation
Opcode
Freescale Semiconductor, Inc...
Source
Form
Address
Mode
Table 15-6. Instruction Set Summary (Continued)
R E Q U I R E D
Instruction Set
Opcode Map
General Release Specification
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
1
DIR
2
REL
Branch
3
DIR
4
5
INH
6
IX1
Read-Modify-Write
INH
7
IX
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
EOR
IMM 2
2
ADC
IMM 2
2
ORA
IMM 2
2
ADD
IMM 2
2
2
SUB
IMM 2
2
CMP
IMM 2
2
SBC
IMM 2
2
CPX
IMM 2
2
AND
IMM 2
2
BIT
IMM 2
2
LDA
IMM 2
A
IMM
MSB
0
LSB
0
5
SUB
IX2 2
5
CMP
IX2 2
5
SBC
IX2 2
5
CPX
IX2 2
5
AND
IX2 2
5
BIT
IX2 2
5
LDA
IX2 2
6
STA
IX2 2
5
EOR
IX2 2
5
ADC
IX2 2
5
ORA
IX2 2
5
ADD
IX2 2
4
JMP
IX2 2
7
JSR
IX2 2
5
LDX
IX2 2
6
STX
IX2 2
D
IX2
4
SUB
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
AND
IX1 1
4
BIT
IX1 1
4
LDA
IX1 1
5
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
JMP
IX1 1
6
JSR
IX1 1
4
LDX
IX1 1
5
STX
IX1 1
E
IX1
MSB of Opcode in Hexadecimal
4
SUB
EXT 3
4
CMP
EXT 3
4
SBC
EXT 3
4
CPX
EXT 3
4
AND
EXT 3
4
BIT
EXT 3
4
LDA
EXT 3
5
STA
EXT 3
4
EOR
EXT 3
4
ADC
EXT 3
4
ORA
EXT 3
4
ADD
EXT 3
3
JMP
EXT 3
6
JSR
EXT 3
4
LDX
EXT 3
5
STX
EXT 3
C
EXT
Register/Memory
3
SUB
DIR 3
3
CMP
DIR 3
3
SBC
DIR 3
3
CPX
DIR 3
3
AND
DIR 3
3
BIT
DIR 3
3
LDA
DIR 3
4
STA
DIR 3
3
EOR
DIR 3
3
ADC
DIR 3
3
ORA
DIR 3
3
ADD
DIR 3
2
JMP
DIR 3
5
JSR
DIR 3
3
LDX
DIR 3
4
STX
DIR 3
B
DIR
5 Number of Cycles
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode
2
6
BSR
REL 2
2
LDX
2
IMM 2
2
TAX
INH
2
CLC
INH 2
2
SEC
INH 2
2
CLI
INH 2
2
SEI
INH 2
2
RSP
INH
2
NOP
INH 2
9
2
STOP
INH
2
2
TXA
WAIT
INH 1
INH
10
SWI
INH
9
RTI
INH
6
RTS
INH
8
INH
Control
INH
LSB of Opcode in Hexadecimal
5
5
3
5
3
3
6
5
BRSET0
BRA
BSET0
NEG
NEGA
NEGX
NEG
NEG
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
BRCLR0
BRN
BCLR0
3
1
DIR 2
DIR 2
REL
5
11
5
3
BRSET1
MUL
BHI
BSET1
3
1
DIR 2
INH
DIR 2
REL
5
5
3
5
3
3
6
5
BRCLR1
BLS
BCLR1
COM
COMA
COMX
COM
COM
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
5
3
3
6
5
BRSET2
BCC
BSET2
LSR
LSRA
LSRX
LSR
LSR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR2
BCLR2 BCS/BLO
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET3
BNE
BSET3
ROR
RORA
RORX
ROR
ROR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR3
BEQ
BCLR3
ASR
ASRA
ASRX
ASR
ASR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET4
BHCC
BSET4
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR4
BHCS
BCLR4
ROL
ROLA
ROLX
ROL
ROL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET5
BPL
BSET5
DEC
DECA
DECX
DEC
DEC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR5
BMI
BCLR5
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET6
BMC
BSET6
INC
INCA
INCX
INC
INC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
4
3
3
5
4
BRCLR6
BMS
BCLR6
TST
TSTA
TSTX
TST
TST
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRSET7
BIL
BSET7
3
1
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRCLR7
BIH
BCLR7
CLR
CLRA
CLRX
CLR
CLR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
0
DIR
Bit Manipulation
Table 15-7. Opcode Map
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
F
IX
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
3
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
nc...
N O N - D I S C LFreescale
O S U R E Semiconductor,
A G R E E M E IN
T
R E Q U I R E D
Freescale Semiconductor, Inc.
Instruction Set
MC68HC05CT4 — Rev. 2.0
Freescale Semiconductor, Inc...
16.1 Contents
16.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
16.3
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
16.4
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
16.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
16.6
5.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .128
16.7
3.3 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .129
16.8
3.3 V and 5.0 V Control Timing. . . . . . . . . . . . . . . . . . . . . . . .130
16.9
Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
16.10 PWM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
16.11 PLL Signal Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
16.2 Introduction
This section contains the electrical and timing specifications.
MC68HC05CT4 — Rev. 2.0
General Release Specification
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
Section 16. Electrical Specifications
N O N - D I S C L O S U R E
General Release Specification — MC68HC05CT4
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
16.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table below. Keep VIN and VOUT within the range
VSS ≤ (VIN or VOUT) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
Rating
Symbol
Value
Unit
Supply Voltage
VDD
–0.3 to +7.0
V
Input Voltage
VIN
VSS –0.3
to VDD + 0.3
V
Self-Check Mode (IRQ Pin Only)
VIN
VSS –0.3 to
2 x VDD + 0.3
I
25
mA
TJ
+150
°C
Tstg
–65 to +150
°C
Current Drain Per Pin Excluding VDD and VSS
Operating Junction Temperature
Storage Temperature Range
NOTE:
This device is not guaranteed to operate properly at the maximum
ratings. Refer to 16.6 5.0 V DC Electrical Characteristics and
16.7 3.3 V DC Electrical Characteristics for guaranteed operating
conditions.
General Release Specification
MC68HC05CT4 — Rev. 2.0
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Characteristic
Symbol
Value
Unit
TA
TL to TH
0 to +70
°C
Symbol
Value
Unit
θJA
70
°C/W
Operating Temperature Range
MC68HC05CT4 (Standard)
Freescale Semiconductor, Inc...
16.5 Thermal Characteristics
Characteristic
N O N - D I S C L O S U R E
Thermal Resistance
Plastic Dual In-Line Package
A G R E E M E N T
16.4 Operating Range
R E Q U I R E D
Electrical Specifications
Operating Range
MC68HC05CT4 — Rev. 2.0
General Release Specification
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
16.6 5.0 V DC Electrical Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
VOL
VOH
—
VDD –0.1
—
—
0.1
—
V
Output High Voltage
(ILoad -–0.8 mA) Port A, Port B, Port C, Port D
VOH
VDD –0.8
—
—
V
Output Low Voltage
(ILoad = 1.6 mA) Port A, Port B, Port C, Port D
VOL
—
—
0.4
V
Input High Voltage
Port A, Port B, Port C, Port D, IRQ, RE3.5SET, OSC1
VIH
0.7 x VDD
—
VDD
V
Input Low Voltage
Port A, Port B, Port C, Port D, IRQ, RESET, OSC1
VIL
VSS
—
0.3 x VDD
V
VHYST
0.8
0.9
1
V
—
—
3
0.3
10
1
mA
mA
—
—
10
20
25
30
µA
µA
—
—
1.5
0.5
3
1.3
mA
mA
—
—
200
250
300
350
µA
µA
Output Voltage
ILoad = 10.0 µA
ILoad = –10.0 µA
Input Hysteresis
TCAP, RESET, IRQ, PD4/SCK
Supply Current (see Notes)
Run
Wait
Stop
25 °C
0 °C to +70 °C
IDD
Supply Current (see Notes)
Run
Wait
Stop
25 °C
0 °C to +70 °C
IDD2
I/O Ports Hi-Z Leakage Current
Port A, Port B, Port D
IOZ
—
—
5
µA
Input Current
RESET, IRQ, OSC1
PC0–PC7 with Pullups Enabled
IIN
—
–20
—
–125
10
–250
µA
COUT
CINT
—
—
—
—
12
8
pF
Capacitance
Ports (as Input or Output)
RESET, IRQ
NOTES:
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = 0 °C to +70 °C, unless otherwise noted
2. All values shown reflect average measurements.
3. Typical values at midpoint of voltage range, 25 °C only
4. Wait IDD and IDD2 : Only timer system active.
5. Run (operating) IDD, IDD2, Wait IDD, and IDD2: Measured using external square wave clock source (fOSC = 10.24 MHz); all inputs 0.2 V
from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2
6. Wait, stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD –0.2 V
7. Stop IDD and IDD2 are measured with OSC1 = VSS.
8. Wait IDD and IDD2 are affected linearly by the OSC2 capacitance.
9. Run, wait, and stop IDD2 are measured directly off the VDD2 power supply.
General Release Specification
MC68HC05CT4 — Rev. 2.0
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Symbol
Min
Typ
Max
Unit
VOL
VOH
—
VDD –0.1
—
—
0.1
—
V
Output High Voltage
(ILoad –0.2 mA) Port A, Port B, Port C, Port D
VOH
VDD –0.3
—
—
V
Output Low Voltage
(ILoad = 1.6 mA) Port A, Port B, Port C, Port D
VOL
—
—
0.3
V
Input High Voltage
Port A, Port B, Port C, Port D, IRQ, RESET, OSC1
VIH
0.7 x VDD
—
VDD
V
Input Low Voltage
Port A, Port B, Port C, Port D, IRQ, RESET, OSC1
VIL
VSS
—
0.3 x VDD
V
—
—
1.5
0.15
5
0.5
mA
mA
—
—
5
10
12
15
µA
µA
—
—
0.5
0.3
2
0.8
mA
mA
—
—
100
125
150
175
µA
µA
Freescale Semiconductor, Inc...
Output Voltage
ILoad = 10.0 µA
ILoad = –10.0 µA
Supply Current (see Notes)
Run
Wait
Stop
25 °C
0 °C to +70 °C
IDD
Supply Current (see Notes)
Run
Wait
Stop
25 °C
0 °C to +70 °C
IDD2
I/O Ports Hi-Z Leakage Current
Port A, Port B, Port D
IOZ
—
—
5
µA
Input Current
RESET, IRQ, OSC1
PC0–PC7 with Pullups Enabled
IIN
—
–20
—
–50
10
–125
µA
COUT
CINT
—
—
—
—
12
8
pF
Capacitance
Ports (as Input or Output)
RESET, IRQ
NOTES:
1. VDD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = 0 °C to +70 °C, unless otherwise noted
2. All values shown reflect average measurements.
3. Typical values at midpoint of voltage range, 25 °C only
4. Wait IDD and IDD2 : Only timer system active.
5. Run (operating) IDD, IDD2, Wait IDD, and IDD2: Measured using external square wave clock source (fOSC = 10.24 MHz); all inputs 0.2 V
from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2
6. Wait, stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD –0.2 V
7. Stop IDD and IDD2 are measured with OSC1 = VSS.
8. Wait IDD and IDD2 are affected linearly by the OSC2 capacitance.
9. Run, wait, and stop IDD2 are measured directly off the VDD2 power supply.
MC68HC05CT4 — Rev. 2.0
General Release Specification
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
Characteristic
N O N - D I S C L O S U R E
16.7 3.3 V DC Electrical Characteristics
R E Q U I R E D
Electrical Specifications
3.3 V DC Electrical Characteristics
Freescale Semiconductor, Inc.
16.8 3.3 V and 5.0 V Control Timing
Characteristic
Symbol
Min
Max
Unit
Frequency of Operation
Crystal
External Clock
fOSC
—
dc
10.24
10.24
MHz
Internal Operating Frequency
Crystal (fOSC /5)
External Clock (fOSC /5)
fOP
—
dc
2.048
2.048
MHz
Cycle Time
tCYC
488
—
ns
Crystal Oscillator Startup Time
tOXOV
—
100
ms
Stop Recovery Startup Time (Crystal Oscillator)
tILCH
—
100
ms
RESET Pulse Width
tRL
1.5
—
tCYC
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
125
—
ns
Interrupt Pulse Period
tILIL
(Note 2)
—
tCYC
tOH,tOL
90
—
ns
OSC1 Pulse Width
NOTES:
1. VDD = 3.0 to 5.5 Vdc, VSS = 0 Vdc, TA = 0 oC to +70 oC, unless otherwise noted
2. The minimum period tILIL, should not be less than the number of cycle times it takes to execute the interrupt
service routine plus 2T tcyc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
General Release Specification
MC68HC05CT4 — Rev. 2.0
Electrical Specifications
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Symbol
Min
Max
Unit
VINT
VSS –0.5
VDD +0.5
V
Voltage Comparator Propagation Time Measured at 100
mV Overdrive (see Note 3)
tCOMP
—
10
µs
Common Mode Range (see Note 4)
VCOM
VSS +1.5
VDD –0.5
V
Offset (see Note 5)
VOFF
—
± 20
mV
Comparator Enable Time (see Note 6)
tCEN
—
100
ms
Input Current VSS ≤ VIN ≤ VDD
IIN
—
1
µA
Input Current VIN ≤ VSS
IIN
—
4.0
mA
—
10
kHz
SR
5
—
V/µs
Saturation Voltage (IOUT = –5 mA)
VSAT
—
0.5
V
Internal Voltage Reference CMP–
VREF
x 90%
x 110%
(2/3) VDD
Freescale Semiconductor, Inc...
Input Voltage Range (see Note 2)
Gain Bandwidth Product
Slew Rate
NOTES:
1. VDD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = 0 °C to +70 °C, unless otherwise noted
2. The comparator is guaranteed to function over the specified input voltage range with no erroneous outputs.
3. Signal propagation time through the comparators measured with 100 mv of overdrive.
4. Comparator is guaranteed to meet specifications; for example, SR, tCOMP, and VOFF.
5. Input offset voltage is guaranteed over the temperature range.
6. Enable time is the time from enabling the comparator with the CEN bit until the comparator is fully functional.
16.10 PWM Timing
Characteristic
Symbol
Min
Max
Unit
PWM Rise Time
tPWMR
15
35
ns
PWM Fall Time
tPWMR
15
35
ns
Symbol
Min
Max
Unit
Input Voltage on FINTX and FINRX (peak-to-peak)
VVCO
200
—
mVp-p
Input Frequency on FINTX and FINRX
fVCO
—
60
MHz
16.11 PLL Signal Input
Characteristic
MC68HC05CT4 — Rev. 2.0
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A G R E E M E N T
Characteristic
N O N - D I S C L O S U R E
16.9 Comparators
R E Q U I R E D
Electrical Specifications
Comparators
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
OSC11
tRL
RESET
tILIH
IRQ2
tILCH
4064 tCYC
IRQ3
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
1FFE
1FFE
1FFE
NOTES:
1. Represents the internal gating of the OSC1 pin
2. IRQ pin edge-sensitive mask option
3. IRQ pin level- and edge-sensitive mask option
4. RESET vector address shown for timing example
1FFE
1FFF4
RESET OR INTERRUPT
VECTOR FETCH
Figure 16-1. Stop Recovery Timing Diagram
General Release Specification
MC68HC05CT4 — Rev. 2.0
Electrical Specifications
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17.1 Contents
17.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
17.3
44-Lead Plastic-Leaded Chip Carrier (Case 777-02) . . . . . . .134
17.4
44-Lead Quad Flat Pack (Case 824A-01) . . . . . . . . . . . . . . .135
17.2 Introduction
The MC68HC05CT4 is available in a 44-pin plastic-leaded chip carrier
(PLCC) and a 44-pin quad flat pack (QFP). Package dimensions are
provided in this section.
The following figures show the latest package information at the time of
this publication. To make sure that you have the latest package
specifications, contact one of the following:
•
Local Motorola Sales Office
•
Motorola Fax Back System (Mfax™)
– Phone 1-602-244-6609
– EMAIL [email protected];
http://sps.motorola.com/mfax/
•
Worldwide Web (wwweb) home page at http://motorola.com/sps/
Follow Mfax or wwweb on-line instructions to retrieve the current
mechanical specifications.
MC68HC05CT4 — Rev. 2.0
General Release Specification
Mechanical Specifications
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A G R E E M E N T
Section 17. Mechanical Specifications
N O N - D I S C L O S U R E
General Release Specification — MC68HC05CT4
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
17.3 44-Lead Plastic-Leaded Chip Carrier (Case 777-02)
-N-
Freescale Semiconductor, Inc...
N O N - D I S C L O S U R E
Y BRK
0.007(0.180) M T
B
D
L-M S
0.007(0.180) M T
U
N S
L-M S
N S
Z
-M-
-L-
A G R E E M E N T
R E Q U I R E D
Mechanical Specifications
V
44
X
D
W
1
G1
0.010 (0.25) S T
VIEW D-D
A
0.007(0.180) M T
L-M S
N S
R
0.007(0.180) M T
L-M S
N S
0.007(0.180) M T
H
L-M S
L-M S
N S
N S
Z
J
K1
E
C
0.004 (0.10)
G
-TG1
0.010 (0.25) S T
L-M S
N S
K
SEATING
PLANE
F
VIEW S
0.007(0.180) M T
L-M S
N S
VIEW S
NOTES:
1. DATUMS -L-, -M-, AND -N- ARE DETERMINED
WHERE TOP OF LEAD SHOLDERS EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSION R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010
(0.25) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE DETERMINED
AT THE OUTERMOST EXTREMES OF THE
PLASTIC BODY EXCLUSIVE OF THE MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND
INTERLEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
7. DIMINSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTUSION(S) SHALL NOT CAUSE THE H
DIMINSION TO BE GREATER THAN 0.037
(0.940136). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMINISION TO SMALLER
THAN 0.025 (0.635).
INCHES
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
MIN
MAX
0.685
0.695
0.685
0.695
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
0.025
0.650
0.656
0.650
0.656
0.042
0.048
0.042
0.048
0.042
0.056
0.020
2°
10°
0.610
0.630
0.040
MILLIMETERS
MIN
MAX
17.40
17.65
17.40
17.65
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
0.64
16.51
16.66
16.51
16.66
1.07
1.21
1.07
1.21
1.07
1.42
0.50
2°
10°
15.50
16.00
1.02
General Release Specification
MC68HC05CT4 — Rev. 2.0
Mechanical Specifications
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17.4 44-Lead Quad Flat Pack (Case 824A-01)
L
23
B
DETAIL A
!
!
!
V
L
-A,B,DB
-B-
B
DETAIL A
44
12
1
11
F
-DA
S
BASE METAL
!
!
!
!
N
J
D
M
DETAIL C
!
!
SECTION B–B
C E
-H-
-C
H
M
G
M
T
-H-
R
K
W
X
DETAIL C
Q
"!
! " !
' " ! " "# (( ! " " "" ! " %" " % " &"! " !" ' " "
"" " " "#! (( (( (( " " "
"# ((
!! ! $ " " "
!" ((
!! " # " #! % " #! ! ! !! # !" " " "# ((
! ! " # " #! % " #!
! "" &!! " ! " &# " "
" " " %
#! " "
MC68HC05CT4 — Rev. 2.0
!
)
°
°
°
°
)
)
°
)
!
)
°
°
°
°
)
)
°
)
General Release Specification
Mechanical Specifications
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N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
-A-
!
22
34
A G R E E M E N T
33
R E Q U I R E D
Mechanical Specifications
44-Lead Quad Flat Pack (Case 824A-01)
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Mechanical Specifications
General Release Specification
MC68HC05CT4 — Rev. 2.0
Mechanical Specifications
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18.1 Contents
18.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
18.3
MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
18.4
Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .138
18.5
ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .139
18.6
ROM Verification Units (RVUs) . . . . . . . . . . . . . . . . . . . . . . .140
18.7
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
18.2 Introduction
This section contains instructions for ordering custom-masked ROM
MCUs.
18.3 MCU Ordering Forms
To initiate an order for a ROM-based MCU, first obtain the current
ordering form for the MCU from a Motorola representative. Submit the
following items when ordering MCUs:
•
A current MCU ordering form that is completely filled out
(Contact your Motorola sales office for assistance.)
•
A copy of the customer specification if the customer specification
deviates from the Motorola specification for the MCU
•
Customer’s application program on one of the media listed in 18.4
Application Program Media
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A G R E E M E N T
Section 18. Ordering Information
N O N - D I S C L O S U R E
General Release Specification — MC68HC05CT4
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Ordering Information
The current MCU ordering form is also available through the Motorola
Freeware Bulletin Board Service (BBS). The telephone number is (512)
891-FREE. After making the connection, type bbs in lower-case letters.
Then press the return key to start the BBS software.
18.4 Application Program Media
Please deliver the application program to Motorola in one of the following
media:
•
Macintosh1 3 1/2 inch diskette (double-sided 800 K or
double-sided high-density 1.4 M)
•
MS-DOS2 or PC-DOSTM3 3 1/2 inch diskette (double-sided 720 K
or double-sided high-density 1.44 M)
•
MS-DOS or PC-DOSTM 5 1/4 inch diskette (double-sided
double- density 360K or double-sided high-density 1.2M)
Use positive logic for data and addresses.
When submitting the application program on a diskette, clearly label the
diskette with this information:
•
Customer name
•
Customer part number
•
Project or product name
•
File name of object code
•
Date
•
Name of operating system that formatted diskette
•
Formatted capacity of diskette
On diskettes, the application program must be in Motorola’s S-record
format (S1 and S9 records), a character-based object file format
generated by M6805 cross assemblers and linkers.
1. Macintosh is a registered trademark of Apple Computer, Inc.
2. MS-DOS is a registered trademark of Microsoft Corporation.
3. PC-DOS is a trademark of International Business Machines Corporation.
General Release Specification
MC68HC05CT4 — Rev. 2.0
Ordering Information
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Freescale Semiconductor, Inc...
If the memory map has two user ROM areas with the same address,
then write the two areas in separate files on the diskette. Label the
diskette with both file names.
In addition to the object code, a file containing the source code can be
included. Motorola keeps this code confidential and uses it only to
expedite ROM pattern generation in case of any difficulty with the object
code. Label the diskette with the file name of the source code.
18.5 ROM Program Verification
The primary use for the on-chip ROM is to hold the customer’s
application program. The customer develops and debugs the application
program and then submits the MCU order along with the application
program.
Motorola inputs the customer’s application program code into a
computer program that generates a listing verify file. The listing verify file
represents the memory map of the MCU. The listing verify file contains
the user ROM code and may also contain nonuser ROM code, such as
self-check code. Motorola sends the customer a computer printout of the
listing verify file along with a listing verify form.
To aid the customer in checking the listing verify file, Motorola will
program the listing verify file into customer-supplied blank preformatted
Macintosh or DOS disks. All original pattern media are filed for
contractual purposes and are not returned.
Check the listing verify file thoroughly, then complete and sign the listing
verify form and return it to Motorola. The signed listing verify form
constitutes the contractual agreement for the creation of the custom
mask.
MC68HC05CT4 — Rev. 2.0
General Release Specification
Ordering Information
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A G R E E M E N T
Begin the application program at the first user ROM location. Program
addresses must correspond exactly to the available on-chip user ROM
addresses as shown in the memory map. Write $00 in all nonuser ROM
locations or leave all nonuser ROM locations blank. Refer to the current
MCU ordering form for additional requirements. Motorola may request
pattern re-submission if nonuser areas contain any nonzero code.
N O N - D I S C L O S U R E
NOTE:
R E Q U I R E D
Ordering Information
ROM Program Verification
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Ordering Information
18.6 ROM Verification Units (RVUs)
After receiving the signed listing verify form, Motorola manufactures a
custom photographic mask. The mask contains the customer’s
application program and is used to process silicon wafers. The
application program cannot be changed after the manufacture of the
mask begins. Motorola then produces 10 MCUs, called RVUs, and
sends the RVUs to the customer. RVUs are usually packaged in
unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are
not tested to environmental extremes because their sole purpose is to
demonstrate that the customer’s user ROM pattern was properly
implemented. The 10 RVUs are free of charge with the minimum order
quantity. These units are not to be used for qualification or production.
RVUs are not guaranteed by Motorola Quality Assurance.
18.7 MC Order Numbers
Table 18-1 shows the MC order numbers for the available package
types.
Table 18-1. MC Order Numbers
MC Order Number
Operating
Temperature Range
MC68HC05CT4FN
0 °C to 70 °C
MC68HC05CT4FB
0 °C to 70 °C
NOTE: FN = 44-Lead Plastic-Leaded Chip Carrier
FB = 44-Lead Quad Flat Pack
General Release Specification
MC68HC05CT4 — Rev. 2.0
Ordering Information
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Freescale Semiconductor, Inc.
Home Page:
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