FUJITSU MB85RC64PNF-G

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05–13109–3E
Memory FRAM
64 K (8 K × 8) Bit I2C
MB85RC64
■ DESCRIPTION
The MB85RC64 is a FRAM (Ferroelectric Random Access Memory) Stand-Alone chip in a configuration of
8,192 words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming
the nonvolatile memory cells.
The MB85RC64 adopts the two-wire serial interface.
Unlike SRAM, the MB85RC64 is able to retain data without using a data backup battery.
The read/write endurance of the nonvolatile memory cells used for the MB85RC64 has improved to be at
least 1010 cycles, significantly out performing Flash memory and E2PROM in the number.
The MB85RC64 does not need a polling sequence after writing to the memory such as the case of Flash
memory nor E2PROM.
■ FEATURES
•
•
•
•
•
•
•
•
•
Bit configuration
: 8,192 words × 8 bits
Operating power supply voltage : 2.7 V to 3.6 V
Operating frequency
: 400 kHz (Max)
Two-wire serial interface
: I2C-bus specification ver. 2.1 compliant, supports Standard-mode/
Fast-mode.
Fully controllable by two ports: serial clock (SCL) and serial data (SDA).
Operating temperature range : − 40 °C to +85 °C
Data retention
: 10 years ( + 75 °C)
Read/write endurance
: 1010 times
Package
: Plastic / SOP, 8-pin (FPT-8P-M02)
Low power consumption
: Operating current 0.15 mA (Max: @400 kHz), Standby current 5 μA (Typ)
Copyright©2010-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2011.6
MB85RC64
■ PIN ASSIGNMENT
(TOP VIEW)
A0
1
8
VDD
A1
2
7
WP
A2
3
6
SCL
VSS
4
5
SDA
(FPT-8P-M02)
■ PIN FUNCTIONAL DESCRIPTIONS
Pin
Number
2
Pin Name
Functional Description
1 to 3
A0 to A2
Device Address pins
The MB85RC64 can be connected to the same data bus up to 8 devices.
Device addresses are used in order to identify each of the devices. Connect
these pins to VDD pin or VSS pin externally. Only if the combination of VDD and
VSS pins matches a device, an address and a code inputted from the SDA pin,
the device operates. In the open pin state, A0, A1, and A2 pins are pulled-down
and recognized as “L”.
4
VSS
Ground pin
5
SDA
Serial Data I/O pin
This is an I/O pin of serial data for performing bidirectional communication of
address and writing or reading data of FRAM memory cell array. It is an open
drain output that may be wired OR with other open drain or open collector signals on the bus, so a pull-up resistance is required to be connected to the external circuit.
6
SCL
Serial Clock pin
This is a clock input pin for input/output timing serial data. Data is sampled on
the rising edge of the clock and output on the falling edge.
7
WP
Write Protect pin
When the Write Protect pin is “H”, the writing operation is disabled. When the
Write Protect pin is “L”, the entire memory region can be overwritten. The reading operation is always enabled regardless of the Write Protect pin condition. In
the open pin state, the Write Protect pin is pulled-down and recognized as “L”.
8
VDD
Supply Voltage pin
DS05–13109–3E
MB85RC64
■ BLOCK DIAGRAM
Control Logic
SCL
WP
Row Decoder
Serial/Parallel Converter
Address Counter
SDA
FRAM Array
8,192 × 8
Column Decoder/Sense Amp/
Write Amp
A0, A1, A2
■ I2C (Inter-Integrated Circuit)
The MB85RC64 has the two-wire serial interface; the I2C bus,and operates as a slave device.
The I2C bus defines communication roles of “master” and “slave” devices, with the master side holding the
authority to initiate control. Furthermore, a I2C bus connection is possible where a single master device is
connected to multiple slave devices in a party-line configuration. In this case, it is necessary to assign a
unique device address to the slave device.
• I2C Interface System Configuration Example
VDD
Pull-up
Resistors
SCL
SDA
I2C Bus
Master
I2C Bus
MB85RC64
I2C Bus
MB85RC64
I2C Bus
MB85RC64
A2
0
A2
0
A2
0
A1
0
A0
0
A1
0
A0
1
A1
1
...
A0
0
Device address
DS05–13109–3E
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MB85RC64
■ I2C COMMUNICATION PROTOCOL
The I2C bus is a two wire serial interface that uses a bidirectional data bus (SDA) and serial clock (SCL). A
data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The SDA signal should change while SCL is Low. However, as an exception, when starting and
stopping communication sequence, SDA is allowed to change while SCL is High.
• Start Condition
To start read or write operations by the I2C bus, set the SDA input from High to Low while the SCL input is
in High in order to start reading and writing.
• Stop Condition
Set the SDA input from Low to High while the SCL input is in High in order to terminate the I2C bus communication. Because the MB85RC64 does not need the writing wait time unlike E2PROM, it goes to the standby
state immediately after the stop condition input.
• Start Condition, Stop Condition
SCL
SDA
Start
Stop
Note : The FRAM device does not need the programming wait time like tWC after issuing the Stop Condition
such as.
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MB85RC64
■ ACKNOWLEDGE (ACK)
In the I2C bus, serial data including address or memory information is sent in units of 8 bits. The acknowledge
signal indicates that every each 8 bits of the data is successfully sent and received. The information receiver
side usually outputs “L” every time on the 9th SCL clock after each 8 bits are successfully transmitted. On
the transmitter side, the bus is temporarily released to Hi-Z every time on this 9th clock to allow the acknowledge signal to be received and checked. During this Hi-Z-released period, the receiver side pulls the SDA
line down to indicate “L” that the previous 8bits communication is successfully received.
If the information receiver side detects Stop condition before driving the acknowledge “L”, the read operation
ends and the I2C bus enters the standby state. If Stop condition is not sent, nor does the transmitter detect
the acknowledge “L”, the bus remains in the released state “H” without doing anything.
• Acknowledge timing overview diagram
1
SCL
2
3
8
SDA
9
ACK
Start
DS05–13109–3E
The transmitter side should always release SDA on the
9th bit. At this time, the receiver side outputs a pull-down
to indicate a successful byte transfer (ACK response).
5
MB85RC64
■ DEVICE ADDRESS WORD (Slave address)
Following the start condition, the bus master sends the 8bits device address word (Slave address) to start
I2C communication. The device address word (8bits) consists of a device Type code (4bits), device address
code (3bits), and a read/write code (1bit).
• Device Type Code (4bits)
The upper 4 bits of the device address word are a device type code that identifies the device type, and are
fixed at “1010” for the MB85RC64.
• Device Address Code (3bits)
Following the device type code, the 3 bits of the device address code are input in order of A2, A1, and A0.
Each MB85RC64 is given a unique 3bits code on the device address pin (external hardware pin A2, A1, and
A0). When the device address code is received by the slave device, the slave only responds if the hardware
device address of which is equal to its unique 3bits code.
• Read/Write Code (1bit)
The 8th bit of the device address word is the R/W (read/write) code. When the R/W code is “0”, a write
operation is enabled, and the R/W code is “1”, a read operation is enabled for the MB85RC64.
It turns to a stand-by state if the device code is not “1010” or device address code does not equal to pins
A2, A1, and A0.
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MB85RC64
■ DATA STRUCTURE
In the I2C bus, the acknowledge “L” is output on the 9th bit after the 8 bits of the device and address word
following the start condition. After confirming the acknowledge response at the slave, the I2C master outputs
8bits × 2 memory address to the I2C slave. When the memory address input ends, the slave again outputs
the acknowledge “L”. After this operation, the I/O data follows in units of 8 bits, with the acknowledge “L”
output after every 8bits.
It is determined by the R/W code whether the data line is driven by the master or the slave. For a write
operation the slave will accept 8bits from the master then send an acknowledge. If the master detects the
acknowledge, the master will transfer the next 8bits. For a read operation the slave will place 8bits on the
I2C bus, then wait for an acknowledge from the master.
• Data Structure Diagram
Start
1
2
3
4
5
6
7
8
9
1
2
..
SCL
SDA
ACK
S
1
0
1
0
A2
A1
A0
R/W
A
..
Access from master
Access from slave
S Start Condition
A ACK
■ FRAM ACKNOWLEDGE -- POLLING NOT REQUIRED
The MB85RC64 performs write operations at the same speed as read operations, so any waiting time for
an ACK polling* does not occur. The write cycle takes no additional time.
*: As to E2PROM, the Acknowledge Polling is performed as a progress check in the write programming step.
It places NAK condition on the bus as of “not acknowledged” during the writing programming period. The
busy status for the write programming is given from 9th ACK bit. That “done” condition is placed onto I2C
bus by E2PROM I2C device and your program had to poll the bus in order to sense that condition.
■ WRITE PROTECT (WP)
The entire memory array can be write protected using the Write Protect pin. When the Write Protect pin is
set to “H”, the entire memory map will be write protected. When the Write Protect pin is “L”, all addresses
may be overwritten. Reading is allowed regardless of the WP pin's High/Low.
Note : The Write Protect pin is pulled down internally to VSS pin, therefore if the Write Protect pin is open, the
pin status is detected as Low (write enabled).
DS05–13109–3E
7
MB85RC64
■ COMMAND
• Byte Write
If the 8th bit of the device address word (R/W = 0) is sent following the start condition, the slave responds
with an ACK. After this ACK, write addresses and data are sent in the same way, and the write ends by
master, generating a stop condition at the end.
S
1 0 1 0 A2 A1 A0 0 A
Address
High 8bits
A
0 00XXXXX
Address
Low 8bits
A
Write
Data 8bits
A P
X X X X X X XX
Access from master
MSB
LSB
Access from slave
S Start Condition
P Stop Condition
A ACK
Note : In the MB85RC64, input “000” as the upper 3 bits of the MSB.
• Page Write
If additional 8bits are sent after the same command as Byte Write, a page write is performed. If more bytes
are sent than will fit up to the end of the address, the address rolls over to 0000H. Therefore, if more than
8KBytes are sent, the data is overwritten in order starting from the start of the FRAM memory address that
was written first. Because FRAM performs write operations at bus speed, the data will be written to FRAM
after the ACK response finishes immediately.
S
1 0 1 0 A2 A1 A0 0 A
Address
High 8bits
A
Address
Low 8bits
A
Write
Data 8bits
A
Write
Data
...
A P
Access from master
Access from slave
S Start Condition
P Stop Condition
A ACK
Note : It is not necessary to take a period for internal write operation cycles from the buffer to the memory after
the stop condition is generated.
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DS05–13109–3E
MB85RC64
• Current Address Read
When the previous write or read operation finishes successfully up to the stop command and if the last
accessed address is taken to be “n”, then the address at “n+1” is read by sending the following command
unless turning the power off. If the end of the address range is reached internally, the address counter will
roll over to 0000H. The current address is undefined immediately after the power is turned on.
Access from master
Access from slave
S Start Condition
(n+1) address
S
1 0 1 0 A2 A1 A0 1 A
Read
Data 8bits
N P
P Stop Condition
A ACK
N NACK
• Random Read
The one byte of data at the address as saved in the buffer can be read out synchronously to SCL by specifying
the address in the same way as for a write, and then issuing another start condition and sending the Control
Byte (R/W = 1).
The final NACK is issued by the receiver that receives the data. In this case, this bit is issued by the master
side.
n address
S
1 0 1 0 A2 A1 A0 0 A
Address
High 8bits
A
Address
Low 8bits
A S
1 0 1 0 A2 A1 A0 1 A
Read
Data 8bits
N P
Access from master
Access from slave
S Start Condition
P Stop Condition
A ACK
N NACK
DS05–13109–3E
9
MB85RC64
• Sequential Read
Data can be received continuously following the control byte after specifying the address the same as for
Random Read. If the read reaches the end of address for the MB85RC64, the internal read address automatically rolls over to 0000H.
...
A
Read
Data 8bits
A
Read
Data
...
A
Read
Data 8bits
N P
Access from master
Access from slave
P Stop Condition
A ACK
N NACK
10
DS05–13109–3E
MB85RC64
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Min
Max
Unit
Power supply voltage*
VCC
− 0.5
+4.0
V
Input pin voltage*
VIN
− 0.5
VCC + 0.5 ( ≤ 4.0)
V
VOUT
− 0.5
VCC + 0.5 ( ≤ 4.0)
V
Ambient temperature
TA
− 40
+ 85
°C
Storage temperature
Tstg
− 40
+ 125
°C
Output pin voltage*
*: These parameters are based on the condition that VSS is 0 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Min
Typ
Max
Unit
Power supply voltage*
VCC
2.7
3.3
3.6
V
“H” level input voltage*
VIH
VCC × 0.8
⎯
VCC + 0.5
( ≤ 4.0)
V
“L” level input voltage*
VIL
− 0.5
⎯
+ 0.6
V
Ambient temperature
TA
− 40
⎯
+ 85
°C
*: These parameters are based on the condition that VSS is 0 V.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS05–13109–3E
11
MB85RC64
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(within recommended operating conditions)
Parameter
Symbol
Condition
Input leakage current
|ILI|
Output leakage current
Value
Unit
Min
Typ
Max
SCL, SDA = 0 V to VCC
A0, A1, A2, WP = 0 V or VCC
⎯
⎯
1
μA
|ILO|
VOUT = 0 V to VCC
⎯
⎯
1
μA
Operating power supply current
ICC
SCL = 400 kHz
⎯
100
150
μA
Standby current
ISB
SCL, SDA = VCC
A0, A1, A2, WP = 0 V or VCC
⎯
5
20
μA
“L” level output voltage
VOL
IOL = 2 mA
⎯
⎯
0.4
V
2. AC Characteristics
Parameter
Symbol
Value
Min
Max
Unit
SCL clock frequency
FSCL
0
400
kHz
Clock high time
THIGH
600
⎯
ns
Clock low time
TLOW
1300
⎯
ns
SCL/SDA rise time
Tr
⎯
300
ns
SCL/SDA fall time
Tf
⎯
300
ns
Start condition hold
THD:STA
600
⎯
ns
Start condition setup
TSU:STA
600
⎯
ns
SDA input hold
THD:DAT
0
⎯
ns
SDA input setup
TSU:DAT
100
⎯
ns
SDA output hold
TDH:DAT
0
⎯
ns
Stop condition setup
TSU:STO
600
⎯
ns
SDA output access after SCL fall
TAA
⎯
900
ns
Pre-charge time
TBUF
1300
⎯
ns
50
ns
Pulse width ignored
⎯
TSP
(Input Filter on SCL and SDA)
AC characteristics were measured under the following measurement conditions.
Power supply voltage
: 2.7 V to 3.6 V
Operating temperature
: − 40 °C to + 85 °C
Input voltage magnitude : 0.3 V to 2.7 V
12
Input rise time
: 5 ns
Input fall time
: 5 ns
Input judge level
: VCC/2
Output judge level
: VCC/2
DS05–13109–3E
MB85RC64
3. AC Timing Definitions
TSU:DAT
SCL
VIH
VIL
SDA
Start
THD:DAT
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
TSU:STA THD:STA
TSU:STO
Tr
THIGH
SCL
Stop
VIH
Tf
TLOW
VIH
VIL
VIL
VIH
VIH
VIL
VIL
VIH
SDA
Stop
VIH
VIL
Start
VIH
VIL
VIH
VIL
VIL
Tbuf
Tr
T
TDH:DAT f
Taa
Tsp
VIH
SCL
VIL
VIL
VIH
SDA
VIL
Valid
VIH
VIL
VIL
1/FSCL
4. Pin Capacitance
Parameter
Symbol
Conditions
I/O capacitance
CI/O
Input capacitance
CIN
VIN = VOUT = 0 V,
f = 1 MHz, TA = + 25 °C
Value
Unit
Min
Typ
Min
⎯
⎯
15
pF
⎯
⎯
15
pF
5. AC Test Load Circuit
3.3 V
Output
100 pF
DS05–13109–3E
13
MB85RC64
■ POWER ON SEQUENCE
tr
tpd
tpu
VCC
VCC
2.7 V
2.7 V
VIH (Min)
VIH (Min)
1.0 V
1.0 V
VIL (Max)
VIL (Max)
0V
0V
SDA, SCL
SDA, SCL >VCC × 0.8 *
SDA, SCL : Don't care
SDA, SCL >VCC × 0.8 *
SDA, SCL
* : SDA, SCL (Max) < VCC + 0.5 V
Parameter
Symbol
SDA, SCL level hold time during power down
SDA, SCL level hold time during power up
Power supply rise time
Value
Unit
Min
Max
tpd
85
⎯
ns
tpu
85
⎯
ns
tr
10
⎯
μs
■ NOTES ON USE
• Data written before performing IR reflow is not guaranteed.
• VDD pin is required to be rising from 0 V because turning the power on from an intermediate level may
cause malfunctions, when the power is turned on.
During the access period from the start condition to the stop condition, keep the level of WP, A0, A1, and
A2 pins to “H” or “L”.
14
DS05–13109–3E
MB85RC64
■ ORDERING INFORMATION
Part number
Package
MB85RC64PNF-G-JNE1
8-pin, plastic SOP
(FPT-8P-M02)
MB85RC64PNF-G-JNERE1
8-pin, plastic SOP
(FPT-8P-M02)
DS05–13109–3E
Remarks
Embossed Carrier tape
15
MB85RC64
■ PACKAGE DIMENSION
8-pin plastic SOP
Lead pitch
1.27 mm
Package width ×
package length
3.9 mm × 5.05 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.75 mm MAX
Weight
0.06 g
(FPT-8P-M02)
8-pin plastic SOP
(FPT-8P-M02)
+0.25
Note 1) *1 : These dimensions include resin protrusion.
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
+.010
+0.03
*1 5.05 –0.20 .199 –.008
0.22 –0.07
+.001
.009 –.003
8
5
*2 3.90±0.30 6.00±0.40
(.154±.012) (.236±.016)
Details of "A" part
45°
1.55±0.20
(Mounting height)
(.061±.008)
0.25(.010)
0.40(.016)
1
"A"
4
1.27(.050)
0.44±0.08
(.017±.003)
0.13(.005)
0~8°
M
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.15±0.10
(.006±.004)
(Stand off)
0.10(.004)
C
2002-2010 FUJITSU SEMICONDUCTOR LIMITED F08004S-c-4-9
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
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MEMO
DS05–13109–3E
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MB85RC64
MEMO
18
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MEMO
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MB85RC64
FUJITSU SEMICONDUCTOR LIMITED
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Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
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For further information please contact:
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http://www.fujitsu.com/sg/services/micro/semiconductor/
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http://emea.fujitsu.com/semiconductor/
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Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fss/
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http://kr.fujitsu.com/fsk/
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10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
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by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
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limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
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Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
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by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions.
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