FUJITSU MB90F335APMC

FUJITSU MICROELECTRONICS
DATA SHEET
DS07-13734-7E
16-bit Microcontroller
CMOS
F2MC-16LX MB90330A Series
MB90333A/F334A/F335A/V330A
■ DESCRIPTION
The MB90330A series are 16-bit microcontrollers designed for applications, such as personal computer peripheral
devices, that require USB communications. The USB feature supports not only 12-Mbps Function operation but
also HOST operation. It is equipped with functions that are suitable for personal computer peripheral devices
such as displays and audio devices, and control of mobile devices that support USB communications. While
inheriting the AT architecture of the F2MC family, the instruction set supports the C language and extended
addressing modes and contains enhanced signed multiplication and division instructions as well as a substantial
collection of improved bit manipulation instructions. In addition, long word processing is now available by introducing a 32-bit accumulator.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• Clock
• Built-in oscillation circuit and PLL clock frequency multiplication circuit
• Oscillation clock
• The main clock is the oscillation clock divided into 2 (for oscillation 6 MHz : 3 MHz)
• Clock for USB is 48 MHz
• Machine clock frequency of 6 MHz, 12 MHz, or 24 MHz selectable
• Minimum execution time of instruction : 41.7 ns (6 MHz oscillation clock, 4-time multiplied : machine clock
24 MHz and at operating VCC = 3.3 V).
• The maximum memory space : 16 Mbytes
• 24-bit addressing
(Continued)
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2004-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.9
MB90330A Series
(Continued)
• Bank addressing
• Instruction system
• Data types : Bit, Byte, Word and Long word
• Addressing mode (23 types)
• Enhanced high-precision computing with 32-bit accumulator
• Enhanced Multiply/Divide instructions with sign and the RETI instruction
• Instruction system compatible with high-level language (C language) and multi-task
• Employing system stack pointer
• Instruction set symmetry and barrel shift instructions
• Program Patch Function (2 address pointer)
• 4-byte instruction queue
• Interrupt function
• Priority levels are programmable
• 32 interrupts function
• Data transfer function
• Extended intelligent I/O service function (EI2OS) : Maximum of 16 channels
• μDMAC : Maximum 16 channels
• Low Power Consumption Mode
• Sleep mode (with the CPU operating clock stopped)
• Time-base timer mode (with the oscillator clock and time-base timer operating)
• Stop mode (with the oscillator clock stopped)
• CPU intermittent operation mode (with the CPU operating at fixed intervals of set cycles)
• Watch mode (with 32 kHz oscillator clock and watch timer operating)
• Package
• LQFP-120P (FPT-120P-M24 : 0.40 mm pin pitch)
• LQFP-120P (FPT-120P-M21 : 0.50 mm pin pitch)
• Process : CMOS technology
• Operation guaranteed temperature : − 40 °C to + 85 °C (0 °C to + 70 °C when USB is in use)
2
DS07-13734-7E
MB90330A Series
■ INTERNAL PERIPHERAL FUNCTION (RESOURCE)
• I/O port : Max 94 ports
• Time-base timer : 1 channel
• Watchdog timer : 1 channel
• Watch timer : 1 channel
• 16-bit reload timer : 3 channels
• Multi-functional timer
• 16-bit free run timer : 1 channel
• Output compare : 4 channels
An interrupt request can be output when the 16-bit free-run timer value matches the compare register value.
• Input capture : 4 channels
Upon detection of the effective edge of the signal input to the external input pin, the input capture unit sets the
input capture data register to the 16-bit free-run timer value to output an interrupt request.
• 8/16-bit PPG timer (8-bit × 6 channels or 16-bit × 3 channels) the period and duty of the output pulse can be
set by the program.
• 16-bit PWC timer : 1 channel
Timer function and pulse width measurement function
• UART : 4 channels
• Full-duplex double buffer (8-bit length)
• Asynchronous transfer or clock-synchronous serial (Extended I/O serial) transfer can be set.
• Extended I/O serial interface : 1 channel
• DTP/External interrupt circuit (8 channels)
• Activate the extended intelligent I/O service by external interrupt input
• Interrupt output by external interrupt input
• Delay interrupt output module
• Output an interrupt request for task switching
• 8/10-bit A/D converter : 16 channels
• 8-bit resolution or 10-bit resolution can be set.
• USB : 1 channel
• USB function (correspond to USB Full Speed)
• Full Speed is supported/Endpoint are specifiable up to six.
• Dual port RAM (The FIFO mode is supported).
• Transfer type : Control, Interrupt, Bulk, or Isochronous transfer possible
• USB HOST function
• I2C Interface : 3 channels
• Supports Intel SM bus standard and Phillips I2C bus standards
• Two-wire data transfer protocol specification
• Master and slave transmission/reception
DS07-13734-7E
3
MB90330A Series
■ PRODUCT LINEUP
Part number
MB90V330A
MB90F334A
MB90F335A
MB90333A
For evaluation
Built-in Flash
memory
Built-in Flash
memory
Built-in MASK
ROM
ROM capacity
No
384 Kbytes
512 Kbytes
256 Kbytes
RAM capacity
28 Kbytes
24 Kbytes
30 Kbytes
16 Kbytes
Type
Emulator-specific power supply *
Yes
⎯
CPU functions
Number of basic instructions
: 351 instructions
Minimum instruction execution time : 41.7 ns/at oscillation of 6 MHz
(When 4 times are used : Machine clock
of 24 MHz)
Addressing type
: 23 types
Program Patch Function
: For 2 address pointers
Maximum memory space
: 16 Mbytes
Ports
I/O Ports (CMOS) 94 ports
UART
Equipped with full-duplex double buffer
Clock synchronous or asynchronous operation selectable
It can also be used for I/O serial
Built-in special baud-rate generator
Built-in 4 channels
16-bit reload timer
16-bit reload timer operation
Built-in 3 channels
Multi-functional timer
16-bit free run timer × 1 channel
Output compare × 4 channels
Input capture × 4 channels
8/16-bit PPG timer (8-bit mode × 6 channels, 16-bit mode × 3 channels)
16-bit PWC timer × 1 channel
8/10-bit A/D converter
16 channels (input multiplex)
8-bit resolution or 10-bit resolution can be set.
Conversion time : 7.16 μs at minimum (24 MHz machine clock at maximum)
DTP/External interrupt
8 channels
Interrupt factor : “L”→“H” edge/“H”→“L” edge/“L” level/“H” level selectable
I2C
3 channels
Extended I/O serial interface
1 channel
USB
1 channel
USB function (correspond to USB Full Speed)
USB HOST function
External bus interface
For multi-bus/non-multi-bus
Withstand voltage of 5 V
16 ports (excluding UTEST and I/O for I2C)
Low Power Consumption Mode
Sleep mode/Time-base timer mode/Stop mode/CPU intermittent mode/
Watch mode
Process
CMOS
Operating voltage
3.3 V ± 0.3 V (at maximum machine clock 24 MHz)
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the
MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details.
4
DS07-13734-7E
MB90330A Series
■ PACKAGES AND PRODUCT MODELS
Package
MB90333A
MB90F334A
MB90F335A
MB90V330A
FPT-120P-M24 (LQFP-0.40 mm)
×
FPT-120P-M21 (LQFP-0.50 mm)
×
PGA-299C-A01 (PGA)
×
×
×
: Yes × : No
Note : For detailed information on each package, refer to “■ PACKAGE DIMENSIONS”.
DS07-13734-7E
5
P92/SCK2
P93/SIN3
P94/SOT3
P95/SCK3
P96/ADTG/FRCK
AVCC
AVRH
AVSS
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7
VSS
P80/AN8
P81/AN9
P82/AN10
P83/AN11
P84/AN12
P85/AN13
P86/AN14
P87/AN15
PA0/IN0
PA1/IN1
PA2/IN2
PA3/IN3
PA4/OUT0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
P27/A23/PPG3
P26/A22/PPG2
P25/A21/PPG1
P24/A20/PPG0
P23/A19
P22/A18
P21/A17
P20/A16
P17/AD15/D15
P16/AD14/D14
P15/AD13/D13
P14/AD12/D12
X0
X1
VSS
VCC
P13/AD11/D11
P12/AD10/D10
P11/AD09/D09
P10/AD08/D08
P07/AD07/D07
P06/AD06/D06
P05/AD05/D05
P04/AD04/D04
P03/AD03/D03
P02/AD02/D02
P01/AD01/D01
P00/AD00/D00
P57/CLK
P56/RDY
MB90330A Series
■ PIN ASSIGNMENT
(TOP VIEW)
P30/A00/TIN1
P31/A01/TOT1
P32/A02/TIN2
P33/A03/TOT2
P34/A04
P35/A05
P36/A06
P37/A07
P40/A08/TIN0
P41/A09/TOT0
P42/A10/SIN0
P43/A11/SOT0
X0A
X1A
VCC
VSS
P44/A12/SCK0
P45/A13/SIN1
P46/A14/SOT1
P47/A15/SCK1
P60/INT0
P61/INT1
P62/INT2/SIN
P63/INT3/SOT
P64/INT4/SCK
P65/INT5/PWC
P66/INT6/SCL0
P67/INT7/SDA0
P90/SIN2
P91/SOT2
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
RST
MD0
MD1
MD2
P55/HAK
P54/HRQ
P53/WRH
P52/WRL
P51/RD
P50/ALE
HCON
VCC
HVP
HVM
VSS
VCC
DVP
DVM
VSS
UTEST
PB6/PPG5
PB5/PPG4
PB4
PB3/SDA2
PB2/SCL2
PB1/SDA1
PB0/SCL1
PA7/OUT3
PA6/OUT2
PA5/OUT1
(FPT-120P-M24 / FPT-120P-M21)
DS07-13734-7E
MB90330A Series
■ PIN DESCRIPTION
Pin no.
Pin name
I/O
Circuit
type*
108, 107
X0, X1
A
Terminals to connect the oscillator.
When connecting an external clock, leave the X1 pin side unconnected.
13, 14
X0A, X1A
A
32 kHz oscillation terminals.
90
RST
F
External reset input pin.
General purpose input/output port.
The ports can be set to be added with a pull-up resistor (RD00 to RD07 = 1)
by the pull-up resistor setting register (RDR0). (When the power output is
set, it is invalid.)
P00 to P07
93 to 100
Function
H
AD00 to AD07
Function as an I/O pin for the low-order external address and data bus in
multiplex mode.
D00 to D07
Function as an output pin for the low-order external data bus in nonmultiplex mode.
P10 to P13
General purpose input/output port.
The ports can be set to be added with a pull-up resistor (RD10 to RD13 = 1)
by the pull-up resistor setting register (RDR1). (When the power output is
set, it is invalid.)
101 to 104
H
AD08 to AD11
Function as an I/O pin for the high-order external address and data bus in
multiplex mode.
D08 to D11
Function as an output pin for the high-order external data bus in nonmultiplex mode.
P14 to P17
General purpose input/output port.
The ports can be set to be added with a pull-up resistor (RD14 to RD17 = 1)
by the pull-up resistor setting register (RDR1). (When the power output is
set, it is invalid.)
109 to 112
H
AD12 to D15
Function as an I/O pin for the high-order external address and data bus in
multiplex mode.
D12 to D15
Function as an output pin for the high-order external data bus in nonmultiplex mode.
P20 to P23
This is a general purpose I/O port. When the bits of external address output
control register (HACR) are set to “1” in external bus mode, these pins
function as general purpose I/O ports.
113 to 116
D
A16 to A19
When the bits of external address output control register (HACR) are set to
“0” in multiplex mode, these pins function as address high output pins.
When the bits of external address output control register (HACR) are set to
“0” in non-multiplex mode, these pins function as address high output pins.
(Continued)
DS07-13734-7E
7
MB90330A Series
Pin no.
Pin name
I/O
Circuit
type*
This is a general purpose I/O port. When the bits of external address
output control register (HACR) are set to “1” in external bus mode, these
pins function as general purpose I/O ports.
P24 to P27
117 to 120
D
A20 to A23
Function as ch.0 to ch.3 output pins for the 8-bit PPG timer.
P30
2
A00
General purpose input/output port.
D
Function as an event input pin for 16-bit reload timer ch.1.
P31
General purpose input/output port.
A01
D
A02
General purpose input/output port.
D
Function as an event input pin for 16-bit reload timer ch.2.
P33
General purpose input/output port.
A03
D
P34 to P37
A04 to A07
A08
D
G
12
General purpose input/output port.
G
Function as the external address pin in non-multi-bus mode.
SIN0
Function as a data input pin for UART ch.0.
P43
General purpose input/output port.
A11
G
SOT0
A12
SCK0
Function as the external address pin in non-multi-bus mode.
Function as a data output pin for UART ch.0.
P44
17
Function as the external address pin in non-multi-bus mode.
Function as the output pin for 16-bit reload timer ch.0.
P42
A10
Function as the external address pin in non-multi-bus mode.
General purpose input/output port.
G
TOT0
11
Function as the external address pin in non-multi-bus mode.
Function as an event input pin for 16-bit reload timer ch.0.
P41
A09
General purpose input/output port.
General purpose input/output port.
TIN0
10
Function as the external address pin in non-multi-bus mode.
Function as the output pin for 16-bit reload timer ch.2.
P40
9
Function as the external address pin in non-multi-bus mode.
TIN2
TOT2
5 to 8
Function as the external address pin in non-multi-bus mode.
Function as the output pin for 16-bit reload timer ch.1.
P32
4
Function as the external address pin in non-multi-bus mode.
TIN1
TOT1
3
When the bits of external address output control register (HACR) are set
to “0” in multiplex mode, these pins function as address high output pins.
When the bits of external address output control register (HACR) are set
to “0” in non-multiplex mode, these pins function as address high output
pins.
PPG0 to PPG3
1
Function
General purpose input/output port.
G
Function as the external address pin in non-multi-bus mode.
Function as a clock I/O pin for UART ch.0.
(Continued)
8
DS07-13734-7E
MB90330A Series
Pin no.
Pin name
I/O
Circuit
type*
P45
18
A13
19
General purpose input/output port.
G
Function as a data input pin for UART ch.1.
P46
General purpose input/output port.
G
SOT1
A15
General purpose input/output port.
G
SCK1
P50
ALE
P51
82
RD
WRL
L
L
WRH
L
HRQ
L
HAK
L
RDY
L
21, 22
CLK
P60, P61
INT0, INT1
Function as the data write strobe output pin on the lower side in external
bus mode. This pin functions as a general-purpose I/O port when the WRE
bit in the EPCR register is “0”.
Function as the data write strobe output pin on the higher side in bus width
16-bit external bus mode. This pin functions as a general-purpose I/O port
when the WRE bit in the EPCR register is “0”.
Function as the hold request input pin in external bus mode. This pin
functions as a general-purpose I/O port when the HDE bit in the EPCR
register is “0”.
Function as the hold acknowledge output pin in external bus mode. This pin
functions as a general-purpose I/O port when the HDE bit in the EPCR
register is “0”.
General purpose input/output port.
L
P57
92
Function as the read strobe output pin in external bus mode.
General purpose input/output port.
P56
91
General purpose input/output port.
General purpose input/output port.
P55
86
Function as the address latch enable signal pin in external bus mode.
General purpose input/output port.
P54
85
General purpose input/output port.
General purpose input/output port.
P53
84
Function as the external address pin in non-multi-bus mode.
Function as a clock I/O pin for UART ch.1.
P52
83
Function as the external address pin in non-multi-bus mode.
Function as a data output pin for UART ch.1.
P47
81
Function as the external address pin in non-multi-bus mode.
SIN1
A14
20
Function
Function as the external ready input pin in external bus mode. This pin
functions as a general-purpose I/O port when the RYE bit in the EPCR
register is “0”.
General purpose input/output port.
L
C
Function as the machine cycle clock output pin in external bus mode. This
pin functions as a general-purpose I/O port when the CKE bit in the EPCR
register is “0”.
General purpose input/output port. (With stand voltage of 5 V)
Function as external interrupt ch.0 and ch.1 input pins.
(Continued)
DS07-13734-7E
9
MB90330A Series
Pin no.
Pin name
I/O
Circuit
type*
P62
23
24
25
INT2
General purpose input/output ports. (Withstand voltage of 5 V)
C
Extended I/O serial interface data input pin.
P63
General purpose input/output port. (Withstand voltage of 5 V)
INT3
C
Extended I/O serial interface data output pin.
P64
General purpose input/output port. (Withstand voltage of 5 V)
INT4
C
INT5
General purpose input/output port. (Withstand voltage of 5 V)
C
Function as the PWC input pin.
P66
General purpose input/output port. (Withstand voltage of 5 V)
INT6
C
INT7
29
30
31
32
33
34
P70 to P77
AN0 to AN7
P80 to P87
AN8 to AN15
P90
SIN2
P91
SOT2
P92
SCK2
P93
SIN3
P94
SOT3
P95
SCK3
C
I
I
D
D
D
D
D
D
P96
35
ADTG
FRCK
Function as an external interrupt ch.6 input pin.
Function as the ch.0 clock I/O pin for the I2C interface. Set port output to
High-Z during I2C interface operations.
General purpose input/output port. (Withstand voltage of 5 V)
SDA0
48 to 55
Function as an external interrupt ch.5 input pin.
PWC
P67
39 to 46
Function as an external interrupt ch.4 input pin.
Extended I/O serial interface clock input/output pin.
SCL0
28
Function as an external interrupt ch.3 input pin.
SOT
P65
27
Function as an external interrupt ch.2 input pin.
SIN
SCK
26
Function
Function as an external interrupt ch.7 input pin.
Function as the ch.0 data I/O pin for the I2C interface. Set port output to
High-Z during I2C interface operations.
General purpose input/output port.
Function as input pins for analog ch.0 to ch.7.
General purpose input/output port.
Function as input pins for analog ch.8 to ch.15.
General purpose input/output port.
Function as a data input pin for UART ch.2.
General purpose input/output port.
Function as a data output pin for UART ch.2.
General purpose input/output port.
Function as a clock I/O pin for UART ch.2.
General purpose input/output port.
Function as a data input pin for UART ch.3.
General purpose input/output port.
Function as a data output pin for UART ch.3.
General purpose input/output port.
Function as a clock I/O pin for UART ch.3.
General purpose input/output port. (Withstand voltage of 5 V)
C
Function as the external trigger input pin when the A/D converter is being used.
Function as the external clock input pin when the free-run timer is being used.
(Continued)
10
DS07-13734-7E
MB90330A Series
(Continued)
Pin no.
56 to 59
60 to 63
Pin name
PA0 to PA3
IN0 to IN3
PA4 to PA7
OUT0 to OUT3
I/O
Circuit
type*
C
C
PB0
64
SCL1
SDA1
SCL2
C
68
69, 70
SDA2
PB4
PB5, PB6
PPG4, PPG5
General purpose input/output port. (Withstand voltage of 5 V)
Function as the output compare ch.0 to ch.3 event output pins.
Function as the ch.1 clock I/O pin for the I2C interface. Set port output to
High-Z during I2C interface operations.
Function as the ch.1 data I/O pin for the I2C interface. Set port output to
High-Z during I2C interface operations.
General purpose input/output port. (Withstand voltage of 5 V)
C
PB3
67
Function as the input capture ch.0 to ch.3 trigger inputs.
General purpose input/output port. (Withstand voltage of 5 V)
PB2
66
General purpose input/output port. (Withstand voltage of 5 V)
General purpose input/output port. (Withstand voltage of 5 V)
C
PB1
65
Function
Function as the ch.2 clock I/O pin for the I2C interface. Set port output to
High-Z during I2C interface operations.
General purpose input/output port. (Withstand voltage of 5 V)
C
C
D
Function as the ch.2 data I/O pin for the I2C interface. Set port output to
High-Z during I2C interface operations.
General purpose input/output port. (Withstand voltage of 5 V)
General purpose input/output port.
Function as ch.4 and ch.5 output pins for the 8-bit PPG timer.
71
UTEST
C
USB test pin. Connect this to a pull-down resistor during normal usage.
73
DVM
K
USB function D− pin.
74
DVP
K
USB function D+ pin.
77
HVM
K
USB HOST D− pin.
78
HVP
K
USB HOST D+ pin.
80
HCON
E
External pull-up resistor connect pin.
36
AVcc
⎯
A/D converter power supply pin.
37
AVRH
J
A/D converter external reference power supply pin.
38
AVss
⎯
A/D converter power supply pin.
87 to 89
MD2 to MD0
B
Operation mode select input pin.
15, 75,
79, 105
Vcc
⎯
Power supply pin.
16, 47,
72, 76,
106
Vss
⎯
Power supply pin (GND).
* : For circuit information, refer to “■ I/O CIRCUIT TYPE”.
DS07-13734-7E
11
MB90330A Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
X1
Clock input
X1A
X0
X0A
Standby control signal
B
• High-rate oscillation feedback resistor,
approx.1 MΩ
• Low-rate oscillation feedback resistor,
approx.10 MΩ
• With standby control
CMOS hysteresis input
CMOS hysteresis
input
C
• CMOS hysteresis input
• N-ch open drain output
N-ch
Nout
CMOS hysteresis input
Standby control signal
D
P-ch
Pout
N-ch
Nout
CMOS hysteresis input
Standby control signal
E
• CMOS output
• CMOS hysteresis input
(With input interception function at
standby)
Notes : • Share one output buffer because
both output of I/O port and
internal resource are used.
• Share one input buffer because
both input of I/O port and internal
resource are used.
CMOS output
P-ch
Pout
N-ch
Nout
F
CMOS hysteresis input with pull-up resistor
R
CMOS hysteresis
input
(Continued)
12
DS07-13734-7E
MB90330A Series
Type
Circuit
Remarks
G
P-ch
Pout
N-ch
Nout
Open drain control
signal
• CMOS output
• CMOS hysteresis input
(With input interception function at
standby)
With open drain control signal
CMOS hysteresis
input
Standby control
signal
H
• CMOS output
• CMOS input
(With input interception function at
standby)
• With input pull-up register control
CTL
R
P-ch
Pout
N-ch
Nout
CMOS input
Standby control signal
I
P-ch
Pout
N-ch
Nout
CMOS hysteresis
input
Standby control signal
A/D converter analog
input
J
• CMOS output
• CMOS hysteresis input
(With input interception function at
standby)
• Analog input
(The A/D converter analog input is enabled
when the corresponding bit in the analog
input enable register (ADER) is 1.)
Notes: • Because the output of the I/O port and
the output of internal resources are
used combinedly, one output buffer
is shared.
• Because the input of the I/O port
and the input of internal resources
are used combinedly, one input
buffer is shared.
A/D converter (AVRH) voltage input pin
P-ch
P-ch
N-ch
N-ch
AVRH input
A/D converter
analog input
enable signal
(Continued)
DS07-13734-7E
13
MB90330A Series
(Continued)
Type
Circuit
Remarks
K
USB I/O pin
D + input
D - input
D+
Differential input
D−
Full D + output
Full D - output
Low D + output
Low D - output
Direction
Speed
L
P-ch
Pout
N-ch
Nout
• CMOS output
• CMOS input
• With standby control
CMOS input
Standby control signal
14
DS07-13734-7E
MB90330A Series
■ HANDLING DEVICES
1. Preventing latch-up and turning on power supply
Latch-up may occur on CMOS IC under the following conditions:
• If a voltage higher than VCC or lower than VSS is applied to input and output pins.
• A voltage higher than the rated voltage is applied between VCC pin and VSS pin.
• If the AVCC power supply is turned on before the VCC voltage.
Ensure that you apply a voltage to the analog power supply at the same time as VCC or after you turn on the
digital power supply (when you perform power-off, turn off the analog power supply first or at the same time as
VCC and the digital power supply).
If latch-up occurs, the supply current increases rapidly, sometimes resulting in thermal breakdown of the device.
Use meticulous care not to let any voltage exceed the maximum rating.
2. Treatment of unused pins
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent
damage.
Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/
output pins may be set to output mode and left open, or set to input mode and treated the same as unused input
pins. If there is unused output pin, make it to open.
3. Treatment of power supply pins on models with A/D converters
Even when the A/D converters are not in use, be sure to make the necessary connections AVCC = AVRH = VCC,
and AVSS = VSS.
4. About the attention when the external clock is used
Even when using an external clock signal, an oscillation stabilization delay is applied after a power-on reset or
when recovering from sub clock or stop mode. When suing an external clock, 25 MHz should be the upper
frequency limit.
The following figure shows a sample use of external clock signals.
• Using external clock
X0
OPEN
X1
5. Treatment of power supply pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the
current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC pin and VSS pin
near this device.
DS07-13734-7E
15
MB90330A Series
6. About Crystal oscillator circuit
Noise near the X0/X1 pins and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1 pins and X0A/X1A pins, the crystal oscillator (or the ceramic oscillator) and the bypass
capacitor to ground are located as close to the device as possible.
It is strongly recommended to design the PC board artwork with the X0/X1 pins and X0A/X1A pins surrounded
by ground plane because stable operation can be expected with such a layout.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
7. Caution on Operations during PLL Clock Mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
8. Stabilization of supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage
operating range. For stabilization reference, the supply voltage should be stabilized so that VCC ripple variations
(peak-to-peak value) at commercial frequencies (50 Hz/60 Hz) fall below 10% of the standard VCC supply voltage
and the transient regulation does not exceed 0.1 V/ms at temporary changes such as power supply switching.
9. When the dual-supply is used as a single-supply device
If you are using only a single-system of the MB90330A series that come in the dual-system product, use it with
X0A = VSS : X1A = OPEN.
10. Writing to flash memory
For serial writing to flash memory, always make sure that the operating voltage VCC is between 3.13 V and 3.6 V.
For normal writing to flash memory, always make sure that the operating voltage VCC is between 3.0 V and 3.6 V.
11. Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication. Therefore,
design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example, apply a checksum to detect an error.
If an error is detected, retransmit the data.
16
DS07-13734-7E
MB90330A Series
■ BLOCK DIAGRAM
X0, X1
X0A,X1A
RST
MD0 to MD2
Clock control
circuit
F2MC-16LX
CPU
Interrupt
controller
8/16-bit
PPG timer
ch.0 to ch.5*
PPG0 to PPG5
Input capture
ch.0 to ch.3
IN0 to IN3
16-bit free-run
timer
FRCK
RAM
SIN0 to SIN3
SOT0 to SOT3
SCK0 to SCK3
UART/SIO
ch.0 to ch.3
SCL0 to SCL2
SDA0 to SDA2
I2C
ch.0 to ch.2
AVCC
AVRH
AVSS
AN0 to AN15
ADTG
8/10-bit A/D
converter
TOT0 to TOT2
TIN0 to TIN2
16-bit reload
timer
ch.0 to ch.2
DVP
DVM
HVP
HVM
HCON
UTEST
Internal data bus
ROM
Output compare
ch.0 to ch.3
USB
(Function)
(HOST)
OUT0 to OUT3
16-bit PWC
PWC
SIO
SIN
SOT
SCK
µDMAC
External
interrupt
INT0 to INT7
I/O port (port 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B)
P00
P10
P20
P30
P40
P50
P60
P70
P80
P90
PA0 PB0
P07
P17
P27
P37
P47
P57
P67
P77
P87
P96
PA7 PB6
* : Channel for use in 8-bit mode. 3 channels (ch.1, ch.3, ch.5) are used in 16-bit mode.
Note : I/O ports share pins with peripheral function (resources) .
For details, refer to “■ PIN ASSIGNMENT” and “■ PIN DESCRIPTION”.
Note also that pins used for peripheral function (resources) cannot serve as I/O ports.
DS07-13734-7E
17
MB90330A Series
■ MEMORY MAP
Memory map of MB90330A series (1/3)
Single chip mode (with ROM mirror function)
MB90V330A
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
ROM (FF bank)
008000H
007FFFH
FFFFFFH
ROM (FE bank)
FF0000H
FEFFFFH
ROM (FD bank)
FE0000H
FDFFFFH
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (F8 bank)
F80000H
00FFFFH
MB90F334A
ROM
(image of FF bank)
Peripheral area
007900H
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
F80000H
00FFFFH
008000H
007FFFH
ROM (FF bank)
MB90F335A
FFFFFFH
ROM (FE bank)
FF0000H
FEFFFFH
ROM (FD bank)
FE0000H
FDFFFFH
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM
(image of FF bank)
Peripheral area
007900H
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
F80000H
00FFFFH
008000H
007FFFH
000100H
Register
0000FBH
18
ROM (FD bank)
FE0000H
FDFFFFH
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (F8 bank)
ROM
(image of FF bank)
Peripheral area
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
F80000H
000100H
Register
0000FBH
ROM (FE bank)
ROM (FD bank)
ROM (FB bank)
ROM
008000H (image of FF bank)
007FFFH
Peripheral area
007900H
004100H
RAM area
(16 Kbytes)
000100H
Register
0000FBH
Peripheral area
000000H
ROM (FF bank)
00FFFFH
RAM area
(24 Kbytes)
Peripheral area
000000H
ROM (FE bank)
RAM area
(30 Kbytes)
006100H
FFFFFFH
FF0000H
FEFFFFH
007900H
007100H
RAM area
(28 Kbytes)
ROM (FF bank)
MB90333A
000100H
0000FBH
Peripheral area
Peripheral area
000000H
Register
000000H
DS07-13734-7E
MB90330A Series
Memory map of MB90330A series (2/3)
Internal ROM external bus mode (with ROM mirror function)
MB90V330A
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (F8 bank)
F80000H
MB90F334A
008000H
007FFFH
ROM
(image of FF bank)
Peripheral area
007900H
FFFFFFH
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
F80000H
External area
00FFFFH
MB90F335A
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
*1
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
*1
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
F80000H
External area
00FFFFH
008000H
007FFFH
ROM
(image of FF bank)
Peripheral area
007900H
External area
RAM area
(28 Kbytes)
0000FBH
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (F8 bank)
00FFFFH
008000H
007FFFH
ROM
(image of FF bank)
Peripheral area
007900H
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
F80000H
Register
Peripheral area
ROM (FD bank)
*2
ROM (FB bank)
*2
External area
External area
00FFFFH
008000H
007FFFH
ROM
(image of FF bank)
Peripheral area
External area
004100H
RAM area
(16 Kbytes)
000100H
Register
0000FBH
Peripheral area
000000H
ROM (FE bank)
External area
RAM area
(24 Kbytes)
000100H
ROM (FF bank)
007900H
RAM area
(30 Kbytes)
0000FBH
000000H
ROM (FE bank)
FF0000H
FEFFFFH
External area
006100H
Register
FFFFFFH
ROM (FF bank)
External area
007100H
000100H
MB90333A
000100H
0000FBH
Peripheral area
Peripheral area
000000H
Register
000000H
*1 : In the area of F80000H to F8FFFFH and FC0000H to FCFFFFH at MB90F334A, a value of “1” is read at
read operating.
*2 : In the area of FA0000H to FAFFFFH and FC0000H to FCFFFFH at MB90333A, a value of “1” is read at
read operating.
DS07-13734-7E
19
MB90330A Series
Memory map of MB90330A series (3/3)
External ROM external bus mode
MB90V330A
FFFFFFH
MB90F334A
008000H
007FFFH
Peripheral area
007900H
007100H
FFFFFFH
FFFFFFH
External area
MB90F335A
External area
008000H
007FFFH
Peripheral area
007900H
External area
External area
008000H
007FFFH
0000FBH
External area
008000H
007FFFH
000100H
Register
0000FBH
RAM area
(30 Kbytes)
004100H
RAM area
(16 Kbytes)
000100H
Register
0000FBH
Peripheral area
000000H
Peripheral area
007900H
External area
RAM area
(24 Kbytes)
Peripheral area
000000H
Peripheral area
007900H
006100H
Register
FFFFFFH
External area
RAM area
(28 Kbytes)
000100H
MB90333A
000100H
0000FBH
Peripheral area
000000H
Register
Peripheral area
000000H
Notes: • When the ROM mirror function register has been set, the mirror image data at higher addresses
(“FF8000H to FFFFFFH”) of bank FF is visible from the higher addresses (“008000H to 00FFFFH”) of
bank 00.
• The ROM mirror function is effective for using the C compiler small model.
• The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in
bank FF exceeds 48 Kbytes, however, the mirror image of all the data in the ROM area cannot be
reproduced in bank 00.
• When the C compiler small model is used, the data table mirror image can be shown at “008000H to
00FFFFH” by storing the data table at “FF8000H to FFFFFFH”. Therefore, data tables in the ROM
area can be referred without declaring the far addressing with the pointer.
• MB90F335A has the larger size of RAM area than MB90V330A, so that the emulation memory area needs
to be set in the tools for a larger size of emulation area than 007100H.
For details of setting, please refer to “Notes on Debug Environment Setting for MB90330A Series” by
clicking "Application note" at the following URL.
http://edevice.fujitsu.com/micom/en-support/
• 3 cycles are required to access to the emulation memory area (007100H to 0078FFH), which is 1 cycle
more than to the mounted RAM area.
20
DS07-13734-7E
MB90330A Series
■ F2MC-16LX CPU PROGRAMMING MODEL
• Dedicated register
AH
Accumulator
AL
USP
User stack pointer
SSP
System stack pointer
PS
Processor status
PC
Program counter
DPR
Direct page register
PCB
Program bank register
DTB
Data bank register
USB
User stack bank register
SSB
System stack bank register
ADB
Additional data bank register
8-bit
16-bit
32-bit
• General purpose register
MSB
LSB
16-bit
000180H + RP × 10H
RW0
RL0
RW1
RW2
RL1
RW3
R1
R0
RW4
R3
R2
RW5
R5
R4
RW6
R7
R6
RW7
RL2
RL3
• Processor status
Bit 15
PS
DS07-13734-7E
13 12
ILM
8 7
RP
0
CCR
21
MB90330A Series
■ I/O MAP
Address
000000H
000001H
000002H
000003H
000004H
000005H
000006H
000007H
000008H
000009H
00000AH
00000BH
00000CH
00000DH
00000EH
00000FH
000010H
000011H
000012H
000013H
000014H
000015H
000016H
000017H
000018H
000019H
00001AH
Register
abbreviation
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
PDRA
Read/
Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Register
Port 0 Data Register
Port 1 Data Register
Port 2 Data Register
Port 3 Data Register
Port 4 Data Register
Port 5 Data Register
Port 6 Data Register
Port 7 Data Register
Port 8 Data Register
Port 9 Data Register
Port A Data Register
Resource name
Initial Value
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
- XXXXXXXB
XXXXXXXXB
R/W
R/W
Port B
Port B
- XXXXXXXB
- 0 0 0 0 0 0 0B
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port 4
(open drain control)
Port 0 (PULL-UP)
Port 1 (PULL-UP)
Port 7, 8, A/D
Port 7, 8, A/D
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
- 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
Prohibited
PDRB
DDRB
Port B Data Register
Port B Direction Register
Prohibited
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
DDR6
DDR7
DDR8
DDR9
DDRA
Port 0 Direction Register
Port 1 Direction Register
Port 2 Direction Register
Port 3 Direction Register
Port 4 Direction Register
Port 5 Direction Register
Port 6 Direction Register
Port 7 Direction Register
Port 8 Direction Register
Port 9 Direction Register
Port A Direction Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00001BH
ODR4
Port 4 Output Pin Register
R/W
00001CH
00001DH
00001EH
00001FH
000020H
000021H
RDR0
RDR1
ADER0
ADER1
SMR0
SCR0
SIDR0
SODR0
SSR0
UTRLR0
UTCR0
Port 0 Pull-up Resistance Register
Port 1 Pull-up Resistance Register
Analog Input Enable Register 0
Analog Input Enable Register 1
Serial Mode Register 0
Serial Control Register 0
Serial Input Data Register 0
Serial Output Data Register 0
Serial Status Register 0
UART Prescaler Reload Register 0
UART Prescaler Control Register 0
R/W
R/W
R/W
R/W
R/W
R/W
R
W
R/W
R/W
R/W
000022H
000023H
000024H
000025H
UART0
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
0 0 1 0 0 0 0 0B
0 0 0 0 0 1 0 0B
XXXXXXXXB
0 0 0 0 1 0 0 0B
Communication 0 0 0 0 0 0 0 0B
Prescaler (UART0) 0 0 0 0 - 0 0 0B
(Continued)
22
DS07-13734-7E
MB90330A Series
Address
000026H
000027H
000028H
000029H
00002AH
00002BH
00002CH
00002DH
00002EH
00002FH
000030H
000031H
000032H
000033H
000034H
000035H
000036H
000037H
000038H
to
00003BH
00003CH
00003DH
00003EH
00003FH
000040H
000041H
000042H
000043H
000044H
Register
abbreviation
SMR1
SCR1
SIDR1
SODR1
SSR1
UTRLR1
UTCR1
SMR2
SCR2
SIDR2
SODR2
SSR2
UTRLR2
UTCR2
SMR3
SCR3
SIDR3
SODR3
SSR3
UTRLR3
UTCR3
Register
Serial Mode Register 1
Serial Control Register 1
Serial Input Data Register 1
Serial Output Data Register 1
Serial Status Register 1
UART Prescaler Reload Register 1
UART Prescaler Control Register 1
Serial Mode Register 2
Serial Control Register 2
Serial Input Data Register 2
Serial Output Data Register 2
Serial Status Register 2
UART Prescaler Reload Register 2
UART Prescaler Control Register 2
Serial Mode Register 3
Serial Control Register 3
Serial Input Data Register 3
Serial Output Data Register 3
Serial Status Register 3
UART Prescaler Reload Register 3
UART Prescaler Control Register 3
Read/
Write
R/W
R/W
R
W
R/W
R/W
R/W
R/W
R/W
R
W
R/W
R/W
R/W
R/W
R/W
R
W
R/W
R/W
R/W
Resource name
Initial Value
0 0 1 0 0 0 0 0B
0 0 0 0 0 1 0 0B
UART1
XXXXXXXXB
0 0 0 0 1 0 0 0B
0
0 0 0 0 0 0 0B
Communication
Prescaler (UART1) 0 0 0 0 - 0 0 0B
0 0 1 0 0 0 0 0B
0 0 0 0 0 1 0 0B
UART2
XXXXXXXXB
0 0 0 0 1 0 0 0B
0
0 0 0 0 0 0 0B
Communication
Prescaler (UART2) 0 0 0 0 - 0 0 0B
0 0 1 0 0 0 0 0B
0 0 0 0 0 1 0 0B
UART3
XXXXXXXXB
0 0 0 0 1 0 0 0B
0
0 0 0 0 0 0 0B
Communication
Prescaler (UART3) 0 0 0 0 - 0 0 0B
Prohibited
ENIR
EIRR
ELVR
ADCS0
ADCS1
ADCR0
ADCR1
000045H
ADMR
000046H
PPGC0
000047H
PPGC1
000048H
PPGC2
DTP/Interrupt Enable Register
DTP/Interrupt Source Register
Request Level Setting Register Lower
Request Level Setting Register Upper
A/D Control Status Register Lower
A/D Control Status Register Upper
A/D Data Register Lower
A/D Data Register Upper
Prohibited
A/D Conversion Channel Selection
Register
PPG0 Operation Mode Control
Register
PPG1 Operation Mode Control
Register
PPG2 Operation Mode Control
Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DTP/External
Interrupt
8/10-bit
A/D Converter
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 - - - - - 0B
0 0 0 0 0 0 0 0B
XXXXXXXXB
0 0 1 0 1 XXXB
R/W
8/10-bit
A/D Converter
0 0 0 0 0 0 0 0B
R/W
PPG ch.0
0X0 0 0XX1B
R/W
PPG ch.1
0X0 0 0 0 0 1B
R/W
PPG ch.2
0X0 0 0XX1B
(Continued)
DS07-13734-7E
23
MB90330A Series
Address
Register
abbreviation
Register
Read/
Write
Resource name
Initial Value
000049H
PPGC3
PPG3 Operation Mode Control Register
R/W
PPG ch.3
0X0 0 0 0 0 1B
00004AH
PPGC4
PPG4 Operation Mode Control Register
R/W
PPG ch.4
0X0 0 0XX1B
00004BH
PPGC5
PPG5 Operation Mode Control Register
R/W
PPG ch.5
0X0 0 0 0 0 1B
00004CH
PPG01
PPG0 and PPG1 Output Control
Register
R/W
PPG ch.0/ch.1
0 0 0 0 0 0XXB
R/W
PPG ch.2/ch.3
0 0 0 0 0 0 XXB
R/W
PPG ch.4/ch.5
0 0 0 0 0 0 XXB
Input Capture
ch.0/ch.1
0 0 0 0 0 0 0 0B
00004DH
00004EH
Prohibited
PPG23
PPG2 and PPG3 Output Control
Register
00004FH
000050H
Prohibited
PPG45
PPG4 and PPG5 Output Control
Register
000051H
Prohibited
000052H
ICS01
Input Capture Control Status Register 01
R/W
000053H
ICS23
Input Capture Control Status Register 23
R/W
000054H
OCS0
Output Compare Control Register ch.0
Lower
R/W
000055H
OCS1
Output Compare Control Register ch.1
Upper
R/W
000056H
OCS2
Output Compare Control Register ch.2
Lower
R/W
000057H
OCS3
Output Compare Control Register ch.3
Upper
R/W
SMCS
Serial Mode Control Status Register
R/W
Serial Data Register
R/W
Communication Prescaler Control
Register
R/W
PWC Control Status Register
R/W
PWC Data Buffer Register
R/W
000058H
000059H
00005AH
SDR
00005BH
SDCR
00005CH
00005DH
00005EH
00005FH
000060H
PWCSR
PWCR
DIVR
000061H
000062H
000063H
000064H
000065H
PWC Dividing Ratio Control Register
Input
0 0 0 0 0 0 0 0B
Capture ch.2/ch.3
Output
Compare
ch.0/ch.1
0 0 0 0 - - 0 0B
Output
Compare
ch.2/ch.3
0 0 0 0 - - 0 0B
- - - 0 0 0 0 0B
- - - 0 0 0 0 0B
XXXX0 0 0 0B
Extended Serial
I/O
0 0 0 0 0 0 1 0B
Communication
Prescaler
0XXX0 0 0 0B
XXXXXXXXB
0 0 0 0 0 0 0 0B
16-bit
PWC Timer
R/W
0 0 0 0 0 0 0 XB
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
- - - - - - 0 0B
Prohibited
TMCSR0
TMR0
TMRLR0
TMR0
TMRLR0
Timer Control Status Register 0
0 0 0 0 0 0 0 0B
R/W
XXXX 0 0 0 0B
16-bit
Reload Timer
ch.0
16-bit Timer Register 0 Lower
R
16-bit Reload Register 0 Lower
W
XXXXXXXXB
16-bit Timer Register 0 Upper
R
XXXXXXXXB
16-bit Reload Register 0 Upper
W
XXXXXXXXB
XXXXXXXXB
(Continued)
24
DS07-13734-7E
MB90330A Series
Address
000066H
000067H
000068H
000069H
00006AH
00006BH
00006CH
00006DH
Register
abbreviation
TMCSR1
TMR1
Read/
Write
Register
Timer Control Status Register 1
Initial Value
0 0 0 0 0 0 0 0B
R/W
XXXX 0 0 0 0B
16-bit Timer Register 1 Lower
R
16-bit Reload Register 1 Lower
W
16-bit Timer Register 1 Upper
R
XXXXXXXXB
TMRLR1
16-bit Reload Register 1 Upper
W
XXXXXXXXB
TMCSR2
Timer Control Status Register 2
R/W
TMRLR1
TMR1
TMR2
TMRLR2
TMR2
TMRLR2
16-bit Reload
Timer ch.1
XXXXXXXXB
XXXXXXXXB
0 0 0 0 0 0 0 0B
XXXX 0 0 0 0B
16-bit Timer Register 2 Lower
R
16-bit Reload Register 2 Lower
W
16-bit Timer Register 2 Upper
R
XXXXXXXXB
16-bit Reload Register 2 Upper
W
XXXXXXXXB
00006EH
16-bit Reload
Timer ch.2
XXXXXXXXB
XXXXXXXXB
Prohibited
00006FH
ROMM
ROM Mirror Function Selection
Register
W
000070H
IBSR0
I2C Bus Status Register 0
R
000071H
Resource name
IBCR0
2
I C Bus Control Register 0
ROM Mirror
Function
Selection Module
0 0 0 0 0 0 0 0B
R/W
2
- - - - - - 1 1B
0 0 0 0 0 0 0 0B
I2C Bus Interface
ch.0
000072H
ICCR0
I C Bus Clock Control Register 0
R/W
000073H
IADR0
I2C Bus Address Register 0
R/W
XXXXXXXXB
000074H
IDAR0
I2C Bus Data Register 0
R/W
XXXXXXXXB
2
R
0 0 0 0 0 0 0 0B
2
R/W
000075H
000076H
000077H
000078H
000079H
00007AH
Prohibited
IBSR1
IBCR1
ICCR1
IADR1
IDAR1
I C Bus Status Register 1
I C Bus Control Register 1
00007DH
00007EH
00007FH
000080H
0 0 0 0 0 0 0 0B
I2C Bus Interface
ch.1
2
R/W
2
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R
0 0 0 0 0 0 0 0B
I C Bus Clock Control Register 1
I C Bus Address Register 1
2
I C Bus Data Register 1
00007BH
00007CH
XX 0 XXXXXB
XX 0 XXXXXB
Prohibited
IBSR2
IBCR2
ICCR2
IADR2
IDAR2
000081H
to
000085H
I2C Bus Status Register 2
2
I C Bus Control Register 2
R/W
0 0 0 0 0 0 0 0B
I2C Bus Interface
ch.2
2
R/W
2
R/W
XXXXXXXXB
2
R/W
XXXXXXXXB
I C Bus Clock Control Register 2
I C Bus Address Register 2
I C Bus Data Register 2
XX 0 XXXXXB
Prohibited
(Continued)
DS07-13734-7E
25
MB90330A Series
Address
000086H
000087H
000088H
000089H
00008AH
00008BH
Register
abbreviation
TCDT
TCCS
CPCLR
Read/
Write
Register
Resource name
Initial Value
Timer Data Register Lower
R/W
0 0 0 0 0 0 0 0B
Timer Data Register Upper
R/W
0 0 0 0 0 0 0 0B
Timer Control Status Register Lower
R/W
Timer Control Status Register Upper
R/W
Compare Clear Register Lower
R/W
XXXXXXXXB
Compare Clear Register Upper
R/W
XXXXXXXXB
0 0 0 0 0 0 0 0B
00008CH
to
00009AH
16-bit Free-Run
Timer
0 0 0 0 0 0 0 0B
0 - - 0 0 0 0 0B
Prohibited
00009BH
DCSR
DMA Descriptor Channel
Specification Register
R/W
00009CH
DSRL
DMA Status Register Lower
R/W
00009DH
DSRH
DMA Status Register Upper
R/W
00009EH
PACSR
Program Address Detection Control
Status Register
R/W
Address Match
Detection
0 0 0 0 0 0 0 0B
00009FH
DIRR
Delay Interruption Factor Generation/
Release Register
R/W
Delay Interrupt
- - - - - - - 0B
0000A0H
LPMCR
Low Power Consumption Mode
Control Register
R/W
Low Power
Consumption
Control Circuit
0 0 0 1 1 0 0 0B
0000A1H
CKSCR
Clock Selection Register
R/W
Clock
1 1 1 1 1 1 0 0B
R/W
μDMAC
0 0 0 0 0 0 0 0B
0000A2H
μDMAC
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
Prohibited
0000A3H
0000A4H
DSSR
DMA Stop Status Register
0000A5H
ARSR
Automatic Ready Function Selection
Register
W
0000A6H
HACR
External Address Output Control
Register
W
0000A7H
EPCR
Bus Control Signal Selection Register
W
0000A8H
WDTC
Watchdog Timer Control Register
R/W
Watchdog Timer
X - XXX 1 1 1B
0000A9H
TBTC
Time-base Timer Control Register
R/W
Time-base Timer
1 - - 0 0 1 0 0B
0000AAH
WTC
Watch Timer Control Register
R/W
Watch Timer
1 0 0 0 1 0 0 0B
0000ABH
External Pin
∗∗∗∗∗∗∗∗B
1 0 0 0 ∗ 1 0 -B
Prohibited
0000ACH
DERL
DMA Enable Register Lower
R/W
0000ADH
DERH
DMA Enable Register Upper
R/W
0000AEH
FMCS
Flash Memory Control Status
Register
R/W
0000AFH
0 0 1 1- - 0 0B
μDMAC
Flash Memory
I/F
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 X 0 0 0 0B
Prohibited
(Continued)
26
DS07-13734-7E
MB90330A Series
Address
Register
abbreviation
Read/
Write
0000B0H
ICR00
Interrupt Control Register 00
R/W
0 0 0 0 0 1 1 1B
0000B1H
ICR01
Interrupt Control Register 01
R/W
0 0 0 0 0 1 1 1B
0000B2H
ICR02
Interrupt Control Register 02
R/W
0 0 0 0 0 1 1 1B
0000B3H
ICR03
Interrupt Control Register 03
R/W
0 0 0 0 0 1 1 1B
0000B4H
ICR04
Interrupt Control Register 04
R/W
0 0 0 0 0 1 1 1B
0000B5H
ICR05
Interrupt Control Register 05
R/W
0 0 0 0 0 1 1 1B
0000B6H
ICR06
Interrupt Control Register 06
R/W
0 0 0 0 0 1 1 1B
0000B7H
ICR07
Interrupt Control Register 07
R/W
0000B8H
ICR08
Interrupt Control Register 08
R/W
0000B9H
ICR09
Interrupt Control Register 09
R/W
0 0 0 0 0 1 1 1B
0000BAH
ICR10
Interrupt Control Register 10
R/W
0 0 0 0 0 1 1 1B
0000BBH
ICR11
Interrupt Control Register 11
R/W
0 0 0 0 0 1 1 1B
0000BCH
ICR12
Interrupt Control Register 12
R/W
0 0 0 0 0 1 1 1B
0000BDH
ICR13
Interrupt Control Register 13
R/W
0 0 0 0 0 1 1 1B
0000BEH
ICR14
Interrupt Control Register 14
R/W
0 0 0 0 0 1 1 1B
0000BFH
ICR15
Interrupt Control Register 15
R/W
0 0 0 0 0 1 1 1B
0000C0H
HCNT0
Host Control Register 0
R/W
0 0 0 0 0 0 0 0B
0000C1H
HCNT1
Host Control Register 1
R/W
0 0 0 0 0 0 0 1B
0000C2H
HIRQ
Host Interruption Register
R/W
0 0 0 0 0 0 0 0B
0000C3H
HERR
Host Error Status Register
R/W
0 0 0 0 0 0 1 1B
0000C4H
HSTATE
Host State Status Register
R/W
XX 0 1 0 0 1 0B
0000C5H
HFCOMP
SOF Interrupt FRAME Compare Register
R/W
0 0 0 0 0 0 0 0B
HRTIMER
Retry Timer Setting Register
Register
R/W
0000C8H
0000C9H
HADR
Host Address Register
HEOF
EOF Setting Register
0000CAH
0000CBH
0000CCH
0000CDH
0000CEH
HFRAME
FRAME Setting Register
HTOKEN
Host Token End Point Register
0000CFH
0000D0H
0000D1H
Interrupt
Controller
R/W
0000C6H
0000C7H
Resource name
Initial Value
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 0 0 0B
USB HOST
0 0 0 0 0 0 0 0B
R/W
XXXXXX 0 0B
R/W
X 0 0 0 0 0 0 0B
R/W
0 0 0 0 0 0 0 0B
R/W
XX 0 0 0 0 0 0B
R/W
0 0 0 0 0 0 0 0B
R/W
XXXXX 0 0 0B
R/W
0 0 0 0 0 0 0 0B
Prohibited
UDCC
UDC Control Register
R/W
R/W
USB Function
1 0 1 0 0 0 0 0B
0 0 0 0 0 0 0 0B
(Continued)
DS07-13734-7E
27
MB90330A Series
Address
0000D2H
Register
abbreviation
Register
EP0C
EP0 Control Register
EP1C
EP1 Control Register
EP2C
EP2 Control Register
EP3C
EP3 Control Register
EP4C
EP4 Control Register
EP5C
EP5 Control Register
TMSP
Time Stamp Register
0000E0H
UDCS
UDC Status Register
0000E1H
UDCIE
UDC Interrupt Enable Register
EP0IS
EP0I Status Register
EP0OS
EP0O Status Register
0000D3H
0000D4H
0000D5H
0000D6H
0000D7H
0000D8H
0000D9H
0000DAH
0000DBH
0000DCH
0000DDH
0000DEH
0000DFH
0000E2H
0000E3H
0000E4H
0000E5H
0000E6H
0000E7H
0000E8H
0000E9H
0000EAH
0000EBH
0000ECH
0000EDH
0000EEH
0000EFH
0000F0H
0000F1H
0000F2H
0000F3H
0000F4H
0000F5H
0000F6H
0000F7H
EP1S
EP1 Status Register
EP2S
EP2 Status Register
EP3S
EP3 Status Register
EP4S
EP4 Status Register
EP5S
EP5 Status Register
EP0DT
EP0 Data Register
EP1DT
EP1 Data Register
EP2DT
EP2 Data Register
EP3DT
EP3 Data Register
Read/
Write
Resource name
Initial Value
R/W
0 1 0 0 0 0 0 0B
R/W
XXXX 0 0 0 0B
R/W
0 0 0 0 0 0 0 0B
R/W
0 1 1 0 0 0 0 1B
R/W
0 1 0 0 0 0 0 0B
R/W
0 1 1 0 0 0 0 0B
R/W
0 1 0 0 0 0 0 0B
R/W
0 1 1 0 0 0 0 0B
R/W
0 1 0 0 0 0 0 0B
R/W
0 1 1 0 0 0 0 0B
R/W
0 1 0 0 0 0 0 0B
R/W
0 1 1 0 0 0 0 0B
R
0 0 0 0 0 0 0 0B
R
XXXXX0 0 0B
R/W
XX0 0 0 0 0 0B
R/W, R
0 0 0 0 0 0 0 0B
R/W
XXXXXXXXB
R/W
1 0 XXX 1 XXB
R/W, R
R/W
USB Function
0 XXXXXXXB
1 0 0 XX 0 0 0B
R
XXXXXXXXB
R/W, R
1 0 0 0 0 0 0 XB
R
XXXXXXXXB
R/W, R
1 0 0 0 0 0 0 0B
R
XXXXXXXXB
R/W, R
1 0 0 0 0 0 0 0B
R
XXXXXXXXB
R/W, R
1 0 0 0 0 0 0 0B
R
XXXXXXXXB
R/W, R
1 0 0 0 0 0 0 0B
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
(Continued)
28
DS07-13734-7E
MB90330A Series
Address
0000F8H
0000F9H
0000FAH
0000FBH
Register
abbreviation
EP4DT
EP5DT
Read/
Write
Register
Resource name
R/W
EP4 Data Register
R/W
R/W
EP5 Data Register
Initial Value
XXXXXXXXB
USB Function
XXXXXXXXB
XXXXXXXXB
R/W
XXXXXXXXB
Program Address Detection Register
ch.0 Lower
R/W
XXXXXXXXB
Program Address Detection Register
ch.0 Middle
R/W
XXXXXXXXB
001FF2H
Program Address Detection Register
ch.0 Upper
R/W
001FF3H
Program Address Detection Register
ch.1 Lower
R/W
Program Address Detection Register
ch.1 Middle
R/W
XXXXXXXXB
Program Address Detection Register
ch.1 Upper
R/W
XXXXXXXXB
0000FCH
to
0000FFH
Prohibited
000100H
to
#H
RAM Area
001FF0H
001FF1H
001FF4H
PADR0
PADR1
001FF5H
#H
to
0078FFH
Address Match
Detection
XXXXXXXXB
XXXXXXXXB
Unused Area
007900H
PRLL0
PPG Reload Register Lower ch.0
R/W
007901H
PRLH0
PPG Reload Register Upper ch.0
R/W
007902H
PRLL1
PPG Reload Register Lower ch.1
R/W
007903H
PRLH1
PPG Reload Register Upper ch.1
R/W
007904H
PRLL2
PPG Reload Register Lower ch.2
R/W
007905H
PRLH2
PPG Reload Register Upper ch.2
R/W
007906H
PRLL3
PPG Reload Register Lower ch.3
R/W
007907H
PRLH3
PPG Reload Register Upper ch.3
R/W
007908H
PRLL4
PPG Reload Register Lower ch.4
R/W
007909H
PRLH4
PPG Reload Register Upper ch.4
R/W
00790AH
PRLL5
PPG Reload Register Lower ch.5
R/W
00790BH
PRLH5
PPG Reload Register Upper ch.5
R/W
00790CH
to
00790FH
PPG ch.0
PPG ch.1
PPG ch.2
PPG ch.3
PPG ch.4
PPG ch.5
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Prohibited
(Continued)
DS07-13734-7E
29
MB90330A Series
(Continued)
Address
007910H
007911H
007912H
007913H
007914H
007915H
007916H
007917H
007918H
007919H
00791AH
00791BH
00791CH
00791DH
00791EH
00791FH
Register
Read/
Write
Input Capture Data Register Lower ch.0
R
Input Capture Data Register Upper ch.0
R
Input Capture Data Register Lower ch.1
R
Register
abbreviation
IPCP0
IPCP1
IPCP2
IPCP3
OCCP0
OCCP1
OCCP2
OCCP3
Resource name
Initial Value
XXXXXXXXB
Input Capture
ch.0/ch.1
XXXXXXXXB
XXXXXXXXB
Input Capture Data Register Upper ch.1
R
XXXXXXXXB
Input Capture Data Register Lower ch.2
R
XXXXXXXXB
Input Capture Data Register Upper ch.2
R
Input Capture Data Register Lower ch.3
R
Input Capture Data Register Upper ch.3
Input Capture
ch.2/ch.3
XXXXXXXXB
XXXXXXXXB
R
XXXXXXXXB
Output Compare Register Lower ch.0
R/W
XXXXXXXXB
Output Compare Register Upper ch.0
R/W
Output Compare Register Lower ch.1
R/W
Output Compare
ch.0/ch.1
XXXXXXXXB
XXXXXXXXB
Output Compare Register Upper ch.1
R/W
XXXXXXXXB
Output Compare Register Lower ch.2
R/W
XXXXXXXXB
Output Compare Register Upper ch.2
R/W
Output Compare Register Lower ch.3
R/W
Output Compare
ch.2/ch.3
XXXXXXXXB
XXXXXXXXB
Output Compare Register Upper ch.3
R/W
XXXXXXXXB
007920H
DBAPL
DMA Buffer Address Pointer Lower 8-bit
R/W
XXXXXXXXB
007921H
DBAPM
DMA Buffer Address Pointer Middle 8-bit
R/W
XXXXXXXXB
007922H
DBAPH
DMA Buffer Address Pointer Upper 8-bit
R/W
XXXXXXXXB
007923H
DMACS
DMA Control Register
R/W
XXXXXXXXB
R/W
007924H
DIOAL
DMA I/O Register Address Pointer
Lower 8-bit
007925H
DIOAH
DMA I/O Register Address Pointer
Upper 8-bit
R/W
XXXXXXXXB
007926H
DDCTL
DMA Data Counter Lower 8-bit
R/W
XXXXXXXXB
007927H
DDCTH
DMA Data Counter Upper 8-bit
R/W
XXXXXXXXB
007928H
to
007FFFH
μDMAC
XXXXXXXXB
Prohibited
• Explanation on read/write
R/W : Readable / Writable
R
: Read only
W : Write only
• Explanation on initial values
0
: Initial value is “0”.
1
: Initial value is “1”.
X
: Initial value is undefined.
: Initial value is undefined (None) .
∗
: Initial value of this bit is “1” or “0”.
Note : No I/O instruction can be used for registers located between 007900H and 007FFFH.
30
DS07-13734-7E
MB90330A Series
■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
Interrupt source
EI2OS
μDMAC
support
Interrupt control
register
Priority
Address ICR Address
Interrupt vector
Number*1
Reset
×
×
#08
08H FFFFDCH
⎯
⎯
INT 9 instruction
×
×
#09
09H
FFFFD8H
⎯
⎯
Exceptional treatment
×
×
#10
0AH
FFFFD4H
⎯
⎯
USB Function1
×
0, 1
#11
0BH
FFFFD0H
USB Function2
×
#12
0CH FFFFCCH
USB Function3
×
×
#13
0DH FFFFC8H
USB Function4
×
×
#14
0EH
FFFFC4H
USB HOST1
×
×
#15
0FH
FFFFC0H
USB HOST2
×
×
#16
10H
FFFFBCH
I2C ch.0
×
×
#17
11H
FFFFB8H
×
#18
12H
FFFFB4H
×
#19
13H
FFFFB0H
×
#20
14H
FFFFACH
×
#21
15H
FFFFA8H
×
#22
16H
FFFFA4H
14
#23
17H
FFFFA0H
DTP/External interrupt ch.6/ch.7
×
#24
18H
FFFF9CH
Input capture ch.0/ch.1
7
#25
19H
FFFF98H
Reload timer ch.1
×
#26
1AH
FFFF94H
Input capture ch.2/ch.3
8
#27
1BH
FFFF90H
Reload timer ch.2
×
#28
1CH FFFF8CH
Output compare ch.0/ch.1
×
#29
1DH
FFFF88H
×
#30
1EH
FFFF84H
×
#31
1FH
FFFF80H
×
#32
20H
FFFF7CH
11
#33
21H
FFFF78H
×
#34
22H
FFFF74H
UART (Reception completed) ch.2/ch.3
10
#35
23H
FFFF70H
A/D converter/Free-run timer
15
#36
24H
FFFF6CH
UART (Send completed) ch.0/ch.1
13
#37
25H
FFFF68H
9
#38
26H
FFFF64H
12
#39
27H
FFFF60H
DTP/External interrupt ch.0/ch.1
I2C ch.1
×
DTP/External interrupt ch.2/ch.3
I2C ch.2
×
DTP/External interrupt ch.4/ch.5
PWC/Reload timer ch.0
PPG ch.0/ch.1
×
Output compare ch.2/ch.3
PPG ch.2/ch.3
×
UART (Send completed) ch.2/ch.3
PPG ch.4/ch.5
Extended serial I/O
×
×
UART (Reception completed) ch.0/ch.1
2
2 to 6*
Time-base timer/Watch timer
×
×
#40
28H
FFFF5CH
Flash memory status
×
×
#41
29H
FFFF58H
Delay interrupt output module
×
×
#42
2AH
FFFF54H
High
ICR00 0000B0H
ICR01 0000B1H
ICR02 0000B2H
ICR03 0000B3H
ICR04 0000B4H
ICR05 0000B5H
ICR06 0000B6H
ICR07 0000B7H
ICR08 0000B8H
ICR09 0000B9H
ICR10 0000BAH
ICR11 0000BBH
ICR12 0000BCH
ICR13 0000BDH
ICR14 0000BEH
ICR15 0000BFH
Low
(Continued)
DS07-13734-7E
31
MB90330A Series
(Continued)
: Available, EI2OS stop function provided (The interrupt request flag is cleared by the interrupt clear signal.
With a stop request).
: Available (The interrupt request flag is cleared by the interrupt clear signal.)
: Available when any interrupt source sharing ICR is not used.
× : Unavailable
*1 : If the same level interrupt is output simultaneously, the lower interrupt factor of interrupt vector number has priority.
*2 : ch.2 and 3 can also be used during USB HOST operation.
Notes : • If the same interrupt control register (ICR) has two interrupt factors and the use of the EI2OS is permitted,
the EI2OS is activated when either of the factors is detected. As any interrupt other than the activation
factor is masked while the EI2OS is running, it is recommended that you should mask either of the interrupt
requests when using the EI2OS.
• The interrupt flag is cleared by the EI2OS interrupt clear signal for the resource that has two interrupt
factors in the same interrupt control register (ICR).
• If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are
cleared by the μDMAC interrupt clear signal. Therefore, when you use either of two interrupt factors for the
DMAC function, another interrupt function is disabled. Set the interrupt request permission bit to “0” in the
appropriate resource, and take measures by software polling.
• Content of USB interruption factor
USB interrupt factor
Details
USB function 1
End Point0-IN End Point0-OUT
USB function 2
End Point1-5 *
USB function 3
SUSP SOF BRST WKUP CONF
USB function 4
SPK
USB HOST1
DIRQ CNNIRQ URIRQ RWKIRQ
USB HOST2
SOFIRQ CMPIRQ
* : Endpoints 1 and 2 can also be used during USB HOST operation.
32
DS07-13734-7E
MB90330A Series
■ USB
1. USB Function
The USB function is an interface supporting the USB (Universal Serial Bus) communications protocol.
• Feature of USB function
• Correspond to USB Full Speed
• Full speed (12 Mbps) is supported.
• The device status is auto-answer.
• Bit stripping, bit stuffing, and automatic generation and check of CRC5 and CRC16
• Toggle check by data synchronization bit
• Automatic response to all standard commands except Get/SetDescriptor and SynchFrame commands (these
3 commands can be processed the same way as the class vendor commands).
• The class vendor commands can be received as data and responded via firmware.
• Supports up to 6 EndPoints (EndPoint0 is fixed to control transfer)
• 2 transfer data buffers integrated for each end point (one IN buffer and one OUT buffer for EndPoint 0)
• Supports automatic transfer mode for transfer data via DMA (except buffers for EndPoint 0)
DS07-13734-7E
33
MB90330A Series
2. USB HOST
USB HOST provides the minimal host operations required and is a function that enables data to be transferred
to and from a device without PC intervention.
• Feature of USB HOST
• Automatic detection of Low Speed/Full Speed transfer
• Low Speed/Full Speed transfer support
• Automatic detection of connection and cutting device
• Reset sending function support to USB-bus
• Support of IN/OUT/SETUP/SOF token
• In-token handshake packet automatic transmission (excluding STALL)
• Out-token handshake packet automatic detection
• Supports a maximum packet length of 256 bytes.
• Error (CRC error/toggle error/time-out) various supports
• Wake-Up function support
• Restrictions of USB HOST
USB HOST
HUB support
*
Bulk transfer
Transfer
Control transfer
Interrupt transfer
Isochronous transfer
Transfer speed
×
Low Speed
Full Speed
×
PRE packet support
SOF packet support
CRC error
Error
Toggle error
Time-out
Maximum packet < receive data
Detection of connection and cutting of device
Transfer speed detection
: Supported
× : Not supported
* : It corresponds to Full Speed only, and the HUB supports up to one step.
34
DS07-13734-7E
MB90330A Series
■ SECTOR CONFIGURATION OF FLASH MEMORY
• Sector configuration of 3Mbit flash memory
3 Mbits flash memory is located in F9H to FFH bank on the CPU memory map.
Flash Memory CPU address Writer address *
Prohibited
SA0 (64 Kbytes)
SA1 (64 Kbytes)
SA2 (64 Kbytes)
Prohibited
SA3 (64 Kbytes)
SA4 (64 Kbytes)
SA5 (32 Kbytes)
SA6 (8 Kbytes)
SA7 (8 Kbytes)
SA8 (16 Kbytes)
F80000H
00000H
F8FFFFH
0FFFFH
F90000H
10000H
F9FFFFH
1FFFFH
FA0000H
20000H
FAFFFFH
2FFFFH
FB0000H
30000H
FBFFFFH
3FFFFH
FC0000H
40000H
FCFFFFH
4FFFFH
FD0000H
50000H
FDFFFFH
5FFFFH
FE0000H
60000H
FEFFFFH
6FFFFH
FF0000H
70000H
FF7FFFH
77FFFH
FF8000H
78000H
FF9FFFH
79FFFH
FFA000H
7A000H
FFBFFFH
7BFFFH
FFC000H
7C000H
FFFFFFH
7FFFFH
* : The writer address is relative to the CPU address when data is programmed into flash memory by a
parallel programmer. Programming and erasing by the general-purpose parallel programmer are
executed based on writer addresses.
DS07-13734-7E
35
MB90330A Series
• Sector configuration of 4Mbit flash memory
4 Mbits flash memory is located in F8H to FFH bank on the CPU memory map.
Flash Memory
SA0 (64 Kbytes)
SA1 (64 Kbytes)
SA2 (64 Kbytes)
SA3 (32 Kbytes)
SA4 (8 Kbytes)
CPU address Writer address *
F80000H
00000H
F8FFFFH
F90000H
0FFFFH
10000H
F9FFFFH
FA0000H
1FFFFH
20000H
FAFFFFH
FB0000H
2FFFFH
30000H
FB7FFFH
FB8000H
37FFFH
38000H
FB9FFFH
FBA000H
39FFFH
3A000H
FBBFFFH
FBC000H
3BFFFH
3C000H
FBFFFFH
FC0000
3FFFFH
40000H
FCFFFF
FD0000
4FFFFH
50000H
FDFFFF
FE0000H
5FFFFH
60000H
FEFFFFH
FF0000H
6FFFFH
70000H
FF7FFFH
FF8000H
77FFFH
78000H
FF9FFFH
FFA000H
79FFFH
7A000H
FFBFFFH
FFC000H
7BFFFH
7C000H
FFFFFFH
7FFFFH
SA5 (8 Kbytes)
SA6 (16 Kbytes)
SA7 (64 Kbytes)
SA8 (64 Kbytes)
SA9 (64 Kbytes)
SA10 (32 Kbytes)
SA11 (8 Kbytes)
SA12 (8 Kbytes)
SA13 (16 Kbytes)
* : The writer address is relative to the CPU address when data is programmed into flash memory by a
parallel programmer. Programming and erasing by the general-purpose parallel programmer are
executed based on writer addresses.
36
DS07-13734-7E
MB90330A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.3
VSS + 4.0
V
AVCC
VSS − 0.3
VSS + 4.0
V
VCC ≥ AVCC*2
AVRH
VSS − 0.3
VSS + 4.0
V
AVCC ≥ AVR ≥ 0 V*3
VSS − 0.3
VSS + 4.0
V
*4
VSS − 0.3
VSS + 6.0
V
N-ch open-drain
(Withstand voltage of
5 V I/O)*5
− 0.5
VSS + 4.5
V
USB I/O
VSS − 0.3
VSS + 4.0
V
*4
− 0.5
VSS + 4.5
V
USB I/O
ICLAMP
− 2.0
+2.0
mA
*6
Σ⏐ICLAMP⏐
⎯
20
mA
*6
IOL1
⎯
10
mA
Other than USB I/O*7
IOL2
⎯
43
mA
USB I/O*7
IOLAV1
⎯
4
mA
*8
IOLAV2
⎯
15/4.5
mA
USB-IO (Full speed/
Low speed) *8
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
*9
IOH1
⎯
− 10
mA
Other than USB I/O*7
IOH2
⎯
− 43
mA
USB I/O*7
IOHAV1
⎯
−4
mA
*8
IOHAV2
⎯
−15/−4.5
mA
USB-IO (Full speed/
Low speed) *8
ΣIOH
⎯
− 100
mA
ΣIOHAV
⎯
− 50
mA
Power consumption
Pd
⎯
340
mW
Operating temperature
TA
− 40
+ 85
°C
− 55
+ 150
°C
− 55
+ 125
°C
Power supply voltage*
1
Input voltage*1
Output voltage*1
Maximum clamp current
Total maximum clamp current
“L” level maximum output current
“L” level average output current
“L” level maximum total output current
“L” level average total output current
“H” level maximum output current
“H” level average output current
“H” level maximum total output current
“H” level average total output current
Storage temperature
VI
VO
Tstg
*9
USB I/O
*1 : The parameter is based on VSS = AVSS = 0.0 V.
*2 : Be careful not to let AVCC exceed VCC, for example, when the power is turned on.
*3 : Be careful not to let AVRH exceed AVcc.
*4 : VI and VO must not exceed Vcc + 0.3 V. However, if the maximum current to/from an input is limited by some
means with external components, the ICLAMP rating supersedes the VI rating.
*5 : Applicable to pins : P60 to P67, P96, PA0 to PA7, PB0 to PB4, UTEST
(Continued)
DS07-13734-7E
37
MB90330A Series
(Continued)
*6 : • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P77,
P80 to P87, P90 to P95, PB5, PB6
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than P60 to P67, P96, PA0 to PA7, PB0 to PB4, DVP, DVM,
HVP, HVM, UTEST, HCON
• Sample recommended circuits:
• Input/output equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
+B input (0 V to 16 V)
N-ch
R
*7 : A peak value of an applicable one pin is specified as a maximum output current.
*8 : The average output current specifies the mean value of the current flowing in the relevant single pin during a
period of 100 ms.
*9 : The average total output current specifies the mean value of the currents flowing in all of the relevant pins during
a period of 100 ms.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
38
DS07-13734-7E
MB90330A Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V)
Parameter
Symbol
Value
Unit
Remarks
Min
Max
3.0
3.6
V
At normal operation (when using USB)
2.7
3.6
V
At normal operation (when not using USB)
1.8
3.6
V
Hold state of stop operation
VIH
0.7 VCC
VCC + 0.3
V
CMOS input pin
VIHS1
0.8 VCC
VCC + 0.3
V
CMOS hysteresis input pin
VIHS2
0.8 VCC
VSS + 5.3
V
N-ch open-drain
(Withstand voltage of 5 V I/O)*
VIHM
VCC − 0.3
VCC + 0.3
V
MD pin input
VIHUSB
2.0
VCC + 0.3
V
USB pin input
VIL
VSS − 0.3
0.3 VCC
V
CMOS input pin
VILS
VSS − 0.3
0.2 VCC
V
CMOS hysteresis input pin
VILM
VSS − 0.3
VSS + 0.3
V
MD pin input
VILUSB
VSS
0.8
V
USB pin input
Differential input
sensitivity
VDI
0.2
⎯
V
USB pin input
Differential common
mode input voltage
range
VCM
0.8
2.5
V
USB pin input
Operating
temperature
TA
− 40
+ 85
°C
When not using USB
0
+ 70
°C
When using USB
Power supply voltage
Input “H” voltage
Input “L” voltage
VCC
* : Applicable to pins : P60 to P67, P96, PA0 to PA7, PB0 to PB4, UTEST
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS07-13734-7E
39
MB90330A Series
3. DC Characteristics
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Output “H”
voltage
Output “L”
voltage
Input leak
current
Symbol
VOH
VOL
IIL
Pin name
Output pins other than
P60 to P67, P96,
PA0 to PA7, PB0 to PB4,
HVP, HVM, DVP, DVM
HVP, HVM, DVP, DVM
Output pins other than
HVP, HVM, DVP, DVM
HVP, HVM, DVP, DVM
Output pins other than
P60 to P67, P96,
PA0 to PA7,
PB0 to PB4, HVP, HVM,
DVP, DVM
HVP, HVM, DVP, DVM
Conditions
Value
Unit
Min Typ Max
Remarks
VCC
− 0.5
⎯
Vcc
V
RL = 15 kΩ ± 5%
2.8
⎯
V
IOL = 4.0 mA
Vss
⎯
V
0
⎯
3.6
Vss
+ 0.4
0.3
VCC = 3.3 V,
Vss < VI < VCC
− 10
⎯
+ 10
μA
⎯
−5
⎯
+5
μA
25
50
100
kΩ
⎯
0.1
10
μA
⎯
75
85
mA
⎯
65
75
mA MB90333A
⎯
70
80
mA
⎯
60
70
mA MB90333A
⎯
27
40
mA
⎯
3.5
10
mA
⎯
1
2
mA
⎯
25
150
μA
IOH = − 4.0 mA
RL = 1.5 kΩ ± 5%
VCC = 3.3 V,
Pull-up
RPULL P00 to P07, P10 to P17
resistance
TA = + 25 °C
Open drain
P60 to P67, P96,
output
ILIOD
⎯
PA0 to PA7, PB0 to PB4
current
VCC = 3.3 V,
Internal frequency 24 MHz,
At normal operating
At USB operating
(USTP = 0)
ICC
VCC = 3.3 V,
Internal frequency 24 MHz,
At normal operating
At non-operating USB
(USTP = 1)
VCC = 3.3 V,
Power
ICCS
Internal frequency 24 MHz,
supply
VCC
At sleep mode
current
VCC = 3.3 V,
Internal frequency 24 MHz,
At timer mode
ICTS
VCC = 3.3 V,
Internal frequency 3 MHz,
At timer mode
VCC = 3.3 V,
Internal frequency 8 kHz,
ICCL
At sub clock operation,
(TA = +25 °C)
V
MB90F334A
MB90F335A
MB90F334A
MB90F335A
(Continued)
40
DS07-13734-7E
MB90330A Series
(Continued)
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Value
Unit
Min
Typ
Max
VCC = 3.3 V,
Internal frequency 8 kHz,
At sub clock,
At sleep operating,
(TA = + 25 °C)
⎯
10
50
μA
ICCT
VCC = 3.3 V,
Internal frequency 8 kHz,
Watch mode,
(TA = + 25 °C)
⎯
1.5
40
μA
ICCH
TA = + 25 °C,
At stop
⎯
1
40
μA
ICCLS
Power
supply
current
Conditions
VCC
Input
capacitance
CIN
Other than AVcc,
AVss, Vcc, Vss
⎯
⎯
5
15
pF
Pull-up
resistor
Rup
RST
⎯
25
50
100
kΩ
USB I/O
output
impedance
ZUSB
DVP, DVM
HVP, HVM
⎯
3
⎯
14
Ω
Remarks
Note : P60 to P67, P96, PA0 to PA7, and PB0 to PB4 are N-ch open-drain pins usually used as CMOS.
DS07-13734-7E
41
MB90330A Series
4. AC Characteristics
(1)Clock input timing
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
SymPin name
bol
Parameter
Value
Min
Typ
Max
Unit
Remarks
⎯
6
⎯
MHz When oscillator is used
6
⎯
24
MHz External clock input
⎯
32.768
⎯
kHz
⎯
166.7
⎯
ns
When oscillator is used
166.7
⎯
41.7
ns
External clock input
⎯
30.5
⎯
s
X0
10
⎯
⎯
ns
PWHL
PWLL
X0A
⎯
15.2
⎯
s
Input clock rise time and fall
time
tcr
tcf
X0
⎯
⎯
5
ns
Internal operating clock
frequency
fCP
⎯
3
⎯
24
MHz When main clock is used
fCPL
⎯
⎯
8.192
⎯
kHz When sub clock is used
tCP
⎯
42
⎯
333
ns
When main clock is used
tCPL
⎯
⎯
122.1
⎯
s
When sub clock is used
fCH
X0, X1
fCL
X0A, X1A
tHCYL
X0, X1
tLCYL
X0A, X1A
PWH
PWL
Clock frequency
Clock cycle time
Input clock pulse width
Internal operating clock
cycle time
A reference duty ratio is
30% to 70%.
At external clock
• Clock Timing
tHCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tcr
tcf
tLCYL
0.8 VCC
X0A
0.2 VCC
PWHL
PWLL
tcf
42
tcr
DS07-13734-7E
MB90330A Series
• PLL operation guarantee range
Relation between power supply voltage and internal operation clock frequency
PLL operation guarantee range
Power voltage VCC (V)
3.6
3.0
2.7
Normal Operation
Assurance Range
3
6
12
24
Internal clock FCP (MHz)
Note : When the USB is used, operation is guaranteed at voltages between 3.0 V and 3.6 V.
Relation between internal operation clock frequency and external clock frequency
Multiplied by 4
Internal clock FCP (MHz)
24
Multiplied by 2
12
External clock
6
Multiplied by 1
3
6
24
External clock Fc (MHz)
DS07-13734-7E
43
MB90330A Series
The AC standards assume the following measurement reference voltages.
• Input signal waveform
• Output signal waveform
Hysteresis input pin
Output pin
0.8 VCC
2.4 V
0.2 VCC
0.8 V
Hysteresis input/other than MD input pin
0.7 VCC
0.3 VCC
44
DS07-13734-7E
MB90330A Series
(2)Clock output timing
Parameter
Cycle time
CLK↑→CLK↓
Symbol Pin name
tCYC
tCHCL
Conditions
⎯
CLK
CLK
VCC = 3.0 V to 3.6 V
(VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Unit
Remarks
Min
Max
tCP
⎯
ns
tCP/2 − 15
tCP/2 + 15
ns
At fcp = 24 MHz
tCP/2 − 20
tCP/2 + 20
ns
At fcp = 12 MHz
tCP/2 − 64
tCP/2 + 64
ns
At fcp = 6 MHz
Note : tCP : Refer to “ (1) Clock input timing”.
tCYC
tCHCL
2.4 V
CLK
DS07-13734-7E
2.4 V
0.8 V
45
MB90330A Series
(3) Reset
Parameter
Symbol
Pin
name
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Conditions
Unit
Remarks
Min
Max
⎯
500
Reset input time
tRSTL
RST
ns
At normal operating,
At time base timer mode,
At main sleep mode,
At PLL sleep mode
μs
At stop mode,
At sub clock mode,
At sub sleep mode,
At watch mode
⎯
Oscillation time
of oscillator* +
500 ns
⎯
* : Oscillation time of oscillator is the time that the amplitude reaches 90%. It takes several milliseconds to several
dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a
ceramic oscillator, and 0 milliseconds on an external clock.
• During normal operation, time-base timer mode, main sleep mode and PLL sleep mode
tRSTL
RST
0.2 Vcc
0.2 Vcc
• During stop mode, sub clock mode, sub-sleep mode and watch mode
tRSTL
RST
0.2 Vcc
X0
Internal
operation
clock
0.2 Vcc
90% of
amplitude
Oscillation time
of oscillator
500 ns
Oscillation stabilization wait time
Execute
instruction
Internal reset
46
DS07-13734-7E
MB90330A Series
(4) Power-on reset
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to +85 °C)
Parameter
Power supply rising
time
Power supply shutdown
time
Symbol Pin name Conditions
tR
VCC
tOFF
VCC
Value
Unit
Min
Max
0.05
30
ms
1
⎯
ms
⎯
Remarks
Waiting time until
power-on
tR
VCC
2.7 V
0.2 V
0.2 V
0.2 V
tOFF
Notes : • VCC must be lower than 0.2 V before the power supply is turned on.
• The above standard is a value for performing a power-on reset.
• In the device, there are internal registers which is initialized only by a power-on reset.
When the initialization of these items is expected, turn on the power supply according to the standards.
• Sudden change of power supply voltage may activate the power-on reset function.
When changing the power supply voltage during operation as illustrated below, voltage fluctuation should
be minimized so that the voltage rises as smoothly as possible. When raising the power, do not use PLL
clock. However, if voltage drop is 1 V/s or less, use of PLL clock is allowed during operation.
VCC
The rising edge should be 50 mV/ms
or less.
3.0 V
RAM data hold
VSS
DS07-13734-7E
47
MB90330A Series
(5) UART0, UART1, UART2, UART3 I/O extended serial timing
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCKx
SCK↓→SOT delay time
tSLOV
SCKx,
SOTx
Valid SIN→SCK↑
tIVSH
SCKx,
SINx
SCK↑→valid SIN hold time
tSHIX
Serial clock H pulse width
Conditions
Value
Unit
Min
Max
8 tCP
⎯
ns
− 80
+ 80
ns
100
⎯
ns
SCKx,
SINx
60
⎯
ns
tSHSL
SCKx, SINx
4 tCP
⎯
ns
Serial clock L pulse width
tSLSH
SCKx, SINx
4 tCP
⎯
ns
SCK↓→SOT delay time
tSLOV
SCKx,
SOTx
⎯
150
ns
Valid SIN→SCK↑
tIVSH
SCKx,
SINx
60
⎯
ns
SCK↑→valid SIN hold time
tSHIX
SCKx,
SINx
60
⎯
ns
Internal shift clock
mode output pin is :
CL = 80 pF + 1TTL
External shift clock
mode output pin is :
CL = 80 pF + 1TTL
Notes : • Above rating is the case of CLK synchronous mode.
• CL is a load capacitance value on pins for testing.
• tCP : Refer to “ (1) Clock input timing”.
48
DS07-13734-7E
MB90330A Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
SOT
0.8 V
tIVSH
SIN
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
• External shift clock mode
tSLSH
SCK
0.2 VCC
tSHSL
0.8 VCC
0.8 VCC
0.2 VCC
tSLOV
2.4 V
SOT
0.8 V
tIVSH
SIN
DS07-13734-7E
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
49
MB90330A Series
(6) I2C timing
Parameter
SCL clock frequency
(Repeat) [start] condition hold
time
SDA ↓ → SCL ↓
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Symbol
Conditions
Unit
Min
Max
tHDSTA
SCL clock “L” width
tLOW
SCL clock “H” width
tHIGH
Repeat [start] condition setup time
SCL ↑ → SDA ↓
tSUSTA
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
Data setup time
SDA ↓ ↑ → SCL ↑
[Stop] condition setup time
SCL ↑ → SDA ↑
Bus free time between [stop]
condition and [start] condition
0
100
kHz
4.0
⎯
μs
4.7
⎯
μs
4.0
⎯
μs
4.7
⎯
μs
0
3.45*3
μs
Power-supply voltage of external pull-up
resistor at 5.0 V.
fCP*1 ≤ 20 MHz, R = 1.2 kΩ, C = 50 pF*2
Power-supply voltage of external pull-up
resistor at 3.6 V.
fCP*1 ≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*2
250*4
⎯
Power-supply voltage of external pull-up
resistor at 5.0 V.
fCP*1 > 20 MHz, R = 1.2 kΩ, C = 50 pF*2
Power-supply voltage of external pull-up
resistor at 3.6 V.
fCP*1 > 20 MHz, R = 1.0 kΩ, C = 50 pF*2
200*4
⎯
4.0
⎯
μs
4.7
⎯
μs
fSCL
tSUDAT
tSUSTO
tBUS
Power-supply voltage of external pull-up
resistor at 5.0 V.
R = 1.2 kΩ, C = 50 pF*2
Power-supply voltage of external pull-up
resistor at 3.6 V.
R = 1.0 kΩ, C = 50 pF*2
Power-supply voltage of external pull-up
resistor at 5.0 V.
R = 1.2 kΩ, C = 50 pF*2
Power-supply voltage of external pull-up
resistor at 3.6 V.
R = 1.0 kΩ, C = 50 pF*2
ns
*1 : fCP is internal operating clock frequency. Refer to “ (1) Clock input timing”.
*2 : R and C are pull-up resistance of SCL and SDA lines and load capacitance.
*3 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*4 : Refer to “• Note of SDA, SCL set-up time”.
50
DS07-13734-7E
MB90330A Series
• Note of SDA, SCL set-up time
SDA
Input data set-up time
SCL
6 tcp
Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending
on the load capacitance or pull-up resistor. Be sure to adjust the pull-up resistor of SDA and SCL if the rating
of the input data set-up time cannot be satisfied.
•Timing definition
SDA
tLOW
tBUS
tHDSTA
tSUDAT
SCL
tHDSTA
DS07-13734-7E
tHDDAT
tHIGH
tSUSTA
tSUSTO
51
MB90330A Series
(7) Timer input timing
Parameter
Symbol
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Pin name
Conditions
Unit
Min
Max
FRCK,
INx, TINx,
PWC
tTIWH
tTIWL
Input pulse width
⎯
⎯
4 tCP
ns
Note : tCP : Refer to “ (1) Clock input timing”.
0.8 VCC
0.8 VCC
PWC
TINx
INx
FRCK
0.2 VCC
0.2 VCC
tTIWH
tTIWL
(8) Timer output timing
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Symbol
Pin name
Conditions
Unit
Min
Max
Parameter
CLK↑→TOUT change time
TOTx,
PPG0 to PPG5 change time
tTO
⎯
PPGx,
OUT0 to OUT3 change time
⎯
30
ns
OUTx
2.4 V
CLK
tTO
PPGx
OUTx
2.4 V
0.8 V
(9) Trigger input timing
Parameter
Input pulse width
Symbol
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Pin name Conditions
Unit
Remarks
Min
Max
tTRGH
tTRGL
INTx,
ADTG
⎯
5 tCP
⎯
ns
At normal operating
1
⎯
μs
In Stop mode
Note : tCP : Refer to “ (1) Clock input timing”.
0.8 VCC
0.8 VCC
0.2 VCC
INTx
ADTG
tTRGH
52
0.2 VCC
tTRGL
DS07-13734-7E
MB90330A Series
(10) Bus read timing
Parameter
ALE pulse width
Symbol
tLHLL
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Pin name Conditions
Unit
Remarks
Min
Max
ALE
⎯
tCP/2 − 15
⎯
ns
At fcp = 24 MHz
tCP/2 − 20
⎯
ns
At fcp = 12 MHz
tCP/2 − 35
⎯
ns
At fcp = 6 MHz
tCP/2 − 17
⎯
ns
tCP/2 − 40
⎯
ns
Valid address→ALE↓time
tAVLL
Address,
ALE
⎯
ALE↓→Address valid time
tLLAX
ALE,
Address
⎯
tCP/2 − 15
⎯
ns
Valid address→RD↓time
tAVRL
RD,
Address
⎯
tCP − 25
⎯
ns
Valid address→valid data
input
tAVDV
Address/
data
⎯
⎯
5 tCP/2 − 55
ns
⎯
5 tCP/2 − 80
ns
At fcp = 6 MHz
RD pulse width
tRLRH
RD
⎯
3 tCP/2 − 25
⎯
ns
At fcp = 24 MHz
3 tCP/2 − 20
⎯
ns
At fcp = 12 MHz
RD↓→valid data input
tRLDV
RD,
Data
⎯
⎯
3 tCP/2 − 55
ns
⎯
3 tCP/2 − 80
ns
RD↓→data hold time
tRHDX
RD,
Data
⎯
0
⎯
ns
RD↑→ALE↑time
tRHLH
RD, ALE
⎯
tCP/2 − 15
⎯
ns
RD↑→address valid time
tRHAX
Address,
RD
⎯
tCP/2 − 10
⎯
ns
Valid address→CLK↑time
tAVCH
Address,
CLK
⎯
tCP/2 − 17
⎯
ns
RD↓→CLK↑time
tRLCH
RD, CLK
⎯
tCP/2 − 17
⎯
ns
ALE↓→RD↓time
tLLRL
RD, ALE
⎯
tCP/2 − 15
⎯
ns
At fcp = 6 MHz
At fcp = 6 MHz
Note : tCP : Refer to “ (1) Clock input timing”.
DS07-13734-7E
53
MB90330A Series
tAVCH
tRLCH
2.4 V
2.4 V
CLK
tRHLH
ALE
2.4 V
2.4 V
tLHLL
2.4 V
0.8 V
tRLRH
2.4 V
RD
tAVLL
tLLAX
0.8 V
tLLRL
In multiplex mode
tAVRL
A23 to A16
tRLDV
2.4 V
2.4 V
0.8 V
0.8 V
tAVDV
AD15 to AD00
2.4 V
2.4 V
tRHDX
0.7 VCC
0.7 VCC
Read data
Address
0.8 V
0.8 V
0.3 VCC
0.3 VCC
tRHAX
In non-multiplex mode
A23 to A00
tRHAX
2.4 V
2.4 V
0.8 V
0.8 V
tRLDV
tRHDX
tAVDV
D15 to D00
0.7 VCC
0.3 VCC
54
0.7 VCC
Read data
0.3 VCC
DS07-13734-7E
MB90330A Series
(11) Bus write timing
Parameter
Symbol
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Pin name Conditions
Unit
Remarks
Min
Max
Valid address→WR↓
time
tAVWL
Address,
WR
WR pulse width
tWLWH
WRL, WRH
Valid data output→WR↑
time
tDVWH
Data, WR
tWHDX
WR,
Data
WR↑→data hold time
⎯
tCP − 15
⎯
ns
⎯
3 tCP/2 − 25
⎯
ns
At fcp = 24 MHz
⎯
3 tCP/2 − 20
⎯
ns
At fcp = 12 MHz
⎯
3 tCP/2 − 15
⎯
ns
⎯
10
⎯
ns
At fcp = 24 MHz
⎯
20
⎯
ns
At fcp = 12 MHz
⎯
30
⎯
ns
At fcp = 6 MHz
WR↑→address valid time
tWHAX
WR,
Address
⎯
tCP/2 − 10
⎯
ns
WR↑→ALE↑time
tWHLH
WR, ALE
⎯
tCP/2 − 15
⎯
ns
WR↓→CLK↑time
tWLCH
WR, CLK
⎯
tCP/2 − 17
⎯
ns
Note : tCP : Refer to “ (1) Clock input timing”.
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tWLWH
2.4 V
WR
(WRL, WRH)
0.8 V
In multiplex mode
tAVWL
A23 to A16
tWHAX
2.4 V
2.4 V
0.8 V
0.8 V
tDVWH
AD15 to AD00
2.4 V
Address
0.8 V
2.4 V
0.8 V
0.8 V
tWHAX
2.4 V
2.4 V
0.8 V
0.8 V
tDVWH
D15 to D00
2.4 V
0.8 V
DS07-13734-7E
2.4 V
Write data
In non-multiplex mode
A23 to A00
tWHDX
Write data
tWHDX
2.4 V
0.8 V
55
MB90330A Series
(12) Ready input timing
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C)
Parameter
Symbol
RDY set-up time
tRYHS
RDY hold time
tRYHH
Pin name
RDY
Conditions
Value
Unit
Min
Max
⎯
35
⎯
ns
⎯
70
⎯
ns
⎯
0
⎯
ns
2.4 V
Remarks
fcp = 6 MHz
2.4 V
CLK
ALE
RD/WR
tRYHS
tRYHH
RDY
wait not
applied
RDY
wait applies
(1cycle)
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tRYHS
56
DS07-13734-7E
MB90330A Series
(13) Hold timing
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C)
Parameter
Symbol
Pin name
Pin floating → HAK ↓ time
tXHAL
HAK
HAK ↓ → pin valid time
tHAHV
HAK
Conditions
⎯
Value
Unit
Min
Max
30
tCP
ns
tCP
2 tCP
ns
Notes : • It takes one cycle or more for HAK to change after the HRQ pin is captured.
• tCP : Refer to “ (1) Clock input timing”.
HAK
2.4 V
0.8 V
tXHAL
2.4 V
Each pin
DS07-13734-7E
0.8 V
tHAHV
High-Z
2.4 V
0.8 V
57
MB90330A Series
5. Electrical Characteristics for the A/D Converter
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Symbol
Pin name
Resolution
⎯
Total error
Parameter
Value
Unit
Min
Typ
Max
⎯
⎯
⎯
10
bit
⎯
⎯
⎯
⎯
± 3.0
LSB
Nonlinear error
⎯
⎯
⎯
⎯
± 2.5
LSB
Differential linear
error
⎯
⎯
⎯
⎯
± 1.9
LSB
Zero transition
voltage
VOT
AN0 to AN15
AVSS −
1.5 LSB
AVSS +
0.5 LSB
AVSS +
2.5 LSB
V
VFST
AN0 to AN15
AVRH −
3.5 LSB
AVRH −
1.5 LSB
AVRH +
0.5 LSB
V
Conversion time
⎯
⎯
⎯
176 tCP*1
⎯
ns
Sampling time
⎯
⎯
⎯
64 tCP*1
⎯
ns
Analog port input
current
IAIN
AN0 to AN15
⎯
⎯
10
μA
Analog input
voltage
VAIN
AN0 to AN15
0
⎯
AVRH
V
Reference
voltage
⎯
AVRH
2.7
⎯
AVCC
V
Power supply
current
IA
AVCC
⎯
1.4
3.5
mA
IAH
AVCC
⎯
⎯
5
μA
Full-scale transition
voltage
Reference voltage
supplying current
IR
AVRH
⎯
95
170
μA
IRH
AVRH
⎯
⎯
5
μA
Interchannel
disparity
⎯
AN0 to AN15
⎯
⎯
4
LSB
Remarks
1 LSB = (AVRH −
AVSS)/1024
*2
*2
*1 : tCP : Refer to “ 4. AC Characteristics (1) Clock input timing”.
*2 : The current when the CPU is in stop mode and the A/D converter is not operating (For VCC = AVCC = AVRH = 3.3 V).
58
DS07-13734-7E
MB90330A Series
Notes :
• About the external impedance of the analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision.
• Analog input circuit model
R
Comparator
Analog input
C
During sampling : ON
R
1.9 kΩ (Max)
1.9 kΩ (Max)
1.9 kΩ (Max)
1.9 kΩ (Max)
MB90333A
MB90F334A
MB90F335A
MB90V330A
Note : The values are reference values.
C
32.3 pF (Max)
25.0 pF (Max)
25.0 pF (Max)
32.3 pF (Max)
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the resistor value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.
• The relationship between the external impedance and minimum sampling time
(External impedance = 0 kΩ to 20 kΩ)
MB90333A/
MB90V330A
MB90333A/
MB90V330A
100
90
80
70
60
50
40
30
20
10
0
External impedance [kΩ]
External impedance [kΩ]
(External impedance = 0 kΩ to 100 kΩ)
MB90F334A
MB90F335A
0
5
10
15
20
25
30
35
Minimum sampling time [μs]
20
18
16
14
12
10
8
6
4
2
0
MB90F334A
MB90F335A
0
1
2
3
4
5
6
7
8
Minimum sampling time [μs]
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
• About errors
As |AVRH| becomes smaller, values of relative errors grow larger.
DS07-13734-7E
59
MB90330A Series
A/D Converter Glossary
Resolution :
Analog changes that are identifiable with the A/D converter.
Linearity error :
The deviation of the straight line connecting the zero transition point
(“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point
(“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics.
Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value.
Total error :
The total error is defined as a difference between the actual value and the theoretical
value, which includes zero-transition error/full-scale transition error and linearity error.
Total error
3FFH
3FEH
Digital output
3FDH
Actual conversion
value
0.5 LSB
{1 LSB × (N − 1) + 0.5 LSB}
004H
VNT
(Measured value)
003H
Actual conversion
value
002H
Theoretical
characteristics
001H
0.5 LSB
AVSS
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
AVRH − AVss [V]
1024
Total error for digital output N =
1 LSB (Theoretical value) =
[LSB]
VOT (Theoretical value) = AVss + 0.5 LSB [V]
VFST (Theoretical value) = AVRH − 1.5 LSB [V]
VNT : Voltage at a transition of digital output from (N - 1) to N
(Continued)
60
DS07-13734-7E
MB90330A Series
(Continued)
Linearity error
Actual conversion
value
3FEH
{1 LSB × (N − 1)
+ VOT }
Digital output
3FDH
Theoretical
characteristics
N+1
VFST
(Measured
value)
004H
003H
002H
001H
VNT
(Measured value)
Digital output
3FFH
Differential linearity error
Actual conversion
value
Actual conversion
value
N
V (N + 1) T
(Measured
value)
N−1
VNT
(Measured value)
N−2
Actual conversion
value
Theoretical
characteristics
VOT (Measured value)
AVSS
AVRH
AVSS
Analog input
Linearity error of
=
digital output N
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
Differential linearity error
V (N + 1) T − VNT
=
1 LSB
of digital output N
1 LSB =
AVRH
Analog input
VFST − VOT
1022
[LSB]
− 1 [LSB]
[V]
VOT : Voltage at transition of digital output from “000H” to “001H”
VFST : Voltage at transition of digital output from “3FEH” to “3FFH”
DS07-13734-7E
61
MB90330A Series
6. USB characteristics
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Symbol
Min
Max
VIH
2.0
⎯
V
VIL
⎯
0.8
V
VDI
0.2
⎯
V
Differential common mode range
VCM
0.8
2.5
V
Output High level voltage
VOH
2.8
3.6
V
IOH = − 200 μA
Output Low level voltage
VOL
0.0
0.3
V
IOL = 2 mA
Cross over voltage
VCRS
1.3
2.0
V
tFR
4
20
ns
Full Speed
tLR
75
300
ns
Low Speed
tFF
4
20
ns
Full Speed
tLF
75
300
ns
Low Speed
tRFM
90
111.11
%
(TFR/TFF)
tRLM
80
125
%
(TLR/TLF)
ZDRV
28
44
Ω
Including Rs = 27 Ω
RS
25
30
Ω
Recommended value =
27 Ω at using USB*
Parameter
Input High level voltage
Input Low level voltage
Input
characteristics Differential input sensitivity
Rise time
Output
characteristics
Fall time
Rising/falling time matching
Output impedance
Series resistance
Unit
Remarks
* : Arrange the series resistance RS values in order to set the impedance value within the output impedance ZSRV.
• Data signal timing (Full Speed)
Rise time
DVP/HVP
90%
Vcrs
Fall time
90%
10%
10%
DVM/HVM
tFF
tFR
• Data signal timing (Low Speed)
Rise time
HVP
HVM
90%
Vcrs
90%
10%
10%
tLR
62
Fall time
tLF
DS07-13734-7E
MB90330A Series
• Load condition (Full Speed)
ZUSB
DVP/HVP
RS = 27 Ω
Testing point
CL = 50 pF
ZUSB
DVM/HVM
RS = 27 Ω
Testing point
CL = 50 pF
• Load condition (Low Speed)
ZUSB
HVP
RS = 27 Ω
Testing point
CL = 50 pF to 150 pF
ZUSB
HVM
RS = 27 Ω
Testing point
CL = 50 pF to 150 pF
DS07-13734-7E
63
MB90330A Series
7. Flash memory write/erase characteristics
Parameter
Condition
Sector erase time
Chip erase time
Flash memory data
retaining period
Min
Typ
Max
⎯
1
15
⎯
9
⎯
TA = + 25 °C
VCC = 3.0 V
Unit
Remarks
s
Excludes 00H programming
prior to erasure.
s
⎯
14
⎯
⎯
16
3600
μs
⎯
10000
⎯
⎯
cycle
Average
TA = + 85 °C
20
⎯
⎯
year
Word (16-bit width)
programming time
Programming/erase cycle
Value
*:MB90F334A (384 Kbytes)
Excludes 00H programming
prior to erasure.
*:MB90F335A (512 Kbytes)
Excludes 00H programming
prior to erasure.
Except for over head time of
system level
*
* : This value comes from the technology qualification. (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C)
64
DS07-13734-7E
MB90330A Series
■ ORDERING INFORMATION
Part number
Package
MB90F334APMC1
MB90F335APMC1
MB90333APMC1
120-pin plastic LQFP
(FPT-120P-M24)
MB90F334APMC
MB90F335APMC
MB90333APMC
120-pin plastic LQFP
(FPT-120P-M21)
MB90V330ACR
299-pin ceramic PGA
(PGA-299C-A01)
DS07-13734-7E
Remarks
For evaluation
65
MB90330A Series
■ PACKAGE DIMENSIONS
120-pin plastic LQFP
Lead pitch
0.40 mm
Package width ×
package length
14.0 mm × 14.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LFQFP120-14×14-0.40
(FPT-120P-M24)
120-pin plastic LQFP
(FPT-120P-M24)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
90
61
91
60
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
120
31
"A"
0~8˚
LEAD No.
1
0.40(.016)
30
0.16±0.05
(.006±.002)
0.07(.003)
M
0.145±0.055
(.006±.002)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
©2006-2008
FUJITSU MICROELECTRONICS LIMITED F120036S-c-1-2
C
2006 FUJITSU LIMITED F120036S-c-1-1
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
66
DS07-13734-7E
MB90330A Series
(Continued)
120-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
16.0 × 16.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.88 g
Code
(Reference)
P-LFQFP120-16×16-0.50
(FPT-120P-M21)
120-pin plastic LQFP
(FPT-120P-M21)
Note 1) * : These dimensions do not include resin protrusion.
Resin protrusion is +0.25(.010) MAX(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00±0.20(.709±.008)SQ
+0.40
* 16.00 –0.10 .630 +.016
–.004 SQ
90
61
60
91
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
0~8˚
120
LEAD No.
"A"
31
1
30
0.50(.020)
0.22±0.05
(.009±.002)
0.08(.003)
M
©2002-2008
FUJITSU MICROELECTRONICS LIMITED F120033S-c-4-5
C
2002 FUJITSU LIMITED F120033S-c-4-4
0.145
.006
+0.05
–0.03
+.002
–.001
0.60±0.15
(.024±.006)
0.10±0.05
(.004±.002)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-13734-7E
67
MB90330A Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
⎯
⎯
Change Results
Changed the USB.
USB Mini-Host → USB HOST
16
■ HANDLING DEVICES
Added the item of “11. Serial communication”.
⎯
■ PERIPHERAL RESOURCES
Deleted the section.
33
■ USB
Changed the item name from “PERIPHERAL RESOURCES”
to “USB Function”.
2. USB HOST
Changed the title of table:
Differences between the USB HOST and USB Mini-HOST →
Restrictions of USB HOST
Changed “HUB support”.
×→ *
Added the following footnote to table:
“*: It corresponds to Full Speed only, and the HUB supports up
to one step.”
■ SECTOR CONFIGURATION OF
FLASH MEMORY
Changed the item name from “PERIPHERAL RESOURCES”
to “SECTOR CONFIGURATION OF FLASH MEMORY”.
34
35, 36
The vertical lines marked in the left side of the page show the changes.
68
DS07-13734-7E
MB90330A Series
MEMO
DS07-13734-7E
69
MB90330A Series
MEMO
70
DS07-13734-7E
MB90330A Series
MEMO
DS07-13734-7E
71
MB90330A Series
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