FUJITSU MICROELECTRONICS
DATA SHEET
DS07-13731-5E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90895 Series
MB90F897/F897S/F897Y*1/F897YS*1/
MB90V495G
■ DESCRIPTION
MB90895 series devices are 16-bit general-purpose microcontrollers designed for applications which need highspeed real-time processing. The devices of this series are high-performance 16-bit CPU microcontrollers employing of the dual operation flash memory and CAN controller on LQFP-48 small package.
The system, inheriting the architecture of F2MC*2 family, employs additional instruction ready for high-level languages, expanded addressing mode, enhanced multiply-divide instructions, and enriched bit-processing instructions. Furthermore, employment of 32-bit accumulator achieves processing of long-word data (32 bits).
The peripheral resources of MB90895 series include the following:
8/10-bit A/D converter, UART0/UART1 (SCI), 8/16-bit PPG timer, 16-bit input-output timer (16-bit free-run timer,
input capture 0, 1, 2, 3 (ICU)), and CAN controller.
*1 : These devices are under development. This datasheet provides preliminary information for the devices under
development.
*2 : “F2MC” is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• Models that support +125°C (MB90F897/S)
• Models that support +150°C (MB90F897Y/YS)
• Clock
• Built-in PLL clock frequency multiplication circuit
• Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and
multiplication of 1 to 4 times of oscillation clock (for 4-MHz oscillation clock, 4 MHz to 16 MHz).
• Operation by sub-clock (8.192 kHz) is allowed. (MB90F897/Y)
• Minimum execution time of instruction: 62.5 ns (when operating with 4-MHz oscillation clock, and 4-time multiplied PLL clock).
• 16 Mbyte CPU memory space
• 24-bit internal addressing
(Continued)
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2004-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.8
MB90895 Series
(Continued)
• Instruction system best suited to controller
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes (23 types)
• Enhanced multiply-divide instructions and RETI instructions
• Enhanced high-precision computing with 32-bit accumulator
• Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
• Increased processing speed
• 4-byte instruction queue
• Powerful interrupt function with 8 levels and 34 factors
• Automatic data transfer function independent of CPU
• Extended intelligent I/O service function (EI2OS): Maximum of 16 channels
• Low power consumption (standby) mode
• Sleep mode (a mode that halts CPU operating clock)
• Time-base timer mode (a mode that operates oscillation clock, sub clock, time-base timer and watch timer only)
• Watch mode (a mode that operates sub clock and watch timer only)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU intermittent operation mode
• Process
• CMOS technology
• I/O port
• General-purpose input/output port (CMOS output) :
MB90F897/Y
: 34 ports (including 4 high-current output ports)
MB90F897S/YS : 36 ports (including 4 high-current output ports)
• Timer
• Time-base timer, watch timer, watchdog timer: 1 channel
• 8/16-bit PPG timer: 8-bit x 4 channels, or 16-bit x 2 channels
• 16-bit reload timer: 2 channels
• 16-bit input/output timer
- 16-bit free run timer: 1 channel
- 16-bit input capture: (ICU): 4 channels
Interrupt request is issued upon latching a count value of 16-bit free run timer by detection of an edge on pin input.
• CAN controller: 1 channel
• Complied with Ver 2.0A and Ver 2.0B CAN specifications
• 8 built-in message buffers
• Transmission rate of 10 kbps to 1 Mbps (by 16 MHz machine clock)
• CAN wake-up
• UART0 (SCI), UART1(SCI): 2 channels
• Equipped with full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transmission is available.
• DTP/External interrupt: 4 channels, CAN wake-up: 1channel
• Module for activation of extended intelligent I/O service (EI2OS), and generation of external interrupt.
• Delay interrupt generator module
• Generates interrupt request for task switching.
• 8/10-bit A/D converter: 8 channels
• Resolution is selectable between 8-bit and 10-bit.
• Activation by external trigger input is allowed.
• Conversion time: 6.125 μs (at 16-MHz machine clock, including sampling time)
• Program patch function
• Address matching detection for 2 address pointers.
2
DS07-13731-5E
MB90895 Series
■ PRODUCT LINEUP
Part number
MB90F897
MB90F897S
MB90F897Y (Under development)
MB90F897YS (Under development)
MB90V495G
Classification
Flash ROM
Evaluation product
ROM capacity
64 Kbytes
⎯
RAM capacity
2 Kbytes
6 Kbytes
Parameter
Process
CMOS
Package
Operating power supply voltage
Special power supply for emulator*1
LQFP-48 (pin pitch 0.50 mm)
PGA256
3.5 V to 5.5 V
4.5 V to 5.5 V
⎯
None
Number of basic instructions : 351 instructions
Instruction length : 1 byte to 7 bytes
Data bit length : 1 bit, 8 bits, 16 bits
CPU functions
Minimum instruction execution time : 62.5 ns (at 16-MHz machine clock)
Interrupt processing time : 1.5 μs at minimum (at 16-MHz machine clock)
Low power consumption
(standby) mode
Sleep mode/Watch mode/Time-base timer mode/
Stop mode/CPU intermittent
I/O port
General-purpose input/output ports (CMOS output) : 34 ports (36 ports*2)
including 4 high-current output ports (P14 to P17)
Time-base timer
18-bit free-run counter
Interrupt cycle : 1.024 ms, 4.096 ms, 16.834 ms, 131.072 ms
(with oscillation clock frequency at 4 MHz)
Watchdog timer
Reset generation cycle: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(with oscillation clock frequency at 4 MHz)
16-bit input/output
timer
16-bit free-run
timer
Number of channels: 1
Interrupt upon occurrence of overflow
Input capture
Number of channels: 4
Retaining free-run timer value set by pin input (rising edge, falling edge, and
both edges)
16-bit reload timer
Number of channels: 2
16-bit reload timer operation
Count clock cycle: 0.25 μs, 0.5 μs, 2.0 μs (at 16-MHz machine clock frequency)
External event count is allowed.
Watch timer
15-bit free-run counter
Interrupt cycle: 31.25 ms, 62.5 ms, 12 ms, 250 ms, 500 ms, 1.0 s, 2.0 s
(with 8.192 kHz sub clock)
8/16-bit PPG timer
Number of channels: 2 (four 8-bit channels are available also.)
PPG operation is allowed with four 8-bit channels or one 16-bit channel.
Outputting pulse wave of arbitrary cycle or arbitrary duty is allowed.
Count clock: 62.5 ns to 1 μs (with 16 MHz machine clock)
Delay interrupt generator module
Interrupt generator module for task switching. Used for real-time OS.
(Continued)
DS07-13731-5E
3
MB90895 Series
(Continued)
Part number
Parameter
MB90F897
MB90F897S
MB90F897Y (Under development)
MB90F897YS (Under development)
MB90V495G
DTP/External interrupt
Number of inputs: 4
Activated by rising edge, falling edge, “H” level or “L” level input.
External interrupt or extended intelligent I/O service (EI2OS) is available.
8/10-bit A/D converter
Number of channels: 8
Resolution: Selectable 10-bit or 8-bit.
Conversion time: 6.125 μs (at 16-MHz machine clock, including sampling time)
Sequential conversion of two or more successive channels is allowed. (Setting
a maximum of 8 channels is allowed.)
Single conversion mode
: Selected channel is converted only once.
Sequential conversion mode: Selected channel is converted repetitively.
Halt conversion mode
: Conversion of selected channel is stopped and
activated alternately.
UART0 (SCI)
Number of channels: 1
Clock-synchronous transfer: 62.5 kbps to 2 Mbps
Clock-asynchronous transfer: 1,202 bps to 62,500 bps
Communication is allowed by bi-directional serial communication function and
master/slave type connection.
UART1 (SCI)
Number of channels: 1
Clock-synchronous transfer: 62.5 kbps to 2 Mbps
Clock-asynchronous transfer: 9,615 bps to 500 kbps
Communication is allowed by bi-directional serial communication function and
master/slave type connection.
CAN
Complied with Ver 2.0A and Ver 2.0B CAN specifications.
8 built-in message buffers.
Transmission rate of 10 kbps to 1 Mbps (by 16 MHz machine clock)
CAN wake-up
*1 : Settings of DIP switch S2 for using emulation pod MB2145-507. For details, see MB2145-507 Hardware Manual
(2.7 Power Pin solely for Emulator).
*2 : MB90F897S/YS
■ PACKAGES AND PRODUCT MODELS
Package
MB90F897/S/Y/YS
FPT-48P-M26
: Yes, × : No
Note : Refer to “ PACKAGE DIMENSION” for details of the package.
4
DS07-13731-5E
MB90895 Series
■ PRODUCT COMPARISON
Memory space
When testing with test product for evaluation, check the differences between the product and a product to be
used actually. Pay attention to the following points:
• The MB90V495G has no built-in ROM. However, a special-purpose development tool allows the operations
as those of one with built-in ROM. ROM capacity depends on settings on a development tool.
• On MB90V495G, an image from FF4000H to FFFFFFH is viewed on 00 bank and an image of FE0000H to
FF3FFFH is viewed only on FE bank and FF bank. (Modified on settings of a development tool.)
• On MB90F897/S/Y/YS, an image from FF4000H to FFFFFFH is viewed on 00 bank and an image of FF0000H
to FF3FFFH is viewed only on FF bank.
DS07-13731-5E
5
MB90895 Series
■ PIN ASSIGNMENT
48
47
46
45
44
43
42
41
40
39
38
37
AVSS
X1A/P36*
X0A/P35*
P33
P32/SIN0
P31SCK0
P30/SOT0
P44/RX
P43/TX
P42/SOT1
P41/SCK1
P40/SIN1
(TOP VIEW)
LQFP-48
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
P17/PPG3
P16/PPG2
P15/PPG1
P14/PPG0
P13/IN3
P12/IN2
P11/IN1
P10/IN0
X1
X0
C
VSS
P21/TOT0
P22/TIN1
P23/TOT1
P24/INT4
P25/INT5
P26/INT6
P27/INT7
MD2
MD1
MD0
RST
VCC
AVCC
AVR
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
P37/ADTG
P20/TIN0
(FPT-48P-M26)
*: MB90F897/Y
: X1A, X0A
MB90F897S/YS : P36, P35
6
DS07-13731-5E
MB90895 Series
■ PIN DESCRIPTION
Pin No.
Pin name
Circuit
type
1
AVcc
⎯
Vcc power input pin for A/D converter.
2
AVR
⎯
Power (Vref+) input pin for A/D converter. Use as input for Vcc or lower.
P50 to P57
3 to 10
AN0 to AN7
General-purpose input/output ports.
E
P37
11
ADTG
TIN0
TOT0
D
TIN1
16 to 19
TOT1
P24 to P27
INT4 to INT7
Function as an event output pin for reload timer 0. Valid only when output
setting is “enabled.”
General-purpose input/output ports.
D
P23
15
Function as an event input pin for reload timer 0. Use the pin by setting as
input port.
General-purpose input/output ports.
D
P22
14
Function as an external trigger input pin for A/D converter. Use the pin by
setting as input port.
General-purpose input/output ports.
P21
13
Functions as analog input pin for A/D converter. Valid when analog
input setting is “enabled.”
General-purpose input/output ports.
D
P20
12
Function
Function as an event input pin for reload timer 1. Use the pin by setting as
input port.
General-purpose input/output ports.
D
D
Function as an event output pin for reload timer 1. Valid only when output
setting is “enabled.”
General-purpose input/output ports.
Functions as external interrupt input pin. Use the pin by setting as input port.
20
MD2
F
Input pin for specifying operation mode. Connect directly to Vss.
21
MD1
C
Input pin for specifying operation mode. Connect directly to Vcc.
22
MD0
C
Input pin for specifying operation mode. Connect directly to Vcc.
23
RST
B
External reset input pin.
24
Vcc
⎯
Power supply (5 V) input pin.
25
Vss
⎯
Power supply (0 V) input pin.
26
C
⎯
Capacitor pin for stabilizing power supply. Connect a ceramic capacitor of
approximately 0.1 μF.
27
X0
A
Pin for high-rate oscillation.
28
X1
A
Pin for high-rate oscillation.
P10 to P13
29 to 32
IN0 to IN3
General-purpose input/output ports.
D
Functions as trigger input pins of input capture channels 0 to 3. Use the
pins by setting as input ports.
(Continued)
DS07-13731-5E
7
MB90895 Series
(Continued)
Pin No.
Pin name
Circuit
type
P14 to P17
33 to 36
37
PPG0 to PPG3
P40
SIN1
General-purpose input/output ports. High-current output ports.
G
D
P41
38
SCK1
SOT1
D
41
TX
P44
RX
D
SOT0
D
D
44
45
46
47
48
SCK0
P32
SIN0
P33
X0A*
P35*
X1A*
P36*
AVss
Serial clock input/output pin for UART1. Valid only when serial clock input/
output setting on UART1 is “enabled.”
Serial data output pin for UART1. Valid only when serial data output setting
on UART1 is “enabled.”
Transmission output pin for CAN. Valid only when output setting is
“enabled.”
General-purpose input/output port.
Receive input pin for CAN. Use the pin by setting as input port.
General-purpose input/output port.
D
P31
43
Serial data input pin for UART1. Use the pin by setting as input port.
General-purpose input/output port.
P30
42
General-purpose input/output port.
General-purpose input/output port.
P43
40
Functions as output pin of PPG timers 01 and 23. Valid when output
setting is “enabled.”
General-purpose input/output port.
P42
39
Function
Serial data output pin for UART0. Valid only when serial data output setting
on UART0 is “enabled.”
General-purpose input/output port.
D
H
D
A
A
⎯
Serial clock input/output pin for UART0. Valid only when serial clock input/
output setting on UART0 is “enabled.”
General-purpose input/output port.
Serial data input/output pin for UART0. Use the pin by setting as input port.
General-purpose input/output port.
Pin for low-rate oscillation.
General-purpose input/output port.
Pin for low-rate oscillation.
General-purpose input/output port.
Vss power supply input pin for A/D converter.
* : MB90F897/Y
: X1A, X0A
MB90F897S/YS : P36, P35
8
DS07-13731-5E
MB90895 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
X1
Clock input
X1A
X0
X0A
• High-rate oscillation feedback
resistor, approx. 1 MΩ
• Low-rate oscillation feedback
resistor, approx. 10 MΩ
Standby control signal
B
• Hysteresis input with pull-up
resistor.
• Pull-up resistor, approx. 50 kΩ
Vcc
R
R
Hysteresis input
C
Hysteresis input
R
Hysteresis input
D
Vcc
P-ch
R
N-ch
Vss
Digital output
•
•
•
•
CMOS hysteresis input
CMOS level output
Standby control provided
Automotive input
•
•
•
•
•
CMOS hysteresis input
CMOS level output
Shared for analog input pin
Standby control provided
Automotive input
Digital output
Hysteresis input
Standby control
R
Automotive input
E
Vcc
P-ch
R
N-ch
Vss
Digital output
Digital output
Hysteresis input
Standby control
R
Automotive input
Analog input
(Continued)
DS07-13731-5E
9
MB90895 Series
(Continued)
Type
Circuit
Remarks
F
R
Hysteresis input
• Hysteresis input with pull-down
resistor
• Pull-down resistor, approx. 50 kΩ
• FLASH product is not provided with
pull-down resistor.
R
Vss
G
Vcc
P-ch
High-current output
High-current output
R
• CMOS hysteresis input
• CMOS level output (high-current
output)
• Standby control provided
• Automotive input
N-ch
Vss
Hysteresis input
Standby control
R
Automotive input
H
Vcc
P-ch
Digital output
Digital output
R
•
•
•
•
•
CMOS hysteresis input
CMOS level output
Standby control provided
CMOS input
Automotive input
Vss
Hysteresis input
R
Automotive input
R
CMOS input
Standby control
10
DS07-13731-5E
MB90895 Series
■ HANDLING DEVICES
• Do Not Exceed Maximum Rating (preventing “latch up”)
• Latch-up may occur in a CMOS IC if a voltage higher than VCC or less than VSS is applied to an input or output
pin or if a voltage exceeding the rated value is applied between VCC pin and VSS pins.
• Latch-up causes drastic increase of power current, which may lead to destruction of elements by heat. Extreme
caution must be taken not to exceed maximum rating.
• When turning on and off analog power supply, take extra care not to apply an analog power voltages (AVcc
and AVR) and analog input voltage that are higher than digital power voltage (Vcc).
• Handling Unused Pins
• Leaving unused input pins open may cause permanent destruction by malfunction or latch-up. Apply pull-up
or pull-down process to the unused pins using resistors of 2 kΩ or higher. Leave unused I/O pins open under
output status, or process as input pins if they are under input status.
• Using External Clock
• When using an external clock, drive only X0 pin and leave X1 pin open. An example of using an external clock
is shown below.
• Using external clock
X0
Open
X1
MB90895 series
• Notes When Using No Sub Clock on MB90F897/Y
• If an oscillator is not connected to X0A and X1A pins, apply pull-down resistor to the X0A pin and leave the
X1A pin open.
• About Power Supply Pins
• If two or more Vcc and Vss exist, the pins that should be at the same potential are connected to each other
inside the device. For reducing unwanted emissions and preventing malfunction of strobe signals caused by
increase of ground level, however, be sure to connect the Vcc and Vss pins to the power supply and the ground
externally.
• Pay attention to connect a power supply to Vcc and Vss pins of MB90895 series device in a lowest-possible
impedance.
• Near pins of MB90895 series device, connecting a bypass capacitor is recommended at 0.1 μF across Vcc
and Vss pins.
• Crystal Oscillator Circuit
• Noises around X0 and X1 pins cause malfunctions on a MB90895 series device. Design a print circuit so that
X0 and X1 pins, an crystal oscillator (or a ceramic oscillator), and bypass capacitor to the ground become as
close as possible to each other. Furthermore, avoid wires to X0 and X1 pins crossing each other as much as
possible.
• Print circuit designing that surrounds X0 and X1 pins with grounding wires, which ensures stable operation,
is strongly recommended.
DS07-13731-5E
11
MB90895 Series
• Caution on Operations during PLL Clock Mode
• If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
• Sequence of Turning on Power of A/D Converter and Applying Analog Input
• Be sure to turn on digital power (Vcc) before applying signals to the A/D converter and applying analog input
signals (AN0 to AN7 pins).
• Be sure to turn off the power of A/D converter and analog input before turning off the digital power supply.
• Be sure not to apply AVR exceeding AVcc when turning on and off. (No problems occur if analog and digital
power is turned on and off simultaneously.)
• Handling Pins When A/D Converter is Not Used
• If the A/D converter is not used, connect the pins under the following conditions: “AVcc=AVR=Vcc,” and
“AVss=Vss”.
• Note on Turning on Power
• For preventing malfunctions on built-in step-down circuit, maintain a minimum of 50 μs of voltage rising time
(between 0.2 V and 2.7 V) when turning on the power.
• Stabilization of supply voltage
• A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC
supply voltage operating range. Therefore, the VCC supply voltage should be stabilized.
For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values) at
commercial frequencies (50 / 60Hz) fall below 10% of the standard VCC supply voltage and the coefficient of
fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
• Support for +125°C / +150°C
• Users considering application exceeding TA = +105°C are advised to contact their representatives beforehand
for reliability limitations.
12
DS07-13731-5E
MB90895 Series
■ BLOCK DIAGRAM
X0,X1
RST
X0A,X1A
Clock
control circuit
CPU
F2MC-16LX core
Watch timer
Time-base timer
16-bit
free-run timer
RAM
Input
capture
(4ch)
Prescaler
SOT1
SCK1
SIN1
UART1
Prescaler
SOT0
SCK0
SIN0
UART0
Internal data bus
FLASH
16-bit
PPG timer
(2ch)
CAN
DTP/External
interrupt
16-bit
reload timer
(2ch)
IN0 to IN3
PPG0 to PPG3
RX
TX
INT4 to INT7
TIN0,TIN1
TOT0,TOT1
AVcc
AVss
AN0 to AN7
8/10-bit A/D
converter (8ch)
AVR
ADTG
DS07-13731-5E
13
MB90895 Series
■ MEMORY MAP
1. Memory allocation of MB90895
MB90895 series model outputs 24-bit wide internal address bus and up to 24-bit of external address bus.
A maximum of 16 Mbyte memory space of external access memory is accessible.
2. Memory map
(with ROM mirroring
function enabled)
000000H
Peripheral
0000C0H
000100H
RAM area
Register
Address #1
003900H
Extension IO area
004000H
ROM area
(FF bank image)
010000H
FE0000H
ROM area*
FF0000H
FFFFFFH
ROM area
Model
Address #1
MB90V495G
001900H
000900H
MB90F897/S/Y/YS
: Internal access memory
: Access disallowed
* : On MB90F897/S/Y/YS, to read “FE0000H” to “FEFFFFH” is to read out “FF0000H” to “FFFFFFH”.
Note : When internal ROM is operating, F2MC-16LX allows viewing ROM data image on FF bank at upper-level of
00 bank. This function is called “mirroring ROM,” which allows effective use of C compiler small model.
F2MC-16LX assigns the same low order 16-bit address to FF bank and 00 bank, which allows referencing
table in ROM without specifying “far” using pointer.
For example, when accessing to “00C000H”, ROM data at “FFC000H” is accessed actually. However, because
ROM area of FF bank exceeds 48 Kbytes, viewing all areas is not possible on 00 bank image. Because
ROM data of “FF4000H” to “FFFFFFH” is viewed on “004000H” to “00FFFFH” image, store a ROM data table
in area “FF4000H” to “FFFFFFH.”
14
DS07-13731-5E
MB90895 Series
■ I/O MAP
Register
Address abbreviation
Read/
Write
Register
000000H
Resource
Initial value
(Reserved area) *
000001H
PDR1
Port 1 data register
R/W
Port 1
XXXXXXXXB
000002H
PDR2
Port 2 data register
R/W
Port 2
XXXXXXXXB
000003H
PDR3
Port 3 data register
R/W
Port 3
XXXXXXXXB
000004H
PDR4
Port 4 data register
R/W
Port 4
XXXXXXXXB
000005H
PDR5
Port 5 data register
R/W
Port 5
XXXXXXXXB
000006H
to
000010H
(Reserved area) *
000011H
DDR1
Port 1 direction data register
R/W
Port 1
00000000B
000012H
DDR2
Port 2 direction data register
R/W
Port 2
00000000B
000013H
DDR3
Port 3 direction data register
R/W
Port 3
000X0000B
000014H
DDR4
Port 4 direction data register
R/W
Port 4
XXX00000B
000015H
DDR5
Port 5 direction data register
R/W
Port 5
00000000B
8/10-bit
A/D converter
11111111B
000016H
to
00001AH
00001BH
(Reserved area) *
ADER
Analog input permission register
00001CH
to
00001FH
R/W
(Reserved area) *
000020H
SMR0
Serial mode register 0
R/W
00000000B
000021H
SCR0
Serial control register 0
R/W, W
00000100B
000022H
SIDR0/
SODR0
000023H
SSR0
000024H
CDCR0
000025H
Serial input data register 0/
Serial output data register 0
R, W
Serial status register 0
R, R/W
XXXXXXXXB
UART0
00001X00B
Communication prescaler control
register 0
R/W
0XXX1111B
SES0
Serial edge selection register 0
R/W
XXXXXXX0B
000026H
SMR1
Serial mode register 1
R/W
00000000B
000027H
SCR1
Serial control register 1
R/W, W
000028H
SIDR1/
SODR1
Serial input data register 1/
Serial output data register 1
R, W
000029H
SSR1
Serial status data register 1
R, R/W
00002AH
00002BH
00000100B
UART1
XXXXXXXXB
00001000B
(Reserved area) *
CDCR1
Communication prescaler control
register 1
R/W
UART1
0XXX0000B
(Continued)
DS07-13731-5E
15
MB90895 Series
Register
Address abbreviation
Read/
Write
Register
00002CH
to
00002FH
ENIR
DTP/External interrupt permission
register
R/W
000031H
EIRR
DTP/External interrupt source
register
R/W
ELVR
Detection level setting register
ADCS
A/D control status register
000033H
000034H
000035H
000036H
000037H
ADCR
000038H
to
00003EH
DTP/External
interrupt
XXXXXXXXB
00000000B
R/W
00000000B
R/W
00000000B
R/W, W
W, R
A/D data register
00000000B
R/W
8/10-bit
A/D converter
R
00000000B
XXXXXXXXB
00101XXXB
(Reserved area) *
00003FH
PSCCR
PLL/Subclock control register
R/W, W
000040H
PPGC0
PPG0 operation mode control
register
R/W, W
000041H
PPGC1
PPG1 operation mode control
register
R/W, W
000042H
PPG01
PPG0/1 count clock selection
register
R/W
000043H
Clock
XXXX0000B
0X000XX1B
8/16-bit
PPG timer 0/1
0X000001B
000000XXB
(Reserved area) *
000044H
PPGC2
PPG2 operation mode control
register
R/W, W
000045H
PPGC3
PPG3 operation mode control
register
R/W, W
000046H
PPG23
PPG2/3 count clock selection
register
R/W
000047H
to
00004FH
Initial value
(Reserved area) *
000030H
000032H
Resource
0X000XX1B
8/16-bit
PPG timer 2/3
0X000001B
000000XXB
(Reserved area) *
(Continued)
16
DS07-13731-5E
MB90895 Series
Register
Address abbreviation
000050H
000051H
000052H
000053H
IPCP0
Input capture data register 0
R
IPCP1
Input capture data register 1
R
000054H
ICS01
000055H
ICS23
000056H
000057H
000058H
Input capture control status register
R/W
TCDT
Timer counter data register
R/W
TCCS
Timer counter control status
register
R/W
000059H
00005AH
00005BH
00005CH
00005DH
000067H
000068H
000069H
IPCP2
Input capture data register 2
IPCP3
Input capture data register 3
R/W
TMCSR1
R/W
16-bit input/output
timer
00000000B
00000000B
00000000B
00000000B
00000000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
16-bit reload timer 0
16-bit reload timer 1
00000000B
XXXX0000B
00000000B
XXXX0000B
(Reserved area) *
ROMM
ROM mirroring function selection
register
W
ROM mirroring
function selection
module
XXXXXXX1B
(Reserved area) *
BVALR
Message buffer enabling register
R/W
CAN controller
00000000B
CAN controller
00000000B
CAN controller
00000000B
CAN controller
00000000B
(Reserved area) *
TREQR
Send request register
R/W
(Reserved area) *
TCANR
Send cancel register
000085H
000086H
XXXXXXXXB
R
R/W
Timer control status register
000083H
000084H
XXXXXXXXB
R
R/W
TMCSR0
000081H
000082H
XXXXXXXXB
(Reserved area) *
000070H
to
00007FH
000080H
Initial value
XXXXXXXXB
16-bit input/output
timer
00006AH
to
00006EH
00006FH
Resource
(Reserved area) *
00005EH
to
000065H
000066H
Read/
Write
Register
W
(Reserved area) *
TCR
Send completion register
R/W
(Continued)
DS07-13731-5E
17
MB90895 Series
Register
Address abbreviation
000087H
000088H
RCR
Receive completion register
RRTRR
R/W
Receive RTR register
CAN controller
00000000B
R/W
CAN controller
00000000B
CAN controller
00000000B
CAN controller
00000000B
(Reserved area) *
ROVRR
Receive overrun register
00008DH
00008EH
Initial value
(Reserved area) *
00008BH
00008CH
Resource
(Reserved area) *
000089H
00008AH
Read/
Write
Register
R/W
(Reserved area) *
RIER
Receive completion interrupt
permission register
00008FH
to
00009DH
R/W
(Reserved area) *
00009EH
PACSR
Address detection control register
R/W
Address matching
detection function
00000000B
00009FH
DIRR
Delay interrupt request generation/
release register
R/W
Delay interrupt
generation module
XXXXXXX0B
0000A0H
LPMCR
Lower power consumption mode
control register
W,R/W
Lower power
consumption mode
00011000B
0000A1H
CKSCR
Clock selection register
R,R/W
Clock
11111100B
0000A2H
PILR
I/O
0000000XB
Port input level selection register
0000A3H
to
0000A7H
R/W
(Reserved area) *
0000A8H
WDTC
Watchdog timer control register
R,W
Watchdog timer
XXXXX111B
0000A9H
TBTC
Time-base timer control register
R/W,W
Time-base timer
1XX00100B
0000AAH
WTC
Watch timer control register
R,R/W
Watch timer
1X001000B
512K-bit flash
memory
000X0000B
0000ABH
to
0000ADH
0000AEH
0000AFH
(Reserved area) *
FMCS
Flash memory control status
register
R,W,R/W
(Reserved area) *
(Continued)
18
DS07-13731-5E
MB90895 Series
Register
Address abbreviation
Read/
Write
Register
Resource
Initial value
0000B0H
ICR00
Interrupt control register 00
00000111B
0000B1H
ICR01
Interrupt control register 01
00000111B
0000B2H
ICR02
Interrupt control register 02
00000111B
0000B3H
ICR03
Interrupt control register 03
00000111B
0000B4H
ICR04
Interrupt control register 04
00000111B
0000B5H
ICR05
Interrupt control register 05
00000111B
0000B6H
ICR06
Interrupt control register 06
00000111B
0000B7H
ICR07
Interrupt control register 07
0000B8H
ICR08
Interrupt control register 08
0000B9H
ICR09
Interrupt control register 09
00000111B
0000BAH
ICR10
Interrupt control register 10
00000111B
0000BBH
ICR11
Interrupt control register 11
00000111B
0000BCH
ICR12
Interrupt control register 12
00000111B
0000BDH
ICR13
Interrupt control register 13
00000111B
0000BEH
ICR14
Interrupt control register 14
00000111B
0000BFH
ICR15
Interrupt control register 15
00000111B
0000C0H
to
0000FFH
Detection address setting register 0
(low-order)
PADR0
Detection address setting register 0
(middle-order)
001FF2H
Detection address setting register 0
(high-order)
001FF3H
Detection address setting register 1
(low-order)
001FF4H
PADR1
003901H
003902H
003903H
00000111B
00000111B
Detection address setting register 1
(middle-order)
XXXXXXXXB
XXXXXXXXB
R/W
Address matching
detection function
XXXXXXXXB
XXXXXXXXB
TMR0/
TMRLR0
16-bit timer register 0/16-bit reload
register 0
R,W
16-bit reload timer 0
TMR1/
TMRLR1
16-bit timer register 1/16-bit reload
register 1
R,W
16-bit reload timer 1
003904H
to
003909H
XXXXXXXXB
XXXXXXXXB
R/W
Detection address setting register 1
(high-order)
001FF5H
003900H
Interrupt controller
(Reserved area) *
001FF0H
001FF1H
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Reserved area) *
(Continued)
DS07-13731-5E
19
MB90895 Series
Register
Read/
Write
FLASH programing control register 0
R/W
Register
Address abbreviation
00390AH
FWR0
00390BH
FWR1
FLASH programing control register 1
R/W
00390CH
SSR0
Sector conversion set register
R/W
00390DH
to
00390FH
Resource
Initial value
00000000B
Dual operation
FLASH
00000000B
00XXXXX0B
(Reserved area) *
003910H
PRLL0
PPG0 reload register L
R/W
XXXXXXXXB
003911H
PRLH0
PPG0 reload register H
R/W
XXXXXXXXB
003912H
PRLL1
PPG1 reload register L
R/W
XXXXXXXXB
003913H
PRLH1
PPG1 reload register H
R/W
003914H
PRLL2
PPG2 reload register L
R/W
003915H
PRLH2
PPG2 reload register H
R/W
XXXXXXXXB
003916H
PRLL3
PPG3 reload register L
R/W
XXXXXXXXB
003917H
PRLH3
PPG3 reload register H
R/W
XXXXXXXXB
8/16-bit PPG timer
003918H
to
00392FH
(Reserved area) *
003930H
to
003BFFH
(Reserved area) *
003C00H
to
003C0FH
RAM (General-purpose RAM)
003C10H
to
003C13H
003C14H
to
003C17H
003C18H
to
003C1BH
003C1CH
to
003C1FH
003C20H
to
003C23H
003C24H
to
003C27H
003C28H
to
003C2BH
20
IDR0
ID register 0
R/W
IDR1
ID register 1
R/W
IDR2
ID register 2
R/W
IDR3
ID register 3
R/W
IDR4
ID register 4
R/W
IDR5
ID register 5
R/W
IDR6
ID register 6
R/W
CAN controller
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
to
XXXXXXXXB
XXXXXXXXB
to
XXXXXXXXB
XXXXXXXXB
to
XXXXXXXXB
XXXXXXXXB
to
XXXXXXXXB
XXXXXXXXB
to
XXXXXXXXB
XXXXXXXXB
to
XXXXXXXXB
XXXXXXXXB
to
XXXXXXXXB
(Continued)
DS07-13731-5E
MB90895 Series
Address
Register
abbreviation
003C2CH
to
003C2FH
IDR7
003C30H
003C31H
Register
Read/
Write
Resource
Initial value
ID register 7
R/W
XXXXXXXXB
to
XXXXXXXXB
DLCR0
DLC register 0
R/W
XXXXXXXXB
XXXXXXXXB
003C32H
003C33H
DLCR1
DLC register 1
R/W
XXXXXXXXB
XXXXXXXXB
003C34H
003C35H
DLCR2
DLC register 2
R/W
XXXXXXXXB
XXXXXXXXB
003C36H
003C37H
DLCR3
DLC register 3
R/W
XXXXXXXXB
XXXXXXXXB
003C38H
003C39H
DLCR4
DLC register 4
R/W
XXXXXXXXB
XXXXXXXXB
003C3AH
003C3BH
DLCR5
DLC register 5
R/W
XXXXXXXXB
XXXXXXXXB
003C3CH
003C3DH
DLCR6
DLC register 6
R/W
XXXXXXXXB
XXXXXXXXB
003C3EH
003C3FH
DLCR7
DLC register 7
R/W
XXXXXXXXB
XXXXXXXXB
003C40H
to
003C47H
DTR0
Data register 0
R/W
XXXXXXXXB
to
XXXXXXXXB
003C48H
to
003C4FH
DTR1
Data register 1
R/W
XXXXXXXXB
to
XXXXXXXXB
003C50H
to
003C57H
DTR2
Data register 2
R/W
XXXXXXXXB
to
XXXXXXXXB
003C58H
to
003C5FH
DTR3
Data register 3
R/W
XXXXXXXXB
to
XXXXXXXXB
003C60H
to
003C67H
DTR4
Data register 4
R/W
XXXXXXXXB
to
XXXXXXXXB
003C68H
to
003C6FH
DTR5
Data register 5
R/W
XXXXXXXXB
to
XXXXXXXXB
003C70H
to
003C77H
DTR6
Data register 6
R/W
XXXXXXXXB
to
XXXXXXXXB
003C78H
to
003C7FH
DTR7
Data register 7
R/W
XXXXXXXXB
to
XXXXXXXXB
CAN controller
(Continued)
DS07-13731-5E
21
MB90895 Series
(Continued)
Register
Address abbreviation
003C80H
to
003CFFH
003D00H
003D01H
003D02H
CSR
Control status register
LEIR
Last event display register
RTEC
R
Bit timing register
R/W
IDER
IDE register
R/W
0XXXX001B
00XXX000B
000XX000B
CAN controller
00000000B
00000000B
11111111B
X1111111B
XXXXXXXXB
(Reserved area) *
TRTRR
Send RTR register
R/W
00000000B
(Reserved area) *
RFWTR
Remote frame receive wait register
R/W
CAN controller
XXXXXXXXB
CAN controller
00000000B
CAN controller
XXXXXXXXB
XXXXXXXXB
CAN controller
XXXXXXXXB
to
XXXXXXXXB
XXXXXXXXB
to
XXXXXXXXB
(Reserved area) *
TIER
Send completion interrupt
permission register
003D0FH
003D10H
003D11H
003D12H
003D13H
003D14H
to
003D17H
003D18H
to
003D1BH
003D1CH
to
003DFFH
003E00H
to
003EFFH
003FF0H
to
003FFFH
CAN controller
R/W
BTR
003D0DH
003D0EH
R/W, R
Send/receive error counter
003D0BH
003D0CH
Initial value
(Reserved area) *
003D09H
003D0AH
Resource
(Reserved area) *
003D03H
003D04H
003D05H
003D06H
003D07H
003D08H
Read/
Write
Register
R/W
(Reserved area) *
AMSR
Acceptance mask selection register
R/W
(Reserved area) *
AMR0
AMR1
Acceptance mask register 0
Acceptance mask register 1
R/W
R/W
(Reserved area) *
(Reserved area) *
(Reserved area) *
Initial values :
0 : Initial value of this bit is “0.”
1 : Initial value of this bit is “1.”
X : Initial value of this bit is undefined.
* : “Reserved area” should not be written anything. Result of reading from “Reserved area” is undefined.
22
DS07-13731-5E
MB90895 Series
■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
Interrupt source
EI2OS
readiness
Interrupt vector
Number
Interrupt control register
Address
ICR
Address
Priority*3
Reset
×
#08
08H
FFFFDCH
⎯
⎯
High
INT 9 instruction
×
#09
09H
FFFFD8H
⎯
⎯
↑
Exceptional treatment
×
#10
0AH
FFFFD4H
⎯
⎯
CAN controller reception
completed (RX)
×
#11
0BH
FFFFD0H
ICR00
0000B0H*1
ICR01
0000B1H
ICR02
0000B2H*1
ICR03
0000B3H*1
ICR04
0000B4H*1
ICR05
0000B5H*1
ICR06
0000B6H*1
ICR07
0000B7H*2
ICR08
0000B8H*1
ICR09
0000B9H*1
ICR10
0000BAH*1
ICR11
0000BBH*1
ICR12
0000BCH*1
CAN controller transmission
completed (TX) / Node status
transition (NS)
×
#12
0CH
FFFFCCH
Reserved
×
#13
0DH
FFFFC8H
Reserved
×
#14
0EH
FFFFC4H
CAN wakeup
Δ
#15
0FH
FFFFC0H
Time-base timer
×
#16
10H
FFFFBCH
16-bit reload timer 0
Δ
#17
11H
FFFFB8H
8/10-bit A/D converter
Δ
#18
12H
FFFFB4H
16-bit free-run timer overflow
Δ
#19
13H
FFFFB0H
Reserved
×
#20
14H
FFFFACH
Reserved
×
#21
15H
FFFFA8H
PPG timer ch.0, ch.1 underflow
×
#22
16H
FFFFA4H
Input capture 0-input
Δ
#23
17H
FFFFA0H
External interrupt (INT4/INT5)
Δ
#24
18H
FFFF9CH
Input capture 1-input
Δ
#25
19H
FFFF98H
PPG timer ch.2, ch.3 underflow
×
#26
1AH
FFFF94H
External interrupt (INT6/INT7)
Δ
#27
1BH
FFFF90H
Watch timer
Δ
#28
1CH
FFFF8CH
Reserved
×
#29
1DH
FFFF88H
Input capture 2-input
Input capture 3-input
×
#30
1EH
FFFF84H
Reserved
×
#31
1FH
FFFF80H
Reserved
×
#32
20H
FFFF7CH
Reserved
×
#33
21H
FFFF78H
Reserved
×
#34
22H
FFFF74H
Reserved
×
#35
23H
FFFF70H
#36
24H
FFFF6CH
16-bit reload timer 1
↓
Low
(Continued)
DS07-13731-5E
23
MB90895 Series
(Continued)
Interrupt source
EI2OS
readiness
UART1 reception completed
UART1 transmission completed
Δ
UART0 reception completed
Interrupt vector
Number
Address
#37
25H
FFFF68H
#38
26H
FFFF64H
#39
27H
FFFF60H
UART0 transmission completed
Δ
#40
28H
FFFF5CH
Flash memory
×
#41
29H
FFFF58H
Delay interrupt generation
module
×
#42
2AH
FFFF54H
Interrupt control register
ICR
Address
ICR13
0000BDH*1
ICR14
0000BEH*1
ICR15
0000BFH*1
Priority*3
High
↑
↓
Low
: Available
× : Unavailable
: Available, El2OS stop function is provided.
Δ : Available when a cause of interrupt sharing a same ICR is not used.
*1 : • Peripheral functions sharing an ICR register have the same interrupt level.
• If peripheral functions share an ICR register, only one function is available when using extended intelligent
I/O service.
• If peripheral functions share an ICR register, a function using extended intelligent I/O service does not allow
interrupt by another function.
*2 : Only input capture 1 is ready for EI2OS. Because PPG is not ready for EI2OS, disable PPG interrupt when
using EI2OS with Input capture 1.
*3 : Priority when two or more interrupts of a same level occur simultaneously.
24
DS07-13731-5E
MB90895 Series
■ FLASH MEMORY CONFIGURATION
• Sector configuration of 512 Kbit flash memory
Flash memory
CPU address
Writer address*
FF0000H
70000H
FF0FFF H
70FFFH
FF1000H
71000H
FF1FFF H
71FFFH
FF2000H
72000H
FF2FFF H
72FFFH
FF3000H
73000H
FF3FFF H
73FFFH
FF4000H
74000H
FF7FFF H
77FFFH
FF8000H
78000H
FFBFFF H
7BFFF H
FFC000 H
7C000H
FFCFFF H
7CFFF H
FFD000 H
7D000H
FFDFFF H
7DFFF H
FFE000H
7E000H
FFEFFF H
7EFFF H
FFF000H
7F000H
FFFFFF H
7FFFFH
SA1 (4 Kbytes)
SA2 (4 Kbytes)
Lower Bank
SA0 (4 Kbytes)
SA3 (4 Kbytes)
SA4 (16 Kbytes)
SA6 (4 Kbytes)
SA7 (4 Kbytes)
Upper Bank
SA5 (16 Kbytes)
SA8 (4 Kbytes)
SA9 (4 Kbytes)
* : “Writer address” is an address equivalent to CPU address, which is used
when data is written on flash memory, using parallel writer. When writing/
deleting data with general-purpose writer, the writer address is used for
writing and deleting.
DS07-13731-5E
25
MB90895 Series
■ ELECTRIC CHARACTERISTICS
1. Absolute Maximum Rating
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.3
VSS + 6.0
V
AVCC
VSS − 0.3
VSS + 6.0
V
VCC = AVCC*2
AVR
VSS − 0.3
VSS + 6.0
V
AVCC ≥ AVR*2
Input voltage*1
VI
VSS − 0.3
VSS + 6.0
V
*3
Output voltage*1
VO
VSS − 0.3
VSS + 6.0
V
*3
ICLAMP
− 2.0
+ 2.0
mA
*7
Σ| ICLAMP |
⎯
20
mA
*7
IOL1
⎯
15
mA
Normal output*4
IOL2
⎯
40
mA
High-current output*4
IOLAV1
⎯
4
mA
Normal output*5
IOLAV2
⎯
30
mA
High-current output*5
ΣIOL1
⎯
125
mA
Normal output
ΣIOL2
⎯
160
mA
High-current output
ΣIOLAV1
⎯
40
mA
Normal output*6
ΣIOLAV2
⎯
40
mA
High-current output*6
IOH1
⎯
−15
mA
Normal output*4
IOH2
⎯
−40
mA
High-current output*4
IOHAV1
⎯
−4
mA
Normal output*5
IOHAV2
⎯
−30
mA
High-current output*5
ΣIOH1
⎯
−125
mA
Normal output
ΣIOH2
⎯
−160
mA
High-current output
ΣIOHAV1
⎯
−40
mA
Normal output*6
ΣIOHAV2
⎯
−40
mA
High-current output*6
PD
⎯
297
mW
−40
+105
°C
Other than
MB90F897Y/YS
−40
+125
°C
*8
Other than
MB90F897Y/YS
−40
+150
°C
*8, *9
MB90F897Y/YS
−55
+150
°C
1
Power supply voltage*
Maximum clamp current
Total maximum clamp current
“L” level maximum output current
“L” level average output current
“L” level maximum total output current
“L” level average total output current
“H” level maximum output current
“H” level average output current
“H” level maximum total output current
“H” level average total output current
Power consumption
Operating temperature
Storage temperature
TA
Tstg
*1: The parameter is based on VSS = AVSS = 0.0 V.
*2 : AVcc and AVR should not exceed Vcc.
(Continued)
26
DS07-13731-5E
MB90895 Series
(Continued)
*3 : VI and VO should not exceed Vcc + 0.3 V. However, if the maximum current to/from an input is limited by some
means with external components, the ICLAMP rating supersedes the VI rating.
*4 : A peak value of an applicable one pin is specified as a maximum output current.
*5 : An average current value of an applicable one pin within 100 ms is specified as an average output current.
(Average value is found by multiplying operating current by operating rate.)
*6 : An average current value of all pins within 100 ms is specified as an average total output current. (Average
value is found by multiplying operating current by operating rate.)
*7 : • Applicable to pins: P10 to P17, P20 to P27, P30 to P33, P35, P36, P37, P40 to P44, P50 to P57
Note: P35 and P36 are MB90F897S/YS only.
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to the
microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential
may pass through the protective diode and increase the potential at the VCC pin, and this may affect other
devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is
provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input
pins, etc.) cannot accept +B signal input.
• Sample recommended circuits:
• Input/Output Equivalent circuits
Protective diode
VCC
P-ch
Limiting
resistance
+B input (0 V to 16 V)
N-ch
R
*8 : Users considering application exceeding TA = +105°C are advised to contact their FUJITSU MICROELECTRONICS representatives beforehand for reliability limitations.
*9 : Use the PB circuit board which has 4 or more layers.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS07-13731-5E
27
MB90895 Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V)
Parameter
Value
Symbol
Power supply voltage
Smoothing capacitor
Operating temperature
VCC
CS
TA
Unit
Remarks
Min
Typ
Max
3.5
5.0
5.5
V
Under normal operation
3.0
⎯
5.5
V
Retain status of stop
operation
4.0
⎯
5.5
V
Accuracy guarantee voltage
of A/D converter
0.1
⎯
1.0
μF
*1
−40
⎯
+105
°C Other than MB90F897Y/YS
−40
⎯
+125
°C
*2
Other than MB90F897Y/YS
−40
⎯
+150
°C
*2, *3
MB90F897Y/YS
*1 : Use a ceramic capacitor, or a capacitor of similar frequency characteristics. On the Vcc pin, use a bypass
capacitor that has a larger capacity than that of Cs.
Refer to the following figure for connection of smoothing capacitor Cs.
*2: Users considering application exceeding TA = +105°C are advised to contact their FUJITSU MICROELECTRONICS representatives beforehand for reliability limitations.
*3 : Use the PB circuit board which has 4 or more layers.
• C pin connection diagram
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
28
DS07-13731-5E
MB90895 Series
3. DC Characteristics
• MB90F897/S (Models that support + 125 °C)
Parame- Sym
ter
bol
Pin name
CMOS
VIHS hysteresis
input pin
“H” level
input
voltage
“L” level
input
voltage
0.8 VCC
—
VCC + 0.3
V
When selected
CMOS hysteresis
Automotive
input pin
—
0.8 VCC
—
VCC + 0.3
V
When selected
Automotive
VIHC
CMOS input pin
(P32, P40)
—
0.7 VCC
—
VCC + 0.3
V
When selected
CMOS
VIHM MD input pin
—
VCC − 0.3
—
VCC + 0.3
V
CMOS
VILS hysteresis
input pin
—
VSS − 0.3
—
0.2 VCC
V
When selected
CMOS hysteresis
VILA
Automotive
input pin
—
VSS − 0.3
—
0.5 VCC
V
When selected
Automotive
VILC
CMOS input pin
(P32, P40)
—
VSS − 0.3
—
0.3 VCC
V
When selected
CMOS
—
VSS − 0.3
—
VSS + 0.3
V
VCC – 0.5
—
—
V
VCC – 0.5
—
—
V
—
—
0.4
V
VCC = 4.5 V,
IOL = 20.0 mA
—
—
0.4
V
VCC = 5.5 V,
VSS < VI < VCC
–5
—
+5
μA
VCC = 5.0 V,
Internally operating at
16 MHz, normal operation.
—
25
30
mA
VCC = 5.0 V,
Internally operating at
16 MHz, writing on flash
memory.
—
45
50
mA MB90F897/S
VCC = 5.0 V,
Internally operating at
16 MHz, deleting on flash
memory.
—
45
50
mA MB90F897/S
“H” level
output
voltage
VOH1
“L” level
output
voltage
VOL1
Power
supply
current*
—
VIHA
VILM MD input pin
Input
leak
current
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C)
Value
Remarks
Conditions
Unit
Min
Typ
Max
Pins other than VCC = 4.5 V,
P14 to P17
IOH = −4.0 mA
VOH2 P14 to P17
Pins other than VCC = 4.5 V,
P14 to P17
IOL = 4.0 mA
VOL2 P14 to P17
IIL
ICC
VCC = 4.5 V,
IOH = −14.0 mA
All input pins
VCC
* : Test conditions of power supply current are based on a device using external clock.
(Continued)
DS07-13731-5E
29
MB90895 Series
(Continued)
Parameter
Symbol
Pin name
ICCS
VCC = 5.0 V,
Internally operating at
16 MHz, sleeping.
—
8
12
mA
ICTS
VCC = 5.0 V,
Internally operating at
2 MHz, transition
from main clock
mode, in time-base
timer mode.
—
0.2
0.35
mA
ICTSPII
VCC = 5.0 V,
Internally operating at
16 MHz, transition
from PLL clock mode,
in time-base timer
mode.
—
3
5
mA
ICCL
VCC = 5.0 V,
Internally operating at
8 kHz, subclock
operation,
TA = + 25°C
—
40
100
μA
ICCLS
VCC = 5.0 V,
Internally operating at
8 kHz, subclock,
sleep mode,
TA = + 25°C
—
10
50
μA
ICCT
VCC = 5.0 V,
Internally operating at
8 kHz, watch mode,
TA = + 25°C
—
8
30
μA
ICCH
Stopping,
TA = + 25°C
—
5
25
μA
Power
supply
current*
Input
capacity
Pull-up
resistor
Pull-down
resistor
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C)
Value
Conditions
Unit
Remarks
Min
Typ
Max
VCC
CIN
Other than
AVCC, AVSS,
AVR, C, VCC,
VSS
⎯
—
5
15
pF
RUP
RST
⎯
25
50
100
kΩ
RDOWN MD2
⎯
25
50
100
kΩ
FLASH product is
not provided with
pull-down resistor.
* : Test conditions of power supply current are based on a device using external clock.
30
DS07-13731-5E
MB90895 Series
•
• MB90F897Y/YS (Models that support + 150 °C) (Under development)
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +150 °C)
Value
Sym
Remarks
Parameter
Pin name
Conditions
Unit
bol
Min
Typ
Max
CMOS
VIHS hysteresis
input pin
“H” level
input
voltage
“L” level
input
voltage
—
VCC + 0.3
V
When selected
CMOS hysteresis
Automotive
input pin
—
0.8 VCC
—
VCC + 0.3
V
When selected
Automotive
VIHC
CMOS input pin
(P32, P40)
—
0.7 VCC
—
VCC + 0.3
V
When selected
CMOS
VIHM MD input pin
—
VCC − 0.3
—
VCC + 0.3
V
CMOS
VILS hysteresis
input pin
—
VSS − 0.3
—
0.2 VCC
V
When selected
CMOS hysteresis
VILA
Automotive
input pin
—
VSS − 0.3
—
0.5 VCC
V
When selected
Automotive
VILC
CMOS input pin
(P32, P40)
—
VSS − 0.3
—
0.3 VCC
V
When selected
CMOS
—
VSS − 0.3
—
VSS + 0.3
V
VCC – 0.5
—
—
V
VCC – 0.5
—
—
V
Pins other than VCC = 4.5 V,
P14 to P17
IOL = 3.0 mA
—
—
0.4
V
VCC = 4.5 V,
IOL = 16 mA
—
—
0.4
V
VCC = 5.5 V,
VSS < VI < VCC
–5
—
+5
μA
VCC = 5.0 V,
Internally operating at
16 MHz, normal
operation.
—
25
32
mA
VCC = 5.0 V,
Internally operating at
16 MHz, writing on
flash memory.
TA = −40 °C to +125 °C
—
45
50
mA Up to + 125 °C
VCC = 5.0 V,
Internally operating at
16 MHz, deleting on
flash memory.
TA = −40 °C to +125 °C
—
45
50
mA Up to + 125 °C
“H” level
output voltage
VOH1
“L” level
output voltage
VOL1
Power
supply
current*
0.8 VCC
VIHA
VILM MD input pin
Input leak
current
—
Pins other than VCC = 4.5 V,
P14 to P17
IOH = −3.0 mA
VOH2 P14 to P17
VOL2 P14 to P17
IIL
ICC
All input pins
VCC
VCC = 4.5 V,
IOH = −12.0 mA
* : Test conditions of power supply current are based on a device using external clock.
(Continued)
DS07-13731-5E
31
MB90895 Series
(Continued)
Parameter
Symbol
Pin name
ICCS
ICTS
Power
supply
current*
ICTSPII
VCC
ICCL
ICCLS
ICCT
ICCH
Input
capacity
Pull-up
resistor
Pull-down
resistor
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +150 °C)
Value
Conditions
Unit
Remarks
Min
Typ
Max
VCC = 5.0 V,
Internally operating at
—
8
14
mA
16 MHz, sleeping.
VCC = 5.0 V,
Internally operating at
2 MHz, transition from
—
0.2
0.35
mA Up to + 125 °C
main clock mode, in
time-base timer mode.
TA = −40 °C to +125 °C
VCC = 5.0 V,
Internally operating at
2 MHz, transition from
main clock mode, in
—
0.2
T.B.D mA
time-base timer mode.
TA = +125 °C to
+150 °C
VCC = 5.0 V,
Internally operating at
16 MHz, transition
—
3
7
mA
from PLL clock mode,
in time-base timer
mode.
VCC = 5.0 V,
Internally operating at
—
40
100
μA
8 kHz, subclock
operation,
TA = + 25°C
VCC = 5.0 V,
Internally operating at
8 kHz, subclock,
—
10
50
μA
sleep mode,
TA = + 25°C
VCC = 5.0 V,
Internally operating at
—
8
30
μA
8 kHz, watch mode,
TA = + 25°C
Stopping,
—
5
25
μA
TA = + 25°C
CIN
Other than
AVCC, AVSS,
AVR, C, VCC,
VSS
⎯
—
5
15
pF
RUP
RST
⎯
25
50
100
kΩ
RDOWN MD2
⎯
25
50
100
kΩ
FLASH product is
not provided with
pull-down resistor.
* : Test conditions of power supply current are based on a device using external clock.
32
DS07-13731-5E
MB90895 Series
4. AC Characteristics
(1) Clock timing
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C/+150 °C (only MB90F897Y/YS))
Value
Parameter
Symbol Pin name
Unit
Remarks
Min
Typ
Max
fC
Clock frequency
Clock cycle time
Input clock pulse width
Input clock rise time and
fall time
Internal operation clock
frequency
Internal operation clock
cycle time
X0, X1
When crystal or ceramic
resonator is used
3
—
8
MHz
3
—
16
MHz External clock
4
—
16
MHz PLL multiplied by 1
4
—
8
MHz PLL multiplied by 2
4
—
5.33
MHz PLL multiplied by 3
4
—
4
MHz PLL multiplied by 4
fCL
X0A, X1A
—
32.768
—
kHz
MB90F897/Y only
tHCYL
X0, X1
125
—
333
ns
tLCYL
X0A, X1A
—
30.5
—
μs
MB90F897/Y only
PWH, PWL
X0
10
—
—
ns
Set duty factor at 30% to 70%
as a guideline.
PWLH,PWLL
X0A
—
15.2
—
μs
MB90F897/Y only
tCR, tCF
X0
—
—
5
ns
When external clock is used
fCP
—
1.5
—
16
MHz When main clock is used
fLCP
—
—
8.192
—
kHz
When sub clock is used,
MB90F897/Y only
tCP
—
62.5
—
666
ns
When main clock is used
tLCP
—
—
122.1
—
μs
When sub clock is used,
MB90F897/Y only
• Clock timing
tHCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tCF
tCR
tLCYL
0.8 VCC
X0A
0.2 VCC
PWLH
PWLL
tCF
DS07-13731-5E
tCR
33
MB90895 Series
• PLL operation guarantee range
Relation between internal operation clock
frequency and power supply voltage
Operation guarantee range of MB90F897/S/Y/YS
Power voltage VCC (V)
5.5
A/D converter
accuracy
guarantee range
4.0
3.5
3.0
PLL operation guarantee range
1.5
3 4
12
8
16
Internal clock fCP (MHz)
Relation among external clock frequency and internal clock frequency
4x
3x
2x
1x
Internal clock fCP (MHz)
16
12
1/2 x
(no multiplication)
9
8
4
1.5
3
4
8
16
External clock fC (MHz)*
* : fc is 8 MHz at maximum when crystal or ceramic resonator circuit is used.
34
DS07-13731-5E
MB90895 Series
Rating values of alternating current is defined by the measurement reference voltage values shown below:
• Input signal waveform
• Output signal waveform
Hysteresis input pin
Output pin
VIH
2.4 V
VIL
0.8 V
(2) Reset input timing
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C/+150 °C (only MB90F897Y/YS))
Value
Pin
CondiParameter
Symbol
Unit
Remarks
name
tions
Min
Max
16 tCP*3
Reset input time
tRSTL
RST
⎯
⎯
ns
Normal operation
Oscillation time
of oscillator*1 +
100 μs + 16 tCP*3
⎯
⎯
In sub clock*2, sub
sleep*2, watch*2 and
stop mode
100
⎯
μs
In timebase timer
*1 : Oscillation time of oscillator is time that the amplitude reached the 90%. In the crystal oscillator, the oscillation
time is between several ms to tens of ms. In ceramic oscillator, the oscillation time is between hundreds
of μs to several ms. In the external clock, the oscillation time is 0 ms.
*2 : Except for MB90F897S/YS.
*3 : Refer to “(1) Clock timing” ratings for tCP (internal operation clock cycle time).
• In sub clock, sub sleep, watch and stop mode
tRSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal operation
clock
100 s
+ 16 tCP
Oscillation
time of
oscillator
Wait time for stabilizing
oscillation
Execute instruction
Internal reset
DS07-13731-5E
35
MB90895 Series
(3) Power-on reset
Parameter
(VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C/+150 °C (only MB90F897Y/YS))
Value
Symbol Pin name Conditions
Unit
Remarks
Min
Max
Power supply rise time
tR
VCC
Power supply shutdown
time
tOFF
VCC
⎯
0.05
30
ms
1
⎯
ms
Repeated operation
tR
VCC
2.7 V
0.2 V
0.2 V
0.2 V
tOFF
Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power
supply voltages during operation, raise the power smoothly by suppressing variation of voltages as shown
below. When raising the power, do not use PLL clock. However, if voltage drop is 1V/s or less, use of PLL
clock is allowed during operation.
VCC
3.0 V
VSS
36
Limiting the slope of rising within
50 mV/ms is recommended.
RAM data hold period
DS07-13731-5E
MB90895 Series
(4) UART0/UART1 timing
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +125 °C/+150 °C (only MB90F897Y/YS))
Value
Parameter
Symbol Pin name
Conditions
Unit Remarks
Min
Max
8 tCP *
⎯
ns
−80
+80
ns
100
⎯
ns
SCK0/SCK1,
SIN0/SIN1
60
⎯
ns
tSHSL
SCK0/SCK1
4 tCP *
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK0/SCK1
4 tCP *
⎯
ns
SCK ↓ → SOT delay time
tSLOV
⎯
150
ns
Valid SIN → SCK ↑
tIVSH
60
⎯
ns
SCK ↑ →valid SIN hold time
tSHIX
60
⎯
ns
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOV
Valid SIN → SCK ↑
tIVSH
SCK ↑ → valid SIN hold time
tSHIX
Serial clock “H” pulse width
SCK0/SCK1
SCK0/SCK1,
SOT0/SOT1 Internal shift clock
SCK0/SCK1, mode output pin is :
SIN0/SIN1 CL = 80 pF+1TTL
SCK0/SCK1,
External shift clock
SOT0/SOT1
mode output pin is :
SCK0/SCK1, CL = 80 pF+1TTL
SIN0/SIN1
SCK0/SCK1,
SIN0/SIN1
* : Refer to "(1) Clock timing" ratings for tCP (internal operation clock cycle time).
Notes: • AC rating in CLK synchronous mode.
• CL is a load capacitance value on pins for testing.
DS07-13731-5E
37
MB90895 Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
SOT
0.8 V
tIVSH
SIN
tSHIX
VIH
VIH
VIL
VIL
• External shift clock mode
tSLSH
SCK
tSHSL
VIH
VIL
VIH
VIL
tSLOV
2.4 V
SOT
0.8 V
tIVSH
SIN
38
tSHIX
VIH
VIH
VIL
VIL
DS07-13731-5E
MB90895 Series
(5) Timer input timing
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +125 °C/+150 °C (only MB90F897Y/YS))
Value
Parameter
Symbol
Pin name
Conditions
Unit Remarks
Min
Max
Input pulse width
tTIWH
TIN0, TIN1
tTIWL
IN0 to IN3
⎯
⎯
4 tCP *
ns
* : Refer to "(1) Clock timing" ratings for tCP (internal operation clock cycle time).
• Timer input timing
VIH
VIH
TIN0, TIN1,
IN0 to IN3
VIL
VIL
tTIWH
tTIWL
(6) Trigger input timing
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +125 °C/+150 °C (only MB90F897Y/YS))
Value
Parameter
Symbol
Pin name
Conditions
Unit Remarks
Min
Max
Input pulse width
tTRGH
tTRGL
INT4 to INT7,
ADTG
⎯
⎯
3 tCP *
ns
* : Refer to "(1) Clock timing" ratings for tCP (internal operation clock cycle time).
• Trigger input timing
INT4 to INT7,
ADTG
VIH
VIH
VIL
tTRGH
DS07-13731-5E
VIL
tTRGL
39
MB90895 Series
5. A/D converter
(VCC = AVCC = 5.0 V ± 10 %, 3.0 V ≤ AVR − AVSS, VSS = AVSS = 0.0 V,
TA = −40 °C to +125 °C/+150 °C (only MB90F897Y/YS))
Value
Unit
Remarks
Min
Typ
Max
Symbol
Pin
name
Resolution
⎯
⎯
⎯
⎯
10
bit
Total error
⎯
⎯
⎯
⎯
± 3.0
LSB
Nonlinear error
⎯
⎯
⎯
⎯
± 2.5
LSB
Differential linear error
⎯
⎯
⎯
⎯
± 1.9
LSB
Zero transition voltage
VOT
AN0 to
AN7
AVSS −
1.5 LSB
AVSS +
0.5 LSB
AVSS +
2.5 LSB
V
VFST
AN0 to
AN7
AVR −
3.5 LSB
AVR −
1.5 LSB
AVR +
0.5 LSB
V
66 tCP *1
⎯
⎯
ns
With 16 MHz
machine clock
5.5 V ≥ AVCC ≥ 4.5 V
88 tCP *1
⎯
⎯
ns
With 16 MHz
machine clock
4.5 V > AVCC ≥ 4.0 V
32 tCP *1
⎯
⎯
ns
With 16 MHz
machine clock
5.5 V ≥ AVCC ≥ 4.5 V
128 tCP *1
⎯
⎯
ns
With 16 MHz
machine clock
4.5 V > AVCC ≥ 4.0 V
Parameter
Full-scale transition
voltage
Compare time
Sampling time
⎯
⎯
⎯
⎯
Analog port input
current
IAIN
AN0 to
AN7
⎯
⎯
10
μA
Analog input voltage
VAIN
AN0 to
AN7
AVSS
⎯
AVR
V
⎯
AVR
AVSS + 2.7
⎯
AVCC
V
IA
AVCC
⎯
3.5
7.5
mA
IAH
AVCC
⎯
⎯
5
μA
Reference voltage
Power supply current
Reference voltage
supplying current
IR
AVR
⎯
165
250
μA
IRH
AVR
⎯
⎯
5
μA
Variation among
channels
⎯
AN0 to
AN7
⎯
⎯
4
LSB
1 LSB = (AVR −
AVSS) /1024
*2
*2
*1 : Refer to "(1) Clock timing" ratings for tCP (internal operation clock cycle time).
*2 : If A/D converter is not operating, a current when CPU is stopped is applicable (Vcc=AVcc=AVR=5.0 V).
40
DS07-13731-5E
MB90895 Series
6. Definition of A/D Converter Terms
Resolution
Linear error
Differential linear
error
Total error
: Analog variation that is recognized by an A/D converter.
: Deviation between a line across zero-transition line (“00 0000 0000” ←→“00 0000 0001”)
and full-scale transition line (“11 1111 1110” ←→ “11 1111 1111”) and actual conversion
characteristics.
: Deviation of input voltage, which is required for changing output code by 1 LSB, from an
ideal value.
: Difference between an actual value and an ideal value. A total error includes zero transition
error, full-scale transition error, and linear error.
Total error
3FFH
3FEH
Actual conversion
characteristics
1.5 LSB
Digital output
3FDH
{1 LSB × (N − 1) + 0.5 LSB}
004H
VNT
(Actually-measured value)
003H
Actual conversion
characteristics
Ideal characteristics
002H
001H
0.5 LSB
AVss
Total error of digital output “N” =
1 LSB = (Ideal value)
Analog input
AVR
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
AVR − AVSS
1024
[LSB]
[V]
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVR − 1.5 LSB [V]
VNT : A voltage at which digital output transits from (N-1) to N.
(Continued)
DS07-13731-5E
41
MB90895 Series
(Continued)
Differential linear error
Linear error
3FFH
3FDH
004H
003H
N+1
VFST (actual
measurement
value)
Digital output
Digital output
3FEH
Ideal characteristics
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
VNT (actual
measurement value)
Actual conversion
characteristics
Actual conversion
characteristics
N
V (N + 1) T
(actual measurement
value)
N−1
VNT
(actual measurement value)
002H
Ideal characteristics
Actual conversion
characteristics
N−2
001H
VOT (actual measurement value)
AVss
AVR
AVss
Analog input
AVR
Analog input
Linear error of digital output N =
Differential linear error of digital output N =
1 LSB =
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
V (N + 1) T − VNT
1 LSB
VFST − VOT
1022
[LSB]
−1LSB [LSB]
[V]
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
42
DS07-13731-5E
MB90895 Series
7. Notes on A/D Converter Section
<About the external impedance of the analog input and its sampling time>
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision.
Analog input circuit model
R
Comparator
Analog input
C
During sampling : ON
MB90F897/S
MB90F897Y/YS
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
R
2.4 kΩ (Max)
16.4 kΩ (Max)
C
36.4 pF (Max)
36.4 pF (Max)
Note : The values are reference values.
(Continued)
DS07-13731-5E
43
MB90895 Series
(Continued)
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the resistor value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.
(At 4.5 V ≤ AVCC ≤ 5.5 V)
[External impedance = 0 kΩ to 20 kΩ]
MB90F897/S/
MB90F897Y/YS
100
90
80
70
60
50
40
30
20
10
0
→ External impedance [kΩ]
→ External impedance [kΩ]
[External impedance = 0 kΩ to 100 kΩ]
0
5
10
15
20
25
30
20
18
16
14
12
10
8
6
4
2
0
35
MB90F897/S/
MB90F897Y/YS
0
1
2
3
4
5
6
7
8
→ Minimum sampling time [μs]
→ Minimum sampling time [μs]
(At 4.0 V ≤ AVCC < 4.5 V)
[External impedance = 0 kΩ to 20 kΩ]
MB90F897/S/
MB90F897Y/YS
100
90
80
70
60
50
40
30
20
10
0
→ External impedance [kΩ]
→ External impedance [kΩ]
[External impedance = 0 kΩ to 100 kΩ]
0
5
10
15
20
25
30
→ Minimum sampling time [μs]
35
20
18
16
14
12
10
8
6
4
2
0
MB90F897/S/
MB90F897Y/YS
0
1
2
3
4
5
6
7
8
→ Minimum sampling time [μs]
The relationship between the external impedance and minimum sampling time
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
<About errors>
• As ⏐AVR − AVss⏐ become smaller, values of relative errors grow larger.
44
DS07-13731-5E
MB90895 Series
8. Flash Memory Program/Erase Characteristics*1
Parameter
Conditions
Value
Unit
Remarks
0.5
s
Excludes 00H programming
prior to erasure
0.5
7.5
s
Excludes 00H programming
prior to erasure
⎯
2.6
⎯
s
Excludes 00H programming
prior to erasure
⎯
16
3,600
μs
Except for the over head
time of the system
Min
Typ
Max
Sector erase time
(4 KB sector)
⎯
0.2
Sector erase time
(16 KB sector)
⎯
Chip erase time
TA = + 25 °C,
VCC = 5.0 V
Word (16 bit width)
programming time
Program/Erase cycle
⎯
10,000
⎯
⎯
cycle
Flash Data Retention
Time
Average
TA = + 85 °C
20
⎯
⎯
Years *2
*1 : For MB90F897Y/YS, it is prohibited to write or erase data in the range of TA = + 125 °C to + 150 °C.
*2 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C) .
DS07-13731-5E
45
MB90895 Series
■ EXAMPLE CHARACTERISTICS
• MB90F897
ICC − VCC
TA = +25 °C, In external clock operation
f = Internal operating frequency
30
25
f = 16 MHz
ICC (mA)
20
f = 10 MHz
15
f = 8 MHz
10
f = 4 MHz
5
f = 2 MHz
0
2.5
3.5
4.5
VCC (V)
5.5
6.5
ICCS − VCC
TA = +25 °C, In external clock operation
f = Internal operating frequency
10
ICCS (mA)
8
f = 16 MHz
6
f = 10 MHz
4
f = 8 MHz
2
f = 4 MHz
f = 2 MHz
0
2.5
3.5
4.5
VCC (V)
5.5
6.5
ICCL − VCC
TA = +25 °C, In external clock operation
f = Internal operating frequency
350
300
f = 8 kHz
ICCL (µA)
250
200
150
100
50
0
3
4
5
VCC (V)
6
7
(Continued)
46
DS07-13731-5E
MB90895 Series
ICCLS − VCC
ICCLS (µA)
TA = +25 °C, In external clock operation
f = Internal operating frequency
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
f = 8 kHz
3
4
5
VCC (V)
6
7
ICCT − VCC
TA = +25 °C, In external clock operation
f = Internal operating frequency
10
9
8
f = 8 kHz
ICCT (µA)
7
6
5
4
3
2
1
0
4
3
5
6
7
VCC (V)
ICCH − VCC
Stopping, TA = +25 °C
30
ICCH (µA)
25
20
15
10
5
0
2
3
4
5
6
7
VCC (V)
(Continued)
DS07-13731-5E
47
MB90895 Series
(Continued)
(VCC - VOH) − IOH
TA = +25 °C, VCC = 4.5 V
1000
900
VCC - VOH (mV)
800
700
600
500
400
300
200
100
0
0
1
2
3
4
5
6
7
8
9
10
IOH (mA)
VOL − IOL
TA = +25 °C, VCC = 4.5 V
1000
900
800
VOL (mV)
700
600
500
400
300
200
100
0
0
2
4
6
8
10
IOL (mA)
“H” level input voltage/ “L” level input voltage
VIN − VCC
TA = +25 °C
5
VIN (V)
4
VIH
3
VIL
2
1
0
2.5
3
3.5
4
4.5
5
5.5
6
VCC (V)
48
DS07-13731-5E
MB90895 Series
■ ORDERING INFORMATION
Part number
MB90F897PMT
MB90F897SPMT
MB90F897YPMT
MB90F897YSPMT
DS07-13731-5E
Package
Remarks
48-pin plastic LQFP
(FPT-48P-M26)
49
MB90895 Series
■ PACKAGE DIMENTION
48-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
7 × 7 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.17 g
Code
(Reference)
P-LFQFP48-7×7-0.50
(FPT-48P-M26)
48-pin plastic LQFP
(FPT-48P-M26)
Note 1) * : These dimensions include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00±0.20(.354±.008)SQ
+0.40
+.016
* 7.00 –0.10 .276 –.004 SQ
36
0.145±0.055
(.006±.002)
25
37
24
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
INDEX
48
13
"A"
0˚~8˚
LEAD No.
0.50(.020)
1
(Mounting height)
.059 –.004
0.10±0.10
(.004±.004)
(Stand off)
12
0.20±0.05
(.008±.002)
0.08(.003)
0.25(.010)
M
0.60±0.15
(.024±.006)
©2003-2008
FUJITSU
LIMITED F48040S-c-2-3
C
2003 FUJITSU
LIMITEDMICROELECTRONICS
F48040S-c-2-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
50
DS07-13731-5E
MB90895 Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
⎯
⎯
Change Results
Added the following part numbers under development.
MB90F897Y, MB90F897YS
1
■ FEATURES
Added as follows.
• Models that support + 150 °C (MB90F897Y/YS)
8
■ PIN DESCRIPTION
Corrected the function of pin SCK0 on pin number 43.
UART1 → UART0
11
■ HANDLING DEVICES
Corrected the description for “• Handling Unused Pins”.
unused input pins → unused I/O pins
“• Support for + 125 °C” →
“• Support for + 125 °C / + 150 °C”
12
■ BLOCK DIAGRAM
13
23
Corrected the arrow for “pin X0 and X1” in the clock control
circuit.
“input → ”→ “input/output←→”
Corrected the arrow for “pin TIN0 and pin TIN1” in 16-bit
reload timer (2ch).
“output →” →“ input←”
■ INTERRUPT SOURCES, INTERRUPT Corrected footnotes in the address column for ICR05 and
VECTORS, AND INTERRUPT CONTROL ICR07 of the interrupt control register.
REGISTERS
0000B5H*2 → 0000B5H*1
10000B7H*1 → 0000B7H*2
Corrected the description for footnote *2.
16-bit reload timer → Input capture 1
24
■ PERIPHERAL RESOURCES
Deleted the section
Refer to the hardware manual, for details of peripheral resources.
25
■ FLASH MEMORY CONFIGURATION
Changed the item name from “PERIPHERAL RESOURCES” to “FLASH MEMORY CONFIGURATION”.
26
■ ELECTRIC CHARACTERISTICS
1. Absolute Maximum Rating
Item: Added the rating value for MB90F897Y/YS to the
operating temperature.
Min: − 40 °C, Max: + 150 °C
⎯
27
Added footnote*9.
2. Recommended Operating Conditions
28
Item: Added the rating value for MB90F897Y/YS to the
operating temperature.
Min: − 40 °C,Max: + 150 °C
Added footnote *3.
31, 32
3. DC Characteristics
Added DC characteristics for “MB90F897Y/YS”.
4. AC Characteristics
Changed the condition description in the upper right of the
table.
TA = − 40 °C to +125 °C →
TA = − 40 °C to +125 °C/ + 150 °C (Only MB90F897Y/YS)
33 to 40 5. A/D converter
49
■ ORDERING INFORMATION
Added the following part numbers.
MB90F897YPMT, MB90F897YSPMT
The vertical lines marked in the left side of the page show the changes.
DS07-13731-5E
51
MB90895 Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3329
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
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The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
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The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
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