ClockWorks™ SY10H641A ClockWorks™ SY100H641A SINGLE SUPPLY 1:9 PECL-TO-TTL SYNERGY SY10H641A SY100H641A SEMICONDUCTOR FEATURES DESCRIPTION ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Input frequencies up to 80MHz PECL-to-TTL version of popular ECLinPS E111 Guaranteed low skew specification Latched input Differential ECL internal design VBB output for single-ended operation Single +5V supply Reset/enable Extra TTL and ECL power/ground pins Choice of ECL compatibility: MECL 10KH (10Hxxx) or 100K (100Hxxx) ■ ESD protection of 2000V ■ Fully compatible with Motorola MC10H641/100H641 ■ Available in 28-pin PLCC package The SY10/100H641A are single supply, low skew translating 1:9 clock drivers. Devices in the Synergy H600 translator series utilize the 28-lead PLCC for optimal power pinning, signal flow-through and electrical performance. The devices feature a 24mA TTL output stage with AC performance specified into a 50pF load capacitance. A latch is provided on-chip. When LEN is LOW (or left open, in which case it is pulled LOW by the internal pulldowns), the latch is transparent. A HIGH on the enable pin (EN) forces all outputs LOW. The 10H version is compatible with MECL 10KH ECL logic levels. The 100H version is compatible with 100K levels. BLOCK DIAGRAM PIN CONFIGURATION Q8 GT Q7 VT Q0 Q6 VT GT TTL Outputs 25 24 23 22 21 20 19 GT Q5 VT Q4 VT Q3 GT Q1 Q2 26 18 27 17 28 16 TOP VIEW PLCC 1 15 2 14 3 13 4 12 5 6 7 8 9 VBB D D VE LEN GE EN 10 11 D D Q4 Q0 GT GT Q2 VT Q Q1 VT Q3 PECL Input PIN NAMES D VBB Pin Q5 Function LEN GT TTL Ground (0V) EN VT TTL VCC (+5.0V) VE ECL VCC (+5.0V) GE ECL Ground (0V) D, D Signal Input (PECL) VBB VBB Reference Output (PECL) Q0 - Q8 Signal Outputs (TTL) EN Enable Input (PECL) LEN Latch Enable Input (PECL) Q6 Q7 Q8 © 1999 Micrel-Synergy Rev.: D 5-356 Amendment: /0 Issue Date: February, 1999 ClockWorks™ SY10H641A SY100H641A SYNERGY SEMICONDUCTOR ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating TRUTH TABLE Value Unit D LEN EN Q L L L L H L L H X H L Q0 X X H L VE (ECL) VT (TTL) Power Supply Voltage –0.5 to +7.0 –0.5 to +7.0 V VI (ECL) Input Voltage 0.0 to VE V VOUT (TTL) Disabled 3-State Output 0.0 to VT V IOUT (ECL) Output Current - Continuous - Surge Tstore Storage Temperature TA Operating Temperature mA 50 100 –65 to +150 ˚C 0 to +85 ˚C NOTE: 1. Do not exceed. VCC AND CLOAD Ranges to meet duty cycle requirement: 0°C ≤ TA ≤ 85°C. Output duty cycle measured relative to 1.5V. Symbol Parameter Min. Typ. Max. Unit Condition PW1 Ranges of VCC and CL to meet min. pulse width (HIGH or LOW) at fOUT ≤ 40MHz VCC CL PW 4.75 10 11 5.0 — — 5.25 50 — V pF ns All Outputs PW2 Ranges of VCC and CL to meet min. pulse width (HIGH or LOW) at fOUT ≤ 50MHz VCC CL PW 4.875 15 9.0 5.0 — — 5.125 27 — V pF ns All Outputs DC ELECTRICAL CHARACTERISTICS VT = VE = 5.0V ± 5% TA = 0°C Symbol IEE Parameter Power Supply Current ICCH TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit ECL — 30 — 30 — 30 mA TTL — 30 — 30 — 30 — 37 — 37 — 37 ICCL Condition VE Pin Total all VT pins TTL DC ELECTRICAL CHARACTERISTICS VT = VE = 5.0V ± 5% TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit Condition VOH Output HIGH Voltage 2.5 — 2.5 — 2.5 — V IOH = –15mA VOL Output LOW Voltage — 0.5 — 0.5 — 0.5 V IOL = 24mA IOS Output Short Circuit Current –100 –225 –100 –225 –100 –225 mA VOUT = 0V 5-357 ClockWorks™ SY10H641A SY100H641A SYNERGY SEMICONDUCTOR 10H ECL DC ELECTRICAL CHARACTERISTICS VT = VE = 5.0V ± 5% TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit Condition IIH Input HIGH Current — 225 — 175 — 175 µA — IIL Input LOW Current 0.5 — 0.5 — 0.5 — µA — VIH Input HIGH Voltage(1) 3.830 4.160 3.870 4.190 3.940 4.280 V VE = 5.0V VIL Input LOW Voltage(1) 3.050 3.520 3.050 3.520 3.050 3.555 V VE = 5.0V 3.620 3.730 3.650 3.750 3.690 3.810 V VE = 5.0V VBB Output Reference Voltage(1) NOTE: 1. VIH, VIL and VBB are referenced to VE and will vary 1:1 with the power supply. The levels shown are for VE = +5.0V. 100H ECL DC ELECTRICAL CHARACTERISTICS VT = VE = 5.0V ± 5% TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit Condition — 225 — 175 — 175 µA — IIH Input HIGH Current IIL Input LOW Current 0.5 — 0.5 — 0.5 — µA — VIH Input HIGH Voltage(1) 3.835 4.120 3.835 4.120 3.835 4.120 V VE = 5.0V VIL Input LOW Voltage(1) 3.190 3.525 3.190 3.525 3.190 3.525 V VE = 5.0V 3.620 3.740 3.620 3.740 3.620 3.740 V VE = 5.0V Max. Unit Condition VBB Output Reference Voltage(1) NOTE: 1. VIH, VIL and VBB are referenced to VE and will vary 1:1 with the power supply. The levels shown are for VE = +5.0V. AC ELECTRICAL CHARACTERISTICS VT = VE = 5.0V ± 5% TA = 0°C Symbol Parameter Min. TA = +25°C Max. Min. TA = +85°C Max. Min. tPLH tPHL Propagation Delay D to Output 5.0 6.0 5.0 6.0 5.0 6.0 ns CL = 50pF tskpp Part-to-Part Skew(1,4) — 0.5 — 0.5 — 0.5 ns CL = 50pF Within-Device Skew(2,4) — 0.3 — 0.3 — 0.3 ns CL = 50pF tskew– – Within-Device Skew(3,4) — 0.3 — 0.3 — 0.3 ns CL = 50pF tPLH tPHL Propagation Delay LEN to Output 4.9 6.9 4.9 6.9 5.0 7.0 ns CL = 50pF tPLH tPHL Propagation Delay EN to Output 5.0 7.0 4.9 6.9 5.0 7.0 ns CL = 50pF tr tf Output Rise/Fall Time 0.8V to 2.0V — — 1.7 1.6 — — 1.7 1.6 — — 1.7 1.6 ns CL = 50pF fMAX Maximum Input Frequency(5,6) 80 — 80 — 80 — MHz CL = 50pF — Pulse Width 1.5 — 1.5 — 1.5 — ns — — Recovery Time 1.25 — 1.25 — 1.25 — ns — tS Set-up Time 0.5 (typ.) 0.5 (typ.) 0.5 (typ.) ns — tH Hold Time 0.5 (typ.) 0.5 (typ.) 0.5 (typ.) ns — tskew++ NOTES: 1. Device-to-Device Skew considering HIGH-to-HIGH transitions at common power supply voltage. 2. Within-Device Skew considering HIGH-to-HIGH transitions at common power supply voltage. 3. Within-Device Skew considering LOW-to-LOW transitions at common power supply voltage. 4. All skew parameters are guaranteed but not tested. 5. Frequency at which output levels will meet a 0.8V to 2.0V minimum swing. 6. The fMAX value is specified as the minimum guaranteed maximum frequency. Actual operational maximum frequency may be greater. 5-358 ClockWorks™ SY10H641A SY100H641A SYNERGY SEMICONDUCTOR TTL SWITCHING CIRCUIT VE VT USE 0.1µF CAPACITORS FOR DECOUPLING. TTL PECL 50 COAX IN PULSE GENERATOR 50 USE OSCILLOSCOPE INTERNAL 50 LOAD FOR TERMINATION. COAX DEVICE UNDER TEST 50 OUT 450 COAX CH A CH B OSCILLOSCOPE ECL/TTL PROPAGATION DELAY — SINGLE ENDED 50% VIN Tpd++ Tpd– – 1.5V VOUT ECL/TTL WAVEFORMS: RISE AND FALL TIMES 2.0V 0.8V VOUT Trise Tfall LOGIC DIAGRAM PRODUCT ORDERING CODE Ordering Code 5-359 Package Type Operating Range SY10H641AJC J28-1 Commercial SY10H641AJCTR J28-1 Commercial SY100H641AJC J28-1 Commercial SY100H641AJCTR J28-1 Commercial ClockWorks™ SY10H641A SY100H641A SYNERGY SEMICONDUCTOR 28 LEAD PLASTIC LEADED CHIP CARRIER (J28-1) 5-360