ONSEMI MC100H641

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Single Supply PECL-TTL
1:9 Clock Distribution Chip
MC10H641
MC100H641
The MC10H/100H641 is a single supply, low skew translating 1:9 clock
driver. Devices in the Motorola H600 translator series utilize the 28–lead
PLCC for optimal power pinning, signal flow through and electrical
performance.
SINGLE SUPPLY
PECL–TTL 1:9 CLOCK
DISTRIBUTION CHIP
The device features a 24mA TTL output stage, with AC performance
specified into a 50pF load capacitance. A latch is provided on–chip. When
LEN is LOW (or left open, in which case it is pulled LOW by the internal
pulldown) the latch is transparent. A HIGH on the enable pin (EN) forces
all outputs LOW. Both the LEN and EN pins are positive ECL inputs.
The VBB output is provided in case the user wants to drive the device
with a single–ended input. For single–ended use the VBB should be
connected to the D input and bypassed with a 0.01µF capacitor.
The 10H version of the H641 is compatible with positive MECL 10H
logic levels. The 100H version is compatible with positive 100K levels.
•
•
•
•
•
•
•
•
•
•
PECL–TTL Version of Popular ECLinPS E111
Low Skew
Guaranteed Skew Spec
Latched Input
Differential ECL Internal Design
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
VBB Output for Single–Ended Use
Single +5V Supply
Logic Enable
Extra Power and Ground Supplies
Separate ECL and TTL Supply Pins
Pinout: 28–Lead PLCC (Top View)
GT
Q6
VT
Q7
VT
Q8
GT
25
24
23
22
21
20
19
PIN NAMES
GT
26
18
VBB
Q5
27
17
D
VT
28
16
D
Q4
1
15
VE
VT
2
14
LEN
Q3
3
13
GE
GT
4
12
EN
5
6
7
8
9
10
11
GT
Q2
VT
Q1
VT
Q0
GT
Pins
Function
GT, VT
GE, VE
D, D
VBB
TTL GND, TTL VCC
ECL GND, ECL VCC
Signal Input (Positive ECL)
VBB Reference Output
(Positive ECL)
Signal Outputs (TTL)
Enable Input (Positive ECL)
Latch Enable Input
(Positive ECL)
Q0–Q8
EN
LEN
MECL 10H is a trademark of Motorola, Inc.
11/93
 Motorola, Inc. 1996
2–1
REV 3
MC10H641 MC100H641
LOGIC DIAGRAM
TTL Outputs
Q0
Q1
Q2
Q3
PECL Input
D
D Q
Q4
D
VBB
Q5
LEN
EN
Q6
Q7
Q8
DC CHARACTERISTICS (VT = VE = 5.0V ±5%)
Symbol
Characteristic
Min
TA = 0°C
Typ
Max
Min
TA = + 25°C
Typ
Max
Min
TA = + 85°C
Typ
Max
Unit
IEE
Power Supply Current
PECL
24
30
24
30
24
30
mA
ICCH
TTL
24
30
24
30
24
30
mA
27
35
27
35
27
35
mA
Max
Unit
ICCL
Condition
TTL DC CHARACTERISTICS (VT = VE = 5.0V ±5%)
0°C
Symbol
Characteristic
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IOS
Output Short Circuit Current
Min
25°C
Max
Min
2.5
85°C
Max
2.5
2.5
0.5
–100
Min
0.5
–225
–100
Max
Min
–225
–100
Max
Min
Condition
V
IOH = –15mA
0.5
V
IOL = 24mA
–225
mA
VOUT = 0V
Max
Unit
175
µA
10H PECL DC CHARACTERISTICS
0°C
Symbol
Characteristic
Min
25°C
225
85°C
175
Condition
IIH
Input HIGH Current
IIL
Input LOW Current
0.5
VIH
Input HIGH Voltage
3.83
4.16
3.87
4.19
3.94
4.28
V
VE = 5.0V1
VIL
Input LOW Voltage
3.05
3.52
3.05
3.52
3.05
3.55
V
VE = 5.0V1
0.5
µA
0.5
VBB
Output Reference Voltage
3.62
3.73
3.65
3.75
3.69
3.81
V
VE = 5.0V1
1. PECL VIH, VIL, and VBB are referenced to VE and will vary 1:1 with the power supply. The levels shown are for VE = 5.0V.
MOTOROLA
2–2
MECL Data
DL122 — Rev 6
MC10H641 MC100H641
100H PECL DC CHARACTERISTICS
0°C
Symbol
Characteristic
Min
25°C
Max
Min
85°C
Max
225
Min
175
Max
Unit
175
µA
Condition
IIH
Input HIGH Curren
IIL
Input LOW Current
0.5
VIH
Input HIGH Voltage
3.835
4.120
3.835
4.120
3.835
4.120
V
VE = 5.0V1
VIL
Input LOW Voltage
3.190
3.525
3.190
3.525
3.190
3.525
V
VE = 5.0V1
VBB
Output Reference Voltage
3.62
3.74
3.62
3.74
3.62
3.74
V
VE = 5.0V1
0.5
µA
0.5
1. PECL VIH, VIL, and VBB are referenced to VE and will vary 1:1 with the power supply. The levels shown are for VE = 5.0V.
AC CHARACTERISTICS (VT = VE = 5.0V ±5%)
Symbol
1.
2.
3.
4.
5.
Characteristic
TJ = 0°C
Min
Typ
Max
TJ = + 25°C
Min
Typ
Max
TJ = + 85°C
Min
Typ
Max
5.00
5.36
4.86
5.27
5.08
5.43
5.50
5.86
6.00
6.36
5.36
5.77
5.86
6.27
5.58
5.93
6.08
6.43
Unit
ns
Condition
CL = 50 pF1
tPLH
tPHL
Propagation Delay
D to Q
tskew
Device Skew
Part–to–Part
Single VCC
Output–to–Output
tPLH
tPHL
Propagation Delay
LEN to Q
4.9
6.9
4.9
6.9
5.0
7.0
ns
CL = 50 pF
tPLH
tPHL
Propagation Delay
EN to Q
5.0
7.0
4.9
6.9
5.0
7.0
ns
CL = 50 pF
tr
tf
Output Rise/Fall
0.8V to 2.0V
1.7
1.6
ns
CL = 50 pF
fMAX
Max Input Frequency
CL = 50 pF5
tREC
ps
1000
750
350
1000
750
350
1.7
1.6
1000
750
350
1.7
1.6
65
65
65
MHz
Recovery Time EN
1.25
1.25
1.25
ns
tS
Setup Time
0.75
0.50
0.75
0.50
0.75
0.50
ns
tH
Hold Time
0.75
0.50
0.75
0.50
0.75
0.50
ns
CL = 50pF2
CL = 50 pF3
CL = 50 pF4
Propagation delay measurement guaranteed for junction temperatures. Measurements performed at 50MHz input frequency.
Skew window guaranteed for a single temperature across a VCC = VT = VE of 4.75V to 5.25V (See Application Note in this datasheet).
Skew window guaranteed for a single temperature and single VCC = VT = VE
Output–to–output skew is specified for identical transitions through the device.
Frequency at which output levels will meet a 0.8V to 2.0V minimum swing.
DETERMINING SKEW FOR A SPECIFIC APPLICATION
The H641 has been designed to meet the needs of very low
skew clock distribution applications. In order to optimize the
device for this application special considerations are
necessary in the determining of the part–to–part skew
specification limits. Older standard logic devices are specified
with relatively slack limits so that the device can be
guaranteed over a wide range of potential environmental
conditions. This range of conditions represented all of the
potential applications in which the device could be used. The
result was a specification limit that in the vast majority of cases
was extremely conservative and thus did not allow for an
optimum system design. For non–critical skew designs this
practice is acceptable, however as the clock speeds of
MECL Data
DL122 — Rev 6
systems increase overly conservative specification limits can
kill a design.
The following will discuss how users can use the
information provided in this data sheet to tailor a part–to–part
skew specification limit to their application. The skew
determination process may appear somewhat tedious and
time consuming, however if the utmost in performance is
required this procedure is necessary. For applications which
do not require this level of skew performance a generic
part–to–part skew limit of 2.5ns can be used. This limit is good
for the entire ambient temperature range, the guaranteed VCC
(VT, VE) range and the guaranteed operating frequency range.
2–3
MOTOROLA
MC10H641 MC100H641
Figure 2 illustrates the thermal resistance (in °C/W) for the
28–lead PLCC under various air flow conditions. By reading
the thermal resistance from the graph and multiplying by the
power dissipation calculated above the junction temperature
increase above ambient of the device can be calculated.
Temperature Dependence
A unique characteristic of the H641 data sheet is that the
AC parameters are specified for a junction temperature rather
than the usual ambient temperature. Because very few
designs will actually utilize the entire commercial temperature
range of a device a tighter propagation delay window can be
established given the smaller temperature range. Because
the junction temperature and not the ambient temperature is
what affects the performance of the device the parameter
limits are specified for junction temperature. In addition the
relationship between the ambient and junction temperature
will vary depending on the frequency, load and board
environment of the application. Since these factors are all
under the control of the user it is impossible to provide
specification limits for every possible application. Therefore a
baseline specification was established for specific junction
temperatures and the information that follows will allow these
to be tailored to specific applications.
THERMAL RESISTANCE (°C/W)
70
Since the junction temperature of a device is difficult to
measure directly, the first requirement is to be able to
“translate” from ambient to junction temperatures. The
standard method of doing this is to use the power dissipation
of the device and the thermal resistance of the package. For
a TTL output device the power dissipation will be a function of
the load capacitance and the frequency of the output. The total
power dissipation of a device can be described by the
following equation:
60
50
40
30
0
200
400
600
Finally taking this value for junction temperature and
applying it to Figure 3 allows the user to determine the
propagation delay for the device in question. A more common
use would be to establish an ambient temperature range for
the H641’s in the system and utilize the above methodology
to determine the potential increased skew of the distribution
network. Note that for this information if the TPD versus
Temperature curve were linear the calculations would not be
required. If the curve were linear over all temperatures a
simple temperature coefficient could be provided.
where:
VS= Output Voltage Swing = 3V
f = Output Frequency
CL = Load Capacitance
ICC = IEE + ICCH
Figure 1 plots the ICC versus Frequency of the H641 with
no load capacitance on the output. Using this graph and the
information specific to the application a user can determine
the power dissipation of the H641.
6.4
5
6.2
PROPAGATION DELAY (ns)
4
NORMALIZED ICC
1000
Figure 2. ∅JA versus Air Flow
PD (watts) = ICC (no load) * VCC +
VS * VCC * f * CL * # Outputs
3
2
1
0
800
AIRFLOW (LFPM)
TPHL
6.0
5.8
TPLH
5.6
5.4
5.2
0
10
20
30
40
50
60
70
80
–10
10
30
50
70
90
110
130
JUNCTION TEMPERATURE (°C)
FREQUENCY (MHz)
Figure 3. TPD versus Junction Temperature
Figure 1. ICC versus f (No Load)
MOTOROLA
–30
2–4
MECL Data
DL122 — Rev 6
MC10H641 MC100H641
VCC Dependence
1.15
MORMALIZED PROPAGATION DELAY (ns)
TTL and CMOS devices show a significant propagation
delay dependence with VCC. Therefore the VCC variation in a
system will have a direct impact on the total skew of the clock
distribution network. When calculating the skew between two
devices on a single board it is very likely an assumption of
identical VCC’s can be made. In this case the number provided
in the data sheet for part–to–part skew would be overly
conservative. By using Figure 4 the skew given in the data
sheet can be reduced to represent a smaller or zero variation
in VCC. The delay variation due to the specified VCC variation
is ≈270ps. Therefore, the 1ns window on the data sheet can
be reduced by 270ps if the devices in question will always
experience the same VCC. The distribution of the propagation
delay ranges given in the data sheet is actually a composite
of three distributions whose means are separated by the fixed
difference in propagation delay at the typical, minimum and
maximum VCC.
1.10
1.05
TPLH
1.00
MEASURED
0.95
0.90
TPHL
0.85
0.80
0.75
THEORETICAL
0
10
20
30
40
50
60
70
80
90
100
CAPACITIVE LOAD (pF)
Figure 5. TPD versus Load
140
Rise/Fall Skew Determination
The rise–to–fall skew is defined as simply the difference
between the TPLH and the TPHL propagation delays. This
skew for the H641 is dependent on the VCC applied to the
device. Notice from Figure 4 the opposite relationship of TPD
versus VCC between TPLH and TPHL. Because of this the
rise–to–fall skew will vary depending on VCC. Since in all
likelihood it will be impossible to establish the exact value for
VCC, the expected variation range for VCC should be used. If
this variation will be the ±5% shown in the data sheet the
rise–to–fall skew could be established by simply subtracting
the fastest TPLH from the slowest TPHL; this exercise yields
1.41ns. If a tighter VCC range can be realized Figure 4 can be
used to establish the rise–to–fall skew.
100
∆ TPD (ps)
60
20
–20
–60
TPLH
TPHL
–100
–140
4.75
4.85
4.95
5.05
5.15
Specification Limit Determination Example
The situation pictured in Figure 6 will be analyzed as an
example. The central clock is distributed to two different cards;
on one card a single H641 is used to distribute the clock while
on the second card two H641’s are required to supply the
needed clocks. The data sheet as well as the graphical
information of this section will be used to calculate the skew
between H641a and H641b as well as the skew between all
three of the devices. Only the TPLH will be analyzed, the TPHL
numbers can be found using the same technique. The
following assumptions will be used:
5.25
VCC (V)
Figure 4. ∆TPD versus VCC
Capacitive Load Dependence
–
–
–
–
All outputs will be loaded with 50pF
All outputs will toggle at 30MHz
The VCC variation between the two boards is ±3%
The temperature variation between the three
devices is ±15°C around an ambient of 45°C.
– 500LFPM air flow
As with VCC the propagation delay of a TTL output is
intimately tied to variation in the load capacitance. The skew
specifications given in the data sheet, of course, assume
equal loading on all of the outputs. However situations could
arise where this is an impossibility and it may be necessary to
estimate the skew added by asymmetric loading. In addition
the propagation delay numbers are provided only for 50pF
loads, thus necessitating a method of determining the
propagation delay for alternative loads.
The first task is to calculate the junction temperature for the
devices under these conditions. Using the power equation
yields:
Figure 5 shows the relationship between the two
propagation delays with respect to the capacitive load on the
output. Utilizing this graph and the 50pF limits the specification
of the H641 can be mapped into a spec for either a different
value load or asymmetric loads.
MECL Data
DL122 — Rev 6
PD = ICC (no load) * VCC +
VCC * VS * f * CL * # outputs
= 1.8 * 48mA * 5V + 5V * 3V * 30MHz *
50pF * 9
= 432mW + 203mW = 635mW
2–5
MOTOROLA
MC10H641 MC100H641
Using the thermal resistance graph of Figure 2 yields a
thermal resistance of 41°C/W which yields a junction
temperature of 71°C with a range of 56°C to 86°C. Using the
TPD versus Temperature curve of Figure 3 yields a
propagation delay of 5.42ns and a variation of 0.19ns.
the conservative worst case limits provided at the beginning
of this note. For very high performance designs, this extra
information and effort can mean the difference between going
ahead with prototypes or spending valuable engineering time
searching for alternative approaches.
Since the design will not experience the full ±5% VCC
variation of the data sheet the 1ns window provided will be
unnecessarily conservative. Using the curve of Figure 4
shows a delay variation due to a ±3% VCC variation of
±0.075ns. Therefore the 1ns window can be reduced to
1ns – (0.27ns – 0.15ns) = 0.88ns. Since H641a and H641b
are on the same board we will assume that they will always be
at the same VCC; therefore the propagation delay window will
only be 1ns – 0.27ns = 0.73ns.
Card 1
H641a
Q0
ECL
TTL
Q8
Putting all of this information together leads to a skew
between all devices of
H641b
Q0
0.19ns + 0.88ns
(temperature + supply, and inherent device),
BACKPLANE
ECL
while the skew between devices A and B will be only
0.19ns + 0.73ns
(temperature + inherent device only).
TTL
Q8
Card 2
In both cases, the propagation delays will be centered
around 5.42ns, resulting in the following tPLH windows:
H641c
Q0
TPLH = 4.92ns – 5.99ns; 1.07ns window
(all devices)
TPLH = 5.00ns – 5.92ns; 0.92ns window
(devices a & b)
ECL
TTL
Q8
Of course the output–to–output skew will be as shown in
the data sheet since all outputs are equally loaded.
Figure 6. Example Application
This process may seem cumbersome, however the delay
windows, and thus skew, obtained are significantly better than
MOTOROLA
2–6
MECL Data
DL122 — Rev 6
MC10H641 MC100H641
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776–02
ISSUE D
0.007 (0.180)
B
T L–M
M
N
S
T L–M
S
S
Y BRK
–N–
0.007 (0.180)
U
M
N
S
D
Z
–M–
–L–
W
28
D
X
G1
0.010 (0.250)
T L–M
S
N
S
S
V
1
VIEW D–D
A
0.007 (0.180)
R
0.007 (0.180)
M
T L–M
S
N
S
C
M
T L–M
S
N
0.007 (0.180)
H
Z
M
T L–M
N
S
S
S
K1
E
0.004 (0.100)
G
J
S
K
SEATING
PLANE
F
VIEW S
G1
0.010 (0.250)
–T–
T L–M
S
N
S
M
T L–M
S
N
S
VIEW S
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
MECL Data
DL122 — Rev 6
0.007 (0.180)
2–7
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
–––
0.025
–––
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
–––
0.020
2_
10_
0.410
0.430
0.040
–––
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
–––
0.64
–––
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
–––
0.50
2_
10_
10.42
10.92
1.02
–––
MOTOROLA
MC10H641 MC100H641
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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◊
MOTOROLA
2–8
*MC10H641/D*
MC10H641/D
MECL Data
DL122 — Rev 6