MICREL SY89546UMG

Precision Edge®
SY89546U
®
2.5V, 3.2Gbps DIFFERENTIAL 4:1 LVDS
MULTIPLEXER WITH 1:2 FANOUT
AND INTERNAL TERMINATION
Micrel, Inc.
Precision Edge
SY89546U
FEATURES
■ Selects among four differential inputs
■ Provides two copies of the selected input
■ Guaranteed AC performance over temp and voltage:
• DC-to > 3.2Gbps data rate throughput
• < 620ps In-to-Out tpd
• < 150ps tr/tf
■ Unique input isolation design minimizes crosstalk
■ Ultra-low jitter design:
• < 1psRMS random jitter
• < 10psPP deterministic jitter
• < 10psPP total jitter (clock)
• < 0.7psRMS crosstalk-induced jitter
■ Internal input termination
■ Unique input termination and VT pin accepts DCcoupled and AC-coupled inputs (LVDS, LVPECL,
CML)
■ 350mV LVDS output swing
■ Power supply 2.5V ±5%
■ –40°C to +85°C temperature range
■ Available in 32-pin (5mm x 5mm) MLF® package
Precision Edge®
DESCRIPTION
The SY89546U is a precision, high-speed 4:1 differential
multiplexer that provides two copies of the selected input.
The high speed LVDS (350mV) compatible outputs with a
guaranteed throughput of up to 3.2Gbps over temperature
and voltage.
The SY89546U differential inputs include Micrel’s unique,
3-pin internal termination design that allows access to the
termination network through a VT pin. This feature allows
the device to easily interface to different logic standards,
both AC- and DC-coupled without external resistor-bias and
termination networks. The result is a clean, stub-free, low
jitter interface solution.
The SY89546U operates from a single 2.5V supply, and
is guaranteed over the full industrial temperature range
(–40°C to +85°C). For applications that require a 3.3V supply,
consider the SY89547L. Or, for applications that only require
one differential output, consider the SY89544U or SY89545L.
The SY89546U is part of Micrel’s Precision Edge® product
family.
All support documentation can be found on Micrel’s web
site at www.micrel.com.
APPLICATIONS
■ SONET/SDH multi-channel select applications
■ Fibre Channel applications
■ GigE applications
FUNCTIONAL BLOCK DIAGRAM
IN0
50Ω
VT0
50Ω
4:1 MUX
/IN0
TYPICAL PERFORMANCE
1:2 Fanout
0
IN1
OUTPUT AMPLITUDE (mV)
400
50Ω
VT1
50Ω
Output Amplitude
vs. Frequency
Q0
/Q0
1
/IN1
350
MUX
300
2
IN2
250
50Ω
200
VT2
50Ω
150
/IN2
50
Q1
/Q1
S1
3 S0
100
0
0
LVDS
IN3
50Ω
VT3
50Ω
1000 2000 3000 4000 5000 6000
FREQUENCY (MHz)
/IN3
SEL0 (CMOS/TTL)
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
M9999-060308
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SEL1 (CMOS/TTL)
Rev.: D
1
Amendment: /0
Issue Date: June 2008
Precision Edge®
SY89546U
Micrel, Inc.
PACKAGE/ORDERING INFORMATION
IN1
VT1
/IN1
VCC
VCC
IN2
VT2
/IN2
Ordering Information(1)
Part Number
Package
Type
Operating
Range
Package
Marking
Lead
Finish
SY89546UMI
MLF-32
Industrial
SY89546U
Sn-Pb
SY89546UMITR(2)
MLF-32
Industrial
SY89546U
Sn-Pb
SY89546UMG(3)
MLF-32
Industrial
SY89546U with
Pb-Free bar-line indicator
Pb-Free
NiPdAu
SY89546UMGTR(2, 3)
MLF-32
Industrial
SY89546U with
Pb-Free bar-line indicator
Pb-Free
NiPdAu
32 31 30 29 28 27 26 25
VCC
/IN0
VT0
IN0
VCC
SEL0
GND
VCC
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
VCC
IN3
VT3
/IN3
VCC
SEL1
GND
VCC
GND
Q
/Q
GND
GND
NC
NC
GND
9 10 11 12 13 14 15 16
32-Pin
MLF®
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only.
2. Tape and Reel.
3. Recommended for new designs.
PIN DESCRIPTION
Pin Number
Pin Name
Pin Function
4, 2, 32,
30, 27, 25, 23, 21
IN0, /IN0,
IN1, /IN1,
IN2, /IN2,
IN3, /IN3
Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs
accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally
terminates to a VT pin through 50Ω. Note that these inputs will default to an indeterminate
state if left open. Unused differential input pairs can be terminated by connecting one input
to VCC and the complementary input to GND through a 1kΩ resistor. The VT pin is to be
left open in this configuration. Please refer to the “Input Interface Applications” section for
more details.
3, 31, 26, 22
VT0, VT1,
VT2, VT3
Input Termination Center-Tap: Each side of the differential input pair, terminates to a VT
pin. The VTA0, VTA1, VTB0, VTB1 pins provide a center-tap to a termination network for
maximum interface flexibility. See “Input Interface Applications” section for more details.
6, 19
SEL0, SEL1
These single-ended TTL/CMOS-compatible inputs select the inputs to the multiplexers.
Note that these inputs are internally connected to a 25kΩ pull-up resistor and will default
to a logic HIGH state if left open. Input switching threshold is VCC/2.
1, 5, 8,
17, 20, 24, 28, 29
VCC
10, 11, 14, 15
Q0, /Q0,
Q1, /Q1
7, 9, 12, 13, 16, 18
GND,
Exposed pad
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Positive Power Supply: Bypass with 0.1µF0.01µF low ESR capacitors.
Differential Outputs: These LVDS output pairs are the outputs of the device. They are a
logic function of the INA0, INA1, INB0, INB1 and SELA and SELB inputs. Please refer to
the “Truth Table’” for details. If an output is not used, it must be terminated with 100Ω
across the differential pair.
Ground: Ground pin and exposed pad must be connected to the same ground plane.
2
Precision Edge®
SY89546U
Micrel, Inc.
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VCC) ............................... – 0.5V to + 4.0V
Input Voltage (VIN) ........................................ –0.5V to VCC
Termination Current(3)
Source or sink current on VT ..................................... ±100mA
Input Current
Source or sink current on IN, /IN .......................... ±50mA
Lead Temperature (soldering, 20 sec.) ................... +260°C
Storage Temperature (TS) ...................... –65°C to +150°C
Supply Voltage (VCC) ............................. 2.375V to 2.625V
Ambient Temperature (TA) ........................ –40°C to +85°C
Package Thermal Resistance(4)
MLF® (θJA)
Still-Air ................................................................ 35°C/W
500lfpm .............................................................. 28°C/W
MLF® (ΨJB)
Junction-to-Board ............................................... 20°C/W
DC ELECTRICAL CHARACTERISTICS(5)
TA = –40°C to +85°C; Unless otherwise stated.
Symbol
Parameter
VCC
Power Supply
Condition
Typ
Max
Units
2.375
2.5
2.625
V
75
100
mA
(6)
ICC
Power Supply Current
RDIFF_IN
Differential Input Resistance
(IN-to-/IN)
80
100
120
Ω
RIN
Input Resistance
(IN-to-VT, /IN-to-VT)
40
50
60
Ω
VIH
Input High Voltage
(IN, /IN)
1.2
VCC
V
VIL
Input Low Voltage
(IN, /IN)
0
VIH–0.1
V
VIN
Input Voltage Swing
(IN, /IN)
Note 7
0.1
VCC
V
VDIFF_IN
Differential Input Voltage Swing
|IN – /IN|
Note 7
0.2
IN-to-VT
No Load, Max. VCC
Min
Note 7
V
1.8
V
Notes:
1. Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to “Absolute Maximum Ratings” conditions for
extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability use for input of the same package only.
4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential (GND) on the PCB. ΨJB uses
4-layer θJA in still-air unless otherwise stated.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. Includes current through internal 50Ω pull-ups.
7. See “Single-Ended and Differential Swings” section for VIN and VDIFF_IN definition.
M9999-060308
[email protected] or (408) 955-1690
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Precision Edge®
SY89546U
Micrel, Inc.
LVDS OUTPUTS DC ELECTRICAL CHARACTERISTICS(9)
VCC = 2.5V ±5%; TA = –40°C to +85°C; RL = 100Ω across Q and /Q, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
VOH
Output HIGH Voltage
(Q, /Q)
See Figure 5a
1.475
V
VOL
Output LOW Voltage
(Q, /Q)
See Figure 5a
VOUT
Output Voltage Swing
(Q, /Q)
See Figures 1a, 5a
250
350
mV
VDIFF-OUT
Differential Output Voltage Swing
|Q – /Q|
See Figure 1b
500
700
mV
VOCM
Output Common Mode Voltage
(Q, /Q)
See Figure 5b
1.125
1.275
V
∆VOCM
Change in Common Mode Voltage
(Q, /Q)
See Figure 5b
–50
+50
mV
Max
Units
VCC
V
0.925
V
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(9)
VCC = 2.5V ±5%; TA = –40°C to +85°C; unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
IIH
Input HIGH Current
40
µA
IIL
Input LOW Current
–300
µA
2.0
Note:
9. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
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Precision Edge®
SY89546U
Micrel, Inc.
AC ELECTRICAL CHARACTERISTICS(10)
VCC = 2.5V ±5%; TA = –40°C to +85°C; RL = 100Ω across Q and /Q, unless otherwise stated.
Symbol
Parameter
Condition
fMAX
Maximum Operating Frequency
Min
NRZ Data
VOUT ≥ 200mV
tpd
Differential Propagation Delay
tSKEW
tJITTER
Data
Clock
Typ
Max
3.2
Clock
Units
Gbps
4
GHz
IN-to-Q
330
430
530
ps
SEL-to-Q
200
400
700
ps
Input-to-Input Skew
Note 11
4
20
ps
Output-to-Output Skew
Note 12
8
20
ps
Part-to-Part Skew
Note 13
200
ps
Random Jitter (RJ)
Note 14
1
psRMS
Deterministic Jitter (DJ)
Note 15
10
psPP
Total Jitter (TJ)
Note 16
10
psPP
Cycle-to-Cycle Jitter
Note 17
1
psRMS
0.7
psRMS
150
ps
Crosstalk
Crosstalk-Induced Jitter
Note 18
tr, tf
Output Rise / Fall Time
(20% to 80%)
At full output swing
35
80
Notes:
10. Measured with 100mV input swing. See “Timing Diagrams” section for definition of parameters. High frequency AC parameters are guaranteed by
design and characterization.
11. Input-to-input skew is the difference in time from an input-to-output in comparison to any other input-to-output. In addition, the input-to-input skew
does not include the output skew.
12. Output-to-output skew is measured between two different outputs under identical input transitions.
13. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs. Total skew is calculated as the RMS (Root Mean Square) of the input skew and output skew.
14. Random jitter is measured with a K28.7 comma detect character pattern, measured at 1.25Gbps and 3.2Gbps.
15. Deterministic jitter is measured at 1.25Gbps and 3.2Gbps, with both K28.5 and 223–1 PRBS pattern.
16. Total jitter definition: with an ideal clock input of frequency ≤ fMAX, no more than one output edge in 1012 output edges will deviate by more than the
specified peak-to-peak jitter value.
17. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn-Tn-1 where T is the time between rising edges of the output
signal.
18. Crosstalk is measured at the output while applying two similar clock frequencies to adjacent inputs that are asynchronous with respect to each other
at the inputs.
M9999-060308
[email protected] or (408) 955-1690
5
Precision Edge®
SY89546U
Micrel, Inc.
SINGLE-ENDED AND DIFFERENTIAL SWINGS
VDIFF_IN,
VDIFF_OUT 700mV (Typ.)
VIN,
VOUT 350mV (Typ.)
Figure 1a. Single-Ended Voltage Swing
Figure 1b. Differential Voltage Swing
TIMING DIAGRAM
IN
/IN
tpd
Q
/Q
SEL
SEL-to-Q
tpd
Q
/Q
Figure 2. Timing Diagram
TRUTH TABLE
IN0
IN1
IN2
IN3
SEL0
SEL1
Q
/Q
0
X
X
X
0
0
0
1
1
X
X
X
0
0
1
0
X
0
X
X
1
0
0
1
X
1
X
X
1
0
1
0
X
X
0
X
0
1
0
1
X
X
1
X
0
1
1
0
X
X
X
0
1
1
0
1
X
X
X
1
1
1
1
0
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Precision Edge®
SY89546U
Micrel, Inc.
FUNCTIONAL CHARACTERISTICS
VCC = 2.5V, GND = 0V, VIN = 100mV, TA = 25°C.
2.5GHz Output
200MHz Output
Q
Output Swing
(70mV/div.)
Output Swing
(70mV/div.)
Q
/Q
/Q
TIME (50ps/div.)
OC-12 Mask (223–1 PRBS)
1xFC Mask (223-1 PRBS)
Output Swing
(70mV/div.)
Output Swing
(70mV/div.)
TIME (600ps/div.)
TIME (200ps/div.)
1xGBE Mask (223-1 PRBS)
2xFC Mask (223-1 PRBS)
Output Swing
(70mV/div.)
Output Swing
(70mV/div.)
TIME (300ps/div.)
TIME (100ps/div.)
2xGBE Mask (223–1 PRBS)
3.2Gbps Eye (223–1 PRBS)
Output Swing
(70mV/div.)
Output Swing
(70mV/div.)
TIME (150ps/div.)
TIME (70ps/div.)
TIME (70ps/div.)
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Precision Edge®
SY89546U
Micrel, Inc.
INPUT AND OUTPUT STAGE INTERNAL TERMINATION
VCC
IN
50Ω
VT
GND
50Ω
/IN
Figure 3. Simplified Differential Input Stage
INPUT INTERFACE APPLICATIONS
VCC
VCC
VCC
IN
LVPECL
IN
/IN
CML
IN
VCC
/IN
CML
/IN
SY89546U
SY89546U
GND
VCC – 1.4V
GND
VT
Rp
VT
NC
VT
For VCC = 2.5V, Rp = 19Ω
GND
Figure 4a. CML
Interface (DC-Coupled)
Figure 4b. CML
Interface (AC-Coupled)
VCC
VCC
IN
LVPECL
IN
/IN
Rp
Rp
GND
GND
SY89546U
0.01µF
SY89546U
LVDS
/IN
VCC –1.4V
SY89546U
VT
GND
GND
GND
NC
VT
For VCC = 2.5V, Rp = 50Ω
Figure 4d. LVPECL
Interface (AC-Coupled)
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Figure 4e. LVDS Interface
8
Figure 4c. LVPECL
Interface (DC-Coupled)
Precision Edge®
SY89546U
Micrel, Inc.
OUTPUT INTERFACE APPLICATIONS
ground between an LVDS driver and receiver. Also, change
in common mode voltage, as a function of data input, is
kept to a minimum, to keep EMI low.
LVDS specifies a small swing of 350mV typical, on a
nominal 1.25V common mode above ground. The common
mode voltage has tight limits to permit large variations in
509
VOUT
VOH, VOL
100Ω
509
VOH, VOL
VOCM,
,VOCM
GND
GND
Figure 5a. LVDS Differential Measurement
Figure 5b. LVDS Common Mode Measurement
RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION
Part Number
Function
Data Sheet Link
SY89542U
2.5 V, 3.2Gbps Dual, Differential 2:1 LVDS
Multiplexer with Internal Input Termination
http://www.micrel.com/_PDF/HBW/sy89542u.pdf
SY89543L
3.3V, 3.2Gbps Dual, Differential 2:1 LVDS
Multiplexer with Internal Input Termination
http://www.micrel.com/_PDF/HBW/sy89543l.pdf
SY89544U
2.5V, 3.2Gbps, Differential 4:1 LVDS Multiplexer
with Internal Input Termination
http://www.micrel.com/_PDF/HBW/sy89544u.pdf
SY89545L
3.3V, 3.2Gbps 4:1 LVDS Multiplexer with Internal
Input Termination
http://www.micrel.com/_PDF/HBW/sy89545l.pdf
SY89547L
3.3V, 3.2Gbps, Differential 4:1 LVDS Multiplexer
with 1:2 Fanout and Internal Input Termination
http://www.micrel.com/_PDF/HBW/SY89547l.pdf
HBW Solutions
MLF® Application Note
www.amkor.com/products/notes_papers/MLF_AppNote_0902.pdf
New Products and Applications
www.micrel.com/product-info/products/solutions.shtml
M9999-060308
[email protected] or (408) 955-1690
9
Precision Edge®
SY89546U
Micrel, Inc.
32 LEAD MicroLeadFrame® (MLF-32)
Package
EP- Exposed Pad
Die
CompSide Island
Heat Dissipation
Heat Dissipation
VEE
Heavy Copper Plane
VEE
Heavy Copper Plane
PCB Thermal Consideration for 32-Pin MLF® Package
(Always solder, or equivalent, the exposed pad to the PCB)
Package Notes:
1. Package meets Level 2 qualification.
2. All parts are dry-packaged before shipment.
3. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2005 Micrel, Incorporated.
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10