FAIRCHILD FAN3228TMX_12

FAN3226 / FAN3227 / FAN3228 / FAN3229_F085
Dual 2A High-Speed, Low-Side Gate Drivers
Features






Qualified to AEC Q-100
4.5 to 18V Operating Range
3A Peak Sink/Source at VDD = 12V
2.4A Sink / 1.6A Source at VOUT = 6V
Choice of TTL or CMOS Input Thresholds
Four Versions of Dual Independent Drivers:
-
Dual Inverting + Enable (FAN3226)
Dual Non-Inverting + Enable (FAN3227)
Dual Inputs in Two Pin-Out Configurations:
o
o
Compatible with FAN3225x (FAN3228)
Compatible with TPS2814D (FAN3229)




Internal Resistors Turn Driver Off If No Inputs



Double Current Capability by Paralleling Channels
MillerDrive™ Technology
12ns / 9ns Typical Rise/Fall Times with 1nF Load
Typical Propagation Delay Under 20ns Matched
within 1ns to the Other Channel
8-Lead SOIC Package
Rated from –40°C to +125°C Ambient
Applications





Switch-Mode Power Supplies
High-Efficiency MOSFET Switching
Description
The FAN3226-29 family of dual 2A gate drivers is
designed to drive N-channel enhancement-mode
MOSFETs in low-side switching applications by
providing high peak current pulses during the short
switching intervals. The driver is available with either
TTL or CMOS input thresholds. Internal circuitry
provides an under-voltage lockout function by holding
the output low until the supply voltage is within the
operating range. In addition, the drivers feature matched
internal propagation delays between A and B channels
for applications requiring dual gate drives with critical
timing, such as synchronous rectifiers. This enables
connecting two drivers in parallel to effectively double
the current capability driving a single MOSFET.
The FAN322X drivers incorporate MillerDrive™
architecture for the final output stage. This bipolarMOSFET combination provides high current during the
Miller plateau stage of the MOSFET turn-on / turn-off
process to minimize switching loss, while providing railto-rail voltage swing and reverse current capability.
The FAN3226 offers two inverting drivers and the
FAN3227 offers two non-inverting drivers. Each device
has dual independent enable pins that default to ON if
not connected. In the FAN3228 and FAN3229, each
channel has dual inputs of opposite polarity, which
allows configuration as non-inverting or inverting with an
optional enable function using the second input. If one
or both inputs are left unconnected, internal resistors
bias the inputs such that the output is pulled low to hold
the power MOSFET off.
Synchronous Rectifier Circuits
Related Resources
DC-to-DC Converters

Motor Control
FAN3226
FAN3227
FAN3228
Figure 1.
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
AN-6069: Application Review and Comparative
Evaluation of Low-Side Gate Drivers
FAN3229
Pin Configurations
www.fairchildsemi.com
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
March 2012
Part Number
FAN3226CMX_F085
FAN3226TMX_F085
FAN3227CMX_F085
FAN3227TMX_F085
FAN3228CMX_F085
FAN3228TMX_F085
FAN3229CMX_F085
FAN3229TMX_F085
Logic
Input
Package
Threshold
Eco
Status
Packing
Method
Quantity
per Reel
Dual Inverting Channels +
Dual Enable
CMOS
SOIC-8
RoHS
Tape & Reel
2,500
TTL
SOIC-8
RoHS
Tape & Reel
2,500
Dual Non-Inverting Channels
+ Dual Enable
CMOS
SOIC-8
RoHS
Tape & Reel
2,500
TTL
SOIC-8
RoHS
Tape & Reel
2,500
Dual Channels of Two-Input
/ One-Output Drivers, Pin
Configuration 1
CMOS
SOIC-8
RoHS
Tape & Reel
2,500
TTL
SOIC-8
RoHS
Tape & Reel
2,500
Dual Channels of Two-Input
/ One-Output Drivers, Pin
Configuration 2
CMOS
SOIC-8
RoHS
Tape & Reel
2,500
TTL
SOIC-8
RoHS
Tape & Reel
2,500
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Package Outline
Figure 2. SOIC-8 (Top View)
Thermal Characteristics(1)
Package
JL(2)
JT(3)
JA(4)
JB(5)
JT(6)
Units
40
31
89
43
3.0
°C/W
8-Pin Small Outline Integrated Circuit (SOIC)
Notes:
1.
2.
3.
4.
5.
6.
Estimates derived from thermal simulation; actual values depend on the application.
Theta_JL (JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any
thermal pad) that are typically soldered to a PCB.
Theta_JT (JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is
held at a uniform temperature by a top-side heatsink.
Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.
The value given is for natural convection with no heatsink, as specified in JEDEC standards JESD51-2, JESD51-5, and
JESD51-7, as appropriate.
Psi_JB (JB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an
application circuit board reference point for the thermal environment defined in Note 4. For the SOIC-8 package, the board
reference is defined as the PCB copper adjacent to pin 6.
Psi_JT (JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and
the center of the top of the package for the thermal environment defined in Note 4.
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
www.fairchildsemi.com
2
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
Ordering Information
FAN3227
FAN3228
FAN3229
Figure 3. Pin Configurations (Repeated)
Pin Definitions
Name
Pin Description
ENA
Enable Input for Channel A. Pull pin low to inhibit driver A. ENA has TTL thresholds for both TTL and
CMOS INx threshold.
ENB
Enable Input for Channel B. Pull pin low to inhibit driver B. ENB has TTL thresholds for both TTL and
CMOS INx threshold.
GND
Ground. Common ground reference for input and output circuits.
INA
Input to Channel A.
INA+
Non-Inverting Input to Channel A. Connect to VDD to enable output.
INA-
Inverting Input to Channel A. Connect to GND to enable output.
INB
Input to Channel B.
INB+
Non-Inverting Input to Channel B. Connect to VDD to enable output.
INB-
Inverting Input to Channel B. Connect to GND to enable output.
OUTA
Gate Drive Output A: Held low unless required input(s) are present and VDD is above UVLO threshold.
OUTB
Gate Drive Output B: Held low unless required input(s) are present and VDD is above UVLO threshold.
OUTA
Gate Drive Output A (inverted from the input): Held low unless required input is present and VDD is
above UVLO threshold.
OUTB
Gate Drive Output B (inverted from the input): Held low unless required input is present and VDD is
above UVLO threshold.
Supply Voltage. Provides power to the IC.
VDD
Output Logic
FAN3226 (x=A or B)
ENx
INx
FAN3227 (x=A or B)
OUTx
0
0
0
(7)
0
0
1
1
1(7)
0
1(7)
1
(7)
1(7)
1
0
ENx
INx
(7)
0
0
0
(7)
OUTx
0
FAN3228 and FAN3229
(x=A or B)
INx+
INx−
OUTx
(7)
0
0
(7)
(7)
0
0
1
0
(7)
0
1
0
1
1
1
1
1(7)
0
0
0
1
Note:
7. Default input signal if no external connection is made.
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
www.fairchildsemi.com
3
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
FAN3226
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
Block Diagrams
VDD
VDD
100k
100k
ENA 1
8
ENB
VDD
100k
INA
2
7
OUTA
100k
GND 3
UVLO
6
VDD
VDD_OK
VDD
100k
INB
5
4
OUTB
100k
Figure 4. FAN3226 Block Diagram
Figure 5. FAN3227 Block Diagram
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
www.fairchildsemi.com
4
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
Block Diagrams
Figure 6. FAN3228 Block Diagram
Figure 7. FAN3229 Block Diagram
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
www.fairchildsemi.com
5
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
-0.3
20.0
V
VDD
VDD to PGND
VEN
ENA and ENB to GND
GND - 0.3 VDD + 0.3
V
VIN
INA, INA+, INA–, INB, INB+ and INB– to GND
GND - 0.3 VDD + 0.3
V
OUTA and OUTB to GND
GND - 0.3 VDD + 0.3
V
VOUT
TL
Lead Soldering Temperature (10 Seconds)
TJ
Junction Temperature
TSTG
Storage Temperature
ESD
Human Body Model, JEDEC JESD22-A114
+260
ºC
-55
+150
ºC
-65
+150
ºC
3
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
4.5
18.0
V
VDD
Supply Voltage Range
VEN
Enable Voltage ENA and ENB
0
VDD
V
VIN
Input Voltage INA, INA+, INA–, INB, INB+ and INB–
0
VDD
V
TA
Operating Ambient Temperature
-40
+125
ºC
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
www.fairchildsemi.com
6
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
Absolute Maximum Ratings
Unless otherwise noted, VDD=12V, TJ=-40°C to +125°C. Currents are defined as positive into the device and negative
out of the device.
Symbol
Parameter
Conditions
Min.
Typ. Max.
Unit
Supply
VDD
Operating Range
IDD
Supply Current Inputs / EN
Not Connected
TTL
VON
Turn-On Voltage
INA=ENA=VDD, INB=ENB=0V
3.4
VOFF
Turn-Off Voltage
INA=ENA=VDD, INB=ENB=0V
Inputs (FAN322xT)
VINL_T
4.5
CMOS
18.0
V
0.75
1.20
mA
0.65
1.05
mA
3.9
4.5
V
3.2
3.7
4.3
V
0.8
1.2
(8)
(9)
INx Logic Low Threshold
VINH_T
INx Logic High Threshold
IINx_T
Non-inverting Input Current
IN = 0V
IINx_T
Non-inverting Input Current
IN = VDD
90
IINx_T
Inverting Input Current
IN = 0V
-175.0
IINx_T
Inverting Input Current
IN = VDD
-1.5
VHYS_T
1.6
V
1.5
µA
120
175.0
µA
-120
-90
µA
1.5
µA
0.8
V
0.2
0.4
30
38
(9)
VINL_C
INx Logic Low Threshold
VINH_C
INx Logic High Threshold
IINx_C
Non-Inverting Input Current
IN = 0V
IINx_C
Non-Inverting Input Current
IN = VDD
90
IINx_C
Inverting Input Current
IN = 0V
-175
IINx_C
Inverting Input Current
IN = VDD
-1.5
VHYS_C
2.0
-1.5
TTL Logic Hysteresis Voltage
Inputs (FAN322xC)
V
55
70
%VDD
1.5
µA
120
175
µA
-120
-90
µA
1.5
µA
-1.5
CMOS Logic Hysteresis Voltage
%VDD
17
%VDD
ENABLE (FAN3226C, FAN3226T, FAN3227C, FAN3227T)
VENL
Enable Logic Low Threshold
EN from 5V to 0V
VENH
Enable Logic High Threshold
EN from 0V to 5V
VHYS_T
RPU
tD3
tD4
TTL Logic Hysteresis Voltage
0.8
1.2
1.6
(10)
V
2.0
0.4
(10)
Enable Pull-up Resistance
V
100
(12)
EN to Output Propagation Delay
V
kΩ
0V to 5V EN, 1V/ns Slew Rate
8.5
19
34
ns
5V to 0V EN, 1V/ns Slew Rate
9
18
32
ns
Continued on the following page…
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
www.fairchildsemi.com
7
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
Electrical Characteristics
Unless otherwise noted, VDD=12V, TJ=-40°C to +125°C. Currents are defined as positive into the device and negative
out of the device.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Output
ISINK
OUT Current, Mid-Voltage, Sinking
(10)
(10)
ISOURCE
OUT Current, Mid-Voltage, Sourcing
IPK_SINK
OUT Current, Peak, Sinking
IPK_SOURCE
(10)
OUT Current, Peak, Sourcing
(10)
OUT at VDD/2,
CLOAD=0.1µF, f=1kHz
2.4
A
OUT at VDD/2,
CLOAD=0.1µF, f=1kHz
-1.6
A
CLOAD=0.1µF, f=1kHz
3
A
CLOAD=0.1µF, f=1kHz
-3
A
VOH
High Level Output Voltage
VOH = VDD – VOUT, IOUT = –1mA
15
35
mV
VOL
Low Level Output Voltage
IOUT = 1mA
10
25
mV
CLOAD=1000pF
12
22
ns
Output Fall Time
CLOAD=1000pF
9
17
ns
Output Propagation Delay, CMOS
(12)
Inputs
CMOS Input
7
15
33
CMOS Input
6
15
37.5
Output Propagation Delay, TTL
(12)
Inputs
TTL Input
9
19
34
TTL Input
9
18
32
Propagation Matching Between
Channels
INA=INB, OUTA and OUTB
at 50% point
2
4
tRISE
tFALL
tD1
tD2
tD1
tD2
tDEL.MATCH
IRVS
(12)
Output Rise Time
(12)
Output Reverse Current Withstand
(10)
500
ns
ns
ns
mA
Notes:
8. Lower supply current due to inactive TTL circuitry.
9. EN inputs have TTL thresholds; refer to the ENABLE section.
10. Not tested in production.
11. See Timing Diagrams of Figure 10 and Figure 11.
12. See Timing Diagrams of Figure 8 and Figure 9.
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
www.fairchildsemi.com
8
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
Electrical Characteristics (Continued)
Figure 8. Non-Inverting (EN HIGH or Floating)
Figure 9. Inverting (EN HIGH or Floating)
Figure 10. Non-Inverting (IN HIGH)
Figure 11. Inverting (IN LOW)
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
www.fairchildsemi.com
9
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
Timing Diagrams
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
1.6
1.6
1.4
FAN3226C, 27C
1.2
1.2
1.0
1.0
IDD (mA)
IDD (mA)
1.4
0.8
0.6
0.4
0.8
0.6
0.4
Inputs and Enables
Floating, Outputs
0.2
TTL Input
Inputs and Enables
Floating, Outputs Low
0.2
0.0
0.0
4
6
8
10
12
14
16
4
18
6
Supply Voltage (V)
8
10
12
14
16
18
Supply Voltage (V)
Figure 12. IDD (Static) vs. Supply Voltage
(13)
(13)
Figure 13. IDD (Static) vs. Supply Voltage
1.6
1.4
FAN3228C, 29C
IDD (mA)
1.2
1.0
All Inputs Floating,
Outputs Low
0.8
0.6
0.4
0.2
0.0
4
6
8
10
12
14
16
V DD - Supply Voltage (V)
Figure 14. IDD (Static) vs. Supply Voltage
Figure 15. IDD (No-Load) vs. Frequency
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
18
(13)
Figure 16. IDD (No-Load) vs. Frequency
www.fairchildsemi.com
10
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 17. IDD (1nF Load) vs. Frequency
Figure 18. IDD (1nF Load) vs. Frequency
1.6
1.6
1.4
1.2
1.2
1.0
1.0
IDD (mA)
IDD (mA)
1.4
FAN3226C, 27C
0.8
0.6
0.2
0.0
-50
-25
0
25
50
75
Tem perature (°C)
100
0.8
0.6
Inputs and Enables
Floating, Outputs
0.4
Inputs and Enables
Floating, Outputs
0.4
TTL Input
0.2
0.0
-50
125
(13)
-25
0
25
50
75
Tem perature (°C)
100
125
(13)
Figure 19. IDD (Static) vs. Temperature
Figure 20. IDD (Static) vs. Temperature
1.6
1.4
FAN3228C, 29C
IDD (mA)
1.2
1.0
0.8
0.6
0.4
All Inputs Floating,
Outputs Low
0.2
0.0
-50
-25
0
25
50
75
Tem perature (°C)
100
125
(13)
Figure 21. IDD (Static) vs. Temperature
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
www.fairchildsemi.com
11
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 22. Input Thresholds vs. Supply Voltage
Figure 23. Input Thresholds vs. Supply Voltage
Figure 24. Input Threshold % vs. Supply Voltage
Figure 25. Input Thresholds vs. Temperature
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
Figure 26. Input Thresholds vs. Temperature
www.fairchildsemi.com
12
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 27. UVLO Thresholds vs. Temperature
Figure 28. UVLO Threshold vs. Temperature
Figure 29. Propagation Delays vs. Supply Voltage
Figure 30. Propagation Delays vs. Supply Voltage
Figure 31. Propagation Delays vs. Supply Voltage
Figure 32. Propagation Delays vs. Supply Voltage
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
www.fairchildsemi.com
13
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 33. Propagation Delays vs. Temperature
Figure 34. Propagation Delays vs. Temperature
Figure 35. Propagation Delays vs. Temperature
Figure 36. Propagation Delays vs. Temperature
Figure 37. Fall Time vs. Supply Voltage
Figure 38. Rise Time vs. Supply Voltage
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
www.fairchildsemi.com
14
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 39. Rise and Fall Times vs. Temperature
Figure 40. Rise/Fall Waveforms with 1nF Load
Figure 41. Rise/Fall Waveforms with 10nF Load
Figure 42. Quasi-Static Source Current with
VDD=12V
Figure 43. Quasi-Static Sink Current with VDD=12V
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
www.fairchildsemi.com
15
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted.
Figure 44. Quasi-Static Source Current with
VDD=8V
Figure 45. Quasi-Static Sink Current with VDD=8V
Note:
13. For any inverting inputs pulled low, non-inverting inputs pulled high, or outputs driven high, static IDD increases by
the current flowing through the corresponding pull-up/down resistor shown in the block diagram.
Test Circuit
Figure 46. Quasi-Static IOUT / VOUT Test Circuit
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
www.fairchildsemi.com
16
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Input Thresholds
MillerDrive™ Gate Drive Technology
Each member of the FAN322x driver family consists of
two identical channels that may be used independently
at rated current or connected in parallel to double the
individual current capacity. In the FAN3226 and
FAN3227, channels A and B can be enabled or disabled
independently using ENA or ENB, respectively. The EN
pin has TTL thresholds for parts with either CMOS or
TTL input thresholds. If ENA and ENB are not
connected, an internal pull-up resistor enables the driver
channels by default. If the channel A and channel B
inputs and outputs are connected in parallel to increase
the driver current capacity, ENA and ENB should be
connected and driven together.
FAN322x gate drivers incorporate the MillerDrive™
architecture shown in Figure 47. For the output stage, a
combination of bipolar and MOS devices provide large
currents over a wide range of supply voltage and
temperature variations. The bipolar devices carry the
bulk of the current as OUT swings between 1/3 to 2/3
VDD and the MOS devices pull the output to the high or
low rail.
The FAN322x family offers versions in either TTL or
CMOS input thresholds. In the FAN322xT, the input
thresholds meet industry-standard TTL-logic thresholds
independent of the VDD voltage, and there is a
hysteresis voltage of approximately 0.4V. These levels
permit the inputs to be driven from a range of input logic
signal levels for which a voltage over 2V is considered
logic high. The driving signal for the TTL inputs should
have fast rising and falling edges with a slew rate of
6V/µs or faster, so a rise time from 0 to 3.3V should be
550ns or less. With reduced slew rate, circuit noise
could cause the driver input voltage to exceed the
hysteresis voltage and retrigger the driver input, causing
erratic operation.
For applications that have zero voltage switching during
the MOSFET turn-on or turn-off interval, the driver
supplies high peak current for fast switching even
though the Miller plateau is not present. This situation
often occurs in synchronous rectifier applications
because the body diode is generally conducting before
the MOSFET is switched on.
The purpose of the MillerDrive™ architecture is to
speed up switching by providing high current during the
Miller plateau region when the gate-drain capacitance of
the MOSFET is being charged or discharged as part of
the turn-on / turn-off process.
The output pin slew rate is determined by VDD voltage
and the load on the output. It is not user adjustable, but
a series resistor can be added if a slower rise or fall time
at the MOSFET gate is needed.
VDD
In the FAN322xC, the logic input thresholds are
dependent on the VDD level and, with VDD of 12V, the
logic rising edge threshold is approximately 55% of VDD
and the input falling edge threshold is approximately
38% of VDD. The CMOS input configuration offers a
hysteresis voltage of approximately 17% of VDD. The
CMOS inputs can be used with relatively slow edges
(approaching DC) if good decoupling and bypass
techniques are incorporated in the system design to
prevent noise from violating the input voltage hysteresis
window. This allows setting precise timing intervals by
fitting an R-C circuit between the controlling signal and
the IN pin of the driver. The slow rising edge at the IN
pin of the driver introduces a delay between the
controlling signal and the OUT pin of the driver.
Input
stage
Figure 47. MillerDrive™ Output Architecture
Under-Voltage Lockout
Static Supply Current
The FAN322x startup logic is optimized to drive groundreferenced N-channel MOSFETs with an under-voltage
lockout (UVLO) function to ensure that the IC starts up
in an orderly fashion. When VDD is rising, yet below the
3.9V operational level, this circuit holds the output low,
regardless of the status of the input pins. After the part
is active, the supply voltage must drop 0.2V before the
part shuts down. This hysteresis helps prevent chatter
when low VDD supply voltages have noise from the
power switching. This configuration is not suitable for
driving high-side P-channel MOSFETs because the low
output voltage of the driver would turn the P-channel
MOSFET on with VDD below 3.9V.
In the IDD (static) typical performance characteristics
(see Figure 12 - Figure 14 and Figure 19 - Figure 21),
the curve is produced with all inputs / enables floating
(OUT is low) and indicates the lowest static IDD current
for the tested configuration. For other states, additional
current flows through the 100k resistors on the inputs
and outputs shown in the block diagram of each part
(see Figure 4 - Figure 7). In these cases, the actual
static IDD current is the value obtained from the curves
plus this additional current.
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
VOUT
www.fairchildsemi.com
17
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
Applications Information

To enable this IC to turn a device on quickly, a local
high-frequency bypass capacitor CBYP with low ESR and
ESL should be connected between the VDD and GND
pins with minimal trace length. This capacitor is in
addition to bulk electrolytic capacitance of 10µF to 47µF
commonly found on driver and controller bias circuits.

The turn-on and turn-off current paths should be
minimized, as discussed in the following section.
Figure 48 shows the pulsed gate drive current path
when the gate driver is supplying gate charge to turn the
MOSFET on. The current is supplied from the local
bypass capacitor, CBYP, and flows through the driver to
the MOSFET gate and to ground. To reach the high
peak currents possible, the resistance and inductance in
the path should be minimized. The localized CBYP acts
to contain the high peak current pulses within this driverMOSFET circuit, preventing them from disturbing the
sensitive analog circuitry in the PWM controller.
A typical criterion for choosing the value of CBYP is to
keep the ripple voltage on the VDD supply to ≤5%. This
is often achieved with a value ≥20 times the equivalent
load capacitance CEQV, defined here as QGATE/VDD.
Ceramic capacitors of 0.1µF to 1µF or larger are
common choices, as are dielectrics, such as X5R and
X7R with good temperature characteristics and high
pulse current capability.
If circuit noise affects normal operation, the value of
CBYP may be increased to 50-100 times the CEQV, or
CBYP may be split into two capacitors. One should be a
larger value, based on equivalent load capacitance, and
the other a smaller value, such as 1-10nF mounted
closest to the VDD and GND pins to carry the higher
frequency components of the current pulses. The
bypass capacitor must provide the pulsed current from
both of the driver channels and, if the drivers are
switching simultaneously, the combined peak current
sourced from the CBYP would be twice as large as when
a single channel is switching.
VDD
FAN322x
PWM
The FAN3226-26 family of gate drivers incorporates
fast-reacting input circuits, short propagation delays,
and powerful output stages capable of delivering current
peaks over 2A to facilitate voltage transition times from
under 10ns to over 150ns. The following layout and
connection guidelines are strongly recommended:
Keep high-current output and power ground paths
separate logic and enable input signals and signal
ground paths. This is especially critical when
dealing with TTL-level logic thresholds at driver
inputs and enable pins.

Keep the driver as close to the load as possible to
minimize the length of high-current traces. This
reduces the series inductance to improve highspeed switching, while reducing the loop area that
can radiate EMI to the driver inputs and
surrounding circuitry.


Figure 48. Current Path for MOSFET Turn-on
Figure 49 shows the current path when the gate driver
turns the MOSFET off. Ideally, the driver shunts the
current directly to the source of the MOSFET in a small
circuit loop. For fast turn-off times, the resistance and
inductance in this path should be minimized.
VDD
VDS
CBYP
FAN322x
If the inputs to a channel are not externally
connected, the internal 100k resistors indicated
on block diagrams command a low output. In noisy
environments, it may be necessary to tie inputs of
an unused channel to VDD or GND using short
traces to prevent noise from causing spurious
output switching.
PWM
Many high-speed power circuits can be susceptible
to noise injected from their own output or other
external sources, possibly causing output retriggering. These effects can be obvious if the
circuit is tested in breadboard or non-optimal circuit
layouts with long input, enable, or output leads. For
best results, make connections to all pins as short
and direct as possible.
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
VDS
CBYP
Layout and Connection Guidelines

The FAN322x is compatible with many other
industry-standard drivers. In single input parts with
enable pins, there is an internal 100k resistor tied
to VDD to enable the driver by default; this should be
considered in the PCB layout.
Figure 49. Current Path for MOSFET Turn-off
www.fairchildsemi.com
18
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
VDD Bypass Capacitor Guidelines
Operational Waveforms
The FAN3228/FAN3229 truth table indicates the
operational states using the dual-input configuration. In
a non-inverting driver configuration, the IN- pin should
be a logic low signal. If the IN- pin is connected to logic
high, a disable function is realized, and the driver output
remains low regardless of the state of the IN+ pin.
At power-up, the driver output remains low until the VDD
voltage reaches the turn-on threshold. The magnitude of
the OUT pulses rises with VDD until steady-state VDD is
reached. The non-inverting operation illustrated in
Figure 52 shows that the output remains low until the
UVLO threshold is reached, the output is in-phase with
the input.
IN+
IN-
OUT
0
0
0
0
1
0
1
0
1
1
1
0
In the non-inverting driver configuration in Figure 50, the
IN- pin is tied to ground and the input signal (PWM) is
applied to IN+ pin. The IN- pin can be connected to logic
high to disable the driver and the output remains low,
regardless of the state of the IN+ pin.
Figure 52. Non-Inverting Startup Waveforms
For the inverting configuration of Figure 51, startup
waveforms are shown in Figure 53. With IN+ tied to VDD
and the input signal applied to IN–, the OUT pulses are
inverted with respect to the input. At power-up, the
inverted output remains low until the VDD voltage
reaches the turn-on threshold, then it follows the input
with inverted phase.
Figure 50. Dual-Input Driver Enabled,
Non-Inverting Configuration
In the inverting driver application in Figure 51, the IN+
pin is tied high. Pulling the IN+ pin to GND forces the
output low, regardless of the state of the IN- pin.
Figure 51. Dual-Input Driver Enabled,
Inverting Configuration
Figure 53. Inverting Startup Waveforms
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
www.fairchildsemi.com
19
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
Truth Table of Logic Operation
Thermal Guidelines
Gate drivers used to switch MOSFETs and IGBTs at
high frequencies can dissipate significant amounts of
power. It is important to determine the driver power
dissipation and the resulting junction temperature in the
application to ensure that the part is operating within
acceptable temperature limits.
In the forward converter with synchronous rectifier
shown in the typical application diagrams, the
FDMS8660S is a reasonable MOSFET selection. The
gate charge for each SR MOSFET would be 60nC with
VGS = VDD = 7V. At a switching frequency of 500kHz, the
total power dissipation is:
The total power dissipation in a gate driver is the sum of
two components, PGATE and PDYNAMIC:
PTOTAL = PGATE + PDYNAMIC
(1)
Gate Driving Loss: The most significant power loss
results from supplying gate current (charge per unit
time) to switch the load MOSFET on and off at the
switching frequency. The power dissipation that
results from driving a MOSFET at a specified gatesource voltage, VGS, with gate charge, QG, at
switching frequency, FSW, is determined by:
PGATE = QG • VGS • FSW • n
(5)
PDYNAMIC = 3mA • 7V • 2 = 0.042W
(6)
PTOTAL = 0.462W
(7)
The SOIC-8 has a junction-to-board thermal
characterization parameter of JB = 43°C/W. In a
system application, the localized temperature around
the device is a function of the layout and construction of
the PCB along with airflow across the surfaces. To
ensure reliable operation, the maximum junction
temperature of the device must be prevented from
exceeding the maximum rating of 150°C; with 80%
derating, TJ would be limited to 120°C. Rearranging
Equation 4 determines the board temperature required
to maintain the junction temperature below 120°C:
(2)
n is the number of driver channels in use (1 or 2).
Dynamic Pre-drive / Shoot-through Current: A
power loss resulting from internal current
consumption under dynamic operating conditions,
including pin pull-up / pull-down resistors, can be
obtained using the “IDD (No-Load) vs. Frequency”
graphs in Typical Performance Characteristics to
determine the current IDYNAMIC drawn from VDD
under actual operating conditions:
PDYNAMIC = IDYNAMIC • VDD • n
PGATE = 60nC • 7V • 500kHz • 2 = 0.42W
TB = TJ - PTOTAL • JB
(8)
TB = 120°C – 0.462W • 43°C/W = 100°C
(9)
(3)
Once the power dissipated in the driver is determined,
the driver junction rise with respect to circuit board can
be evaluated using the following thermal equation,
assuming JB was determined for a similar thermal
design (heat sinking and air flow):
TJ
= PTOTAL • JB + TB
(4)
where:
TJ
= driver junction temperature
JB = (psi) thermal characterization parameter
relating temperature rise to total power
dissipation
TB = board temperature in location defined in Note
1 under Thermal Resistance table.
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
www.fairchildsemi.com
20
Figure 54. Forward Converter
with Synchronous Rectification
Figure 55.
Primary-Side Dual Driver
in a Push-Pull Converter
VIN
FAN3227
ENB 8
1 ENA
PWM-A
2
A
3 GND
PWM-B
4
7
VDD 6
B
5
Vbias
FAN3227
PWM-C
Phase Shift
Controller
PWM-D
ENB 8
1 ENA
2
A
3 GND
4
7
Vbias
VDD 6
B
5
Figure 56. Phase-Shifted Full-Bridge with Two Gate Drive Transformers (Simplified)
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
www.fairchildsemi.com
21
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
Typical Application Diagrams
Type
Related Products
Part
Number
(14)
Gate Drive
(Sink/Src)
Input
Threshold
Logic
Single Channel of Dual-Input/Single-Output
Package
Single 1A
FAN3111C
+1.1A / -0.9A
CMOS
Single 1A
FAN3111E
+1.1A / -0.9A
External
Single 2A
FAN3100C
+2.5A / -1.8A
CMOS
Single Channel of Two-Input/One-Output
SOT23-5
Single 2A
FAN3100T
+2.5A / -1.8A
TTL
Single Channel of Two-Input/One-Output
SOT23-5
Dual 2A
FAN3216T
+2.4A / -1.6A
TTL
Dual Inverting Channels
SOIC8
Dual 2A
FAN3217T
+2.4A / -1.6A
TTL
Dual Non-Inverting Channels
SOIC8
Dual 2A
FAN3226C
+2.4A / -1.6A
CMOS
Dual Inverting Channels + Dual Enable
SOIC8
Dual 2A
FAN3226T
+2.4A / -1.6A
TTL
Dual Inverting Channels + Dual Enable
SOIC8
Dual 2A
FAN3227C
+2.4A / -1.6A
CMOS
Dual Non-Inverting Channels + Dual Enable
SOIC8
Dual 2A
FAN3227T
+2.4A / -1.6A
TTL
Dual Non-Inverting Channels + Dual Enable
SOIC8
Dual 2A
FAN3228C
+2.4A / -1.6A
CMOS
Dual Channels of Two-Input/One-Output, Pin Config.1
SOIC8
Dual 2A
FAN3228T
+2.4A / -1.6A
TTL
Dual Channels of Two-Input/One-Output, Pin Config.1
SOIC8
Dual 2A
FAN3229C
+2.4A / -1.6A
CMOS
Dual Channels of Two-Input/One-Output, Pin Config.2
SOIC8
Dual 2A
FAN3229T
+2.4A / -1.6A
TTL
Dual Channels of Two-Input/One-Output, Pin Config.2
SOIC8
Dual 2A
FAN3268T
+2.4A / -1.6A
TTL
20V Non-Inverting Channel (NMOS) and Inverting
Channel (PMOS) + Dual Enables
SOIC8
Dual 2A
FAN3278T
+2.4A / -1.6A
TTL
30V Non-Inverting Channel (NMOS) and Inverting
Channel (PMOS) + Dual Enables
SOIC8
Dual 4A
FAN3213T
+2.5A / -1.8A
TTL
Dual Inverting Channels
SOIC8
Dual 4A
FAN3214T
+2.5A / -1.8A
TTL
Dual Non-Inverting Channels
SOIC8
Dual 4A
FAN3223C
+4.3A / -2.8A
CMOS
Dual Inverting Channels + Dual Enable
SOIC8
Dual 4A
FAN3223T
+4.3A / -2.8A
TTL
Dual Inverting Channels + Dual Enable
SOIC8
Dual 4A
FAN3224C
+4.3A / -2.8A
CMOS
Dual Non-Inverting Channels + Dual Enable
SOIC8
Dual 4A
FAN3224T
+4.3A / -2.8A
TTL
Dual Non-Inverting Channels + Dual Enable
SOIC8
Dual 4A
FAN3225C
+4.3A / -2.8A
CMOS
Dual Channels of Two-Input/One-Output
SOIC8
Dual 4A
FAN3225T
+4.3A / -2.8A
TTL
Dual Channels of Two-Input/One-Output
SOIC8
Single 9A
FAN3121C
+9.7A / -7.1A
CMOS
Single Inverting Channel + Enable
SOIC8
Single 9A
FAN3121T
+9.7A / -7.1A
TTL
Single Inverting Channel + Enable
SOIC8
Single 9A
FAN3122T
+9.7A / -7.1A
CMOS
Single Non-Inverting Channel + Enable
SOIC8
Single 9A
FAN3122C
+9.7A / -7.1A
TTL
Single Non-Inverting Channel + Enable
SOIC8
(15)
SOT23-5
Single Non-Inverting Channel with External Reference SOT23-5
Notes:
14. Typical currents with OUTx at 6V and VDD=12V.
15. Thresholds proportional to an externally supplied reference voltage.
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
www.fairchildsemi.com
22
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
Table 1.
5.00
4.80
A
0.65
3.81
8
5
B
6.20
5.80
PIN ONE
INDICATOR
1.75
4.00
3.80
1
5.60
4
1.27
(0.33)
0.25
M
1.27
C B A
LAND PATTERN RECOMMENDATION
0.25
0.10
SEE DETAIL A
1.75 MAX
R0.10
0.51
0.33
0.50 x 45
0.25
0.10 C
OPTION A - BEVEL EDGE
GAGE PLANE
R0.10
8ٛ
0ٛ
0.90
0.406
0.25
0.19
C
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 57. 8-Lead, Small Outline Integrated Curcuit (SOIC)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
www.fairchildsemi.com
23
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
Physical Dimensions (Continued)
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 — Dual 2A High-Speed, Low-Side Gate Drivers
© 2012 Fairchild Semiconductor Corporation
FAN3226 / FAN3227 / FAN3228 / FAN3229_F085 • Rev. 1.0.0
www.fairchildsemi.com
24