FAIRCHILD MM74HC32M

MM74HC32
Quad 2-Input OR Gate
Features
General Description
■ Typical propagation delay: 10ns
The MM74HC32 OR gates utilize advanced silicon-gate
CMOS technology to achieve operating speeds similar to
LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered
outputs providing high noise immunity and the ability to
drive 10 LS-TTL loads. The 74HC logic family is functionally as well as pin-out compatible with the standard
74LS logic family. All inputs are protected from damage
due to static discharge by internal diode clamps to VCC
and ground.
■ Wide power supply range: 2V–6V
■ Low quiescent current: 20µA maximum (74HC Series)
■ Low input current: 1µA maximum
■ Fanout of 10 LS-TTL loads
Ordering Information
Order Number
Package
Number
Package Description
MM74HC32M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC32SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC32MTC
MM74HC32N
MTC14
N14A
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Logic Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Y=A+B
(1 of 4)
Top View
©1983 Fairchild Semiconductor Corporation
MM74HC32 Rev. 1.3.0
www.fairchildsemi.com
MM74HC32 — Quad 2-Input OR Gate
February 2008
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
VCC
Supply Voltage
VIN
DC Input Voltage
–1.5 to VCC+1.5V
DC Output Voltage
–0.5 to VCC+0.5V
VOUT
IIK, IOK
–0.5 to +7.0V
Clamp Diode Current
±20mA
IOUT
DC Output Current, per pin
±25mA
ICC
DC VCC or GND Current, per pin
±50mA
TSTG
PD
Storage Temperature Range
–65°C to +150°C
Power Dissipation
Note 2
600mW
S.O. Package only
TL
500mW
Lead Temperature (Soldering 10 seconds)
260°C
Notes:
1. Unless otherwise specified all voltages are referenced to ground.
2. Power Dissipation temperature derating — plastic “N” package: –12mW/°C from 65°C to 85°C.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC
VIN, VOUT
TA
t r, t f
Parameter
Min.
Max.
Units
Supply Voltage
2
6
V
DC Input or Output Voltage
0
VCC
V
–40
+85
°C
Operating Temperature Range
Input Rise or Fall Times
VCC = 2.0V
1000
ns
VCC = 4.5V
500
ns
VCC = 6.0V
400
ns
©1983 Fairchild Semiconductor Corporation
MM74HC32 Rev. 1.3.0
www.fairchildsemi.com
2
MM74HC32 — Quad 2-Input OR Gate
Absolute Maximum Ratings(1)
TA = 25°C
Symbol
Parameter
VCC (V)
VIH
Minimum HIGH Level
Input Voltage
2.0
1.5
1.5
4.5
3.15
3.15
6.0
4.2
4.2
Maximum LOW Level
Input Voltage
2.0
0.5
0.5
4.5
1.35
1.35
6.0
1.8
1.8
2.0
1.9
1.9
4.5
4.4
4.4
6.0
5.9
5.9
VIL
VOH
Minimum HIGH Level
Output Voltage
2.0
4.5
Conditions
VIN = VIH or VIL,
|IOUT| ≤ 20µA
6.0
VOL
Maximum LOW Level
Output Voltage
Typ
TA = –40°C to
85°C
Guaranteed Limits
4.5
VIN = VIH or VIL,
|IOUT| ≤ 4.0mA
4.7
3.98
3.84
6.0
|VIN = VIH or VIL,
|IOUT| ≤ 5.2mA
5.2
5.48
5.34
2.0
VIN = VIL,
|IOUT| ≤ 20 µA
0
0.1
0.1
0
0.1
0.1
0
0.1
0.1
4.5
6.0
4.5
VIN = VIL,
|IOUT| ≤ 4.0mA
0.2
0.26
0.33
6.0
VIN = VIL,
|IOUT| ≤ 5.2mA
0.2
0.26
0.33
Units
V
V
V
V
IIN
Maximum Input
Current
6.0
VIN = VCC or GND
±0.1
±1.0
µA
ICC
Maximum Quiescent
Supply Current
6.0
VIN = VCC or GND,
IOUT = 0µA
2.0
20
µA
Note:
3. For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V
values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V
respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at
the higher voltage and so the 6.0V values should be used.
©1983 Fairchild Semiconductor Corporation
MM74HC32 Rev. 1.3.0
www.fairchildsemi.com
3
MM74HC32 — Quad 2-Input OR Gate
DC Electrical Characteristics(3)
VCC = 5V, TA = 25°C, CL = 15pF, tr = tf = 6ns
Symbol
Parameter
tPHL, tPLH
Conditions
Typ.
Guaranteed
Limit
Units
10
18
ns
Maximum Propagation Delay
AC Electrical Characteristics
VCC = 2.0V to 6.0V, CL = 50pF, tr = tf = 6ns (unless otherwise specified)
TA = 25°C
Symbol
Parameter
tPHL, tPLH Maximum Propagation
Delay
tTLH, tTHL
Maximum Output Rise
and Fall Time
CPD
Power Dissipation
Capacitance(4)
CIN
Maximum Input
Capacitance
VCC (V)
Conditions
Typ
TA = –40°C
to 85°C
Guaranteed Limits
2.0
30
100
125
4.5
12
20
25
6.0
9
17
21
2.0
30
75
95
4.5
8
15
19
6.0
7
13
16
(per gate)
50
5
Units
ns
ns
pF
10
10
pF
Note:
4. CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic
current consumption, IS = CPD VCC f + ICC.
©1983 Fairchild Semiconductor Corporation
MM74HC32 Rev. 1.3.0
www.fairchildsemi.com
4
MM74HC32 — Quad 2-Input OR Gate
AC Electrical Characteristics
8.75
8.50
0.65
A
7.62
14
8
B
5.60
4.00
3.80
6.00
PIN ONE
INDICATOR
1
1.70
7
0.51
0.35
1.27
0.25
(0.33)
1.75 MAX
1.50
1.25
1.27
LAND PATTERN RECOMMENDATION
M
C B A
SEE DETAIL A
0.25
0.10
C
0.25
0.19
0.10 C
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
GAGE PLANE
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
0.36
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.50 X 45°
0.25
R0.10
R0.10
8°
0°
0.90
0.50
(1.04)
SEATING PLANE
DETAIL A
SCALE: 20:1
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1983 Fairchild Semiconductor Corporation
MM74HC32 Rev. 1.3.0
www.fairchildsemi.com
5
MM74HC32 — Quad 2-Input OR Gate
Physical Dimensions
MM74HC32 — Quad 2-Input OR Gate
Physical Dimensions (Continued)
Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1983 Fairchild Semiconductor Corporation
MM74HC32 Rev. 1.3.0
www.fairchildsemi.com
6
MM74HC32 — Quad 2-Input OR Gate
Physical Dimensions (Continued)
0.65
0.43 TYP
1.65
6.10
0.45
12.00° TOP
& BOTTOM
R0.09 min
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
E. LANDPATTERN STANDARD: SOP65P640X110-14M
F. DRAWING FILE NAME: MTC14REV6
1.00
R0.09min
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1983 Fairchild Semiconductor Corporation
MM74HC32 Rev. 1.3.0
www.fairchildsemi.com
7
MM74HC32 — Quad 2-Input OR Gate
Physical Dimensions (Continued)
19.56
18.80
14
8
6.60
6.09
1
7
(1.74)
8.12
7.62
1.77
1.14
3.56
3.30
0.35
0.20
5.33 MAX
0.38 MIN
3.81
3.17
0.58
0.35
8.82
2.54
NOTES: UNLESS OTHERWISE SPECIFIED
THIS PACKAGE CONFORMS TO
A) JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS ARE EXCLUSIVE OF BURRS,
C) MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5-1994
E) DRAWING FILE NAME: MKT-N14AREV7
Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1983 Fairchild Semiconductor Corporation
MM74HC32 Rev. 1.3.0
www.fairchildsemi.com
8
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when properly used in accordance with instructions for use
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I33
©1983 Fairchild Semiconductor Corporation
MM74HC32 Rev. 1.3.0
www.fairchildsemi.com
9
MM74HC32 — Quad 2-Input OR Gate
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