SAMSUNG K8S6815ETD

Rev. 1.2, Sep. 2010
K8S6815ET(B)D
64Mb D-die SLC NOR FLASH
7.5x5, 44FBGA, 8M Partition, x16, Muxed Burst, 8Banks
1.7V ~ 1.95V
datasheet
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-1-
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
Revision History
Revision No.
History
Draft Date
Remark
Editor
0.0
- Initial issue
Jan.14, 2009
Target
-
1.0
- Final datasheet.
Mar. 30, 2010
Final
-
1.1
- Added "CLK "HIGH" should be prohibited in asynchronous read
mode start (From CE LOW)" in Asynchronous read operation.
Sep. 06, 2010
Final
-
1.2
- Change tRH value ("Max 200ns" to "Min 200ns") in Vcc Power-up.
Sep. 15, 2010
Final
-
-2-
K8S6815ET(B)D
datasheet
Rev. 1.2
NOR FLASH MEMORY
Table Of Contents
64Mb D-die SLC NOR FLASH
1.0 FEATURES................................................................................................................................................................. 4
2.0 GENERAL DESCRIPTION ......................................................................................................................................... 4
3.0 PIN DESCRIPTION .................................................................................................................................................... 5
4.0 PIN CONFIGURATION ............................................................................................................................................... 5
5.0 FUNCTIONAL BLOCK DIAGRAM .............................................................................................................................. 6
6.0 ORDERING INFORMATION ...................................................................................................................................... 6
7.0 PRODUCT INTRODUCTION...................................................................................................................................... 8
8.0 COMMAND DEFINITIONS ......................................................................................................................................... 9
9.0 DEVICE OPERATION ................................................................................................................................................ 11
9.1 Read Mode .............................................................................................................................................................. 11
9.1.1 Asynchronous Read Mode................................................................................................................................ 11
9.1.2 Synchronous (Burst) Read Mode...................................................................................................................... 11
9.2 Programmable Wait State ....................................................................................................................................... 12
9.3 Handshaking............................................................................................................................................................ 12
9.4 Set Burst Mode Configuration Register ................................................................................................................... 13
9.4.1 Extended Configuration Register (option : K8S6615ET(B)D only).................................................................... 13
9.4.2 Programmable Wait State Configuration........................................................................................................... 13
9.4.3 Burst Read Mode Setting .................................................................................................................................. 13
9.4.4 RDY Configuration ............................................................................................................................................ 13
9.5 Autoselect Mode...................................................................................................................................................... 14
9.6 Standby Mode ......................................................................................................................................................... 14
9.7 Automatic Sleep Mode ............................................................................................................................................ 14
9.8 Output Disable Mode ............................................................................................................................................... 14
9.9 Block Protection & Unprotection.............................................................................................................................. 14
9.10 Hardware Reset..................................................................................................................................................... 15
9.11 Software Reset ...................................................................................................................................................... 15
9.12 Program ................................................................................................................................................................. 15
9.13 Accelerated Program Operation ............................................................................................................................ 15
9.14 Unlock Bypass....................................................................................................................................................... 16
9.15 Chip Erase ............................................................................................................................................................. 16
9.16 Block Erase ........................................................................................................................................................... 16
9.17 Erase Suspend / Resume...................................................................................................................................... 16
9.18 Program Suspend / Resume ................................................................................................................................. 17
9.19 Read While Write Operation .................................................................................................................................. 17
9.20 OTP Block Region ................................................................................................................................................. 17
9.21 Low VCC Write Inhibit ........................................................................................................................................... 17
9.22 Logical Inhibit......................................................................................................................................................... 17
9.23 Power-up Protection .............................................................................................................................................. 17
10.0 FLASH MEMORY STATUS FLAGS ......................................................................................................................... 18
11.0 COMMON FLASH MEMORY INTERFACE .............................................................................................................. 20
12.0 ABSOLUTE MAXI010MUM RATINGS ..................................................................................................................... 22
13.0 RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND)........................................................... 22
14.0 DC CHARACTERISTICS .......................................................................................................................................... 22
15.0 CAPACITANCE (TA = 25 °C, VCC = 1.8V, f = 1.0MHz)........................................................................................... 24
16.0 AC TEST CONDITION.............................................................................................................................................. 24
17.0 AC CHARACTERISTICS .......................................................................................................................................... 25
17.1 Synchronous/Burst Read....................................................................................................................................... 25
17.2 Asynchronous Read .............................................................................................................................................. 29
17.3 Hardware Reset(RESET) ...................................................................................................................................... 31
17.4 Erase/Program Operation...................................................................................................................................... 32
17.5 FLASH Erase/Program Performance .................................................................................................................... 32
18.0 CROSSING OF FIRST WORD BOUNDARY IN BURST READ MODE ................................................................... 39
-3-
K8S6815ET(B)D
datasheet
Rev. 1.2
NOR FLASH MEMORY
4M Bit (8M Partition, x16) Muxed Burst, 8 Banks, NOR Flash Memory
1.0 FEATURES
2.0 GENERAL DESCRIPTION
• Single Voltage, 1.7V to 1.95V for Read and Write operations
• Organization
- 4,194,304 x 16 bit (Word Mode Only)
• Multiplexed Data and Address for reduction of interconnections
- A/DQ0 ~ A/DQ15
• Read While Program/Erase Operation
• Multiple Bank Architecture
- 8 Banks (8Mb Partition)
• OTP Block : Extra 256word block
• Read Access Time (@ CL=30pF)
- Asynchronous Random Access Time : 70ns
- Synchronous Random Access Time : 70ns
- Burst Access Time :
14.5ns (54MHz) / 11ns (66MHz) / 9ns (83Mhz) / 7ns (108Mhz)
• Burst Length :
- Continuous Linear Burst
- Linear Burst : 8-word & 16-word with Wrap
• Block Architecture
- Eight 4Kword blocks and one hundred twenty seven 32Kword
blocks
- Bank 0 contains eight 4 Kword blocks and fifteen 32Kword
blocks
- Bank 1~Bank 7 contain one hundred twelve 32Kword blocks
• Reduce program time using the VPP
• Support Single & Quad word accelerate program
• Power Consumption (Typical value, CL=30pF)
- Burst Access Current : 24mA
- Program/Erase Current : 15mA
- Read While Program/Erase Current : 40mA
- Standby Mode/Auto Sleep Mode : 15uA
• Block Protection/Unprotection
- Using the software command sequence
- Last two boot blocks are protected by WP=VIL
- All blocks are protected by VPP=VIL
• Handshaking Feature
- Provides host system with minimum latency by monitoring
RDY
• Erase Suspend/Resume
• Program Suspend/Resume
• Unlock Bypass Program/Erase
• Hardware Reset (RESET)
• Data Polling and Toggle Bits
- Provides a software method of detecting the status of program
or erase completion
• Endurance
100K Program/Erase Cycles Minimum
• Extended Temperature : -25°C ~ 85°C
• Support Common Flash Memory Interface
• Low Vcc Write Inhibit
• Package : Package : 44-ball FBGA Type, 7.5 x 5 mm
0.5 mm ball pitch
1.0 mm (Max.) Thickness
The K8S6815E featuring single 1.8V power supply is a 64Mbit Synchronous Burst 8Bank Flash Memory organized as 8M, x16. The memory architecture of the device is designed to divide its memory arrays into 135 blocks
with independent hardware protection. This block architecture provides
highly flexible erase and program capability. The K8S6815E NOR Flash
consists of eight banks. This device is capable of reading data from one
bank while programming or erasing in the other bank.
Regarding read access time, the K8S6815E provides an 14.5ns burst
access time and an 70ns initial access time at 54MHz. At 66MHz, the
K8S6815E provides an 11ns burst access time and 70ns initial access time.
At 83MHz, the K8S6815E provides an 9ns burst access time and 70ns initial access time. At 108MHz, the K8S6815E provides an 7ns burst access
time and 70ns initial access time. The device performs a program operation
in units of 16bits (Word) and an erase operation in units of a block. Single or
multiple blocks can be erased. The block erase operation is completed
within typically 0.7sec. The device requires 15mA as program/erase current
in the extended temperature ranges.
The K8S6815E NOR Flash Memory is created by using Samsung's
advanced CMOS process technology.
-4-
Rev. 1.2
datasheet
K8S6815ET(B)D
NOR FLASH MEMORY
3.0 PIN DESCRIPTION
Pin Name
Pin Function
A16 - A21
Address Inputs
A/DQ0 - A/DQ15
Multiplexed Address/Data input/output
CE
Chip Enable
OE
Output Enable
RESET
Hardware Reset Pin
VPP
Accelerates Programming
WE
Write Enable
WP
Hardware Write Protection Input
CLK
Clock
RDY
Ready Output
AVD
Address Valid Input
Vcc
Power Supply
VSS
Ground
4.0 PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
A
RDY
A21
VSS
CLK
VCC
WE
VPP
A19
A17
NC
B
VCC
A16
A20
AVD
NC
RESET
WP
A18
CE
VSS
C
VSS
A/DQ7
A/DQ6
A/DQ13
A/DQ12
A/DQ3
A/DQ2
A/DQ9
A/DQ8
OE
D
A/DQ15
A/DQ14
VSS
A/DQ5
A/DQ4
A/DQ11
A/DQ10
VCC
A/DQ1
A/DQ0
44-FBGA : Top View (Ball Down)
-5-
Rev. 1.2
datasheet
K8S6815ET(B)D
NOR FLASH MEMORY
5.0 FUNCTIONAL BLOCK DIAGRAM
Bank 0
Address
X
Dec
Vcc
Vss
Vpp
CLK
CE
OE
WE
WP
RESET
RDY
AVD
I/O
Interface
&
Bank
Control
Bank 0
Cell Array
Y Dec
Latch &
Control
Y Dec
Latch &
Control
Bank 1
Address
X
Dec
Bank 1
Cell Array
Bank 7
Address
X
Dec
Bank 7
Cell Array
Latch &
Control
Y Dec
A16~A21
A/DQ0~
A/DQ15
Erase
Control
Block
Inform
High
Voltage
Gen.
Program
Control
6.0 ORDERING INFORMATION
K8 S 68 15 E T D - H E 7E
Samsung
NOR Flash Memory
Access Time
7E : Refer to Table 1
Device Type
S : Multiplexed Burst
Operating Temperature Range
C : Commercial Temp. (0 °C to 70 °C)
E : Extended Temp. (-25 °C to 85 °C)
Density (Note)
66 : 64Mbits 1)
68 : 64Mbits 2)
Package
F : FBGA, D : FBGA(Lead Free)
S : FBGA(Lead Free, OSP)
H : FBGA(Lead Free, OSP, Halogen Free)
Organization
15 : x16 Organization
Version
D : 5th Generation
Operating Voltage Range
E : 1.7 V to 1.95V
Block Architecture
T : Top Boot Block
B : Bottom Boot Block
NOTE :
Density : (1) 66 : 64Mb with the Sync MRS option (Extended Configuration Register)
(2) 68 : 64Mb with no option
-6-
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
[Table 1] PRODUCT LINE-UP
K8S6815E
Speed Option
7B
(54MHz)
7C
(66MHz)
Max. Initial Access Time (tIAA, ns)
70
70
70
70
Max. Burst Access Time (tBA, ns)
14.5
11
9
7
Mode
Synchronous/Burst
VCC=1.7V1.95V
Asynchronous
7D
(83MHz)
Max. Access Time (tAA, ns)
70
70
70
70
Max. CE Access Time (tCE, ns)
70
70
70
70
Max. OE Access Time (tOE, ns)
20
20
20
20
[Table 2] K8S6815E DEVICE BANK DIVISIONS
Bank 0
Bank 1 ~ Bank 7
Mbit
Block Sizes
Mbit
Block Sizes
4 Mbit
Eight 4Kwords,
Fifteen 32Kwords
60 Mbit
One hundred
twelve 32Kwords
[Table 3] K8S6815ETD DEVICE BANK DIVISIONS
Bank
Quantity of Blocks
Block Size
8
4 Kwords
15
32 Kwords
1
16
32 Kwords
2
16
32 Kwords
3
16
32 Kwords
4
16
32 Kwords
5
16
32 Kwords
6
16
32 Kwords
7
16
32 Kwords
Bank
Quantity of Blocks
Block Size
7
16
32 Kwords
6
16
32 Kwords
5
16
32 Kwords
4
16
32 Kwords
3
16
32 Kwords
2
16
32 Kwords
1
16
32 Kwords
15
32 Kwords
8
4 Kwords
0
[Table 4] K8S6815EBD DEVICE BANK DIVISIONS
0
7E
(108MHz)
-7-
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
7.0 PRODUCT INTRODUCTION
The K8S6815E is a 64Mbit (67,108,364 bits) NOR-type Burst Flash memory. The device features 1.8V single voltage power supply operating within the
range of 1.7V to 1.95V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is used to program EPROMs.
The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flexible erase and program capability, the device
adapts a block memory architecture that divides its memory array into 135 blocks (32-Kword x 127, 4-Kword x 8). Programming is done in units of 16
bits (Word). All bits of data in one or multiple blocks can be erased when the device executes the erase operation. To prevent the device from accidental
erasing or over-writing the programmed data, 135 memory blocks can be hardware protected. Regarding read access time, at 54MHz, the K8S6815E
provides a burst access of 14.5ns with initial access times of 70ns at 30pF. At 66MHz, the K8S6815E provides a burst access of 11ns with initial access
times of 70ns at 30pF. At 83MHz, the K8S6815E provides a burst access of 9ns with initial access times of 70ns at 30pF. At 108MHz, the K8S6815E
provides a burst access of 9ns with initial access times of 70ns at 30pF. The command set of K8S6815E is compatible with standard Flash devices. The
device uses Chip Enable (CE), Write Enable (WE), Address Valid(AVD) and Output Enable (OE) to control asynchronous read and write operation. For
burst operations, the device additionally requires Ready (RDY) and Clock (CLK). Device operations are executed by selective command codes. The
command codes to be combined with addresses and data are sequentially written to the command registers using microprocessor write timing. The
command codes serve as inputs to an internal state machine which controls the program/erase circuitry. Register contents also internally latch
addresses and data necessary to execute the program and erase operations. The K8S6815E is implemented with Internal Program/Erase Routines to
execute the program/erase operations. The Internal Program/Erase Routines are invoked by program/erase command sequences. The Internal Program Routine automatically programs and verifies data at specified address. The Internal Erase Routine automatically pre-programs the memory cell
which is not programmed and then executes the erase operation. The K8S6815E has means to indicate the status of completion of program/erase operations. The status can be indicated via Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device automatically
resets itself to the read mode. The device requires 24mA burst read current and 15mA for program/erase operations.
[Table 5] Device Bus Operations
Operation
Asynchronous Read Operation
Write
Standby
Hardware Reset
Load Initial Burst Address
Burst Read Operation
Terminate Burst Read Cycle via CE
Terminate Burst Read Cycle via RESET
Terminate Current Burst Read Cycle and Start
New Burst Read Cycle
CE
OE
WE
A16-21
A/DQ0-15
RESET
CLK
L
L
H
Add In
Add In/DOUT
H
L
L
H
L
Add In
Add In / DIN
H
L
H
X
X
X
High-Z
H
X
X
X
X
X
X
High-Z
L
X
X
L
H
H
Add In
Add In
H
L
L
H
X
Burst
DOUT
H
H
X
X
X
High-Z
H
X
X
X
X
X
X
High-Z
L
X
X
L
H
H
Add In
Add In
H
NOTE :
L=VIL (Low), H=VIH (High), X=Don’t Care.
-8-
AVD
H
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
8.0 COMMAND DEFINITIONS
The K8S6815E operates by selecting and executing its operational modes. Each operational mode has its own command set. In order to select a certain
mode, a proper command with specific address and data sequences must be written into the command register. Writing incorrect information which
include address and data or writing an improper command will reset the device to the read mode. The defined valid register command sequences are
stated in Table 6.
[Table 6] Command Sequences
Command Definitions
Asynchronous Read
Cycle
Add
Data
Add
Reset5)
Data
Add
Autoselect
6)
Manufacturer ID
Data
Autoselect
Add
Device ID6)
Data
Autoselect
Add
Block Protection Verify7)
Data
Autoselect
Add
16)
Handshaking
Program
Unlock Bypass
Unlock Bypass Program8)
Unlock Bypass Block Erase8)
Unlock Bypass Chip Erase8)
Unlock Bypass Reset
Quadruple word Accelerated Program9)
Chip Erase
Block Erase
Erase Suspend 10)
Erase Resume 11)
Program Suspend 12)
Program Resume 11)
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
1
1
4
4
4
4
4
3
2
2
2
2
5
6
6
1
1
1
1
1st Cycle
2nd Cycle 3rd Cycle
4th Cycle
5th Cycle
6th Cycle
RA
RD
XXXH
F0H
555H
2AAH
(DA)555H
(DA)X00H
AAH
55H
90H
ECH
555H
2AAH
(DA)555H
(DA)X01H
AAH
55H
90H
Table 11
555H
2AAH
(BA)555H
(BA)X02H
AAH
55H
90H
555H
2AAH
(DA)555H
00H / 01H
(DA)X03H
AAH
55H
90H
0H/1H
555H
2AAH
555H
PA
PD
AAH
55H
A0H
555H
2AAH
555H
AAH
55H
20H
XXX
PA
A0H
PD
XXX
BA
80H
30H
XXXH
XXXH
80H
10H
XXXH
XXXH
90H
00H
XXX
PA1
PA2
PA3
PA4
A5H
PD1
PD2
PD3
PD4
555H
2AAH
555H
555H
2AAH
555H
AAH
55H
80H
AAH
55H
10H
555H
2AAH
555H
555H
2AAH
BA
AAH
55H
80H
AAH
55H
30H
(DA)XXXH
B0H
(DA)XXXH
30H
(DA)XXXH
B0H
(DA)XXXH
30H
-9-
datasheet
K8S6815ET(B)D
Command Definitions
Block Protection/Unprotection 13)
CFI Query 14)
Set Burst Mode Configuration Register15)
Set Extended Configuration Register17)
Enter OTP Block Region
Exit OTP Block Region
Rev. 1.2
Cycle
Add
Data
Add
Data
Add
Data
Add
Data
Addr
Data
Addr
Data
1st Cycle
2nd Cycle
3rd Cycle
XXX
XXX
ABP
60H
60H
60H
555H
2AAH
(CR)555H
AAH
55H
C0H
555H
2AAH
(CR)555H
AAH
55H
C5H
555H
2AAH
555H
AAH
55H
70H
555H
2AAH
555H
XXX
AAH
55H
75H
00H
3
1
NOR FLASH MEMORY
4th Cycle
5th Cycle
(DA)X55H
98H
3
3
3
4
NOTE :
1) RA : Read Address , PA : Program Address, RD : Read Data, PD : Program Data , BA : Block Address (A21 ~ A12)
DA : Bank Address (A21 ~ A18) , ABP : Address of the block to be protected or unprotected , DI :Die revision ID, CR : Configuration Register Setting
2) The 4th cycle data of autoselect mode and RD are output data. The others are input data.
3) Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD and Device ID.
4) Unless otherwise noted, address bits A21 ~ A11 are don’t cares.
5) The reset command is required to return to read mode.
If a bank entered the autoselect mode during the erase suspend mode, writing the reset command returns that bank to the erase suspend mode.
If a bank entered the autoselect mode during the program suspend mode, writing the reset command returns that bank to the program suspend mode.
If DQ5 goes high during the program or erase operation, writing the reset command returns that bank to read mode or erase suspend mode if that
bank was in erase suspend mode.
6) The 3rd and 4th cycle bank address of autoselect mode must be same.
7) Normal Block Protection Verify : 00H for an unprotected block and 01H for a protected block.
OTP Block Protect verify (with OTP Block Address after Entering OTP Block) : 00H for unlocked, and 01H for locked.
For OTP Block Protection Verify, 3rd command cycle is (DA)555H/90H. DA(Bank address) should be invoked instead of BA(Block address).
8) The unlock bypass command sequence is required prior to this command sequence.
9) Quadruple word accelerated program is invoked only at Vpp=VID ,Vpp setup is required prior to this command sequence.
PA1, PA2, PA3, PA4 have the same A21~A2 address.
10) The system may read and program in non-erasing blocks when in the erase suspend mode.
The system may enter the autoselect mode when in the erase suspend mode.
The erase suspend command is valid only during a block erase operation, and requires the bank address.
11) The erase/program resume command is valid only during the erase/program suspend mode, and requires the bank address.
12) This mode is used only to enable Data Read by suspending the Program operation.
13) Set block address(BA) as either A6 = VIH, A1 = VIH and A0 = VIL for unprotected or A6 = VIL, A1 = VIH and A0 = VIL for protected.
14) Command is valid when the device is in Read mode or Autoselect mode.
15) See "Set Burst Mode Configuration Register" for details.
On the third cycle, the data should be "C0h" and address bits A20-A12 set the code to be latched.
16) 0H for handshaking, 1H for non-handshaking
17) CR is XXXA12 + 555h In Extended Configuration Register
- 10 -
6th Cycle
K8S6815ET(B)D
datasheet
Rev. 1.2
NOR FLASH MEMORY
9.0 DEVICE OPERATION
The device has I/Os that accept both address and data information. To write a command or command sequence (which includes programming data to the
device and erasing blocks of memory), the system must drive CLK, AVD and CE to VIL and OE to VIH when providing an address to the device, and drive
CLK, WE and CE to VIL and OE to VIH when writing commands or data.
The device provide the unlock bypass mode to save its program time for program operation. Unlike the standard program command sequence which is
comprised of four bus cycles, only two program cycles are required to program a word in the unlock bypass mode. One block, multiple blocks, or the
entire device can be erased. Table 3 indicates the address space that each block occupies. The device’s address space is divided into eight banks: Bank
0 contains the boot/parameter blocks, and the other banks(from Bank 1 to 7) consist of uniform blocks. A “bank address” is the address bits required to
uniquely select a bank. Similarly, a “block address” is the address bits required to uniquely select a block. ICC2 in the DC Characteristics table represents
the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations.
9.1 Read Mode
The device automatically enters to asynchronous read mode after device power-up. No commands are required to retrieve data in asynchronous mode.
After completing an Internal Program/Erase Routine, each bank is ready to read array data. The reset command is required to return a bank to the read(or
erase-suspend-read)mode if DQ5 goes high during an active program/erase operation, or if the bank is in the autoselect mode.
The synchronous(burst) mode will automatically start on the last rising edge of the CLK input while AVD is held low. That means device enters burst
read mode from asynchronous read mode to burst read mode using CLK and AVD signal. When the burst read is finished(or terminated), the device
return to asynchronous read mode automatically.
(1) K8S6615ET(B)D : Sync MRS option (Extended Configuration Register)
The synchronous(burst) mode will automatically start on the rising edge of the CLK input while AVD is held low after Extended Mode Register
Setting to A12=1. If several CLKs exist in AVD low, the last rising edge is valid CLK.
(2) K8S6815ET(B)D : No sync MRS option
The synchronous(burst) mode will automatically start on the rising edge of the CLK input while AVD is held low. If several CLKs exist in AVD
low, the last rising edge is valid CLK.
9.1.1 Asynchronous Read Mode
For the asynchronous read mode a valid address should be asserted on A/DQ0-A/DQ15 and A16-A21, while driving AVD and CE to VIL. WE should
remain at VIH . Note that CLK must remain low for asynchronous read mode. The address is latched at the rising edge of AVD, and then the system can
drive OE to VIL. The data will appear on A/DQ0-A/DQ15. Since the memory array is divided into sixteen banks, each bank remains enabled for read
access until the command register contents are altered.
Address access time (tAA) is equal to the delay from valid addresses to valid output data. The chip enable access time(tCE) is the delay from the falling
edge of CE to valid data at the outputs. The output enable access time(tOE) is the delay from the falling edge of OE to valid data at the output. The asynchronous access time is measured from a valid address, falling edge of AVD or falling edge of CE whichever occurs last. To prevent the memory content
from spurious altering during power transition, the initial state machine is set for reading array data upon device power-up, or after a hardware reset.
9.1.2 Synchronous (Burst) Read Mode
The device is capable of continuous linear burst operation and linear burst operation of a preset length. For the burst mode, the system should determine how many clock cycles are desired for the initial word(tIAA) of each burst access and what mode of burst operation is desired using "Burst Mode
Configuration Register" command sequences. See "Set Burst Mode Configuration" for further details. The status data also can be read during burst read
mode by using AVD signal with a bank address. To initiate the synchronous read again, a new address and AVD pulse is needed after the host has completed status reads or the device has completed the program or erase operation.
Continuous Linear Burst Read
(1) K8S6615ET(B)D : Sync MRS option (Extended Configuration Register)
The synchronous(burst) mode will automatically start on the rising edge of the CLK input while AVD is held low after Extended Mode Register
Setting to A12=1. If several CLKs exist in AVD low, the last rising edge is valid CLK.
(2) K8S6815ET(B)D : No sync MRS option
The synchronous(burst) mode will automatically start on the rising edge of the CLK input while AVD is held low. If several CLKs exist in AVD
low, the last rising edge is valid CLK.
Note that the device is enabled for asynchronous mode when it first powers up. The initial word is output tIAA after the rising edge of the last CLK cycle.
Subsequent words are output tBA after the rising edge of each successive clock cycle, which automatically increments the internal address counter. Note
that the device has internal address boundary that occurs every 16 words. When the device is crossing the first word boundary, additional clock cycles are
needed before data appears for the next address. The number of additional clock cycle can vary from zero to seven cycles, and the exact number of additional clock cycle depends on the starting address of burst read. The RDY output indicates this condition to the system by pulsing low. The device will continue to output sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location until the system
asserts CE high, RESET low or AVD low in conjunction with a new address.(See Table 5.) The reset command does not
- 11 -
K8S6815ET(B)D
datasheet
Rev. 1.2
NOR FLASH MEMORY
terminate the burst read operation. When it accessed the bank is programming or erasing , continuous burst read mode will output status data. And status
data will be sustained until the system asserts CE high or RESET low or AVD low in conjunction with a new address. Note that at least 10ns is needed
to start next burst read operation from terminating previous burst read operation in the case of asserting CE high.
8-,16-Word Linear Burst Read
As well as the Continuous Linear Burst Mode, there are two(8 & 16 word) linear wrap, in which a fixed number of words are read from consecutive
addresses. In these modes, the addresses for burst read are determined by the group within which the starting address falls. The groups are sized
according to the number of words read in a single burst sequence for a given mode.(See Table. 7)
[Table 7] Burst Address Groups(Wrap mode only)
Burst Mode
Group Size
Group Address Ranges
8 word
8 words
0-7h, 8-Fh, 10-17h, ....
16 word
16 words
0-Fh, 10-1Fh, 20-2Fh, ....
As an example:
In wrap mode case, if the starting address in the 8-word mode is 2h, the address range to be read would be 0-7h, and the wrap burst sequence would be
2-3-4-5-6-7-0-1h. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group. In a
similar manner, 16-word wrap mode begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the
selected address group.
Output Driver Setting
The device supports four kinds of output driver setting for matching the system characteristics. The users can tune the output driver impedance of the
data and RDY outputs by address bits A20-A19. (See Configuration Register Table) The users can set the output driver strength independently for precise
system characteristic matching. Table 8 shows which output driver would be tuned and the strength according to A20-A19. Upon power-up or reset, the
register will revert to the default setting.
9.2 Programmable Wait State
The programmable wait state feature indicates to the device the number of additional clock cycles that must elapse after AVD is driven active for burst
read mode. Upon power up, the number of total initial access cycles defaults to eight.
9.3 Handshaking
The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst data is ready
to be read. To set the number of initial cycle for optimal burst mode, the host should use the programmable wait state configuration.(See "Set Burst Mode
Configuration Register" for details.) The rising edge of RDY after OE goes low indicates the initial word of valid burst data. Using the autoselect command
sequence the handshaking feature may be verified in the device.
- 12 -
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
9.4 Set Burst Mode Configuration Register
The device uses a configuration register to set the various burst parameters : the number of initial cycles for burst and burst read mode. The burst mode
configuration register must be set before the device enters burst mode.
The burst mode configuration register is loaded with a three-cycle command sequences. On the third cycle, the data should be C0h, address bits A11A0 should be 555h, and address bits A20-A12 set the code to be latched. The device will power up or after a hardware reset with the default setting.
[Table 8] Burst Mode Configuration Register Table
Address Bit
Function
Settings(Binary)
Output Driver Control
00 = Driver Multiplier : 1/3
01 = Driver Multiplier : 1/2
10 = Driver Multiplier : 1 (Default)
11 = Driver Multiplier : 1.5
RDY Active
1 = RDY active one clock cycle before data
0 = RDY active with data(default)
Burst Read Mode
000 = Continuous(default)
001 = 8-word linear with wrap
010 = 16-word linear with wrap
011 ~ 111 = Reserve
Programmable Wait State
000 = Data is valid on the 4th active CLK edge after AVD transition to VIH (50/54Mhz)
001 = Data is valid on the 5th active CLK edge after AVD transition to VIH (60/66/70Mhz)
010 = Data is valid on the 6th active CLK edge after AVD transition to VIH (80/83Mhz)
011 = Data is valid on the 7th active CLK edge after AVD transition to VIH (90/100Mhz)
100 = Data is valid on the 8th active CLK edge after AVD transition to VIH (108Mhz,default)
101 = Reserve
110 = Reserve
111 = Reserve
A20
A19
A18
A17
A16
A15
A14
A13
A12
Note: Initial wait state should be set according to it’s clock frequency. Table 8 recommends the program wait state for each clock frequencies. Not 100% tested
9.4.1 Extended Configuration Register (option : K8S6615ET(B)D only)
The synchronous(burst) mode will start on the last rising edge of the CLK input while AVD is held low after Extended Mode Register Setting to A12=1.
[Table 9] Extended Configuration Register table
Address Bit
A12
Function
Settings(Binary)
Read Mode
0 = Asynchronous Read Mode(default)
1 = Synchronous Burst Read Mode
9.4.2 Programmable Wait State Configuration
This feature informs the device of the number of clock cycles that must elapse after AVD# is driven active before data will be available. This value is
determined by the input frequency of the device. Address bits A14-A12 determine the setting. (See Burst Mode Configuration Register Table)
The Programmable wait state setting instructs the device to set a particular number of clock cycles for the initial access in burst mode. Note that hardware reset will set the wait state to the default setting, that is 8 initial cycles.
9.4.3 Burst Read Mode Setting
The device supports three different burst read modes : continuous linear mode, 8 and 16 word linear burst modes with wrap
9.4.4 RDY Configuration
By default, the RDY pin will be high whenever there is valid data on the output. The device can be set so that RDY goes active one data cycle before
active data. Address bit A18 determine this setting. Note that RDY always go high with valid data in case of word boundary crossing.
[Table 10] Burst Address Sequences
Wrap
Burst Address Sequence
Start
Addr.
Continuous Burst
8-word Burst
16-word Burst
0
0-1-2-3-4-5-6...
0-1-2-3-4-5-6-7
0-1-2-3-4-....-D-E-F
1
1-2-3-4-5-6-7...
1-2-3-4-5-6-7-0
1-2-3-4-5-....-E-F-0
2
2-3-4-5-6-7-8...
2-3-4-5-6-7-0-1
2-3-4-5-6-....-F-0-1
.
.
.
.
.
.
.
.
- 13 -
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
9.5 Autoselect Mode
By writing the autoselect command sequences to the system, the device enters the autoselect mode. This mode can be read only by asynchronous read
mode. The system can then read autoselect codes from the internal register(which is separate from the memory array). Standard asynchronous read
cycle timings apply in this mode. The device offers the Autoselect mode to identify manufacturer and device type by reading a binary code. In addition,
this mode allows the host system to verify the block protection or unprotection. Table 11 shows the address and data requirements. The autoselect command sequence may be written to an address within a bank that is in the read mode, erase-suspend-read mode or program-suspend-read mode. The
autoselect command may not be written while the device is actively programming or erasing in the device. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the address and the autoselect command. Note that the block
address is needed for the verification of block protection. The system may read at any address within the same bank any number of times without initiating another autoselect command sequence. And the burst read should be prohibited during Autoselect Mode. To terminate the autoselect operation,
write Reset command(F0H) into the command register.
[Table 11] Autoselect Mode Description
Description
Address
Read Data
Manufacturer ID
(DA) + 00H
ECH
Device ID
(DA) + 01H
227AH(Top), 227BH(Bottom)
Block Protection/Unprotection
(BA) + 02H
01H (protected), 00H (unprotected)
Handshaking
(DA) + 03H
0H : handshaking, 1H : non-handshaking
9.6 Standby Mode
When the CE and RESET inputs are both held at VCC ± 0.2V or the system is not reading or writing, the device enters Stand-by mode to minimize the
power consumption. In this mode, the device outputs are placed in the high impedance state, independent of the OE input. When the device is in either of
these standby modes, the device requires standard access time (tCE) for read access before it is ready to read data. If the device is deselected during
erasure or programming, the device draws active current until the operation is completed. ICC5 in the DC Characteristics table represents the standby current specification.
9.7 Automatic Sleep Mode
The device features Automatic Sleep Mode to minimize the device power consumption during both asynchronous and burst mode. When addresses
remain stable for tAA+60ns, the device automatically enables this mode. The automatic sleep mode is independent of the CE, WE, and OE control signals. In a sleep mode, output data is latched and always available to the system. When addresses are changed, the device provides new data without
wait time. Automatic sleep mode current is equal to standby mode current.
9.8 Output Disable Mode
When the OE input is at VIH , output from the device is disabled. The outputs are placed in the high impedance state.
9.9 Block Protection & Unprotection
To protect the block from accidental writes, the block protection/unprotection command sequence is used. On power up, all blocks in the device are protected. To unprotect a block, the system must write the block protection/unprotection command sequence. The first two cycles are written: addresses are
don’t care and data is 60h. Using the third cycle, the block address (ABP) and command (60h) is written, while specifying with addresses A6, A1 and A0
whether that block should be protected (A6 = VIL, A1 = VIH, A0 = VIL) or unprotected (A6 = VIH, A1 = VIH, A0 = VIL). After the third cycle, the system can
continue to protect or unprotect additional cycles, or exit the sequence by writing F0h (reset command).
The device offers three types of data protection at the block level:
• The block protection/unprotection command sequence disables or re-enables both program and erase operations in any block.
• When WP is at VIL, the two outermost blocks are protected.
• When VPP is at VIL, all blocks are protected.
Note that user never float the Vpp and WP, that is, Vpp is always connected with VIH, VIL or VID and WP is VIH or VIL.
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K8S6815ET(B)D
datasheet
Rev. 1.2
NOR FLASH MEMORY
9.10 Hardware Reset
The device features a hardware method of resetting the device by the RESET input. When the RESET pin is held low(VIL) for at least a period of tRP, the
device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write commands for the duration of the RESET pulse.
The device also resets the internal state machine to asynchronous read mode. To ensure data integrity, the interrupted operation should be reinitiated
once the device is ready to accept another command sequence. As previously noted, when RESET is held at VSS ± 0.2V, the device enters standby
mode. The RESET pin may be tied to the system reset pin. If a system reset occurs during the Internal Program or Erase Routine, the device will be automatically reset to the asynchronous read mode; this will enable the systems microprocessor to read the boot-up firmware from the Flash memory. If
RESET is asserted during a program or erase operation, the device requires a time of tREADY (during Internal Routines) before the device is ready to
read data again. If RESET is asserted when a program or erase operation is not executing, the reset operation is completed within a time of tREADY (not
during Internal Routines). tRH is needed to read data after RESET returns to VIH. Refer to the AC Characteristics tables for RESET parameters and to
Figure 10 for the timing diagram.
9.11 Software Reset
The reset command provides that the bank is reset to read mode, erase-suspend-read mode or program-suspend-read mode. The addresses are in
Don’t Care state. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins, or in an program command sequence before programming begins. If the device begins erasure or programming, the reset command is ignored until the operation
is completed. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to
the erase-suspend-read mode. The reset command valid between the sequence cycles in an autoselect command sequence. In an autoselect mode,
the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the
reset command returns that bank to the erase-suspend-read mode. Also, if a bank entered the autoselect mode while in the Program Suspend mode,
writing the reset command returns that bank to the program-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the
reset command returns the banks to the read mode. (or erase-suspend-read mode if the bank was in Erase Suspend)
9.12 Program
The K8S6815E can be programmed in units of a word. Programming is writing 0's into the memory array by executing the Internal Program Routine. In
order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles are unlock cycles. The third cycle is
assigned for the program setup command. In the last cycle, the address of the memory location and the data to be programmed at that location are written. The device automatically generates adequate program pulses and verifies the programmed cell margin by the Internal Program Routine. During the
execution of the Routine, the system is not required to provide further controls or timings. During the Internal Program Routine, commands written to the
device will be ignored.
Note that a hardware reset during a program operation will cause data corruption at the corresponding location.
9.13 Accelerated Program Operation
The device provides Single/Quadruple word accelerated program operations through the Vpp input. Using this mode, faster manufacturing throughput at
the factory is possible. When VID is asserted on the Vpp input, the device automatically enters the Unlock Bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for program operations. By removing VID returns the device to normal
operation mode.
Note that Read while Accelerated Program and Program suspend mode are not guaranteed
Single word accelerated program operation
The system would use two-cycle program sequence (One-cycle (XXX - A0H) is for single word program command, and Next one-cycle (PA - PD) is for
program address and data).
Quadruple word accelerated program operation
As well as Single word accelerated program, the system would use five-cycle program sequence (One-cycle (XXX - A5H) is for quadruple word program
command, and four cycles are for program address and data).
•
•
•
•
Only four words programming is possible
Each program address must have the same A21~A2 address
The device automatically generates adequate program pulses and ignores other command after program command
Program/Erase cycling must be limited below 100cycles for optimum performance.
• Read while Write mode is not guaranteed
Requirements : Ambient temperature : TA=30°C±10°C
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K8S6815ET(B)D
datasheet
Rev. 1.2
NOR FLASH MEMORY
9.14 Unlock Bypass
The K8S6815E provides the unlock bypass mode to save its operation time. This mode is possible for program, block erase and chip erase operation.
There are two methods to enter the unlock bypass mode. The mode is invoked by the unlock bypass command sequence or the assertion of VID on VPP
pin. Unlike the standard program/erase command sequence that contains four bus cycles, the unlock bypass program/erase command sequence comprises only two bus cycles. The unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus
cycles. Writing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H). Once the device is in the unlock bypass
mode, the unlock bypass program/erase command sequence is necessary. The unlock bypass program command sequence is comprised of only two bus
cycles; writing the unlock bypass program command (A0H) is followed by the program address and data. This command sequence is the only valid one
for programming the device in the unlock bypass mode. Also, The unlock bypass erase command sequence is comprised of two bus cycles; writing the
unlock bypass block erase command(80H-30H) or writing the unlock bypass chip erase command(80H-10H). This command sequences are the only
valid ones for erasing the device in the unlock bypass mode. The unlock bypass reset command sequence is the only valid command sequence to exit
the unlock bypass mode. The unlock bypass reset command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains only the data (00H). Then, the device returns to the read mode.
To enter the unlock bypass mode in hardware level, the VID also can be used. By assertion VID on the VPP pin, the device enters the unlock bypass
mode. Also, the all blocks are temporarily unprotected when the device using the VID for unlock bypass mode. To exit the unlock bypass mode, just
remove the asserted VID from the VPP pin.(Note that user never float the Vpp, that is, Vpp is always connected with VIH, VIL or VID.).
9.15 Chip Erase
To erase a chip is to write 1′s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus cycles to write the
command sequence. The erase set-up command is written after first two “unlock” cycles. Then, there are two more write cycles prior to writing the chip
erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory for an all zero data pattern prior to erasing. The
automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when DQ7 is "1". After that the device returns
to the read mode.
9.16 Block Erase
To erase a block is to write 1′s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six bus cycles to write the
command sequence shown in Table 6. After the first two "unlock" cycles, the erase setup command (80H) is written at the third cycle. Then there are two
more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory prior
to erasing it. The block address is latched on the rising edge of AVD , while the Block Erase command is latched on the rising edge of WE. Multiple blocks
can be erased sequentially by writing the sixth bus-cycle. Upon completion of the last cycle for the Block Erase, additional block address and the Block
Erase command (30H) can be written to perform the Multi-Block Erase. For the Multi-Block Erase, only sixth cycle(block address and 30H) is
needed.(Similarly, only second cycle is needed in unlock bypass block erase.) An 50us (typical) "time window" is required between the Block Erase command writes. The Block Erase command must be written within the 50us "time window", otherwise the Block Erase command will be ignored. The 50us
"time window" is reset when the falling edge of the WE occurs within the 50us of "time window" to latch the Block Erase command. During the 50us of
"time window", any command other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After
the 50 us of "time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase address and
command following the exceeded "time window" may or may not be accepted. No other commands will be recognized except the Erase Suspend command during Block Erase operation.
The device provides accelerated erase operations through the Vpp input. When VID is asserted on the Vpp input, the device automatically enters the
Unlock Bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for erase. By
removing VID returns the device to normal operation mode.
9.17 Erase Suspend / Resume
The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. Also, it is possible to protect or
unprotect of the block that is not being erased in erase suspend mode. The Erase Suspend command is only valid during the Block Erase operation
including the time window of 50us. The Erase Suspend command is not valid while the Chip Erase or the Internal Program Routine sequence is running.
When the Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 20us(recovery time) to suspend the
erase operation. Therefore system must wait for 20us(recovery time) to read the data from the bank which include the block being erased. Otherwise,
system can read the data immediately from a bank which don’t include the block being erased without recovery time(max. 20us) after Erase Suspend
command. And, after the maximum 20us recovery time, the device is available for programming data in a block that is not being erased. But, when the
Erase Suspend command is written during the block erase time window (50us), the device immediately terminates the block erase time window and suspends the erase operation. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. When the
Erase Resume command is executed, the Block Erase operation will resume. When the Erase Suspend or Erase Resume command is executed, the
addresses are in Don't Care state. In erase suspend followed by resume operation, min. 200ns is needed for checking the busy status.
In the program suspend mode, protect/unprotect command is prohibited.
While erase can be suspended and resumed multiple times, a minimum 30us is required from resume to the next suspend.
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K8S6815ET(B)D
datasheet
Rev. 1.2
NOR FLASH MEMORY
9.18 Program Suspend / Resume
The device provides the Program Suspend/Resume mode. This mode is used to enable Data Read by suspending the Program operation. The device
accepts a Program Suspend command in Program mode(including Program operations performed during Erase Suspend) but other commands are
ignored. After input of the Program Suspend command, 10us is needed to enter the Program Suspend Read mode. Therefore system must wait for
10us(recovery time) to read the data from the bank which include the block being programmed. Otherwise, system can read the data immediately from a
bank which don't include block being programmed without recovery time(max. 10us) after Program Suspend command. Like an Erase Suspend mode,
the device can be returned to Program mode by using a Program Resume command. In program suspend followed by resume operation, min. 200ns is
needed for checking the busy status.
While program operation can be suspended and resumed multiple times, a minimum 30us is required from resume to the next suspend.
9.19 Read While Write Operation
The device is capable of reading data from one bank while writing in the other banks. This is so called the Read While Write operation. An erase operation
may also be suspended to read from or program to another location within the same bank(except the block being erased). The Read While Write operation is prohibited during the chip erase operation. Figure 17 shows how read and write cycles may be initiated for simultaneous operation with zero
latency. Refer to the DC Characteristics table for read-while-write current specifications.
9.20 OTP Block Region
The OTP Block feature provides a 256-word Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN).
The OTP Block is customer lockable and shipped with itself unlocked, allowing customers to utilize the that block in any manner they choose. The customer-lockable OTP Block has the Protection Verify Bit (DQ0) set to a "0" for Unlocked state or a "1" for Locked state.
The system accesses the OTP Block through a command sequence (see "Enter OTP Block / Exit OTP Block Command sequence" at Table 6). After the
system has written the "Enter OTP Block" Command sequence, it may read the OTP Block by using the address (3FFF00h~3FFFFFh, in top boot
device),(000000h~0000FFh, in bottom boot device)normally and may check the Protection Verify Bit (DQ0) by using the "Autoselect Block Protection Verify" Command sequence with OTP Block address. This mode of operation continues until the system issues the "Exit OTP Block" Command sequence, a
hardware reset or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to main
blocks. Note that the Accelerated function and unlock bypass modes are not available when the OTP Block is enabled.
Customer Lockable
In a Customer lockable device, The OTP Block is one-time programmable and can be locked only once. Note that the Accelerated programming and
Unlock bypass functions are not available when programming the OTP Block. Locking operation to the OTP Block is started by writing the "Enter OTP
Block" Command sequence, and then the "Block Protection" Command sequence (Table 6) with an OTP Block address. Hardware reset terminates Locking operation, and then makes exiting from OTP Block. The Locking operation has to be above 100us. (After 3rd cycle of protection command invoked, at
least 100us wait time is required.) "Exit OTP Block" command sequence and Hardware reset makes locking operation finished and then exiting from OTP
Block after 30us.
The OTP Block Lock operation must be used with caution since, once locked, there is no procedure available for unlocking and none of the
bits in the OTP Block space can be modified in any way.
Suspend and resume operation are not supported during OTP protect, nor is OTP protect supported during any suspend operations.
Write Pulse “Glitch” Protection
Noise pulses of less than 5ns (typical) on OE, CE, AVD or WE do not initiate a write cycle.
9.21 Low VCC Write Inhibit
To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than VLKO. If the Vcc < VLKO (Lock-Out
Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the device will reset itself to the read mode.Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the user’s responsibility to ensure that the control pins are logically correct to
prevent unintentional writes when Vcc is above VLKO.
9.22 Logical Inhibit
Write cycles are inhibited by holding any one of OE = VIL , CE = VIH or WE = VIH. To initiate a write cycle, CE and WE must be a logical zero while OE is
a logical one.
9.23 Power-up Protection
To avoid initiation of a write cycle during VCC power-up, RESET low must be asserted during Power-up. After RESET goes high. the device is reset to the
read mode.
- 17 -
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
10.0 FLASH MEMORY STATUS FLAGS
The K8S6815E has means to indicate its status of operation in the bank where a program or erase operation is in processes. Address must include
bank address being executed internal routine operation. The status is indicated by raising the device status flag via corresponding DQ pins. The status
data can be read during burst read mode by using AVD signal with a bank address. That means status read is supported in synchronous mode. If status
read is performed, the data provided in the burst read is identical to the data in the initial access. To initiate the synchronous read again, a new address
and AVD pulse is needed after the host has completed status reads or the device has completed the program or erase operation. The corresponding DQ
pins are DQ7, DQ6, DQ5, DQ3 and DQ2.
[Table 12] Hardware Sequence Flags
Status
DQ7
DQ6
DQ5
DQ3
DQ2
Programming
DQ7
Toggle
0
0
1
Block Erase or Chip Erase
0
Toggle
0
1
Toggle
Erase Suspend Read
Erase Suspended
Block
1
1
0
0
Toggle1)
Erase Suspend Read
Non-Erase Suspended
Block
Data
Data
Data
Data
Data
Erase Suspend
Program
Non-Erase Suspended
Block
DQ7
Toggle
0
0
1
Program Suspend Read
Program Suspended
Block
DQ7
1
0
0
Toggle1)
Program Suspend Read
Non- program
Suspended Block
Data
Data
Data
Data
Data
Programming
DQ7
Toggle
1
0
No
Toggle
Block Erase or Chip Erase
0
Toggle
1
1
(Note 2)
Erase Suspend Program
DQ7
Toggle
1
0
No
Toggle
In Progress
Exceeded
Time Limits
NOTE :
1) DQ2 will toggle when the device performs successive read operations from the erase/program suspended block.
2) If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle.
DQ7 : Data Polling
When an attempt to read the device is made while executing the Internal Program, the complement of the data is written to DQ7 as an indication of the
Routine in progress. When the Routine is completed an attempt to access to the device will produce the true data written to DQ7. When a user attempts
to read the block being erased or bank contains the block, DQ7 will be low. If the device is placed in the Erase/Program Suspend Mode, the status can
be detected via the DQ7 pin. If the system tries to read an address which belongs to a block that is being erase suspended, DQ7 will be high. And, if the
system tries to read an address which belongs to a block that is being program suspended, the output will be the true data of DQ7 itself. If a non-erasesuspended or non-program-suspended block address is read, the device will produce the true data to DQ7. If an attempt is made to program a protected
block, DQ7 outputs complements the data for approximately 1μs and the device then returns to the Read Mode without changing data in the block. If an
attempt is made to erase a protected block, DQ7 outputs complement data in approximately 100us and the device then returns to the Read Mode without erasing the data in the block.
DQ6 : Toggle Bit
Toggle bit is another option to detect whether an Internal Routine is in progress or completed. Once the device is at a busy state, DQ6 will toggle. Toggling
DQ6 will stop after the device completes its Internal Routine. If the device is in the Erase/Program Suspend Mode, an attempt to read an address that
belongs to a block that is being erased or programmed will produce a high output of DQ6. If an address belongs to a block that is not being erased or programmed, toggling is halted and valid data is produced at DQ6. If an attempt is made to program a protected block, DQ6 toggles for approximately 1us
and the device then returns to the Read Mode without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for
approximately 100μs and the device then returns to the Read Mode without erasing the data in the block. #OE or #CE should be toggled in each toggle bit
status read.
DQ5 : Exceed Timing Limits
If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure.
DQ3 : Block Erase Timer
The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50μs of the block erase time window expires. In this
case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write commands until the erase operation is
completed. DQ3 is Low if the block erase time window is not expired. Within the block erase time window, an additional block erase command (30H) can
be accepted. To confirm that the block erase command has been accepted, the software may check the status of DQ3 following each block erase command.
- 18 -
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
DQ2 : Toggle Bit 2
The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase/Program Suspend is in progress. When the device executes
the Internal Erase Routine, DQ2 toggles if the bank including an erasing block is read. Although the Internal Erase Routine is in the Exceeded Time Limits, DQ2 toggles if an erasing block in the Exceeded Time Limits is read. When the device is in the Erase/Program Suspend mode, DQ2 toggles only if
an address in the erasing or programming block is read. If a non-erasing or non-programmed block address is read during the Erase/Program Suspend
mode, then DQ2 will produce valid data. DQ2 will go High if the user tries to program a non-erase suspend block while the device is in the Erase Suspend mode. #OE or #CE should be toggled in each toggle bit status read.
RDY: Ready
Normally the RDY signal is used to indicate if new burst data is available at the rising edge of the clock cycle or not. If RDY is low state, data is not valid
at expected time, and if high state, data is valid. Note that, if CE is low and OE is high, the RDY is high state.
Start
Read(DQ0~DQ7)
Valid Address
Start
Read(DQ0~DQ7)
Valid Address
Read(DQ0~DQ7)
Valid Address
DQ7 = Data ?
DQ6 = Toggle ?
Yes
No
Yes
No
No
No
DQ5 = 1 ?
DQ5 = 1 ?
Yes
Yes
Read twice(DQ0~DQ7)
Valid Address
Read(DQ0~DQ7)
Valid Address
No
Yes
DQ6 = Toggle ?
DQ7 = Data ?
Yes
No
Fail
Fail
Pass
Figure 1: Data Polling Algorithms
Pass
Figure 2: Toggle Bit Algorithms
- 19 -
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
11.0 COMMON FLASH MEMORY INTERFACE
Common Flash Memory Interface is contrived to increase the compatibility of host system software. It provides the specific information of the device, such
as memory size and electrical features. Once this information has been obtained, the system software will know which command sets to use to enable
flash writes, block erases, and control the flash component.
When the system writes the CFI command(98H) to address 55H, the device enters the CFI mode. And then if the system writes the address shown in
Table 15, the system can read the CFI data. Query data are always presented on the lowest-order data outputs(DQ0-7) only. In word(x16) mode, the
upper data outputs(DQ8-15) is 00h. To terminate this operation, the system must write the reset command.
[Table 13] Common Flash Memory Interface Code
Addresses
(Word Mode)
Data
Query Unique ASCII string "QRY"
10H
11H
12H
0051H
0052H
0059H
Primary OEM Command Set
13H
14H
0002H
0000H
Address for Primary Extended Table
15H
16H
0040H
0000H
Alternate OEM Command Set (00h = none exists)
17H
18H
0000H
0000H
Address for Alternate OEM Extended Table (00h = none exists)
19H
1AH
0000H
0000H
Vcc Min. (write/erase)
D7-D4: volt, D3-D0: 100 millivolt
1BH
0017H
Vcc Max. (write/erase)
D7-D4: volt, D3-D0: 100 millivolt
1CH
0019H
Vpp(Acceleration Program) Supply Minimum
00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV
1DH
0085H
Vpp(Acceleration Program) Supply Maximum
00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV
1EH
0095H
Typical timeout per single word write 2N us
1FH
0004H
Description
Typical timeout for Min. size buffer write 2 us(00H = not supported)
20H
0000H
Typical timeout per individual block erase 2N ms
21H
000AH
Typical timeout for full chip erase 2N ms(00H = not supported)
22H
0011H
N
Max. timeout for word write 2 times typical
23H
0005H
Max. timeout for buffer write 2N times typical
24H
0000H
Max. timeout per individual block erase 2 times typical
25H
0004H
Max. timeout for full chip erase 2N times typical(00H = not supported)
26H
0000H
Device Size = 2 byte
27H
0017H
Flash Device Interface description
28H
29H
0000H
0000H
Max. number of byte in multi-byte write = 2N
2AH
2BH
0000H
0000H
Number of Erase Block Regions within device
2CH
0002H
N
N
N
- 20 -
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
Addresses
(Word Mode)
Data
Erase Block Region 1 Information
Bits 0~15: y+1=block number
Bits 16~31: block size= z x 256bytes
2DH
2EH
2FH
30H
0007H
0000H
0020H
0000H
Erase Block Region 2 Information
31H
32H
33H
34H
007EH
0000H
0000H
0001H
Erase Block Region 3 Information
35H
36H
37H
38H
0000H
0000H
0000H
0000H
Erase Block Region 4 Information
39H
3AH
3BH
3CH
0000H
0000H
0000H
0000H
Query-unique ASCII string "PRI"
40H
41H
42H
0050H
0052H
0049H
Major version number, ASCII
43H
0032H
Minor version number, ASCII
44H
0033H
Address Sensitive Unlock(Bits 1-0)
0 = Required, 1= Not Required
Silcon Revision Number(Bits 7-2)
45H
0000H
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46H
0002H
Block Protect
00 = Not Supported, 01 = Supported
47H
0001H
Block Temporary Unprotect 00 = Not Supported, 01 = Supported
48H
0000H
Block Protect/Unprotect scheme 00 = Not Supported, 01 = Supported
49H
0001H
Simultaneous Operation
00 = Not Supported, 01 = Supported
4AH
0001H
Burst Mode Type 00 = Not Supported, 01 = Supported
4BH
0001H
Page Mode Type
00 = Not Supported, 01 = 4 Word Page 02 = 8 Word Page
4CH
0000H
Top/Bottom Boot Block Flag
02H = Bottom Boot Device, 03H = Top Boot Device
4DH
0003H
Max. Operating Clock Frequency (MHz)
4EH
006CH
RWW(Read While Write) Functionality Restriction (00H = non exists , 01H = exists)
4FH
0000H
Handshaking
00 = Not Supported at both mode, 01 = Supported at Sync. Mode
10 = Supported at Async. Mode, 11 = Supported at both Mode
50H
0001H
Description
- 21 -
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
12.0 ABSOLUTE MAXI010MUM RATINGS
Parameter
Symbol
Vcc
Vcc
Voltage on any pin relative to VSS
VPP
Commercial
V
-0.5 to +9.5
-0.5 to +2.5
-10 to +125
Tbias
Extended
Unit
-0.5 to +2.5
VIN
All Other Pins
Temperature Under Bias
Rating
°C
-25 to +125
Storage Temperature
Tstg
-65 to +150
°C
Short Circuit Output Current
IOS
5
mA
TA (Commercial Temp.)
0 to +70
°C
TA (Extended Temp.)
-25 to + 85
°C
Operating Temperature
NOTE :
1) Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level may fall to -2.0V for periods <20ns.
Maximum DC voltage is Vcc+0.6V on input / output pins which, during transitions, may overshoot to Vcc+2.0V for periods <20ns.
2) Minimum DC input voltage is -0.5V on VPP. During transitions, this level may fall to -2.0V for periods <20ns.
Maximum DC input voltage is +9.5V on VPP which, during transitions, may overshoot to +12.0V for periods <20ns.
3) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
13.0 RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND)
Parameter
Symbol
Min
Typ.
Max
Unit
Supply Voltage
VCC
1.7
1.8
1.95
V
Supply Voltage
VSS
0
0
0
V
14.0 DC CHARACTERISTICS
Parameter
Symbol
Input Leakage Current
ILI
Test Conditions
Min
Typ
Max
Unit
VIN=VSS to VCC, VCC=VCCmax
- 1.0
-
+ 1.0
μA
VCC=VCCmax , VPP=VCCmax
- 1.0
-
+ 1.0
μA
-
-
35
μA
- 1.0
-
+ 1.0
μA
VPP Leakage Current
ILIP
Output Leakage Current
ILO
Active Burst Read Current
ICCB1
CE=VIL, OE=VIH (Continuous Burst, 108Mhz)
-
24
36
mA
Active Asynchronous
Read Current
ICC1
CE=VIL, OE=VIH
-
27
40
mA
Active Write Current (Note 2)
ICC2
CE=VIL, OE=VIH, WE=VIL, VPP=VIH
-
15
30
mA
Read While Write Current
ICC3
CE=VIL, OE=VIH
-
40
70
mA
Accelerated Program Current
ICC4
CE=VIL, OE=VIH , VPP=9.5V
-
15
30
mA
Standby Current
ICC5
CE= RESET=VCC ± 0.2V
-
15
50
μA
Standby Current During Reset
ICC6
RESET = VSS ± 0.2V
-
15
50
μA
ICC7
CE=VSS ± 0.2V, Other Pins=VIL or VIH
VIL = VSS ± 0.2V, VIH = VCC ± 0.2V
-
15
50
μA
Automatic Sleep Mode(Note 3)
VCC=VCCmax , VPP=9.5V
VOUT=VSS to VCC, VCC=VCCmax, OE=VIH
10MHz
Input Low Voltage
VIL
-0.5
-
0.4
V
Input High Voltage
VIH
VCC-0.4
-
VCC+0.4
V
Output Low Voltage
VOL
IOL = 100 μA , VCC=VCCmin
-
-
0.1
V
Output High Voltage
VOH
IOH = -100 μA , VCC=VCCmin
VCC-0.1
-
-
V
Voltage for Accelerated Program
VID
8.5
9.0
9.5
V
Low VCC Lock-out Voltage
VLKO
-
-
1.4
V
NOTE:
1) Maximum ICC specifications are tested with VCC = VCCmax.
2) ICC active while Internal Erase or Internal Program is in progress.
3) Device enters automatic sleep mode when addresses are stable for tAA + 60ns.
- 22 -
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
Vcc Power-up
Parameter
Symbol
Vcc Setup Time
Time between RESET (high) and CE (low)
All Speed Options
Max
tVCS
200
-
μs
tRH
200
-
ns
NOTE : Not 100% tested.
SWITCHING WAVEFORMS
tVCS
Vcc/Vccq
Unit
Min
tVCCmin
VIH
RESET
tRH
CE
Figure 3: Vcc Power-up Diagram
- 23 -
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
15.0 CAPACITANCE (TA = 25 °C, VCC = 1.8V, f = 1.0MHz)
Item
Symbol
Test Condition
Min
Max
Unit
Input Capacitance
CIN
VIN=0V
-
10
pF
Output Capacitance
COUT
VOUT=0V
-
10
pF
Control Pin Capacitance
CIN2
VIN=0V
-
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
16.0 AC TEST CONDITION
Parameter
Value
Input Pulse Levels
0V to VCC
Input Rise and Fall Times
3ns(max)@66Mhz, 2.5ns(max)@83Mhz, 1.5ns(max)@108Mhz
Input and Output Timing Levels
VCC/2
Output Load
CL = 30pF
Address to Address Skew
3ns(max)
Device
Under
Test
VCC
VCC/2
Input & Output
Test Point
VCC/2
0V
Input Pulse and Test Point (including CLK characterization)
* CL = 30pF including scope
and Jig capacitance
Output Load
- 24 -
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
17.0 AC CHARACTERISTICS
17.1 Synchronous/Burst Read
Parameter
7B
(54 MHz)
Symbol
7C
(66 MHz)
7D
(83 MHz)
7E
(108 MHz)
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Initial Access Time
tIAA
-
70
-
70
-
70
-
70
ns
Burst Access Time Valid Clock to Output Delay
tBA
-
14.5
-
11
-
9
-
7
ns
AVD Setup Time to CLK
tAVDS
5
-
5
-
4
-
4
-
ns
AVD Hold Time from CLK
tAVDH
2
-
2
-
2
-
2
-
ns
AVD High to OE Low
tAVDO
0
-
0
-
0
-
0
-
ns
Address Setup Time to CLK
tACS
5
-
4
-
4
-
3.5
-
ns
Address Hold Time from CLK
tACH
7
-
6
-
5
-
2
-
ns
Data Hold Time from Next Clock Cycle
tBDH
4
-
3
-
3
-
2
-
ns
Output Enable to Data
tOE
-
20
-
20
-
20
-
20
ns
Output Enable to RDY valid
tOER
-
14.5
-
11
-
9
-
7
ns
CE Disable to High Z
tCEZ
-
15
-
15
-
11
-
8.5
ns
OE Disable to High Z
tOEZ
-
9
-
9
-
9
-
9
ns
CE Setup Time to CLK
tCES
6
-
6
-
4.5
-
4.5
-
ns
CE Enable to RDY active
tRDY
-
7
-
7
-
7
-
7
ns
CLK to RDY Setup Time
tRDYA
-
14.5
-
11
-
9
-
7
ns
RDY Setup Time to CLK
tRDYS
4
-
3
-
3
-
2
-
ns
tCLK
18.5
-
15.1
-
12.05
-
9.26
-
ns
CLK High or Low Time
tCLKH/L
0.4x
tCLK
0.6x
tCLK
0.4x
tCLK
0.6x
tCLK
0.4x
tCLK
0.6x
tCLK
0.4x
tCLK
0.6x
tCLK
ns
CLK Fall or Rise Time
tCLKHCL
-
3
-
3
-
2.5
-
1.5
ns
CLK period
- 25 -
Rev. 1.2
datasheet
K8S6815ET(B)D
NOR FLASH MEMORY
SWITCHING WAVEFORMS
5 cycles for initial access shown.
CR setting : A14=0, A13=0, A12=1
15.2 ns typ(66Mhz).
tCES
tCEZ
≈
CE
5
CLK
≈
tAVDS
≈
tAVDO
AVD
tAVDH
A16-A21
tBA
tACH
Hi-Z
≈
A/DQ0:
A/DQ15
≈ ≈
tBDH
tACS
Aa
Aa
Da
tIAA
Da+1
Da+2
Da+n
Da+3
tOEZ
≈
OE
tOER
tRDYS
tRDYA
≈
RDY
Hi-Z
Hi-Z
Figure 4: Continuous Burst Mode Read (66MHz)
NOTE : In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.
8 cycles for initial access shown.
CR setting : A14=1, A13=0, A12=0
9.25ns typ(108MHz).
tCES
tCEZ
CE
≈
≈
2
1
CLK
3
6
7
8
≈
≈
≈
≈
tAVDS
tAVDS
tAVDO
AVD
4
tAVDH
tACH
tIAA
Da+3
Da+4
Da+5
Da+6
Da+n
tOEZ
tRDYS
tRDYA
≈
Hi-Z
Da+2
Figure 5: Continuous Burst Mode Read (108MHz)
NOTE : In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.
- 26 -
≈
RDY
tOER
Da+1
≈
tRDY
Da
≈
OE
Hi-Z
≈
Aa
tBA
≈ ≈
A/DQ0:
A/DQ15
tBDH
≈ ≈
A16-A21
≈ ≈
tACS
Aa
Hi-Z
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
SWITCHING WAVEFORMS
8 cycles for initial access shown.
CR setting : A14=1, A13=0, A12=0
9.25ns typ(108MHz).
tCES
≈
CE
3
4
AVD
6
7
8
≈
tAVDS
tAVDS
tAVDO
≈
2
1
CLK
tAVDH
A16-A21
tACH
Aa
tIAA
tOER
tRDY
RDY
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D4
D5
D6
D7
D0
≈
OE
tBA
≈ ≈
A/DQ0:
A/DQ15
tBDH
≈ ≈
tACS
Aa
tRDYS
tRDYA
≈
Hi-Z
Figure 6: 8 word Linear Burst Mode with Wrap Around (108MHz)
NOTE : In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.
8 cycles for initial access shown.
CR setting : A14=1, A13=0, A12=0
9.25ns typ(108MHz).
tCES
≈
CE
AVD
4
5
6
7
8
≈
tAVDS
tAVDS
tAVDO
3
≈
2
1
CLK
tAVDH
A16-A21
tACH
Aa
tIAA
tRDY
D0
D1
D2
D3
tRDYS
≈
Hi-Z
tOER
D7
≈
OE
RDY
tBA
≈ ≈
A/DQ0:
A/DQ15
tBDH
≈ ≈
tACS
Aa
tRDYA
Figure 7: 8 word Linear Burst with RDY Set One Cycle Before Data (Wrap Around Mode, CR setting : A18=1)
NOTE : In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.
- 27 -
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
SWITCHING WAVEFORMS
8 cycles for initial access shown.
CR setting : A14=1, A13=0, A12=0
9.25ns typ(108MHz).
tCES
tCEZ
CE
2
1
3
4
5
7
6
8
- 28 -
≈
NOTE : In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.
Hi-Z
D6
D0
tOEZ
≈
Figure 8: 16 word Linear Burst Mode with Wrap Around (108Mhz)
≈ ≈
Hi-Z
D15
≈
tRDYS
tRDYA
≈ ≈
D10
≈
RDY
tOER
D9
≈
tRDY
D8
≈
OE
D7
≈ ≈
tIAA
≈ ≈
Aa
tBA
≈ ≈
tACH
A/DQ0:
A/DQ15
tBDH
≈ ≈
A16-A21
≈
tAVDH
tACS
Aa
≈
≈
AVD
≈
≈
tAVDS
tAVDS
tAVDO
≈
CLK
Hi-Z
Rev. 1.2
datasheet
K8S6815ET(B)D
NOR FLASH MEMORY
AC CHARACTERISTICS
17.2 Asynchronous Read
Parameter
All Speed option
Symbol
Min
Max
Unit
Access Time from CE Low
tCE
-
70
ns
Asynchronous Access Time
tAA
-
70
ns
tAVDP
9
-
ns
Address Setup Time to rising Edge of AVD
tAAVDS
4
-
ns
Address Hold Time from Rising Edge of AVD
tAAVDH
6
-
ns
tOE
-
20
ns
0
-
ns
10
-
ns
-
9
ns
AVD Low Time
Output Enable to Output Valid
Read
Output Enable Hold Time
Output Disable to High
tOEH
Toggle and Data Polling
tOEZ
Z1)
NOTE :
1) Not 100% tested.
SWITCHING WAVEFORMS
Asynchronous Mode Read (tCE)
CLK
VIL
CE
tOE
OE
tOEH
WE
tCE
A/DQ0:
A/DQ15
VA
A16-A21
VA
tAAVDS
tOEZ
Valid RD
tAAVDH
AVD
RDY
Hi-Z
tAVDP
Hi-Z
NOTE: CLK "HIGH" should be prohibited in asynchronous read mode start (From CE LOW).
- 29 -
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
Asynchronous Mode Read (tAA)
Case 1 : Valid Address Transition occurs before AVD is driven to Low
CLK
VIL
CE
tOE
OE
tOEH
WE
tOEZ
A/DQ0:
A/DQ15
VA
Valid RD
tAA
A16-A21
VA
tAAVDS
tAAVDH
AVD
tAVDP
RDY
Hi-Z
Hi-Z
Case 2 : Valid Address Transition occurs after AVD is driven to Low
CLK
VIL
CE
tOE
OE
tOEH
WE
tOEZ
A/DQ0:
A/DQ15
VA
Valid RD
tAA
VA
A16-A21
tAAVDS
tAAVDH
AVD
RDY
Hi-Z
tAVDP
Hi-Z
Figure 9: Asynchronous Mode Read
NOTE:
1) VA=Valid Read Address, RD=Read Data.
Asynchronous mode may not support read following four sequential invalid read condition within 200ns.
2) CLK "HIGH" should be prohibited in asynchronous read mode start (From CE LOW).
- 30 -
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
AC CHARACTERISTICS
17.3 Hardware Reset(RESET)
Parameter
All Speed Options
Symbol
Unit
Min
Max
tReady
-
20
μs
tReady
-
500
ns
RESET Pulse Width1)
tRP
200
-
ns
Reset High Time Before Read 1)
tRH
200
-
ns
RESET Pin Low(During Internal Routines)
to Read Mode 1)
RESET Pin Low(NOT During Internal Routines)
to Read Mode 1)
NOTE:
1) Not 100% tested.
SWITCHING WAVEFORMS
CE, OE
tRH
RESET
tRP
tReady
Reset Timings NOT during Internal Routines
≈
CE, OE
tReady
≈
RESET
tRP
Reset Timings during Internal Routines
Figure 10: Reset Timings
- 31 -
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
AC CHARACTERISTICS
17.4 Erase/Program Operation
Parameter
All Speed Option
Symbol
Min
Typ
Max
Unit
WE Cycle Time1)
tWC
60
-
-
ns
Address Setup Time
tAS
4
-
-
ns
Address Hold Time
tAH
5.5
-
-
ns
tAVDP
9
-
-
ns
Data Setup Time
tDS
30
-
-
ns
Data Hold Time
tDH
0
-
-
ns
tGHWL
0
-
-
ns
CE Setup Time
tCS
0
-
-
ns
CE Hold Time
tCH
0
-
-
ns
WE Disable to AVD Enable
tWEA
30
-
-
ns
WE Pulse Width
tWP
30
-
-
ns
WE Pulse Width High
tWPH
30
-
-
ns
Latency Between Read and Write Operations
tSR/W
0
-
-
ns
Word Programming Operation
tPGM
-
11.5
-
μs
Accelerated Single word Programming Operation
tACCPGM
-
6.5
-
μs
Accelerated Quad word Programming Operation
tACCPGM_QUAD
-
6.5
-
μs
Main Block Erase Operation 2)
tBERS
-
0.7
-
sec
VPP Rise and Fall Time
tVPP
500
-
-
ns
VPP Setup Time (During Accelerated Programming)
tVPS
1
-
-
μs
Unit
Comments
sec
Includes 00h programming prior to
erasure
AVD Low Time
Read Recovery Time Before Write
NOTE :
1) Not 100% tested.
2) Not include the preprogramming time.
17.5 FLASH Erase/Program Performance
Limits
Parameter
Min.
Typ.
Max.
32 Kword
-
0.7
14
4 Kword
-
0.2
4
Chip Erase Time
-
91
-
Word Programming Time
-
11.5
210
Accelerated Single Programming Time (@word)
-
6.5
120
Block Erase Time
Accelerated Quad Programming Time (@word)
μs
μs
1.6
30
Chip Programming Time
-
46
-
Accelerated Single word Chip Programming Time
-
26
-
Accelerated Quad word Chip Programming Time
-
6
-
sec
100,000
-
-
Cycles
Erase/Program Endurance3)
sec
NOTE :
1) 25°C, VCC = 1.8V, 100,000 cycles, typical pattern.
2) System-level overhead is defined as the time required to execute the two or four bus cycle command necessary to program each
word. In the preprogramming step of the Internal Erase Routine, all words are programmed to 00H before erasure.
3) 100K Program/Erase Cycle in all Bank
- 32 -
Excludes system level overhead
Minimum 100,000 cycles guaranteed in all Bank
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
SWITCHING WAVEFORMS
Program Operations
Program Command Sequence (last two cycles)
tAS
Read Status Data
tWEA
AVD
tAVDP
tAH
A16:A21
555h
A0h
PA
VA
≈ ≈
A/DQ0:
A/DQ15
PA
PD
tDS
≈
tCH
OE
≈
tDH
CE
VA
tWP
≈
WE
tWPH
tPGM
tCS
VIL
tWC
≈
CLK
≈
VCC
NOTE :
1) PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2) “In progress” and “complete” refer to status of program operation.
3) A16–A21 are don’t care during command sequence unlock cycles.
4) Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.
Figure 11: Program Operation Timing
- 33 -
VA
In
Progress
VA
Complete
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
SWITCHING WAVEFORMS
Erase Operation
Erase Command Sequence (last two cycles)
tAS
Read Status Data
tWEA
AVD
tAVDP
tAH
A16:A21
2AAh
55h
VA
10h for
chip erase
BA
30h
tDS
≈ ≈
A/DQ0:
A/DQ15
BA
555h for
chip erase
≈
tCH
OE
≈
tDH
CE
VA
tWP
≈
WE
tWPH
tBERS
tCS
VIL
tWC
≈
CLK
≈
VCC
NOTE :
1) BA is the block address for Block Erase.
2) Address bits A16–A21 are don’t cares during unlock cycles in the command sequence.
3) Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.
Figure 12: Chlp/Block Erase Operations
- 34 -
VA
In
Progress
VA
Complete
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
SWITCHING WAVEFORMS
Unlock Bypass Program Operations(Accelerated Program)
CE
AVD
WE
PA
A16:A21
A/DQ0:
A/DQ15
Don’t Care
OE
1us
A0h
PA
PD
Don’t Care
tVPS
VID
tVPP
VPP
VIL or VIH
Unlock Bypass Block Erase Operations
CE
AVD
WE
BA
A16:A21
A/DQ0:
A/DQ15
Don’t Care
OE
1us
80h
555h for
chip erase
10h for
chip erase
BA
30h
tVPS
VID
tVPP
VPP
VIL or VIH
NOTE :
1) VPP can be left high for subsequent programming pulses.
2) Use setup and hold times from conventional program operations.
3) Unlock Bypass Program/Erase commands can be used when the VID is applied to Vpp.
Figure 13: Unlock Bypass Operation Timings
- 35 -
Don’t Care
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
SWITCHING WAVEFORMS
Quad word Accelerated Program
≈
CE
≈
AVD
≈
WE
Don’t Care
Don’t Care
PA2
PA3
PA4
A5H PA1 PD1 PA2 PD2 PA3 PD3 PA4 PD4
VA
≈ ≈ ≈
A/DQ0:
A/DQ15
PA1
≈
A16:A21
VA
≈
OE
1us
tVPS
tACCPGM_QUAD
≈
VID
tVPP
VPP
VIL or VIH
NOTE :
1) VPP can be left high for subsequent programming pulses.
2) Use setup and hold times from conventional program operations.
3) Quad word Accelerate program commands can be used when the VID is applied to Vpp.
Figure 14: Quad word Accelerated Program Operation Timings
- 36 -
Complete
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
SWITCHING WAVEFORMS
Data Polling Operations
tCES
≈
≈
CE
CLK
≈ ≈
AVD
≈ ≈
tAVDS
tAVDH
tIAA
VA
Status Data
≈
tRDYS
Hi-Z
≈
≈
RDY
Status Data
≈
OE
≈ ≈
VA
≈ ≈
tACH
A/DQ0:
A/DQ15
VA
≈ ≈
A16-A21
≈ ≈
tACS
VA
NOTE :
1) VA = Valid Address. When the Internal Routine operation is complete, and Data Polling will output true data.
Figure 15: Data Polling Timings (During Internal Routine)
Toggle Bit Operations
tCES
≈
CE
CLK
AVD
≈ ≈
tAVDS
tAVDH
≈ ≈
A16-A21
tACS
VA
tACH
VA
tIAA
Status Data
Toggle Status Data
tOE
≈
OE
tRDYS
Hi-Z
≈
RDY
≈ ≈
A/DQ0:
A/DQ15
NOTE :
1) VA = Valid Address. When the Internal Routine operation is complete, the toggle bits will stop toggling.
Figure 16: Toggle Bit Timings(During Internal Routine)
- 37 -
Rev. 1.2
datasheet
K8S6815ET(B)D
NOR FLASH MEMORY
SWITCHING WAVEFORMS
Read While Write Operations
Last Cycle in
Program or
Block Erase
Command Sequence
tWC
tRC
tRC
tWC
≈
CE
≈
OE
tOE
tOEH
tGHWL
≈
WE
tWPH
tAA
tOEH
tDH
PD/30h
RA
RD
RA
≈
PA/BA
tWP
tDS
≈
A/DQ0:
A/DQ15
Begin another
Program or Erase
Command Sequences
Read status in same bank
and/or array data from other bank
RA
RD
555h
AAh
tSR/W
A16-A21
PA/BA
RA
≈
tAS
AVD
tAH
Figure 17: Read While Write Operation
NOTE :
Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” and checking the status of the program or erase operation in the
“busy” bank.
- 38 -
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
18.0 CROSSING OF FIRST WORD BOUNDARY IN BURST READ MODE
The additional clock insertion for word boundary is needed only at the first crossing of word boundary. This means that no additional clock cycle is needed
from 2nd word boundary crossing to the end of continuous burst read. Also, the number of additional clock cycle for the first word boundary can varies
from zero to seven cycles, and the exact number of additional clock cycle depends on the starting address of burst read.
The rule to determine the additional clock cycle is as follows. All addresses can be divided into 8 groups. The applied rule is "The residue obtained when
the address is divided by 8" or "three LSB bits of address". Using this rule, all address can be divided by 8 different groups as shown in below table. For
simplicity of terminology, "8N" stands for the address of which the residue is "0"(or the three LSB bits are "000") and "8N+1" for the address of which the
residue is "1"(or the three LSB bits are "001"), etc.
The additional clock cycles for first word boundary crossing are zero, one, two, ... or seven when the burst read start from "8N" address, "8N+1"
address, "8N+2" address .... or "8N+7" address respectively.
Starting Address vs. Additional Clock Cycles for first word boundary
Additional Clock Cycles for First Word Boundary
Starting Address
Group
for Burst Read
The Residue of
(Address/8)
LSB Bits of
Address
A14~A12 "000"
Valid data : 4th
CLK
A14~A12 "001"
Valid data : 5th
CLK
A14~A12
"010" Valid
data : 6th CLK
A14~A12
"011" Valid data
: 7th CLK
A14~A12
"100" Valid
data : 8th CLK
8N
0
000
0 cycle
0 cycle
0 cycle
0 cycle
0 cycle
8N+1
1
001
0 cycle
0 cycle
0 cycle
0 cycle
1 cycle
8N+2
2
010
0 cycle
0 cycle
0 cycle
1 cycle
2 cycle
8N+3
3
011
0 cycle
0 cycle
1 cycle
2 cycle
3 cycle
8N+4
4
100
0 cycle
1 cycle
2 cycle
3 cycle
4 cycle
8N+5
5
101
1 cycle
2 cycle
3 cycle
4 cycle
5 cycle
8N+6
6
110
2 cycle
3 cycle
4 cycle
5 cycle
6 cycle
8N+7
7
111
3 cycle
4 cycle
5 cycle
6 cycle
7 cycle
Case 1 : Start from "8N" address group
8th rising edge CLK (108MHz)
CR setting : A14=1, A13=0, A12=0
Valid Address
38
39
≈ ≈
Address/
Data Bus
3D
3E
3F
40
41
42
≈
38
39
3A
≈
CLK
3E
3F
40
41
42
43
≈
AVD
No Additional Cycle for First Word Boundary
≈
≈
≈
RDY
≈
tOER
≈
OE
≈
CE
NOTE :
1) Address boundary occurs every 16 words beginning at address 00000FH , 00001FH , 00002FH , etc.
2) Address 000000H is also a boundary crossing.
3) No additional clock cycles are needed except for 1st boundary crossing.
Figure 18: Crossing of first word boundary in burst read mode.
- 39 -
tCEZ
tOEZ
Rev. 1.2
datasheet
K8S6815ET(B)D
NOR FLASH MEMORY
Case2 : Start from "8N+1" address group
8th rising edge CLK (108MHz)
CR setting : A14=1, A13=0, A12=0
39
Valid Address
3A
≈ ≈
Address/
Data Bus
3F
40
41
42
43
≈
39
3A
3B
≈
CLK
40
41
42
43
44
≈
AVD
Additional 1 Cycle for First Word Boundary
≈
≈
tOER
≈
OE
≈
CE
tCEZ
tOEZ
≈
≈
RDY
Case 3 : Start from "8N+2" address group
8th rising edge CLK (108MHz)
CR setting : A14=1, A13=0, A12=0
3A
Valid Address
3B
≈ ≈
Address/
Data Bus
3F
40
41
42
≈
3A
3B
3C
≈
CLK
40
41
42
43
≈
AVD
Additional 2 Cycle for First Word Boundary
≈
≈
≈
RDY
≈
tOER
≈
OE
≈
CE
NOTE :
1) Address boundary occurs every 16 words beginning at address 00000FH , 00001FH , 00002FH , etc.
2) Address 000000H is also a boundary crossing.
3) No additional clock cycles are needed except for 1st boundary crossing.
Figure 19: Crossing of first word boundary in burst read mode.
- 40 -
tCEZ
tOEZ
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
Case4 : Start from "8N+7" address group
8th rising edge CLK (108MHz)
CR setting : A14=1, A13=0, A12=0
Address/
Data Bus
41
≈
CLK
40
3F
41
≈
AVD
Additional 7 Cycle for First Word Boundary
≈
CE
tOER
≈
OE
≈
RDY
40
3F
Valid Address
NOTE :
1) Address boundary occurs every 16 words beginning at address 00000FH , 00001FH , 00002FH , etc.
2) Address 000000H is also a boundary crossing.
3) No additional clock cycles are needed except for 1st boundary crossing.
Figure 20: Crossing of first word boundary in burst read mode.
- 41 -
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
[Table 14] Top boot block Address Table(K8S6815ETD)
Bank
Bank0
Bank1
Bank2
Block
Block Size
(x16) Address Range
BA134
4 Kwords
3FF000h-3FFFFFh
BA133
4 Kwords
3FE000h-3FEFFFh
BA132
4 Kwords
3FD000h-3FDFFFh
BA131
4 Kwords
3FC000h-3FCFFFh
BA130
4 Kwords
3FB000h-3FBFFFh
BA129
4 Kwords
3FA000h-3FAFFFh
BA128
4 Kwords
3F9000h-3F9FFFh
BA127
4 Kwords
3F8000h-3F8FFFh
BA126
32 Kwords
3F0000h-3F7FFFh
BA125
32 Kwords
3E8000h-3EFFFFh
BA124
32 Kwords
3E0000h-3E7FFFh
BA123
32 Kwords
3D8000h-3DFFFFh
BA122
32 Kwords
3D0000h-3D7FFFh
BA121
32 Kwords
3C8000h-3CFFFFh
BA120
32 Kwords
3C0000h-3C7FFFh
BA119
32 Kwords
3B8000h-3BFFFFh
BA118
32 Kwords
3B0000h-3B7FFFh
BA117
32 Kwords
3A8000h-3AFFFFh
BA116
32 Kwords
3A0000h-3A7FFFh
BA115
32 Kwords
398000h-39FFFFh
BA114
32 Kwords
390000h-397FFFh
BA113
32 Kwords
388000h-38FFFFh
BA112
32 Kwords
380000h-387FFFh
BA111
32 Kwords
378000h-37FFFFh
BA110
32 Kwords
370000h-377FFFh
BA109
32 Kwords
368000h-36FFFFh
BA108
32 Kwords
360000h-367FFFh
BA107
32 Kwords
358000h-35FFFFh
BA106
32 Kwords
350000h-357FFFh
BA105
32 Kwords
348000h-34FFFFh
BA104
32 Kwords
340000h-347FFFh
BA103
32 Kwords
338000h-33FFFFh
BA102
32 Kwords
330000h-337FFFh
BA101
32 Kwords
328000h-32FFFFh
BA100
32 Kwords
320000h-327FFFh
BA99
32 Kwords
318000h-31FFFFh
BA98
32 Kwords
310000h-317FFFh
BA97
32 Kwords
308000h-30FFFFh
BA96
32 Kwords
300000h-307FFFh
BA95
32 Kwords
2F8000h-2FFFFFh
BA94
32 Kwords
2F0000h-2F7FFFh
BA93
32 Kwords
2E8000h-2EFFFFh
BA92
32 Kwords
2E0000h-2E7FFFh
BA91
32 Kwords
2D8000h-2DFFFFh
BA90
32 Kwords
2D0000h-2D7FFFh
BA89
32 Kwords
2C8000h-2CFFFFh
BA88
32 Kwords
2C0000h-2C7FFFh
- 42 -
datasheet
K8S6815ET(B)D
Bank
Bank2
Bank3
Bank4
Bank5
Rev. 1.2
NOR FLASH MEMORY
Block
Block Size
(x16) Address Range
BA87
32 Kwords
2B8000h-2BFFFFh
BA86
32 Kwords
2B0000h-2B7FFFh
BA85
32 Kwords
2A8000h-2AFFFFh
BA84
32 Kwords
2A0000h-2A7FFFh
BA83
32 Kwords
298000h-29FFFFh
BA82
32 Kwords
290000h-297FFFh
BA81
32 Kwords
288000h-28FFFFh
BA80
32 Kwords
280000h-287FFFh
BA79
32 Kwords
278000h-27FFFFh
BA78
32 Kwords
270000h-277FFFh
BA77
32 Kwords
268000h-26FFFFh
BA76
32 Kwords
260000h-267FFFh
BA75
32 Kwords
258000h-25FFFFh
BA74
32 Kwords
250000h-257FFFh
BA73
32 Kwords
248000h-24FFFFh
BA72
32 Kwords
240000h-247FFFh
BA71
32 Kwords
238000h-23FFFFh
BA70
32 Kwords
230000h-237FFFh
BA69
32 Kwords
228000h-22FFFFh
BA68
32 Kwords
220000h-227FFFh
BA67
32 Kwords
218000h-21FFFFh
BA66
32 Kwords
210000h-217FFFh
BA65
32 Kwords
208000h-20FFFFh
BA64
32 Kwords
200000h-207FFFh
BA63
32 Kwords
1F8000h-1FFFFFh
BA62
32 Kwords
1F0000h-1F7FFFh
BA61
32 Kwords
1E8000h-1EFFFFh
BA60
32 Kwords
1E0000h-1E7FFFh
BA59
32 Kwords
1D8000h-1DFFFFh
BA58
32 Kwords
1D0000h-1D7FFFh
BA57
32 Kwords
1C8000h-1CFFFFh
BA56
32 Kwords
1C0000h-1C7FFFh
BA55
32 Kwords
1B8000h-1BFFFFh
BA54
32 Kwords
1B0000h-1B7FFFh
BA53
32 Kwords
1A8000h-1AFFFFh
BA52
32 Kwords
1A0000h-1A7FFFh
BA51
32 Kwords
198000h-19FFFFh
BA50
32 Kwords
190000h-197FFFh
BA49
32 Kwords
188000h-18FFFFh
BA48
32 Kwords
180000h-187FFFh
BA47
32 Kwords
178000h-17FFFFh
BA46
32 Kwords
170000h-177FFFh
BA45
32 Kwords
168000h-16FFFFh
BA44
32 Kwords
160000h-167FFFh
BA43
32 Kwords
158000h-15FFFFh
BA42
32 Kwords
150000h-157FFFh
- 43 -
datasheet
K8S6815ET(B)D
Bank
Bank5
Bank6
Bank7
Rev. 1.2
NOR FLASH MEMORY
Block
Block Size
(x16) Address Range
BA41
32 Kwords
148000h-14FFFFh
BA40
32 Kwords
140000h-147FFFh
BA39
32 Kwords
138000h-13FFFFh
BA38
32 Kwords
130000h-137FFFh
BA37
32 Kwords
128000h-12FFFFh
BA36
32 Kwords
120000h-127FFFh
BA35
32 Kwords
118000h-11FFFFh
BA34
32 Kwords
110000h-117FFFh
BA33
32 Kwords
108000h-10FFFFh
BA32
32 Kwords
100000h-107FFFh
BA31
32 Kwords
0F8000h-0FFFFFh
BA30
32 Kwords
0F0000h-0F7FFFh
BA29
32 Kwords
0E8000h-0EFFFFh
BA28
32 Kwords
0E0000h-0E7FFFh
BA27
32 Kwords
0D8000h-0DFFFFh
BA26
32 Kwords
0D0000h-0D7FFFh
BA25
32 Kwords
0C8000h-0CFFFFh
BA24
32 Kwords
0C0000h-0C7FFFh
BA23
32 Kwords
0B8000h-0BFFFFh
BA21
32 Kwords
0B0000h-0B7FFFh
BA21
32 Kwords
0A8000h-0AFFFFh
BA20
32 Kwords
0A0000h-0A7FFFh
BA19
32 Kwords
098000h-09FFFFh
BA18
32 Kwords
090000h-097FFFh
BA17
32 Kwords
088000h-08FFFFh
BA16
32 Kwords
080000h-087FFFh
BA15
32 Kwords
078000h-07FFFFh
BA14
32 Kwords
070000h-077FFFh
BA13
32 Kwords
068000h-06FFFFh
BA12
32 Kwords
060000h-067FFFh
BA11
32 Kwords
058000h-05FFFFh
BA10
32 Kwords
050000h-057FFFh
BA9
32 Kwords
048000h-04FFFFh
BA8
32 Kwords
040000h-047FFFh
BA7
32 Kwords
038000h-03FFFFh
BA6
32 Kwords
030000h-037FFFh
BA5
32 Kwords
028000h-02FFFFh
BA4
32 Kwords
020000h-027FFFh
BA3
32 Kwords
018000h-01FFFFh
BA2
32 Kwords
010000h-017FFFh
BA1
32 Kwords
008000h-00FFFFh
BA0
32 Kwords
000000h-007FFFh
Block Address
A21 ~ A8
Block Size
(x16) Address Range
3FFFh
256words
3FFF00h-3FFFFFh
[Table 15] OTP Block Address
OTP
After entering OTP block, any issued addresses should be in the range of OTP block address
- 44 -
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
[Table 16] Bottom Boot Block Address (K8S6815EBD)
Bank
Bank 7
Bank 6
Bank 5
Block
Block Size
(x16) Address Range
BA134
32 Kwords
3F8000h-3FFFFFh
BA133
32 Kwords
3F0000h-3F7FFFh
BA132
32 Kwords
3E8000h-3EFFFFh
BA131
32 Kwords
3E0000h-3E7FFFh
BA130
32 Kwords
3D8000h-3DFFFFh
BA129
32 Kwords
3D0000h-3D7FFFh
BA128
32 Kwords
3C8000h-3CFFFFh
BA127
32 Kwords
3C0000h-3C7FFFh
BA126
32 Kwords
3B8000h-3BFFFFh
BA125
32 Kwords
3B0000h-3B7FFFh
BA124
32 Kwords
3A8000h-3AFFFFh
BA123
32 Kwords
3A0000h-3A7FFFh
BA122
32 Kwords
398000h-39FFFFh
BA121
32 Kwords
390000h-397FFFh
BA120
32 Kwords
388000h-38FFFFh
BA119
32 Kwords
380000h-387FFFh
BA118
32 Kwords
378000h-37FFFFh
BA117
32 Kwords
370000h-377FFFh
BA116
32 Kwords
368000h-36FFFFh
BA115
32 Kwords
360000h-367FFFh
BA114
32 Kwords
358000h-35FFFFh
BA113
32 Kwords
350000h-357FFFh
BA112
32 Kwords
348000h-34FFFFh
BA111
32 Kwords
340000h-347FFFh
BA110
32 Kwords
338000h-33FFFFh
BA109
32 Kwords
330000h-337FFFh
BA108
32 Kwords
328000h-32FFFFh
BA107
32 Kwords
320000h-327FFFh
BA106
32 Kwords
318000h-31FFFFh
BA105
32 Kwords
310000h-317FFFh
BA104
32 Kwords
308000h-30FFFFh
BA103
32 Kwords
300000h-307FFFh
BA102
32 Kwords
2F8000h-2FFFFFh
BA101
32 Kwords
2F0000h-2F7FFFh
BA100
32 Kwords
2E8000h-2EFFFFh
BA99
32 Kwords
2E0000h-2E7FFFh
BA98
32 Kwords
2D8000h-2DFFFFh
BA97
32 Kwords
2D0000h-2D7FFFh
BA96
32 Kwords
2C8000h-2CFFFFh
BA95
32 Kwords
2C0000h-2C7FFFh
BA94
32 Kwords
2B8000h-2BFFFFh
BA93
32 Kwords
2B0000h-2B7FFFh
BA92
32 Kwords
2A8000h-2AFFFFh
- 45 -
datasheet
K8S6815ET(B)D
Bank
Bank 5
Bank 4
Bank 3
Bank 2
Block
Rev. 1.2
NOR FLASH MEMORY
Block Size
(x16) Address Range
BA91
32 Kwords
2A0000h-2A7FFFh
BA90
32 Kwords
298000h-29FFFFh
BA89
32 Kwords
290000h-297FFFh
BA88
32 Kwords
288000h-28FFFFh
BA87
32 Kwords
280000h-287FFFh
BA86
32 Kwords
278000h-27FFFFh
BA85
32 Kwords
270000h-277FFFh
BA84
32 Kwords
268000h-26FFFFh
BA83
32 Kwords
260000h-267FFFh
BA82
32 Kwords
258000h-25FFFFh
BA81
32 Kwords
250000h-257FFFh
BA80
32 Kwords
248000h-24FFFFh
BA79
32 Kwords
240000h-247FFFh
BA78
32 Kwords
238000h-23FFFFh
BA77
32 Kwords
230000h-237FFFh
BA76
32 Kwords
228000h-22FFFFh
BA75
32 Kwords
220000h-227FFFh
BA74
32 Kwords
218000h-21FFFFh
BA73
32 Kwords
210000h-217FFFh
BA72
32 Kwords
208000h-20FFFFh
BA71
32 Kwords
200000h-207FFFh
BA70
32 Kwords
1F8000h-1FFFFFh
BA69
32 Kwords
1F0000h-1F7FFFh
BA68
32 Kwords
1E8000h-1EFFFFh
BA67
32 Kwords
1E0000h-1E7FFFh
BA66
32 Kwords
1D8000h-1DFFFFh
BA65
32 Kwords
1D0000h-1D7FFFh
BA64
32 Kwords
1C8000h-1CFFFFh
BA63
32 Kwords
1C0000h-1C7FFFh
BA62
32 Kwords
1B8000h-1BFFFFh
BA61
32 Kwords
1B0000h-1B7FFFh
BA60
32 Kwords
1A8000h-1AFFFFh
BA59
32 Kwords
1A0000h-1A7FFFh
BA58
32 Kwords
198000h-19FFFFh
BA57
32 Kwords
190000h-197FFFh
BA56
32 Kwords
188000h-18FFFFh
BA55
32 Kwords
180000h-187FFFh
BA54
32 Kwords
178000h-17FFFFh
BA53
32 Kwords
170000h-177FFFh
BA52
32 Kwords
168000h-16FFFFh
BA51
32 Kwords
160000h-167FFFh
BA50
32 Kwords
158000h-15FFFFh
BA49
32 Kwords
150000h-157FFFh
BA48
32 Kwords
148000h-14FFFFh
BA47
32 Kwords
140000h-147FFFh
- 46 -
datasheet
K8S6815ET(B)D
Bank
Bank 2
Bank 1
Bank 0
Rev. 1.2
NOR FLASH MEMORY
Block
Block Size
(x16) Address Range
BA46
32 Kwords
138000h-13FFFFh
BA45
32 Kwords
130000h-137FFFh
BA44
32 Kwords
128000h-12FFFFh
BA43
32 Kwords
120000h-127FFFh
BA42
32 Kwords
118000h-11FFFFh
BA41
32 Kwords
110000h-117FFFh
BA40
32 Kwords
108000h-10FFFFh
BA39
32 Kwords
100000h-107FFFh
BA38
32 Kwords
0F8000h-0FFFFFh
BA37
32 Kwords
0F0000h-0F7FFFh
BA36
32 Kwords
0E8000h-0EFFFFh
BA35
32 Kwords
0E0000h-0E7FFFh
BA34
32 Kwords
0D8000h-0DFFFFh
BA33
32 Kwords
0D0000h-0D7FFFh
BA32
32 Kwords
0C8000h-0CFFFFh
BA31
32 Kwords
0C0000h-0C7FFFh
BA30
32 Kwords
0B8000h-0BFFFFh
BA29
32 Kwords
0B0000h-0B7FFFh
BA28
32 Kwords
0A8000h-0AFFFFh
BA27
32 Kwords
0A0000h-0A7FFFh
BA26
32 Kwords
098000h-09FFFFh
BA25
32 Kwords
090000h-097FFFh
BA24
32 Kwords
088000h-08FFFFh
BA23
32 Kwords
080000h-087FFFh
BA22
32 Kwords
078000h-07FFFFh
BA21
32 Kwords
070000h-077FFFh
BA20
32 Kwords
068000h-06FFFFh
BA19
32 Kwords
060000h-067FFFh
BA18
32 Kwords
058000h-05FFFFh
BA17
32 Kwords
050000h-057FFFh
BA16
32 Kwords
048000h-04FFFFh
BA15
32 Kwords
040000h-047FFFh
BA14
32 Kwords
038000h-03FFFFh
BA13
32 Kwords
030000h-037FFFh
BA12
32 Kwords
028000h-02FFFFh
BA11
32 Kwords
020000h-027FFFh
BA10
32 Kwords
018000h-01FFFFh
BA9
32 Kwords
010000h-017FFFh
BA8
32 Kwords
008000h-00FFFFh
BA7
4 Kwords
007000h-007FFFh
BA6
4 Kwords
006000h-006FFFh
BA5
4 Kwords
005000h-005FFFh
BA4
4 Kwords
004000h-004FFFh
BA3
4 Kwords
003000h-003FFFh
BA2
4 Kwords
002000h-002FFFh
BA1
4 Kwords
001000h-001FFFh
BA0
4 Kwords
000000h-000FFFh
- 47 -
datasheet
K8S6815ET(B)D
Rev. 1.2
NOR FLASH MEMORY
[Table 17] OTP Block Address
OTP
Block Address
A21 ~ A8
Block Size
(x16) Address Range
0000h
256words
000000h-0000FFh
After entering OTP block, any issued addresses should be in the range of OTP block address
- 48 -