KM62V256C, KM62U256C Family CMOS SRAM 32Kx8 bit Low Power & Low Vcc CMOS Static RAM FEATURE SUMMARY GENERAL DESCRIPTION • Process Technology : 0.7µm CMOS • Organization : 32K x 8 • Power Supply Voltage KM62V256C family : 3.3V ± 0.3V KM62U256C family : 3.0V ± 0.3V • Low Data Retention Voltage : 2V(Min) • Three state output and TTL Compatible • Package Type : JEDEC Standard 28-SOP, 28-TSOP(I)-Forward/Reverse The KM62V256C and KM62U256C family are fabricated by SAMSUNG's advanced CMOS process technology. The family can support various operating temperature ranges and has various package types for user flexibility of system design. The family also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Speed (ns) Power Dissipation Product List Operating Temp. Vcc Range KM62V256CL-L Commercial 3.0~3.6V 70*/100 28-SOP** 10 µA KM62U256CL-L (0~70 °C) 2.7~3.3V 85*/100 28-TSOP(I) R/F 10 µA KM62V256CLE-L Extended 3.0~3.6V 70*/100 28-SOP** 20 µA KM62U256CLE-L (-25~85 °C) 2.7~3.3V 85*/100 28-TSOP(I) R/F 15 µA KM62V256CLI-L Industrial 3.0~3.6V 70*/100 28-SOP** 20 µA KM62U256CLI-L (-40~85 °C) 2.7~3.3V 85*/100 28-TSOP(I) R/F 15 µA PKG Type Standby (Isb1, Max) Operating (Icc2) 35mA * measured with 30pF test load ** the device with 100ns SOP package in 3.0~3.6V Vcc range is not produced. PIN DESCRIPTION FUNCTIONAL BLOCK DIAGRAM A0~2, A9~11 28 Vcc A12 2 27 /WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 28-Pin SOP 22 /OE A2 8 21 A10 A1 9 20 /CS A0 10 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 Vss 14 15 I/O4 /OE A11 A9 A8 A13 /WE Vcc A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A3 A4 A5 A6 A7 A12 A14 Vcc /WE A13 A8 A9 A11 /OE 14 13 12 11 10 9 8 7 6 5 4 3 2 1 28-Pin TSOP Type I - Forward 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 /CS IO8 IO7 IO6 IO5 IO4 Vss IO3 IO2 IO1 A0 A1 A2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A2 A1 A0 IO1 IO2 IO3 Vss IO4 IO5 IO6 IO7 IO8 /CS A10 Y-Decoder A3~A8 A12~14 I/O1~8 28-Pin TSOP Type I - Reverse -1- Cell Array I/O Buffer Control Logic 1 X-Decoder A14 /CS, /WE /OE Pin Name Function A0~A14 Address Inputs /WE Write Enable Input /CS Chip Select Input /OE Output Enable Input I/O1~I/O8 Data Input/Output Vcc Power Vss Ground Revision 04 April 1996 ELECTRONICS KM62V256C, KM62U256C Family CMOS SRAM PRODUCT LIST & ORDERING INFORMATION PRODUCT LIST Extended Temp Products (-25~85 °C) Commercial Temp Products (0~70 °C) Part Name Function Part Name Function Industrial Temp Products (-40~85 °C) Part Name Function KM62V256CLG-7L 28-SOP, 70ns, 3.3V KM62V256CLGE-7L 28-SOP, 70ns, 3.3V KM62V256CLGI-7L 28-SOP, 70ns, 3.3V KM62V256CLTG-7L 28-TSOP F, 70ns, 3.3V KM62V256CLTGE-7L 28-TSOP F, 70ns, 3.3V KM62V256CLTGI-7L 28-TSOP F, 70ns, 3.3V KM62V256CLTG-10L 28-TSOP F, 100ns, 3.3V KM62V256CLTGE-10L 28-TSOP F, 100ns, 3.3V KM62V256CLTGI-10L 28-TSOP F, 100ns, 3.3V KM62V256CLRG-7L 28-TSOP R, 70ns, 3.3V KM62V256CLRGE-7L KM62V256CLRGI-7L 28-TSOP R, 70ns, 3.3V KM62V256CLRG-10L 28-TSOP R, 100ns, 3.3V KM62V256CLRGE-10L 28-TSOP R, 100ns, 3.3V KM62V256CLRGI-10L 28-TSOP R, 100ns, 3.3V KM62U256CLG-8L 28-SOP, 85ns, 3.0V KM62U256CLGE-8L 28-SOP, 85ns, 3.0V KM62U256CLGI-8L 28-SOP, 85ns, 3.0V KM62U256CLTG-8L 28-TSOP F, 85ns, 3.0V KM62U256CLTGE-8L 28-TSOP F, 85ns, 3.0V KM62U256CLTGI-8L 28-TSOP F, 85ns, 3.0V KM62U256CLRG-8L 28-TSOP R, 85ns, 3.0V KM62U256CLRGE-8L 28-TSOP R, 85ns, 3.0V KM62U256CLRGI-8L 28-TSOP R, 85ns, 3.0V KM62U256CLG-10L 28-SOP, 100ns, 3.0V KM62U256CLGE-10L 28-SOP, 100ns, 3.0V KM62U256CLGI-10L 28-SOP, 100ns, 3.0V KM62U256CLTG-10L 28-TSOP F, 100ns, 3.0V KM62U256CLTGE-10L 28-TSOP F, 100ns, 3.0V KM62U256CLRG-10L 28-TSOP R, 100ns, 3.0V KM62U256CLRGE-10L 28-TSOP R, 100ns, 3.0V KM62U256CLRGI-10L 28-TSOP R, 100ns, 3.0V 28-TSOP R, 70ns, 3.3V KM62U256CLTGI-10L 28-TSOP F, 100ns, 3.0V ORDERING INFORMATION K M6 2 X 256 C X X X - XX X L-Low Low Power, Blank-Low Power or High Power Access Time : 7=70ns, 8=85ns, 10=100ns Operating Temperature : I=Industrial, E=Extended, Blank=Commercial Package Type : G=SOP, TG=TSOP Forward, RG=TSOP Reverse L-Low Power or Low Low Power, Blank-High Power Die Version : C=4th generation Density : 256=256Kbit V=3.0~3.6V, U=2.7~3.3V, Blank=5V Organization : 2= x8 SEC Standard SRAM -2- Revision 04 April 1996 ELECTRONICS KM62V256C, KM62U256C Family CMOS SRAM ABSOLUTE MAXIMUM RATINGS * Item Symbol Voltage on any pin relative to Vss Ratings Unit Remark V - Vin, Vout -0.5 to Vcc+0.5 Voltage on Vcc supply relative to Vss Vcc -0.3 to 4.6 V - Power Dissipation Pd 0.7 W - Storage temperature Tstg -65 to 150 °C - Operating Temperature Ta 0 to 70 °C KM62V256CL-L, KM62U256CL-L -25 to 85 -40 to 85 °C KM62V256CLE-L, KM62U256CLE-L °C KM62V256CLI-L, KM62U256CLI-L 260 °C, 10sec - Soldering temperature and time Tsolder - (Lead Only) * Stresses greater than those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS* Item Supply voltage Symbol Product Min Typ** Max Unit Vcc KM62V256C Family 3.0 3.3 3.6 V KM62U256C Family 2.7 3.0 3.3 V Ground Vss All 0 0 0 V Input high voltage Vih KM62V256C Family 2.2 - Vcc+0.3 V KM62U256C Family 2.2 - Vcc+0.3 V KM62V256C Family -0.3 - 0.4 V KM62U256C Family -0.3*** - 0.4 V Input low voltage Vil * 1) Commercial Product : Ta=0 to 70 °C, unless otherwise specified 2) Extended Product : Ta=-25 to 85 °C, unless otherwise specified 3) Industrial Product : Ta=-40 to 85 °C, unless otherwise specified ** Ta=25 °C *** Vil(min)=-3.0V for ¡ Â30ns pulse CAPACITANCE * (f=1MHz, Ta=25 °C) Item Input capacitance Input/Output capacitance Symbol Test Condition Min Max Unit Cin Vin=0V - 6 pF Cio Vio=0V - 8 pF * Capacitance is sampled not 100% tested -3- Revision 04 April 1996 ELECTRONICS KM62V256C, KM62U256C Family CMOS SRAM DC AND OPERATING CHARACTERISTICS Item Test Conditions 1) Symbol Min Typ 2) Max Unit Input leakage current Ili Vin=Vss to Vcc -1 - 1 uA Output leakage current Ilo /CS=Vih or Vil or /WE=Vil -1 - 1 uA Vio=Vss to Vcc Operating power supply current Icc /CS=Vil, Vin=Vih or Vil, Iio=0mA - 1.0 2.0 mA Average operating current Cycle time=1uS 100% duty - 2.5 5 mA - 20 3) 354) mA - - 0.4 V 2.2 - - V Icc1 /CS¡ Â0.2V, Vil¡ Â0.2V, Vin¡ ÃVcc-0.2V, Iio=0mA Icc2 Min cycle, 100% duty /CS=Vil, Iio=0mA Output low voltage Vol Iol=2.1mA Output high voltage Voh Ioh=-1.0mA Standby Current(TTL) Isb /CS=Vih - - 0.3 mA Isb1 /CS¡ ÃVcc-0.2V Low Low PWR Low Low PWR Vin¡ Â0.2V or - 1.5 10 uA - 1.5 20 uA Vin¡ ÃVcc-0.2V Low Low PWR Low Low PWR - 1.5 20 uA - 1.0 10 uA KM62U256CLE-L Low Low PWR - 1.0 15 uA KM62U256CLI-L Low Low PWR - 1.0 15 uA Standby KM62V256CL-L Current KM62V256CLE-L (CMOS) KM62V256CLI-L KM62U256CL-L 1) - Commercial Product : Ta=0 to 70 °C , Vcc=3.0 +/- 0.3V(62U256C Family), Vcc=3.3 +/- 0.3V(62V256C Family) - Extended Product : Ta=-25 to 85 °C , Vcc=3.0 +/- 0.3V(62U256CE Family), Vcc=3.3 +/- 0.3V(62V256CE Family) - Industrial Product : Ta=-40 to 85 °C , Vcc=3.0 +/- 0.3V(62U256CI Family), Vcc=3.3 +/- 0.3V(62V256CI Family) 2) Ta=25 °C 3) 25mA for KM62V256C family 4) 30mA for KM62U256C family but it is not 100% tested but obtained statistically A.C CHARACTERISTICS TEST CONDITIONS(1. Test Load and Test Input/Output Reference)* Item Value Input pulse level 0.4 to 2.2V Input rise fall time 5ns Remark - Input and output reference voltage 1.5V Output load(See right) CL=100pF+1TTL CL=30pF+1TTL CL* * Including scope and jig capacitance * See test condition of DC and Operating characteristics -4- Revision 04 April 1996 ELECTRONICS KM62V256C, KM62U256C Family CMOS SRAM TEST CONDITIONS (2. Temperature and Vcc Conditions) Product Family Temperature Power Supply(Vcc) Speed Bin Comments KM62V256CL-L 0~70 °C 3.3V +/- 0.3 70*/100ns Commercial KM62V256CLE-L -25~85 °C 3.3V +/- 0.3 70*/100ns Extended KM62V256CLI-L -40~85 °C 3.3V +/- 0.3 70*/100ns Industrial KM62U256CL-L 0~70 °C 3.0V +/- 0.3 85*/100ns Commercial KM62U256CLE-L -25~85 °C 3.0V +/- 0.3 85*/100ns Extended KM62U256CLI-L -40~85 °C 3.0V +/- 0.3 85*/100ns Industrial * all the AC parameters are measured with 30pF test load PARAMETER LIST FOR EACH SPEED BIN Speed Bins Parameter List Read Read cycle time Address access time Symbol 85ns 70ns 100ns Units Min Max Min Max Min Max tRC 70 - 85 - 100 - ns tAA - 70 - 85 - 100 ns 70 - 85 - 100 ns tCO - Output enable to valid output tOE - 35 - 40 - 50 ns Chip select to low-Z output tLZ 10 - 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - 5 - ns Chip disable to high-Z output tHZ 0 30 0 35 0 35 ns 0 30 0 35 0 35 ns 5 - 10 - 15 - ns 70 - 85 - 100 - ns 60 - 70 - 70 - ns tAS 0 - 0 - 0 - ns - 70 - 70 - ns Chip select to output Output disable to high-Z output tOHZ Output hold from address change tOH Write Write cycle time tWC Chip select to end of write tCW Address set-up time tAW 60 Write pulse width tWP 50 - 60 - 60 - ns Write recovery time tWR 0 - 0 - 0 - ns Write to output high-Z tWHZ 0 25 0 25 0 30 ns Data to write time overlap tDW 50 - 60 - 60 - ns Data hold from write time tDH 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 10 - 10 - ns Address valid to end of write -5- Revision 04 April 1996 ELECTRONICS KM62V256C, KM62U256C Family CMOS SRAM DATA RETENTION CHARACTERISTICS Item Symbol Vcc for data retention Vdr Data retention current Idr Test Condition* /CS¡ ÃVcc-0.2V Min Typ** Max 2.0 - 3.6 KM62V256CL-L Vcc=3.0V - 1 8 KM62U256CL-L /CS¡ ÃVcc-0.2V - 0.6 8 KM62V256CLE-L - 1 10 KM62U256CLE-L - 0.6 10 KM62V256CLI-L - 1 10 KM62U256CLI-L - 0.6 10 See data retention 0 - - waveform 5 - - Data retention set-up time tSDR Recovery time tRDR Unit V uA ms * 1) Commercial Product : Ta=0 to 70 °C, unless otherwise specified 2) Extended Product : Ta=-25 to 85 °C, unless otherwise specified 3) Industrial Product : Ta=-40 to 85 °C, unless otherwise specified ** Ta=25 °C DATA RETENTION TIMING DIAGRAM tSDR Data retention mode tRDR Vcc 3.0/2.7V* 2.2V Vdr /CS¡ ÃVcc-0.2V /CS GND * 3.0V for KM62V256C family, 2.7V for KM62U256C family FUNCTIONAL DESCRIPTION /CS /WE /OE Mode I/O Pin Current Mode H X X Power Down High-Z Isb, Isb1 L H H Output Disable High-Z Icc L H L Read Dout Icc L L X Write Din Icc -6- Revision 04 April 1996 ELECTRONICS KM62V256C, KM62U256C Family CMOS SRAM TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE (1) (Address Controlled) (/CS=/OE=Vil, /WE=Vih) tRC Address tAA tOH Data Out Previous Data Valid Data Valid TIMING WAVEFORM OF READ CYCLE (/WE= VIH ) t RC Address t AA t OH t CO /CS t HZ t OE /OE t OLZ(4) t OHZ t LZ Data out High - Z Data Valid Notes (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, H t Z (max.) is less than tLZ(min.) both for a given device and from device to device. -7- Revision 04 April 1996 ELECTRONICS KM62V256C, KM62U256C Family TIMING WAVEFORM OF WRITE CYCLE CMOS SRAM (/WE Controlled) t WC Address t CW(2) t WR(4) /CS t AW t WP(1) /WE t AS t DW Data in Data Valid t OW t WHZ Data out t DH Data Undefined TIMING WAVEFORM OF WRITE CYCLE (/CS Controlled) t WC Address t AS t WR(4) t CW(2) /CS t AW t WP(1) /WE t DW Data Valid Data in Data out t DH High - Z High - Z Notes (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of a low /CS and low /WE. A write begins at the latest transition among /CS going low and /WE going low : A write end at the earliest transition among /CS going high and /WE going high, tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS, or /WE going high. -8- Revision 04 April 1996 ELECTRONICS KM62V256C, KM62U256C Family CMOS SRAM PACKAGE DIMENSION Unit : Millimeters (Inches) 28 PIN THIN SMALL OUTLINE PACKAGE TYPE I ( 0813.4F ) 13.40 ± 0.10 (0.528 ± 0.008) 1.20 Max. 0.047 0.00 Min. 0.000 #28 #1 +0.10 0.20 -0.05 0.55 (0.022) 8.00 0.315 8.40 Max. 0.331 +0.004 (0.008) -0.002 0.43 0.017 +0.10 0.15 -0.05 0~ 8¡ Æ 11.80 ± 0.10 (0.465 ± 0.004) 0.004Max. 0.10Max. #15 #14 0.006 +0.004 -0.002 0.50± 0.10 0.020 ± 0.004 28 PIN THIN SMALL OUTLINE PACKAGE TYPE I ( 0813.4R ) 13.40 ± 0.10 (0.528 ± 0.008) #14 1.20 Max. 0.047 0.00 Min. 0.000 #15 +0.10 0.20 -0.05 0.55 (0.022) 0.43 0.017 0~ 8¡ Æ 11.80 ± 0.10 (0.465 ± 0.004) 0.004Max. #28 0.10Max. #1 8.00 0.315 8.40 Max. 0.331 +0.004 (0.008) -0.002 +0.10 0.15 -0.05 0.006 +0.004 -0.002 0.50± 0.10 0.020 ± 0.004 -9- Revision 04 April 1996 ELECTRONICS KM62V256C, KM62U256C Family CMOS SRAM 28 PIN PLASTIC SMALL OUTLINE PACKAGE (450mil ) 0 ~ 8° #28 #15 11.81 ± 0.30 0.465 ± 0.012 8.38 ± 0.20 0.330 ± 0.008 #1 1.02 ± 0.20 0.040± 0.008 #14 1.27 0.050 18.69 MAX 0.736 + 0.10 - 0.05 + 0.004 0.006 - 0.002 0.15 2.59 ± 0.20 0.102 ± 0.008 18.29 ± 0.20 0.720± 0.008 0.89 0.41 ± 0.10 0.035 0.016 ± 0.004 3.00 MAX 0.118 0.05 MIN 0.002 - 10 - 0.10 MAX 0.004 Revision 04 April 1996 ELECTRONICS KM62V256C, KM62U256C Family CMOS SRAM TECHNICAL INFORMATION 1) Icc2 characteristics by temperature variation All the values in this graph are depicted by the relative value with the maximum value measured at 3.3V Vcc and -40° Ctemperature. The basic relative value of Icc2 at that condition is set into 1. Icc2(Relative Value) Icc2 v.s Temperature 1.000 0.900 3.0V Device 3.3V Device 0.800 0.700 0.600 0.500 -40 -10 0 25 40 70 85 Temerature( ¡ É) 2) Isb1(CMOS Level Standby Current) characteristics by temperature variation All the values in this graph are depicted by the relative value with the maximum value measured at 3.0V Vcc and 85° Ctemperature. The basic relative value of Isb1 at that condition is set into 1. Isb1(Relative Value) Isb1 v.s Temperature 1.00 0.80 0.60 2.7V 3.0V 0.40 0.20 0.00 -40 -10 0 25 40 70 85 Temperature( ¡ É) - 11 - Revision 04 April 1996 ELECTRONICS KM62V256C, KM62U256C Family CMOS SRAM 3) Idr(Data Retention Current) characteristics by temperature variation All the values in this graph are depicted by the relative value with the maximum value measured at Vdr=3.0V and 85° Ctemperature. The basic relative value of Idr at that condition is set into 1. Idr v.s Temperature @ Vcc=3.0V Idr(Relative Value) 1.00 0.80 0.60 0.40 0.20 0.00 -40 -10 0 25 40 70 85 Temperature(¡ É) - 12 - Revision 04 April 1996 ELECTRONICS