Ordering number : EN*A0908 LC07422T CMOS IC Audio CODEC with Video Driver Overview The LC07422T is an audio CODEC that has a built-in speaker amplifier and headphone amplifier and incorporates a video driver. A 2-input line selector and ALC circuit are provided in the audio recording system. A speaker amplifier with EVR, headphone amplifier, and line output are provided in the playback system. A video driver that obviates the need for an output coupling capacitor is also included to enable AV playback processing with the single chip. Features • Audio systems can be configured using this single chip since almost all the audio system circuits are provided. • A video driver obviating the need for an output coupling capacitor is included. • A high-performance ALC/limiter circuit that meets a variety of different conditions is incorporated. • A wide range of different functions can be set using parameter settings. Functions • The input signals for the speaker amplifier and headphone amplifier can be selected (DAC or PGA output). • Power-down control of individual function block and be exercised. • COCEC ADC for the digital recording of analog input signals DAC for outputting analog signals from the digital playback data • De-emphasis filter • When Y/C video signals are input, composite signals can be generated, and 3-system driver signals can be output. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. O1007 TI IM No.A0908-1/10 LC07422T Main Circuits Power Supply Voltage • Line selector • ALC/Limiter • EVR (analog volume) • ΔΣ type 16bit ADC/DAC • Headphone amplifier • Speaker amplifier • Video driver : 2 stereo inputs : 1 stereo circuit : 1 stereo circuit : 1 stereo circuit : 1 stereo circuit : 1 stereo circuit : 3 circuits (Y,C,V) VDD(digital) VDDio(digital IO) VDDana(analog) VDDsp(speaker) VDDh1,VDDh2(analog) VDDv(video) =2.8V(2.6 to 3.2V) =1.8V(1.71 to 3.2V) =2.8V(2.6 to 3.2V) =2.8V(2.6 to 3.2V) =4.8V(4.5 to 5.5V) =2.8V(2.6 to 3.2V) Package Dimensions unit : mm (typ) 3296 12.0 0.5 10.0 33 32 64 17 10.0 49 1 12.0 48 16 0.5 0.2 0.15 (1.0) 0.1 1.2max (1.25) SANYO : TQFP64(10X10) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Pin Assignment Lin2_R N.C. VSSana Vref_C VDDana VSSsub N.C. VDDadc VSSadc VSSdac VDDdac RESET_X MCLK LRCLK BCLK TESTin BEEPin SP_AMPin MIXout HPout_L HPout_R HPt_C VDDh1 Vref_H_C VSSh Lout_L Lout_R MONana_L MONana_R Lin2_L Lin1_L Lin1_R 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 LC07422T SPn VDDsp VSSsp SPp N.C. CPref_C CPn VSScp CPp CPminus_O CPminus_I Yout VDDv Vout Cout SDCout 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDDh2 VSSv Cin Yin HDin G_PORT2 G_PORT1 G_PORT0 VDDio VSS VDD SDin SCLK CS_X ADC_Dout DAC_Din 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Top view No.A0908-2/10 LC07422T Pin Description (Note) I/O: I=> input, Is=> Schmitt input, O=> output, IOs=> input/output PIN No. I/O Pin Name Is RESET_X Description Digital System 60 Reset (negative polarity) 61 I MCLK Master Clock 62 IOs LRCLK LR Clock (sample rate clock) Audio IF 63 IOs BCLK B Clock (serial data bit clock) Audio IF 64 I TESTin 1 Is DAC_Din For IC testing (VSS fixed in normal operation) 2 O ADC_Dout 3 Is CS_X Chip select (negative polarity) 4 Is SCLK Serial clock Microcontroller IF 5 Is SDin Serial data input Microcontroller IF 9 IOs G_PORT0 For IC testing (open in normal operation) 10 IOs G_PORT1 For IC testing (open in normal operation) 11 IOs G_PORT2 For IC testing (open in normal operation) 12 Is HDin 6 - VDD Digital power supply 7 - VSS Digital ground 8 - VDDio DAC serial data input Audio IF ADC serial data output Audio IF Microcontroller IF HD signal pulse input ( for test / Y signal clamp) Digital IO power supply Analog system 13 I Yin Y signal input 14 I Cin C signal input 17 O SDCout 18 O Cout C signal output 19 O Vout Video signal output 21 O Yout Y signal output DC output for SDC signal 22 I CPminus_I 23 O CPminus_O 24 IO CPp Charge pump pin Connect an external capacitor 26 IO CPn Charge pump pin Connect an external capacitor 27 O CPref_C Reference voltage Connect an external capacitor 29 SPp 32 SPn 33 I BEEPin 34 I SP_AMPin Connect to CPminus O pin Reference voltage (minus) Connect an external capacitor Speaker output Speaker output BEEP signal input Speaker amplifier input 35 O MIXout 36 O HPout_L Headphone output, Left channel Mixing circuit (L+R) output 37 O HPout_R Headphone output, Right channel 38 O HPt_C 40 O Vref_H_C 42 O Lout_L Line output, Left channel 43 O Lout_R Line output, Right channel 44 O MONana_L Time constant setting Connect an external capacitor Reference voltage (4.8V system) Connect an external capacitor For IC testing (open in normal operation) Continued on next page. No.A0908-3/10 LC07422T Continued from preceding page. PIN No. I/O Pin Name Description 45 O MONana_R 46 I Lin2_L Line input, Left channel 2 47 I Lin1_L Line input, Left channel 1 48 I Lin1_R Line input, Right channel 1 49 I Lin2_R Line input, Right channel 2 52 O Vref_C Reference voltage (2.8V system) 15 - VSSv 16 - VDDh2 20 - VDDv Analog power supply for video driver 25 - VSScp Ground for charge pump 30 - VSSsp Speaker analog ground 31 - VDDsp Speaker analog power supply 39 - VDDh1 41 - VSSh 51 - VSSana Analog ground 53 - VDDana Analog power supply 54 - VSSsub Ground 56 - VDDadc ADC analog power supply 57 - VSSadc ADC analog ground 58 - VSSdac DAC analog ground 59 - VDDdac DAC analog power supply Analog system For IC testing (open in normal operation) Connect an external capacitor Analog ground for video driver 4.8V system analog power supply ( for SDC circuit) 4.8V system analog power supply 4.8V system analog ground No.A0908-4/10 LC07422T Block Diagram Yin CLAM PGA Yout LPF Vout + Cin PGA Cout LPF HDin SDCout SDC to Speaker SPp BEEPin AMP control SPn SP_AMPin VREF(VDDh/2) Vref_H_C MIX VREF(VDDana/2) Vref_C EVR MIXout to Headphone HPout_L Selector HPout_R Selector HPt_C Lout_L Lout_R ALC/Limiter Lin1_L PGA Lin2_L ADC 16bit ALC cont. DAC 16bit InterFace Lin1_R PGA Lin2_R MPU MCLK BCLK LRCLK ADC 16bit DAC 16bit Divider 2 I S IF DAC_Din ADC_Dou t CS_X SCLK SDin Serial IF/ Register No.A0908-5/10 LC07422T General specifications (* fs = sampling frequency) Audio block • ΔΣ type 16-bit stereo ADC • ΔΣ type 16-bit stereo DAC • PGA for ALC/limiter • EVR (analog volume) : THD+N = 80dB (typ, with -1dBfs input) : THD+N = 80dB (typ, with 0dBfs input) : Amplifier gain => +34 to -14dB (in 0.5dB steps) : Amplifier gain => 0 to -65dB (The gain can be varied in steps from approx. 0.1 to 3.0dB; see characteristics diagram.) • Line output : Built-in pop noise suppression circuit • Speaker amplifier (monaural) : BTL drive, 250mW (3dBV, VDD = 2.8V, 8Ω, THD+N = 1%) • Headphone amplifier : Output level => 2dBV (typ, 108Ω, VDDh = 4.8V) • Sampling frequency : 48, 32kHz (44.1kHz supported by DAC only) • Audio data format I2S, left justification, right justification, BCLK: 64fs, 32fs, master/slave mode Video block • No need for output coupling capacitor, no generation of V sag • LPF : fc = 8MHz • Amplifier gain : 6.5dB±1.7dB, 0.1dB/step • 75Ω driver : 3 systems (Y, C, V) Common units • Master clock (MCLK pin input) : 256fs or 512fs, duty ratio = 50% (typ) • Microcontroller serial data format (register settings) : 3-line system (Chip select, clock, data) The maximum clock frequency is (1/4) MCLK. Video driver circuit [xxxx]: Resister setting PGA Yin Yout CLAMP LPF Cin LPF Vout + HDin Cout +aV Vref(+aV) -aV CPref_C SDCout SDC circuit CPn CPp [VD_SDC_SW] 11 10 01 00 Charge Pump SDCout Hi-Z VDDh 2.3V 0.0V CPminusO CPminusI Headphone amplifier circuit HPout_L/HPout_R 100Ω H.P. 8Ω HPt_C No.A0908-6/10 LC07422T Outline of operation 1. System reset/power-down When the RESET_X pin is set to “VSS,” the system is reset, and all the circuits go into the power-down mode. After the power is turned on, perform this operation once without fail. When the system is reset, the contents of the register are initialized. (See register tables.) For the subsequent startup of each function, refer to the section “Control/start/stop sequence for reducing pop noise.” 2. ALC When the ALC is active, the PGA (programmable gain amplifier) gain value is automatically adjusted so that the audio level becomes the preset value. The PGA gain can be adjusted in a range from +34 to -14dB. By limiting the gain adjustment range to 0 to -14dB, this adjustment function can be made to work as a limiter function. The ALC operation can be stopped by a register setting. The ALC is then placed in the manual mode, and the PGA gain is adjusted by the register setting. For details, refer to the section “Description of ALC/limiter operation.” 3. A/D converter The A/D converter converts the analog PGA output signals into digital data, and the digital data is then output as 16bit serial audio data. There are three formats supported: I2S, left justification and right justification. The A/D converter incorporates a high-pass filter for canceling DC offset. The analog input range of the ADC is 0.6VDDadc. When VDDadc is 2.8V, 0dBfs is 1.68V. 4. D/A converter The D/A converter converts the digital 16-bit serial audio data into analog signals. There are three formats supported: I2S, left justification and right justification. The D/A converter incorporates a high-pass filter for canceling DC offset. The analog input range of the ADC is 0.6VDDadc. When VDDadc is 2.8V, 0dBfs is 1.68V. 5. EVR This is an analog EVR. The gain can be set within a range from 0 dB to -65dB or mute (adjustable in steps). It is incorporated in the headphone and speaker amplifier path so that the output level of the headphones and speaker can be controlled separately from the line-out output. 6. Selector This selector is for selecting either the DAC or PGA output of the ALC. When the DAC output has been selected, the DAC output signals are output as the speaker amplifier and headphone amplifier output signals. When the PGA output has been selected, the signals from line input are all turned into analog signals to become the speaker amplifier and headphone amplifier output signals. 7. MIX This is the mixing circuit for the left- and right-channel audio signals. In other words, this functions as a monaural signal generator circuit to provide a monaural speaker amplifier input. The left- and right-channel signals are mixed on a 1:1 basis and then output through the -2dB amplifier. If the left- and right-channel signals are identical, the total gain becomes 4dB (= 6dB(doubled) -2dB). 8. SP AMP This is the monaural speaker amplifier. Its maximum output is 250mW (typ VDD =2.8V, 8Ω, THD+N = 10%). Inputs to the amplifier are the audio signal SP_AMPin pin and BEEPin pin signals. For the BEEPin pin signal, the mixing can be set ON or OFF, and the gain level can be selected (from –21 to –12dB). A thermal shutdown function is provided. When it is left enabled, the speaker amplifier operation is automatically shut down when the chip temperature has reached a high level. No.A0908-7/10 LC07422T 9. Video driver Negative power is generated by the charge pump circuit and supplied to the video driver. Therefore, the video driver operates on the positive and negative power supplies. The video signals are output with no DC components for the ground reference. As a result, with 75Ω termination, there is no need for an output coupling capacitor. In principle, no V sag is generated. 10. Register settings This is a 3-line system serial control circuit. The three lines are CS_X (Chip Select/low active), SCLK (Serial Clock) and SDin (Serial Data). Data can only be written into the register: The register data cannot be read out. The data transfer rate—in other words, the maximum SCLK frequency—depends on the MCLK pin clock. For details, refer to the section “Switching characteristics.” 11. Master clock The master clock frequency is 256fs. This clock signal must be input from the MCLK pin. A frequency divider (1/2) incorporated so an input with a frequency of 512fs can also be supplied. 12. Audio data formats I2S, left justification and right justification modes are supported. It is possible to select master or slave mode for BCLK and LRCLK. For details, refer to the section “Audio data formats.” No.A0908-8/10 LC07422T Register Table ADRS(Address): displayed in hexadecimal notation, Init (initial value): displayed in hexadecimal notation “0” settings are used for registers indicated with “0”. The shaded registers are for IC chip testing. Their initial values are fixed. Data must be set in all the registers. (The TEST1-8 addresses, including the registers for test purposes, are set in the sequence of 16 h to 1 Dh.) Function ADRS [7:0] Register Data D[7:0] INIT 7 6 5 4 3 2 1 0 PM1 00h 00h VREF_BIAS[1] VREF_BIAS[0] SYNC_CLR SEL_PDX ALC_PDX ADC_A_PDX DAC_A_PDX VIDEO_PDX PM2 01h 00h SP_OUTEN SP_PDX MIX_PDX HP_PDX LO_PDX ADC_D_PDX DAC_D_PDX EVR_PDX ALC1 02h 11h 0 0 LI_SEL_L[2] LI_SEL_L[1] 0 0 LI_SEL_R[2] LI_SEL_R[1] ALC2 03h 3Dh ALC_VAL[2] ALC_VAL[1] ALC_VAL[0] ALC_FA[1] ALC_FA[0] ALC_FR[2] ALC_FR[1] ALC_FR[0] ALC3 04h 86h ALC_ZCD ALC_ZCDTM[1] ALC_ZCDTM[0] ALC_FULLEN ALC_ATLIM[1] ALC_ATLIM[0] ALC_RWT[1] ALC_RWT[0] ALC4 05h 0Eh ALC_OFF ALC_VMAX[6] ALC_VMAX[5] ALC_VMAX[4] ALC_VMAX[3] ALC_VMAX[2] ALC_VMAX[1] ALC_VMAX[0] ALC5 06h 0Eh ALC_MUTE_L ALC_DVL[6] ALC_DVL[5] ALC_DVL[4] ALC_DVL[3] ALC_DVL[2] ALC_DVL[1] ALC_DVL[0] ALC6 07h 0Eh ALC_MUTE_R ALC_DVR[6] ALC_DVR[5] ALC_DVR[4] ALC_DVR[3] ALC_DVR[2] ALC_DVR[1] ALC_DVR[0] TEST0 08h 04h TEST0[7] TEST0[6] TEST0[5] TEST0[4] TEST0[3] TEST0[2] TEST0[1] TEST0[0] CODEC1 09h 00h 0 0 0 ADF_BCLK MCLK_DIV[1] MCLK_DIV[0] ADF_MODE[1] ADF_MODE[0] CODEC2 0Ah 00h DAC_INV ADC_INV 0 DE_EN ADF_FS[1] ADF_FS[0] ADF_LB ADF_MASTER SEL/MIX 0Bh A3h SEL_L[1] SEL_L[0] SEL_R[1] SEL_R[0] 0 0 MIX_MONO[1] MIX_MONO[0] EVR1 0Ch 80h EVR_MUTE_L 0 EVR_GAIN_L[5] EVR_GAIN_L[4] EVR_GAIN_L[3] EVR_GAIN_L[2] EVR_GAIN_L[1] EVR_GAIN_L[0] EVR2 0Dh 80h EVR_MUTE_R 0 EVR_GAIN_R[5] EVR_GAIN_R[4] EVR_GAIN_R[3] EVR_GAIN_R[2] EVR_GAIN_R[1] EVR_GAIN_R[0] EVR3 0Eh 2Eh 0 0 EVR_ZCD EVR_ZCDTM[1] EVR_ZCDTM[0] EVR_SOFTSW EVR_SSC[1] EVR_SSC[0] LINE 0Fh 0Bh 0 0 0 0 LO_GAIN[1] LO_GAIN[0] LO_VREFSW LO_MUTE HP 10h 01h 0 0 0 0 0 HP_PDNHIZ HP_REFEN HP_MUTE SPK 11h 18h SP_EXTBP_EN SP_EXTBP_G[1] SP_EXTBP_G[0] SP_TSD_EN SP_IDL[1] SP_IDL[0] SP_BIAS[1] SP_BIAS[0] VIDEO1 12h 11h 0 0 VD_Y_GAIN[5] VD_Y_GAIN[4] VD_Y_GAIN[3] VD_Y_GAIN[2] VD_Y_GAIN[1] VD_Y_GAIN[0] VIDEO2 13h 11h 0 0 VD_C_GAIN[5] VD_C_GAIN[4] VD_C_GAIN[3] VD_C_GAIN[2] VD_C_GAIN[1] VD_C_GAIN[0] VIDEO3 14h 30h 0 0 VD_SDC_SW[1] VD_SDC_SW[0] 0 0 VD_V_EN VD_YC_EN VIDEO4 15h 56h 0 VD_CP_CLK[2] VD_CP_CLK[1] VD_CP_CLK[0] 0 VD_CLP_W VD_CLP_POS VD_TEST_CLP TEST1 16h 00h TEST1[7] TEST1[6] TEST1[5] TEST1[4] TEST1[3] TEST1[2] TEST1[1] TEST1[0] TEST2 17h 00h TEST2[7] TEST2[6] TEST2[5] TEST2[4] TEST2[3] TEST2[2] TEST2[1] TEST2[0] TEST3 18h 00h TEST3[7] TEST3[6] TEST3[5] TEST3[4] TEST3[3] TEST3[2] TEST3[1] TEST3[0] TEST4 19h 04h TEST4[7] TEST4[6] TEST4[5] TEST4[4] TEST4[3] TEST4[2] TEST4[1] TEST4[0] TEST5 1Ah 00h TEST5[7] TEST5[6] TEST5[5] TEST5[4] TEST5[3] TEST5[2] TEST5[1] TEST5[0] TEST6 1Bh 00h TEST6[7] TEST6[6] TEST6[5] TEST6[4] TEST6[3] TEST6[2] TEST6[1] TEST6[0] TEST7 1Ch 01h TEST7[7] TEST7[6] TEST7[5] TEST7[4] TEST7[3] TEST7[2] TEST7[1] TEST7[0] TEST8 1Dh 00h TEST8[7] TEST8[6] TEST8[5] TEST8[4] TEST8[3] TEST8[2] TEST8[1] TEST8[0] ADRS INIT PM ALC ADC DAC EVR ADF =Address =Initial value =Power Management =Automatic Level Control =AD Converter =DA Converter =Electronic Variable Resistor =Audio Data Format PGA Lch Rch 2^n Nh Nb ABC[n] =Programmable Gain Amplifier =Left channel =Right channel =2n (ex. 2^10 = 1024) = N denotes a hexadecimal number. = N denotes a binary number. = Register with a multiple number of bits. ABC is the register name, and “n” is the number of bits. No.A0908-9/10 LC07422T Microcontroller Serial Interface The internal registers values are written by the serial interface consisting of the three CS_X, SCLK, and SDin lines. When the CS_X pin is set low, the LC07422T is switched into the mode that enables operation. The data is received on a byte basis with MSB first. Continuous access (burst access) is also possible, and the addresses incremented by 1 are accessed in sequence with each byte following access to the register specified by the address byte. If the size of data exceeding the highest address (1D) is accessed in this process, the data concerned is treated as invalid. In other word, the address never wraps around to 00 (HEX). The maximum data transfer rate (maximum SCLK frequency) depends on the MCLK pin clock. Refer to the section “Switching characteristics.” • Transferring data to one address: Data (D) is written in address (A) A[7:0] D[7:0] X : Designated address : Register data : Invalid CS_X SCLK X SDin X X A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] ADDRESS BYTE X WRITE DATA (address A) • Transferring data to contiguous addresses: Data (D0) is written in address (A), and data (D1) is written into address (A+1). CS_X SCLK X SDin X X A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] D0[7] D0[6] D0[5] D0[4] D0[3] D0[2] D0[1] D0[0] D1[7] D1[6] D1[5] D1[4] D1[3] D1[2] D1[1] D1[0] ADDRESS BYTE WRITE DATA (address A) Dn[0] X WRITE DATA (address A+1) SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of October, 2007. Specifications and information herein are subject to change without notice. PS No.A0908-10/10