Ordering number : ENA1201A CMOS IC LE24LB642M Two Wire Serial Interface EEPROM (64k EEPROM) Overview The LE24LB642M is a 2-wire serial interface EEPROM. It realizes high speed and a high level reliability by incorporating SANYO’s high performance CMOS EEPROM technology. This device is compatible with I2C memory protocol, therefore it is best suited for application that requires small-scale re-writable nonvolatile parameter memory. Functions • Capacity: 64k bits (8k × 8 bits) • Single supply voltage: 1.8V to 5.5V • Interface: Two wire serial interface (I2C Bus*) • Operating clock frequency: 400kHz • Low power consumption : Standby: 2μA (max) : Active (Read): 0.5mA (max) • Automatic page write mode: 32 Bytes • Read mode: Sequential read and random read • Erase/Write cycles: 106 cycles (Page writing), 105 cycles (Byte writing) • Data Retention: 20 years • High reliability: Adopts SANYO’s proprietary symmetric memory array configuration (USP6947325) Noise filters connected to SCL and SDA pins Incorporates a feature to prohibit write operations under low voltage conditions. * I2C Bus is a trademark of Philips Corporation. * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. 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To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 10511 SY/60408 SY IM 20080415-S00009 No.1201-1/12 LE24LB642M Package Dimensions unit:mm (typ) 3032E 5.0 0.63 4.4 6.4 8 1 (0.6) 2 1.27 0.15 0.1 (1.5) 1.7 MAX 0.35 SANYO : MFP8(225mil) Pin Assignment Pin Descriptions 8 1 NC 7 2 NC 6 3 NC 5 4 GND VDD WP SCL SDA PIN.1 NC Nonconnected pin PIN.2 NC Nonconnected pin PIN.3 NC Nonconnected pin PIN.4 GND Ground PIN.5 SDA Serial data input PIN.6 SCL Serial clock input/output PIN.7 WP Write protect PIN.8 VDD Power supply Block Diagram WP Write controller High voltage generator SDA I/O Buffer X decoder Address generator Serial controller Condition detector Input Buffer SCL EEPROM Array Y decoder & Sense AMP Serial-Parallel converter No.1201-2/12 LE24LB642M Specifications Absolute Maximum Ratings Parameter Symbol Conditions Ratings Supply voltage DC input voltage Over-shoot voltage Storage temperature Below 20ns Tstg unit -0.5 to +6.5 V -0.5 to +5.5 V -1.0 to +6.5 V -65 to +150 °C Note: If an electrical stress exceeding the maximum rating is applied, the device may be damaged. Operating Conditions Parameter Symbol Conditions Ratings Operating supply voltage Operating temperature unit 1.8 to 5.5 V -40 to +85 °C DC Electrical Characteristics Parameter Symbol VDD=1.8V to 5.5V Conditions min typ unit max Supply current at reading ICC1 f=400kHz, VDD=VDD max 0.5 mA Supply current at writing ICC2 CMOS standby current ISB f=400kHz, tWC=10ms, VDD=VDD max 3 mA VIN=VDD or VSS, VDD=VDD max 2 Input leakage current ILI VIN=GND to VDD, VDD=VDD max μA -2 2 Output leakage current ILO VIN=GND to VDD, VDD=VDD max μA -2 2 Input low voltage VIL μA VDD*0.2 Input low voltage (CMOS) VILC V 0.2 Input high voltage VIH VDD*0.8 V Input high voltage (CMOS) VIHC VDD-0.2 Output low voltage VOL1 IOL=3.0mA, VDD=2.5V to 5.5V 0.4 V VOL2 IOL=0.7mA, VDD=1.8V to 5.5V 0.2 V V V Capacitance/Ta=25°C, f=1MHz Parameter Symbol Conditions max unit Input pin capacitance CI VIN=0V (other than SDA) 10 pF In/output pin capacitance CI/O VI/O=0V (SDA) 10 pF Note: This parameter is sampled and not 100% tested. AC Electric Characteristics Input pulse level 0.1×VDD to 0.9×VDD Input pulse rise / fall time 20ns Output detection voltage 0.5×VDD Output load 50pF+Pull up resistor 3.0kΩ VDD R=3.0kΩ SDA C=50pF Output Load Circuit No.1201-3/12 LE24LB642M Parameter VDD=1.8V to 5.5V Symbol min unit typ max Slave mode SCL clock frequency fSCLS SCL clock low time tLOW 1200 400 ns SCL clock high time tHIGH 600 ns SDA output delay time tAA 100 SDA data output hold time tDH 100 ns Start condition setup time tSU.STA 600 ns Start condition hold time tHD.STA 600 ns Data in setup time tSU.DAT 100 ns Data in hold time tHD.DAT 0 ns Stop condition setup time tSU.STO 600 SCL SDA rise time tR 300 ns SCL SDA fall time tF 300 ns 900 kHz ns ns Bus release time tBUF Noise suppression time tSP 1200 50 ns ns Write cycle time tWC 10 ms Bus Timing tF tHIGH tLOW tR tSP SCL tSU.STA tHD.DAT tHD.STA tSU.DAT tSU.STO SDA/IN tSP tBUF tDH tAA SDA/OUT Write Timing tWC SCL SDA D0 Write Data Acknowledge Stop condition Start condition No.1201-4/12 LE24LB642M Pin Functions SCL (serial clock input) pin The SCL pin is a serial clock input pin that processes signals at the rising and falling edges of SCL clock signals. SDA (serial data input/output) pin The SDA pin is used to transfer serial data to the input/output, and it consists of a signal input pin and n-channel transistor open drain output pin. Like the SCL pin, the SDA pin must be pulled up by a resistor to the VDD level and wired-ORed with an open drain (or open collector) output device for use. WP (write protect) pin When the WP pin is high, write protection is enabled, and writing into the 64k bit memory areas is prohibited. When the pin is low, writing is possible to all memory areas. Read operations can be performed regardless of the WP pin status. Functional Description 1 Start condition When the SCL line is at the high level, the start condition is established by changing the SDA line from high to low. The operation of the EEPROM as a slave starts in the start condition. 2 Stop condition When the SCL line is at the high level, the stop condition is established by changing the SDA line from low to high. When the device is set up for the read sequence, the read operation is suspended when the stop condition is received, and the device is set to standby mode. When it is set up for the write sequence, the capture of the write data is ended when the stop condition is received, and the EEPROM internal write operation is started. tSU.STA tHD.STA tSU.STO SCL SDA Stop condition Start condition 3 Data transfer Data is transferred by changing the SDA line while the SCL line is low. When the SDA line is changed while the SCL line is high, the resulting condition will be recognized as the start or stop condition. tSU.DAT tHD.DAT SCL SDA No.1201-5/12 LE24LB642M 4 Acknowledge During data transfer, 8-bits are transferred in succession, and then in the ninth clock cycle period the device on the system bus receiving the data sets the SDA line to low, and sends the acknowledge signal indicating that the data has been received. The acknowledge signal is not sent during an EEPROM internal write operation. SCL (EEPROM input) 8 1 9 SDA (Master output) SDA (EEPROM output) Acknowledge bit output Start condition tAA tDH 5 Device addressing For the purposes of communication, the master device in the system generates the start condition for the slave device. Communication with a particular slave device is enabled by sending along the SDA bus the device address, which is 7-bits long, and the read/write command code, which is 1 bit long, immediately following the start condition. The upper four bits of the device address are called the device code which, for this product, is fixed as “1010.” This device has the upper 3-bit of the Slave Device address as the Slave address (S0, S1, S2), which fixed on the inside. The value of Slave address are S0=0, S1=0, S2=0. When the device code input from SDA and the slave addresses are compared with the product’s device code and slave addresses that were set at the mounting stage and found to match, the product sends the acknowledge signal during the ninth clock cycle period, and initiates the read or write operation in accordance with the read or write command code. If they do not match, the EEPROM returns to standby mode. When a read operation is performed immediately after the slave device has been switched, the random read command must be used. Slave Address Device Code 1 0 1 0 S2 MSB S1 S0 R/W LSB Device address word No.1201-6/12 LE24LB642M 6 EEPROM write operation 6-1. Byte writing When the EEPROM receives the 7-bit device address and write command code "0" after the start condition, it generates an acknowledge signal. After this, if it receives 4-bit don’t-care bits and a 12-bit word address, generates an acknowledge signal, receives the 8-bit writing data, and generates an acknowledge signal when it receives the stop condition, the rewrite operation of the EEPROM in the designated memory address will start. Rewriting is completed in the tWC period after the stop condition. During an EEPROM rewrite operation, no input is accepted and no acknowledge signals are generated. 1 0 1 0 S2 S1 S0 W * * A A A * 12 11 10 A9 A8 ACK R/W Data A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Stop SDA Start Word Address ACK ACK ACK *: don’t care 6-2. Page writing This product enables pages with up to 32 bytes to be written. The basic data transfer procedure is the same as for byte writing: Following the start condition, the 7-bit device address and write command code “0,” word address (n), and data (n) are input in this order while confirming acknowledge “0” every 9 bits. The page write mode is established if, after data (n) is input, the write data (n+1) is input without inputting the stop condition. After this, the write data equivalent to the largest page size can be received by a continuous process of repeating the receiving of the 8-bit write data and generating the acknowledge signals. At the point when the write data (n+1) has been input, the lower 5 bits (A0-A4) of the word addresses are automatically incremented to form the (n+1) address. In this way, the write data can be successively input, and the word address on the page is incremented each time the write data is input. If the write data exceeds 32 bytes or the last address of the page is exceeded, the word address on the page is rolled over. Write data will be input into the same address two or more times, but in such cases the write data that was input last will take effect. Finally, the EEPROM internal write operation corresponding to the page size for which the write data is received starts from the designated memory address when the stop condition is received. 1 0 1 0 S2 S1 S0 W * * A A A * 12 11 10 A9 A8 ACK Data(n) A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ACK ACK ACK R/W Data(n+x) Data(n+1) … D7 D6 - D1 D0 ACK ACK D7 D6 - D1 D0 ACK D7 D6 - D1 D0 D7 D6 - D1 D0 ACK Stop SDA Start Word Address(n) ACK *: don’t care No.1201-7/12 LE24LB642M 6-3. Acknowledge polling Acknowledge polling is used to find out when the EEPROM internal write operation is completed. When the stop condition is received and the EEPROM starts rewriting, all operations are prohibited, and no response can be given to the signals sent by the master device. Therefore, in order to find out when the EEPROM internal write operation is completed, the start condition, device address and write command code are sent from the master device to the EEPROM (slave device), and the response of the slave device is detected. In other words, if the slave device does not send the acknowledge signal, it means that the internal write operation is in progress; conversely, if it does send the acknowledge signal, it means that the internal write operation has been completed. When codes are sent by the master device during acknowledge polling, if a write or random read is to be performed next, the write command "0" is executed. If a current read or sequential read is to be performed next, the read command "1" is executed. After the write command "0" is executed and ACK="L" is confirmed, the start condition/stop condition is entered to cancel the command and change to standby mode. 1 0 1 0 S2 S1 S0 W During Write 1 0 1 0 S2 S1 S0 W NO ACK End of Write Start Start SDA Start During Write 1 0 1 0 S2 S1 S0 W NO ACK ACK R/W R/W R/W … 7 EEPROM read operations 7-1. Current address reading The address equivalent to the memory address accessed last +1 is held as the internal address of the EEPROM for both write* and read operations. Therefore, provided that the master device has recognized the position of the EEPROM address pointer, data can be read from the memory address with the current address pointer without specifying the word address. As with writing, current address reading involves receiving the 7-bit device address and read command code “1” following the start condition, at which time the EEPROM generates an acknowledge signal. After this, the 8-bit data of the (n+1) address is output serially starting with the highest bits. After the 8 bits have been output, by not sending an acknowledge signal and inputting the stop condition, the EEPROM completes the read operation and is set to standby mode. If the previous read address is the last address, the address for the current address reading is rolled over to become address 0. *: If the write data is 1 or more bytes but less than 32 bytes, the current address after page writing is the address equivalent to the number of bytes to be written in the specified word address +1. If the write data is 32 or more bytes, it is the designated word address. If the last address (A4-A0=11111b) on the page has been designated by byte write as the word address, the first address (A4-A0=0000b) on the page serves as the internal address after writing. 1 0 1 Data(n+1) 0 S2 S1 S0 R D7 D6 D5 D4 D3 D2 D1 D0 ACK Stop SDA Start Device Address NO ACK R/W No.1201-8/12 LE24LB642M 7-2. Random read Random read is a mode in which a selected memory address is specified and its data is read. The address is specified by a dummy write input. First, when the EEPROM receives the 7-bit device address and write command code "0" following the start condition, it generates an acknowledge signal. It then receives 4-bit don’t-care bits and a 12-bit word address and generates an acknowledge signal. These operations are used to load the word address to the address counter in the EEPROM. Next, the start condition is input again, and the current read is performed. This generates the word address data that was input using the dummy write input. After the data is generated, if the stop condition is input without the input of an acknowledge signal, reading is completed, and standby mode is established. Word Address(n) SDA Start Device Address 1 0 1 0 S2 S1 S0 W * * A A A * 12 11 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ACK ACK ACK R/W Dummy Write Data(n) 1 0 1 0 S2 S1 S0 R Stop Start Device Address D7 D6 - D1 D0 ACK NO ACK ACK R/W Current Read *: don’t care SDA Start Device Address 1 0 1 0 S2 S1 S0 R Data(n) D7 D6 - D1 D0 ACK R/W Data(n+1) Data(n+2) Data(n+x) D7 D6 - D1 D0 D7 D6 - D1 D0 D7 D6 - D1 D0 ACK ACK ACK Stop 7-3. Sequential read In this mode, the data is read continuously, and sequential read operations can be performed with both current address read and random read. If, after the 8-bit data has been output, acknowledge “0” is input and reading is continued without issuing the stop condition, the address is incremented, and the data of the next address is output. If acknowledge “0” continues to be input after the data has been output in this way, the data is successively output while the address is incremented. When the last address is reached, it is rolled over to address 0, and the data continues to be read. As with current address read and random read, the operation is completed by inputting the stop condition without sending an acknowledge signal. NO ACK No.1201-9/12 LE24LB642M Application Notes 1) Software reset function Software reset (start condition + 9 dummy clock cycles + start condition), shown in the figure below, is executed in order to avoid erroneous operation after power-on and to reset while the command input sequence. During the dummy clock input period, the SDA bus must be opened (set to high by a pull-up resistor). Since it is possible for the ACK output and read data to be output from the EEPROM during the dummy clock period, forcibly entering H will result in an overcurrent flow. Note that this software reset function does not work during the internal write cycle. Dummy clock cycle × 9 1 SCL 2 8 9 SDA Start condition Start condition 2) Pull-up resistor of SDA pin Due to the demands of the I2C bus protocol function, the SDA pin must be connected to a pull-up resistor (with a resistance from several kΩ to several tens of kΩ) without fail. The appropriate value must be selected for this resistance (RPU) on the basis of the VIL and IIL of the microcontroller and other devices controlling this product as well as the VOL–IOL characteristics of the product. Generally, when the resistance is too high, the operating frequency will be restricted; conversely, when it is too low, the operating current consumption will increase. RPU maximum resistance The maximum resistance must be set in such a way that the bus potential, which is determined by the sum total (IL) of the input leaks of the devices connected to the SDA bus and by RPU, can completely satisfy the input high level (VIH min) of the microcontroller and EEPROM. However, a resistance value that satisfies SDA rise time tR and fall time tF must be set. RPU maximum value = (VDD - VIH)/IL Example: When VDD=3.0V and IL= 2μA RPU maximum value = (3.0V − 3.0V × 0.8)/2μA = 300kΩ RPU minimum value A resistance corresponding to the low-level output voltage (VOL max) of SANYO’s EEPROM must be set. RPU minimum value = (VDD − VOL)/IOL RPU EEPROM Master device IL SDA CBUS IL Example: When VDD=3.0V, VOL = 0.4V and IOL = 1mA RPU minimum value = (3.0V − 0.4)/1mA = 2.6kΩ Recommended RPU setting RPU is set to strike a good balance between the operating frequency requirements and power consumption. If it is assumed that the SDA load capacitance is 50pF and the SDA output data strobe time is 500ns, RPU will be about RPU = 500ns/50pF = 10kΩ. No.1201-10/12 LE24LB642M 3) Notes on write protect operation This product prohibits all 32k bit writing when the WP pin is high. To ensure full write protection, the WP is set high for all periods from the start condition to the stop condition, and the conditions below must be satisfied. Item VDD=1.8 to 5.5V Symbol min typ unit max WP Setup time tSU.WP 600 ns WP Hold time tHD.WP 600 ns WP tHD.WP tSU.WP SCL SDA Start condition Stop condition 4) Precautions when turning on the power This product contains a power-on reset circuit for preventing the inadvertent writing of data when the power is turned on. The following conditions must be met in order to ensure stable operation of this circuit. No data guarantees are given in the event of an instantaneous power failure during the internal write operation. Item VDD=1.8 to 5.5V Symbol min Power rise time tRISE Power off time tOFF Power bottom voltage Vbot typ unit max 100 10 ms ms 0.2 V tRISE VDD tOFF Vbot 0V Notes: 1) The SDA pin must be set to high and the SCL pin to low or high. 2) Steps must be taken to ensure that the SDA and SCL pins are not placed in a high-impedance state. No.1201-11/12 LE24LB642M A. If it is not possible to satisfy the instruction 1 in Note above, and SDA is set to low during power rise After the power has stabilized, the SCL and SDA pins must be controlled as shown below, with both pins set to high. VDD VDD tLOW SCL SCL SDA SDA tDH tSU.DAT tSU.DAT B. If it is not possible to satisfy the instruction 2 in Note above After the power has stabilized, software reset must be executed. C. If it is not possible to satisfy the instructions both 1 and 2 in Note above After the power has stabilized, the steps in A must be executed, then software reset must be executed. 5) Noise filter for the SCL and SDA pins This product contains a filter circuit for eliminating noise at the SCL and SDA pins. Pulses of 50ns or less are not recognized because of this function. 6) Function to inhibit writing when supply voltage is low This product contains a supply voltage monitoring circuit that inhibits inadvertent writing below the guaranteed operating supply voltage range. The data is protected by ensuring that write operations are not started at voltages (typ.) of 1.3V and below. 7) Slave address setting This product does not include a slave address pin, but the information for the slave addresses, S0, S1 and S2, are held internally. The slave addresses of this product are set to S0=0, S1=0, and S2=0 when it is shipped. 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of January, 2011. Specifications and information herein are subject to change without notice. PS No.1201-12/12