TOSHIBA TC9WMB2FK

TC9WMB1FK,TC9WMB2FK
TOSHIBA CMOS Digital Integrated Circuits Silicon Monolithic
TC9WMB1FK,TC9WMB2FK
TC9WMB1FK: 1024-Bit (128 × 8 Bit) 2-Wire Serial E2PROM
TC9WMB2FK: 2048-Bit (256 × 8 Bit) 2-Wire Serial E2PROM
The TC9WMB1FK and TC9WMB2FK are electrically
erasable/programmable nonvolatile memory (E2PROM).
Features
·
2-wire serial interface (I2C BUSTM) (Note 1)
·
Single power supply
Read: VCC = 1.8 to 5.5 V
Write: VCC = 2.3 to 5.5 V
·
Low power consumption: 5 µA (in standby state)
Weight: 0.01 g (typ.)
: 0.5 mA (in read state)
·
Operating frequency: 400 kHz (VCC = 2.3 to 5.5 V)
·
Byte write and page (8-byte) write
·
Write protection
·
Sequential read
·
Write time: 10 ms (VCC = 3.0 to 5.5 V)
12 ms (VCC = 2.3 to 2.7 V)
·
Write endurance: 105 times
·
Data retention: 10 years
·
Wide operating temperature range: −40 to 85°C
·
Package: US8
2
Note 1: I C BUS is a trademark of Royal Philips Electronics N.V.
Product Marking
Pin Assignment (top view)
VCC WP SCL SDA
8
7
6
5
US8
Type name
B1 or B2
9WM
Pin 1 index
1
NC
2
NC
3
4
NC GND
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to
use these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
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TC9WMB1FK,TC9WMB2FK
Block Diagram
Serial clock input
SCL
Serial input/output
SDA
Timing
generator
Control
circuit
Power supply
(booster circuit)
VCC
Power supply
Write protection input
WP
Command
register
Memory cell
GND Ground
Address Address
register decoder
Input/Output
circuit
Data register
Pin Function
Pin Name
Input/Output
SCL
Input
SDA
Input/output
WP
Input
NC
¾
Description
Serial clock input
Data is fetched on a rising edge of SCL. Data is output on a falling edge of SCL.
Serial input/output
VCC
GND
This pin must be pulled up with a resistor because it is configured as an N-ch
open-drain pin for output.
Write protection input
A high on this input disables writing. A low on this input enables writing.
No connection (not connected internally)
1.8 to 5.5 V (for reading)
Power supply
2.3 to 5.5 V (for writing)
0 V (GND)
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TC9WMB1FK,TC9WMB2FK
Functional Description
1. Start and Stop Conditions
When SCL is high, pulling SDA low produces a start condition and pulling SDA high produces a stop
condition. Every instruction is started when a start condition occurs and terminated when a stop condition
occurs.
During a read, a stop condition causes the read to terminate and the chip to enter the standby state.
During a write, a stop condition causes the fetching of write data to terminate, after which writing starts
automatically. Upon the completion of writing, the chip enters the standby state.
Two or more start conditions cannot be entered consecutively.
tSU.STA tHD.STA
tSU.STO
SCL
SDA
Start condition
Stop condition
Figure 1
2.
Modifying Data
Data on the SDA input can be modified while SCL is low. When SCL is high, modifying the SDA input
means a start or stop condition.
tSU.DAT
tHD.DAT
SCL
SDA
Modify data
Modify data
Figure 2
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3. Acknowledge
Data is transmitted and received in 8-bit units. The receiver sends an acknowledge signal by outputting a
low on SDA in the 9th clock cycle, indicating that it has received data normally. The transmitter releases
the bus in the 9th clock cycle to receive an acknowledge signal.
During a write, the chip is always the receiver so that it outputs an acknowledge signal each time it has
received eight bits of data.
During a read, the chip outputs an acknowledge signal after it receives an address following a start
condition. Then, it outputs read data and releases the bus to wait for an acknowledge signal from the
master. When it detects an acknowledge signal, it outputs data at the next address if it does not detect a
stop condition. If the chip does not detect an acknowledge signal, it stops read operation, and enters the
standby state when a stop condition occurs subsequently.
If the chip does not detect an acknowledge signal nor a stop condition, it keeps the bus released.
SCL
1
8
9
SDA
SDA
tAA
tDH
Start condition
Acknowledge output
Figure 3
4. Device Addressing
After a start condition occurs, a 7-bit device address and a 1-bit read/write instruction code are input to
the chip.
The upper four bits are called device code, which must always be “1010”. The next three bits are used to
select a device on the bus. These three bits are not specified for this IC and can be set to any value.
The least significant bit ( R/ W : READ/ WRITE ) indicates a read instruction when set to 1 and a write
instruction when set to 0.
An instruction is not executed if the device address does not match the specified value.
Read/write instruction
code
Device address
Device code
1
0
1
0
×
×
MSD
×
R/W
LSB
×: Don’t care
Figure 4
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5. Write Operation
(1)
Byte write
A byte write writes data to a specified address. After a start condition, input a device address,
R/ W (= 0), a word address, and write data.
When a stop condition is entered subsequently, write operation starts automatically, rewriting the
data at the specified address with the input data. A next instruction cannot be accepted while write
operation is in progress. Therefore, no acknowledge signal is returned. After writing the data, the chip
automatically enters the standby state.
S
T
A
R
T
SDA LINE
W
R
I
T
E
DEVICE
ADDRESS
*
WRITE
DATA
W W WW W WW W
7 6 5 4 3 2 1 0
1 0 1 0 × × × 0
M
S
B
WORD
ADDRESS
DDDDDDDD
7 6 5 4 3 2 1 0
LA
SC
BK
L RAM
S / CS
BW K B
S
T
O
P
A
C
K
Address
increment
*: Don't care for the TC9WMB1
Figure 5
(2)
Page write
A page write writes up to eight bytes of data collectively to a specified page. After a start condition,
input a device address, R/ W (= 0), a word address (n), and write data (n), in the same way as for a
byte write. Then, input write data (n + 1) immediately without entering a stop condition, while
checking that an acknowledge signal is asserted (0).
The upper four bits (A3 to A6) of the word address are fixed and the lower three bits (A0 to A2) are
automatically incremented so that up to eight bytes of data can be input.
When the last address within the page is reached, the lower three bits (A0 to A2) of the word
address are rolled over to the first address of the page. If more than eight bytes of write data are
input, the last eight bytes are valid.
When a stop condition is entered subsequently, write operation starts automatically, rewriting the
data at the specified addresses with the input data.
S
T
A
R
T
SDA LINE
DEVICE
ADDRESS
W
R
I
T
E
1 0 1 0 × × × 0
M
S
B
WORD
* ADDRESS (n)
WRITE
DATA (n)
WRITE
DATA (n + 1)
W W WW W WW W
7 6 5 4 3 2 1 0
DDDDDDDD
7 6 5 4 3 2 1 0
DDDDDDDD
7 6 5 4 3 2 1 0
LRA
S / C
BW K
A
C
K
A
C
K
Address
increment
S
T
O
P
WRITE
DATA (n + m)
DDDDDD
5 4 3 2 1 0
A
C
K
Address
increment
A
C
K
Address
increment
*: Don't care for the TC9WMB1
Figure 6
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(3)
Acknowledge polling
Acknowledge polling is a feature for determining whether rewrite operation is in progress. During
rewrite operation, input a start condition, a device address, and R/ W (= 0 or 1). The acknowledge
feature does not output an acknowledge signal while rewrite operation is in progress. It outputs a low
acknowledge signal if rewriting has already completed.
If the next instruction is a write, input a word address and write data subsequently. If the next
instruction is a read, supply a stop condition and then start read operation.
(4)
Write protection
Driving the write protection (WR) pin high causes the TC9WMB1FK to protect the entire memory
area from being written and the TC9WMB2FK to protect the bottom half (80h to FFh) of the memory
area from being written. Rewriting is allowed when the write protection pin is low. While a write is in
progress, driving the WP pin high does not stop write operation.
Reading is always enabled regardless of whether the WP pin is high or low.
6. Read Operation
Read operation is performed in one of three modes: current address read, random read, and sequential
read.
For reading, enter a device address and R/W (= 1) after a start condition. After read data is output,
terminate read operation by inputting a high acknowledge signal (or releasing the bus without supplying an
acknowledge signal) and then supplying a stop condition.
(1)
Current address read
The internal address counter maintains the address that is next to the last accessed (read or
written) word address (n). In current address read mode, data is read from address n + 1, as indicated
by the address counter.
In current address read mode, entering a device address and R/W (= 1) after a start condition
causes the chip to output a low acknowledge signal and then data at the address indicated by the
internal address counter.
The address counter is incremented on a falling edge of the SCL pulse where the eighth bit is
output. If the previous operation was reading data from the last address, the current address is rolled
over to address 0. If the previous operation was writing data to the last address of the page, the
address is rolled over to the first address of the page.
The current address is maintained in an internal register so that it is lost when the power is turned
off. For the first read after power-up, specify an address by performing a random read.
S
T
A
R
T
SDA LINE
DEVICE
ADDRESS
1 0 1 0 × × × 1
M
S
B
S
T
O
P
R
E
A
D
DDDDDDDD
7 6 5 4 3 2 1 0
LRA
S / C
BW K
READ
DATA
N
O
A
C
K
Address
increment
Figure 7
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TC9WMB1FK,TC9WMB2FK
(2)
Random read
A random read reads data at a specified address. A dummy write is necessary to specify an address.
In random read mode, enter a device address, R/W (= 0), and a word address after a start condition.
Unlike a byte or page write, where write data is entered immediately, a dummy write only specifies a
word address. Then, supply a start condition and enter a device address and R/W (= 1) in the same
way as for a current address read, to read data from the specified address.
S
T
A
R
T
SDA LINE
DEVICE
ADDRESS
W
R
I
T
E
1 0 1 0 × × × 0
WORD
* ADDRESS (n)
W WW W WW W W
7 6 5 4 3 2 1 0
LA
SC
BK
LRAM
S / CS
BW K B
M
S
B
S
T
A
R
T
R
E
A
D
DEVICE
ADDRESS
S
T
O
P
DDDDDDDD
7 6 5 4 3 2 1 0
1 0 1 0 × × × 1
L
S
B
M
S
B
A
C
K
DATA (n)
READ
DATA (n)
DUMMY WRITE
N
O
A
C
K
Address
increment
*: Don't care for the TC9WMB1
Figure 8
(3)
Sequential read
A sequential read reads data sequentially from successive word addresses.
For either current address read or random read, after entering a start condition, a device address,
and R/W (= 1), inputting a low acknowledge signal causes the word address to be incremented
automatically to read data at the next address.
After the last address is reached, the word address is rolled over to address 0.
DEVICE
ADDRESS
SDA LINE
R
E
A
D
1
RA
/ C
WK
A
C
K
A
C
K
S
T
O
P
A
C
K
DDDDDDDD
7 6 5 4 3 2 1 0
DDDDDDDD
7 6 5 4 3 2 1 0
DDDDDDDD
7 6 5 4 3 2 1 0
DDDDDDDD
7 6 5 4 3 2 1 0
DATA (n)
DATA (n + 1)
DATA (n + 2)
DATA (n + m)
READ
DATA (n)
READ
DATA (n + 1)
READ
DATA (n + 2)
READ
DATA (n + m)
Address
increment
Address
increment
Address
increment
N
O
A
C
K
Address
increment
Figure 9
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7. Notes on Use
(1)
Powering up the chip
This IC contains a power-on clear circuit, which initializes the internal circuit of the IC when the
power is turned on. If initialization fails, the chip may malfunction. When powering up the chip,
observe the following precautions to assure that the clear circuit will operate normally:
(a) Pull SCL and SDA high.
(b) The power rising time (tR) must be 10 ms or less.
(c) After turning off the power, wait at least 100 ms (tOFF) before attempting to power up the chip
again.
(d) The supply voltage must rise from a voltage lower than 0.1 V.
(e) After turning on the power, wait at least 10 ms before attempting to send an instruction to the
chip.
VCC
VCC
0.1 V max
0V
tOFF
tR
10 ms
Figure 10
(2)
Pulling up the SDA and SCL pins
This IC requires the SDA and SCL pins to be pulled up with an external resistor. The recommended
pull-up resistance range is 1 kW to 10 kW.
(3)
Noise elimination time for the SDA and SCL pins
This IC contains a low-pass filter for eliminating noise on the SDA and SCL pins. Its guaranteed
value corresponds to the noise suppression time Ti, given in the AC characteristics table.
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Maximum Ratings (GND = 0 V)
Characteristics
Symbol
Rating
Units
Supply voltage
VCC
-0.3~7.0
V
Input voltage
VIN
-0.3~VCC + 0.3
V
VOUT
-0.3~VCC + 0.3
V
Power dissipation
PD
200 (25°C)
mW
Storage temperature
Tstg
-55~125
°C
Operating temperature
Topr
-40~85
°C
Output voltage
Recommended Operating Conditions (GND = 0 V, Topr = -40 to 85°C)
Characteristics
Symbol
Test Condition
Min
Max
Unit
Supply voltage (for reading)
VCC
¾
1.8
5.5
V
Supply voltage (for writing)
VCC
¾
2.3
5.5
V
2.3 V <
= VCC <
= 5.5 V
0.7 ´
VCC
VCC
1.8 V <
= VCC < 2.3 V
0.8 ´
VCC
VCC
2.3 V <
= VCC <
= 5.5 V
0
0.3 ´
VCC
1.8 V <
= VCC < 2.3 V
0
0.2 ´
VCC
2.3 V <
= VCC <
= 5.5 V
0
400
1.8 V <
= VCC < 2.3 V
0
100
High-level input voltage
Low-level input voltage
Operating frequency
VIH
VIL
fSCL
9
V
V
kHz
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TC9WMB1FK,TC9WMB2FK
Electrical Characteristics
DC Characteristics (GND = 0 V, Topr = -40 to 85°C)
Characteristics
Symbol
Test
Condition
1.8 <
= VCC < 2.3 V 2.3 <
= VCC <
= 3.6 V 4.5 <
= VCC <
= 5.5 V
Min
Max
Min
Max
Min
Max
Unit
Input current
ILI
¾
¾
±1
¾
±1
¾
±1
mA
Output leakage current
ILO
¾
¾
±1
¾
±1
¾
±1
mA
Low-level output voltage
VOL
IOL = 3.2 mA
¾
¾
¾
0.4
¾
0.4
IOL = 1.5 mA
¾
0.5
¾
¾
¾
¾
¾
5
¾
5
¾
5
mA
¾
V
Quiescent supply current
ICC1
Supply current during read
ICC2
f = 400 kHz
¾
0.2*
¾
0.3
¾
0.5
mA
Supply current during write
ICC3
f = 400 kHz
¾
¾
¾
1.5
¾
2.0
mA
*f = 100 kHz
AC Characteristics (GND = 0 V, Topr = -40 to 85°C)
Test Conditions
VCC
Input pulse voltage
0.1 ´ VCC~0.9 ´ VCC
Input rise/fall time
20 ns
Input/output testing voltage
RL = 1 kW
SDA
0.5 ´ VCC
CL = 100 pF
100 pF + 1 kW pull-up resistor
Output load
Characteristics
Symbol
1.8 <
= VCC < 2.3 V
2.3 <
= VCC <
= 3.6 V 4.5 <
= VCC <
= 5.5 V
Min
Max
Min
Max
Min
Max
Unit
SCL clock frequency
fSCL
0
100
0
400
0
400
kHz
SCL clock “low” time
tLOW
4.7
¾
1.2
¾
1.2
¾
ms
SCL clock “high” time
tHIGH
4.0
¾
0.6
¾
0.6
¾
ms
tI
¾
100
¾
50
¾
50
ns
SDA output delay
tAA
0.1
4.5
0.1
0.9
0.1
0.9
ms
Bus free time
tBUF
4.7
¾
1.2
¾
1.2
¾
ms
Start condition hold time
tHD.STA
4.0
¾
0.6
¾
0.6
¾
ms
Start condition setup time
tSU.STA
4.7
¾
0.6
¾
0.6
¾
ms
Data input hold time
tHD.DAT
0
¾
0
¾
0
¾
ns
Data input setup time
tSU.DAT
250
¾
200
¾
200
¾
ns
Noise suppression time
SCL, SDA input rise time
tR
¾
1.0
¾
0.3
¾
0.3
ms
SCL, SDA input fall time
tF
¾
0.3
¾
0.3
¾
0.3
ms
Stop condition setup time
tSU.STO
4.7
¾
0.6
¾
0.6
¾
ms
tDH
100
¾
50
¾
50
¾
ns
SDA output hold time
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TC9WMB1FK,TC9WMB2FK
2
< 2.7 V, Topr = -40 to 85°C)
< VCC =
E PROM Characteristics (GND = 0 V, 2.3 V =
Characteristics
Write time
Symbol
Test Condition
Min
tWR
¾
¾
5
Typ.
Max
Unit
¾
12
ms
Rewrite endurance
NEW
¾
1 ´ 10
¾
¾
Times
Data retention time
tRET
¾
10
¾
¾
Years
Typ.
Max
Unit
¾
10
ms
2
< 5.5 V, Topr = -40 to 85°C)
E PROM Characteristics (GND = 0 V, 2.7 V < VCC =
Characteristics
Write time
Symbol
Test Condition
Min
tWR
¾
¾
5
Rewrite endurance
NEW
¾
1 ´ 10
¾
¾
Times
Data retention time
tRET
¾
10
¾
¾
Years
Typ.
Unit
Capacitance Characteristics (Ta = 25°C)
Characteristics
Symbol
Test Condition
VCC (V)
Input capacitance
CIN
¾
5.0
4
pF
Output capacitance
CO
¾
5.0
3
pF
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AC Characteristics Timing Charts
tF
tHIGH
tLOW
tR
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.STO
tSU.DAT
SDA
(Input)
tAA
tDH
tBUF
SDA
(Output)
Figure 11
Bus Timing
SCL
SDA
(Input)
DO
tWR
Write data
input
Acknowledge
output
Stop
condition
Start
condition
Figure 12 Write Cycle Timing
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Input/Output Circuits of Pins
Pin
Type
Input/Output Circuit
WP
Input
¾
SCL
Input
¾
SDA
Input/output
Open-drain output
13
Remarks
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TC9WMB1FK,TC9WMB2FK
Package Dimensions
Weight: 0.01 g (typ.)
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TC9WMB1FK,TC9WMB2FK
RESTRICTIONS ON PRODUCT USE
000707EBA
· TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
· The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
· The products described in this document are subject to the foreign exchange and foreign trade laws.
· The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
· The information contained herein is subject to change without notice.
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