Ordering number : EN*A1990 LV23411V Bi-CMOS LSI For Home Stereo Systems FM/AM Tuner IC Overview The LV23411V is single chip tuner IC, and FM/AM radio is able to be realized with few external parts. Functions • FM tuner • AM tuner • MPX Stereo Decoder • Tuning system Features • No alignments necessary • Reduction of external component counts • Large audio output signal is available for home stereo systems • Worldwide FM band support (64 to 108MHz) • Worldwide AM band support (520 to 1710kHz) • Soft-mute, Stereo-blend function • LV23411 corresponds to Europe Immunity standard (EN55020-S1) • I2C control interface Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. O2611 SY PC No.A1990-1/23 LV23411V Specifications Absolute Maximum Ratings at Ta = 25°C, GND1 = GND2 = GND3 = GND4 = GND5 = 0V Parameter Symbol Conditions Ratings Unit Maximum supply voltage VCC max 10.0 V Digital output voltage VO max SDA 3.6 V Digital input voltage VIN1 max SDA, SCL 3.6 V VIN2 max CLK IN 3.6 V Allowable power dissipation Pd max Ta ≤ 70°C *1 450 mW Operating temperature Topr -20 to +70 °C Storage temperature Tstg -40 to +125 °C *1 : Mounted on a specified board. Board size is 114.3mm × 76.1mm × 1.6mm, glass epoxy. Operating Conditions at Ta = 25°C, GND1 = GND2 = GND3 = GND4 = GND5 = 0V Parameter Symbol Recommended supply voltage VCC Operating supply voltage Range VCC op * Note Conditions Ratings Unit 9.0 V Register 1Eh bit 1 (LEVSHIF) = 0 4.5 to 6.5 V Register 1Eh bit 1 (LEVSHIF) = 1 8.5 to 9.5 V * Note : supply the stabilized voltage. Interface Conditions at Ta = -20 to +70°C, GND1 = GND2 = GND3 = GND4 = GND5 = 0V Parameter Symbol Ratings Conditions min High level input voltage Low level input voltage typ Unit max VIH1 SDA, SCL 2.3 3.5 V VIH2 CLK IN 2.3 3.5 V VIL1 SDA, SCL 0 0.5 V V VIL2 CLK IN 0 0.3 Output voltage VO SDA 0 3.5 Crystal frequency fin CLK IN Crystal frequency accuracy faccuracy 32.768 -100 V kHz +100 ppm Operating Characteristics at Ta = 25°C, VCC = 9.0V, with the designated circuit. Parameter Symbol Ratings Conditions min typ Unit max [FM characteristics ; MONO] : fc = 98MHz, VIN = 60dBμV, fm = 1kHz, De-emphasis = 50μs, IF = 225KHz, BW = 45% MONO : 75kHz dev STEREO : L+R = 67.5kHz dev, Pilot = 7.5kHz dev Volume level = 3, Register 1Eh bit 1 (LEVSHIF) = 1, Pin 9 output, Audio filter = IHF-BP F, Soft mute = off ,Soft stereo = off Current drain ICC FM No input 30dB S/N sensitivity SN30 S/N = 30dB input level Signal-to-noise ratio SNR MONO Total harmonic distortion THD MONO 35 62 40 45 mA 10 15 dBμV 70 0.5 dB 1.5 % THD-ST STEREO 0.5 2.5 Demodulation output VO3 MONO 518 775 1160 SD operation level SD FS = 4 17 25 33 Mute attenuation Mute MONO 60 75 dB Stereo separation Sep Pin 10 output/Pin 9 output 20 35 dB Carrier leak CL STEREO SNR, Audio filter = OFF 30 Stereo on level ST-ON L+R = 67.5kHz dev, Pilot level 40 % mVrms dBμV dB 3.0 6.5 % 35 40 mA 48 65 dBμV [AM characteristics] : fc = 1MHz, VIN = 94dBμV, fm = 400Hz, mod = 30% IF = 53KHz, BW = 50% Volume level = 2, Register 1Eh bit 1 (LEVSHIF) = 1, Pin 9 output, Audio filter = 15kHz LPF OFF Current drain ICC AM No input 20dB S/N sensitivity SN20 S/N = 20dB input level Signal-to-noise ratio SNR Total harmonic distortion THD 30 42 50 dB 0.8 2.8 % Demodulation output VO2 122 173 245 mVrms SD operation level SD FS = 4 46 54 64 dBμV Mute attenuation Mute 15kHz LPF ON 50 65 dB No.A1990-2/23 LV23411V Package Dimensions unit : mm (typ) 3259 9.75 30 0.5 7.6 5.6 16 15 1 0.65 0.15 0.22 0.08 (1.0) 1.2max (0.33) SANYO : TSSOP30(275mil) Block Diagram 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Ref .osc Osc cap FLL 16 GND LNA Local oscillator Divider Power management LDO State machine Tuning system AGC DET SD out BPF Demodulator Stereo decoder De-emphasis Stereo blend ST out Image det LNA Audio amp. Ant cap 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 No.A1990-3/23 LV23411V Pin descriptions Pin Pin name I/O Descriptions Remarks DC voltage 1 AM-ANT I AM antenna input Connect to pin2 through Matching coil or Ferrite antenna. - 2 AM-REF O Reference voltage for AM part Connect to pin1 through Matching coil or Ferrite antenna. 2.2V 3 AM-CAP I AM capacitor bank Exteranal inductor (recommendation value) is connected - between this pin and GND. 4 GND1 - AM antenna GND Connected to GND 5 VREF1 O Reference voltage for analog Capacitor of 1μF is connected between this pin and GND. 4.3V 0V 6 MPX IN_OUT O Demodulato output When RDS used, LC72725 is applicable 2.5V 7 AM RF-AGC O AM RF AGC output Capacitor of 1μF is connected between this pin and GND. 8 GND2 - Analog GND Connected to GND 9 L-OUT O Audio Lch output According to the VCC_application, Reference Output_level R-OUT O Audio Rch output 11 VCC-Low - Voltage supply pin at low voltage operation 2.6V (3.7V) setting is cangeable by Register Bit. 10 0V Register 1Eh bit 1 (LEVSHIF) =1: Register 1Eh bit 1 (LEVSHIF) =0: When using VCC < 6V, Connect to Pin15 directly - mode 12 AM LCF O AM low_cut filter Capacitor of 0.047uF is connected between this pin and 2.2V GND. 13 SD-OUT O SD indicator output Active low output 3.0V (0.1V) 14 ST-OUT O ST indicator output Active low output 3.0V (0.1V) 15 VCC - Voltage supply pin 16 CLK_IN I Reference clock input 32.768kHz crystal connected to GND. - It is Also applicable to input directly clock signals ( square wave GND_reference) 17 IF AGC CAP - IF-AGC monitor point (test) Open - 18 SD-ADJ - Adjustment for SD on level Incase of changing SD on level, put Resistor between this - 19 NC I 20 SCL I 21 SDA I/O I2C interface Data input/output 22 VREF2 O Output voltage pin for VDD 23 GND3 - Digital GND for control part pin and GND. I2C interface CLK input VDD output_pin of 3.0V. This pin is applicable to supply the current other IC up to 3.0V 10mA. 0V 24 L1 - Local oscillator 25 VREF3 O Reference voltage for local OSC part 39nH connected to pin 25 26 L2 - Local oscillator 39nH connected to pin 25 27 GND4 - Analog GND for OSC part Connected to GND 28 FLL-CAP - Oscillator tuning voltage output Capacitor of 0.1μF is connected between this pin and 5.0V 0V - GND. 29 GND5 - Analog GND for FMRF part Connected to GND 30 FM-ANT I FM antenna input 1 Input impedance is 75Ω 0V 0.8V No.A1990-4/23 LV23411V Pin internal circuit description Pin No. 1 Pin name AM-ANT Pin voltage (V) 2.2 Description AM antenna input pin. The AM antenna coil is connected between pins Internal equivalent circuit 1 2 R 40 and this pin. R R = 100Ω 2 AM-REF 2.2 Reference voltage pin for AM. 15 VAM-REF = 2.2V 2.2V Regulator 2 3 AM-CAP - Tuning pinl for AM. (AM Capacitor Bank) 4 GND1 0 5 VREF1 4.3 CAP-BANK 3 GND pin for Analogue AM_FE part. Analogue part (tuner) reference bias terminal. 15 VREF1 = 4.3V 4.3V Regulator 5 6 MPX IN_OUT 2.5 FM demodulation output /input for MPX. R = 100Ω 6 7 AM RF-AGC - R Pin for AM_RF AGC. R1 = 2MΩ R2 = 5kΩ R2 R3 = 250Ω R4 = 1kΩ R4 7 R3 R1 8 GND2 0 9 L-OUT 2.6 10 R-OUT (3.7V when LEVSHIF = 1) GND pin for Analogue tuner part. L-ch (R-ch) output pin. R = 100Ω 15 ROUT = 150Ω 10 R 9 Continued on next page. No.A1990-5/23 LV23411V Continued from preceding page. Pin No. 11 Pin name VCC-Low Pin voltage (V) - Description Internal equivalent circuit when using with VCC < 6.0V, 11Pin-15 Pin is 15 shorted. 5V Regulator 11 4.3V Regulator 12 AM LCF 2.2 Terminal for AM Low-cut Filter. R4 R1 = 250Ω R2 = 100kΩ R1 12 R2 R3 = 100kΩ R5 R3 R4 = 50kΩ R5 = 50kΩ 13 SD-OUT 3.0 (less than 0.1) SD indicator output pin. 22 Active Low output. R = 100kΩ R 13 SD SW 14 ST-OUT 3.0 (less than 0.1) FM stereo indicator output pin 22 Active Low output R = 100kΩ R 14 ST SW 15 VCC VCC Analogue part power supply pin. When using 8.5 to 9.5V, set to Register 1Eh Bit 1 (LEVSHIF) = 1 When using with VCC < 6.5V, set to Register 1Eh Bit 1 (LEVSHIF) = 0 And 11Pin-15Pin must be shorted “ 16 CLK_IN 2.1 (OSC mode) For internal reference clock. 32.768kHz crystal connected to GND. It is Also R 16 applicable to input directly clock signals ( square wave GND_reference) Crystal oscillator R = 100Ω 17 IF AGC CAP - This pin is for test. R1 Open R2 R3 R1 = 1.5kΩ, R2 = 1kΩ, R3 = 500Ω 17 18 SD-ADJ - Open normally. COMP Adjust pin for SD sensitivity with to kΩ resistor connected to GND 18 R Continued on next page. No.A1990-6/23 LV23411V Continued from preceding page. Pin No. Pin name Pin voltage (V) 19 NC - 20 SCL - Description Internal equivalent circuit Digital interface CLK line. R = 1kΩ 21 SDA SCL R 20 Digital interface DATA line. (Interactive data communication line.) data Require pull_up resistor 3.3k to 10k between this pin and Vref2 (VDD). R = 250Ω R 21 data 22 VREF2 3 Reference voltage output pin for Logic part. 15 Vref2 = 3V 3V Regulator 22 23 GND3 0 GND pin for digital part (Control part). 24 L1 5 OSC coil of 39nH to be connected between this 26 L2 24 pin and pin 25. 26 CAP BANK 25 VREF3 5 CAP BANK Reference voltage pin for local oscillation circuit. 15 5V Regulator 25 27 GND4 0 28 FLL-CAP - GND pin for local oscillation circuit. LPF pi n for controlled FLL internally. R = 80kΩ 28 29 GND5 0 GND pin for local oscillation circuit. Continued on next page. No.A1990-7/23 LV23411V Continued from preceding page. Pin No. 30 Pin name FM-ANT Pin voltage (V) 0.8 Description Internal equivalent circuit FM antenna input pin FM. R = 1.5kΩ Rin = 75Ω 30 R 29 Used parts Component Parameter Value Tolerance Type Supplier L1 Local Osc Coil 39nH 5% LL2012-FHL39NJ TOKO L2 Local Osc Coil 39nH 5% LL2012-FHL39NJ TOKO L3 AM Loop antenna 18.1μH 5% 4910-CSL18R1JN1 SAGAMI T1 AM RF matching 250μH - A90326057 COILS #7003RNS-A1109YZS TOKO C1 Ripple Filter 1μF C2 AM RF AGC Capacitor 1μF C3 Coupling Capacitor 1μF C4 Coupling Capacitor 1μF C5 Supply Bypass Capacitor 0.1μF C6 Supply Bypass Capacitor 22μF C7 AM Low-cut Filter 0.1μF C8 Supply Bypass Capacitor 22μF C9 Osc Filter 0.1μF C10 Ripple Filter 0.1μF R1 Pulled-up Resistor 4.7kΩ R2 Pulled-up Resistor 4.7kΩ to kΩ R3 SD Adjust Resistor BPF FM ANT BPF - - GFMB7 SOSHIN X1 Crystal 32.768kHz 100ppm DT-26 KDS LO1 AM Ferrite antenna 260μH TBD - - No.A1990-8/23 LV23411V Format of Bus Transfers Bus transfers are primarily based on the I2C primitives • Start condition • Repeated start condition • Stop condition • Byte write • Byte read Start, restart, and stop conditions are specified as shown in Table 1 below. Start Repeated start Stop SCL SCL SCL SDA SDA SDA Fig. 1 the I2C start, repeated start and stop conditions. For details, like timing, etc., refer to specifications of I2C. 8-bit write 8-bit data is sent from the master microcomputer to LV23411. Data bit consists of MSB first and LSB last. Data transmission is latched at the rising edge of SCL in synchronization with the SCL clock generated at the master IC. Do not change data while SCL remains HIGH. LV23411 outputs the ACK bit between eighth and ninth falling edges of SCL SCL SDA D7 D6 D5 D4 D3 D2 D1 D0 Ack Fig. 2 Signal pattern of the I2C byte write Read is of the same form as write, only except that the data direction is opposite. Eight data bits are sent from LV23411 to the master while Ack is sent from the master to LV23411. SCL SDA D7 D6 D5 D4 D3 D2 D1 D0 Ack Fig. 3 Signal pattern of the I2C byte read The serial clock SCL is supplied from the master side. It is essential that data bit is output from LV23411 in synchronization with the falling edge while the master side performs latching at the rising edge. No.A1990-9/23 LV23411V LV23411 latches ACK at the rising edge. The sequence to write data D into the register A of LV23411 is shown below. • Start condition • write the device address (C0h) • write the register address, A • write the target data, D • stop condition start write device address SCL DA7 SDA Ack DA6...1 write register address A7 A6...1 write data byte Ack D7 stop Ack D6...0 Fig. 4 Register write through I2C When one or more data has been provided for writing, only the first data is allowed to be written. Read sequence • start condition • write the device address (C0h) • write the register address, A • repeated start condition (or stop + start in a single master network) • write the device address + 1 (C1h) • read the register contents D, transmit NACK (no more data to be read) • stop condition start write device address write register address rep. SCL DA7 SDA start DA6...1 Ack write device address + 1 DA7 DA6...1 A7 A6...0 read data byte with NACK Ack D7 Ack stop D6...0 Fig. 5 Register read through I2C Interrupt Pin INT LV23411 has the dedicated interrupt output pin. For the active level to the host, either LOW or HIGH can be selected. The INT output pin is kept floating while the PWRAD bit is cleared during initialization. Therefore, to avoid influence on the CPU side during initialization, it is recommended to secure the non-active state by means of the pull-up or pull-down resistor. This enables direct INT output connection to non-masking interruption of the host CPU. No.A1990-10/23 LV23411V Digital interface specification (interface specification : reference) (1). Characteristics of SDA and SCL bus line relative to the I2C bus interface Repeated START START Condition Tf TLOW Tr THIGH SCL Tf Tr SDA THD;STA THD;DAT TSU;DAT TSU;STA Standard-mode Parameter SCL clock frequency Fall time of both SDA and SCL Rise time of both SDA and SCL Symbol FSCL min High_Speed-mode max 0 Tf Tr min unit max 100 0 400 kHz 300 20+0.1Cb 300 ns 1000 20+0.1Cb 300 ns High time of SCL THIGH 4.0 0.6 μs Low time of SCL TLOW 4.7 1.3 μs Hold time of STAT condition THD ; STA 4.0 Hold time of Data THD ; DAT 0 Set-up time of STAT condition TSU ; STA 4.7 Set-up time of STOP condition TSU ; STO Set-up time of Data TSU ; DAT TBUF 4.7 Bus free time between a STOP and μs 0.6 3.45 0 0.9 μs 0.6 μs 4.0 0.6 μs 250 100 ns 1.3 μs START condition Capacitivie load for each bus line Cb 400 400 pF *Cb = Total capacitance of one bus line No.A1990-11/23 LV23411V Description of the Register of LV23411V Register 00h - CHIP_ID - Chip identify register (Read-Only) 7 ID[7:0] Bit 7-0 : 6 5 4 3 2 1 0 1 0 1 0 TUNED ID[7:0] : 8-bit Chip ID LV243411 : 1Bh Note : To abort the command, write any value in this register. Register 01h - CHIP_REV - Chip Revision identify register (Read-Only) 7 6 5 4 Revision[7:0] Bit 7-0 : ID[7:0] : 8-bit Chip Revision ES1 : 00h Note : To abort the command, write any value in this register. 3 2 Register 02h - RADIO_STAT - Radio station status (Read-Only) 7 IM_STAT Bit 7 : 6 5 4 3 2 IM_FS[1:0] MO_ST FS[2:0] IM_STAT : State of Image-station avoidance 0 = Normal (Possible to write) 1 = The Image-station avoidance is being processed (Impossible to write) Note : This bit works only at Register14h_bit7 (IM_EVAS) is set to “1”. The writing processing to LV23411 is prohibited when this bit is “1”. Bit 6-5 : IM_FS : Image-signal Fieldstrength 0 : No image-signal 1 : There are weak Image-signal that level is less -10dB or more weaker than desire’s 2 : The level of the image –signal is around 0 - 10dB compared with desire’s 3 : The level of the image-signal is +10dB or more stronger than that of desire’s Bit 4 : MO_ST : Mono/Stereo indicator 0 = Forced monaural 1 = Normal (Receiving in stereo mode) Bit 3-1 : FS[2:0] : Fieldstrength 0 : FS < 10 dBμV 1 : FS = 10 - 20 dBμV 2 : FS = 20 - 30 dBμV ……… 7 : FS > 70 dBμV Bit 0 : TUNED : Radio tuning flag. 0 = No tuned 1 = Tuned Note : When the tuning command succeeds, this bit is set. This bit is cleared under 3 conditions as below. 1. PW_RAD = 0 2. Tuning Frequency 3. When FLL becomes outside the correction range No.A1990-12/23 LV23411V Register 04h - TNPL - Tune position low (Read-Only) 7 6 5 4 3 TUNEPOS[7:0] Bit 7-0 : TUNEPOS[7:0] : Current RF Frequency (Low 8 bit) 2 1 0 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 2 1 0 2 1 0 3 2 1 0 3 2 1 0 Register 05h - TNPH_STAT - Tune position high/status (Read-Only) 7 6 5 4 3 ERROR[1:0] TUNEPOS[12:8] Bit 7-6 : ERROR[1:0] : Error code ERROR[1:0] Remark 0 OK, Command end (No Error) 1 DAC Limit Error 2 Command forced End 3 Command busy Bit 5:0 : TUNEPOS[13:8] : Current RF Frequency (High 5 bit) Register 06h - COUNT_L - Counter low (Read-Only) 7 6 5 4 COUNT[7:0] Bit 7-0 : COUNT[7:0] : Counter value (Low 8 bit) Register 07h - COUNT_H - Counter High (Read-Only) 7 6 5 4 COUNT[15:8] Bit 7-0 : COUNT[15:8] : Counter value (High 8 bit) Register 08h - IF_OSC - DAC for IF OSC (Read/Write) 7 IFOSC[7:0] Bit 7-0 : 6 5 4 IFOSC[7:0] : IF Oscillator DAC Register 09h - IFBW-DAC for IF - Filter Band width (Read/Write) 7 IFBW[7:0] Bit 7-0 : 6 5 4 3 IFBW[7:0] : IF-Filter Band width DAC Register 0Bh - STEREO_OSC - DAC for Stereo Decoder OSC (Read/Write) 7 6 5 4 SDOSC[7:0] Bit 7-0 : SDOSC[7:0] : Stereo Decoder Oscillator DAC 3 Register 0Ch - RF_OSC - DAC for RF OSC (Read/Write) 7 6 5 4 RFCAP[7:0] Bit 7-0 : RFOSC[7:0] : RF Oscillator DAC Register 0Dh - RFCAP - RF Cap bank (Read/Write) 7 6 5 4 RFCAP[7:0] Bit 7-0 : RFCAP[7:0] : RF Oscillator Capacitor-Bank No.A1990-13/23 LV23411V Register 0Eh - AMCAP1 - AM - ANT Cap bank1 (Read/Write) 7 6 5 4 AMCAP[7:0] Bit 7-0 : AMCAP[7:0] : AM Antenna Capacitor-Bank 3 2 1 0 2 ACAP10 1 ACAP9 0 ACAP8 Note : The AM antenna capacitor bank is composed of 12 bits. High 4 bit is arranged at “AMCTRL” register. Register 0Fh - AMCTRL - AM Station Control (Read/Write) 7 AMDIV[2:0] Bit 7-5 : Bit 7 : Bit 6 : Bit 5 : 6 5 4 AM_CAL 3 ACAP11 AMDIV[2:0] : AM Clock Divider AM_CD2 : AM Clock Divider bit 2. AM_CD1 : AM Clock Divider bit 1. AM_CD0 : AM Clock Divider bit 0. Note : The AM_CD[2:0] is used to decrease frequency from FM - band to AM - band. Please set AM_CD to “0” at FM mode. AM_CD[2:0] 0,1 2 3 4 5 6 7 Divide-Rate Divider OFF 224 160 112 80 64 48 Bit 4 : NA (Fixed to “0”) Bit 3-0 : Bit 3 : Bit 2 : Bit 1 : Bit 0 : AMCAP[11:8] : AM Antenna Capacitor-Bank AMCAP_bit 11 AMCAP_bit 10 AMCAP_bit 9 AMCAP_bit 8 AM-RF frequency (In kHz) 0 (FM mode) 338 - 483 474 - 676 676 - 966 947 - 1353 1183 - 1692 1578 - 2256 Register 10h - DO_REF_CLK_CNF - DO output mode and reference clock configuration (Read/Write) 7 IPOL Bit 7-5 : 6 5 DO_SEL[1:0] NA (Fixed to “0”) Bit 4-3 : EXT_CLK_CFG[1:0] : External Clock Setting EXT_CLK_CFG[1:0] 00 01 10 11 Bit 2-0 : 4 3 EXT_CLK_CFG[1:0] 2 FS_S[2:0] 1 0 Reference clock Off Oscillator clock source (External Clock source) 32768Hz crystal oscillator No use FS_S[2:0] : SD (Station Detector) operation level setting No.A1990-14/23 LV23411V Register 11h - IF_SEL - IF frequency selection (Read/Write) 7 FLL_MOD Bit 7 : 6 5 4 AMIF[2:0] FLL_MOD: FLL operation mode 0 : Smoothing Filter = OFF 1 : Smoothing Filter = ON Bit 6-4 : AMIF[2:0] : IF frequency setting at AM mode 0 20kHz Bit 3-0 : 1 31kHz 3 FMIF[3:0] AMIF[2:0] 3 4 53kHz 64kHz 2 42kHz 2 1 5 75kHz 0 6 86kHz 7 97kHz FMIF[3:0] : IF frequency setting at FM mode (kHz) SE_AM RF_SEL FMIF[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 112.5 125 137.5 150 162.5 175 187.5 212.5 225 237.5 250 262.5 275 287.5 312.5 325 0 1 112.5 127.5 142.5 157.5 157.5 172.5 187.5 202.5 217.5 232.5 247.5 262.5 277.5 292.5 307.5 322.5 Register 12h - REF_CLK_MOD - Slope correction (Read/Write) 7 6 5 4 REFMOD[7:0] Bit 7-0 : REFMOD[7:0] : Reference clock collection 3 2 1 0 No.A1990-15/23 LV23411V Register 13h - SM_CTRL - Statemachine control (Read/Write) 7 FLL_ON Bit 7 : 6 5 CLKS_SE[2:0] FLL_ON : FLL control 0 = FLL OFF 1 = FLL ON 4 Bit 6-4 : CLKS_SE : Clock source selection 0 = No select 1 = Stereo Decoder Oscillator is selected 2 = IF Oscillator is selected 3 = AM Antenna Oscillator is selected 4 = FM RF Oscillator is selected 5 = AM RF Oscillator is selected 6 - 7 = No select 3 nSD_PM 2 nIF_PM 1 CM_SE[1:0] 0 Note : Bit[6-4] set oscillator source. Select arbitrary clock oscillator at tuning or calibrations or measure. Bit 3 : nSD_PM : Stereo Decoder PLL mute 0 = SD PLL Off (Calibration) 1 = SD PLL On (Normal operation) Bit 2 : nIF_PM : IF PLL mute 0 = IF PLL Off (Calibration) 1 = IF PLL On (Normal operation) Bit 1-0 : CM_SE : Command mode selection 0 = No command 1 = Measure mode 2 = Calibration mode 3 = Radio tuning (RF frequency tuning) mode Note : This bit used to select command mode. Select the arbitrary command to be executed. The command is executed by setting TARGET_VAL_L/H. Command execution time : SD calibration = 540ms IF calibration = 134ms RF (FM) tuning = 105ms RF (AM) tuning = 158ms Note: Please wait the time provided for the above-mentioned before all processing including reading the register after having executed the command. No.A1990-16/23 LV23411V Register 14h - REF_CLK_PRS - Reference clock pre-scaler (Read/Write) 7 IM_EVAS Bit 7 : 6 5 4 3 Reserved WAIT_SEL AM_FINE REFPRE[3:0] IM_EVAS : Image signal avoidance function ON/OFF 0 = OFF 1 = ON (Recommend) Bit 6 : Reserved : Fixed to “0” Bit 5 : WAIT_SEL : Selection mute release standby time after tuning 0 = 8ms wait 1 = 4ms wait Bit 4 : AM_FINE : Selection AM_ANT adjustment standby time 0 = No wait when DAC value is changed 1 = 2ms wait when DAC value is changed Bit 3-0 : REFPRE[3:0] : Reference Clock pre- scaler 0=1:1 1=1:2 2=1:4 … 15 = 1 : 32768 2 1 0 2 1 0 1 0 1 0 Register 15h - REF_CLK_DIV - Reference clock divider (Read/Write) 7 6 5 4 REFDIV[7:0] Bit 7-0 : REFDIV[7:0] : Reference Clock Divider 0 : Divide rate = 1 1 : Divide rate = 2 … 255 : Divide rate = 256 3 Register 16h - TARGET_VAL_L - Target Value Low Register (Read/Write) 7 6 5 4 TARGET[7:0] Bit 7-0 : TARGET[7:0] : Target frequency low 8 bit : Tuning frequency or Calibration frequency : low byte 3 2 Register 17h - TARGET_VAL_H - Target Value High Register (Read/Write) 7 6 5 4 3 TARGET[15:8] Bit 7-0 : TARGET[15:8] : Target frequency high 8 bit : Tuning frequency or Calibration frequency : high byte 2 With radio power ON, lower eight bits of the target frequency are set. Then, set higher eight bits of the target frequency to this register. The command is executed. TUNEPOS and TARGET : - AM mode : 1kHz span - FM mode : 10kHz span No.A1990-17/23 LV23411V Register 18h - RADIO_CTRL1 - Radio control 1 (Read/Write) 7 IQC_CTR Bit 7 : 6 5 4 3 2 IFPOL OSC_LEV[1:0] DEEM VOL[1:0] IQC_CTR : I/Q phase change 0 = Normal mode (Upper heterodyne) 1 = I/Q phase change : for image signal avoidance (Lower heterodyne) Note : Usually, no-need to change 1 0 EN_AMHC Bit 6 : IF pole change by State Machine 0 = The IF frequency is added to local frequency (Normal) 1 = The IF frequency is subtracted from local frequency Note : Usually, no-need to change Bit 5-4 : OSC_LEV[1:0] : RF-OSC oscillation level setting 0 = minimum level 3 = maximum level Note : 3dB steps, Level = 2 is recommended Bit 3 : DEEM : De-emphasis setting 0 = 50μs : Korea China, Europe, Japan 1 = 75μs : USA Bit 2-1 : VOL[1:0] : Volume setting 0 = minimum (VOL0) …… 3 = maximum (VOL3) Bit 0 : EN_AMHC : AM High-cut Filter ON/OFF 0 = AM HCF OFF 1 = AM HCF ON Register 19h - RADIO_CTRL2 - Radio control 2 (Read/Write) 7 Reserved Bit 7 : 6 5 Reserved EN_AMM Reserved : Fixed to “0” 4 Reserved Bit 6 : Reserved : Fixed to “1” Bit 5 : EN_AMM : AM Mute ON/OFF 0 = AM mute OFF 1 = AM mute ON Bit 4 : Reserved : Fixed to “0” Bit 3 : IF_AGC_LEV : IF-AGC Level Control 0 = AGC slow mode 1 = AGC first mode Bit 2-1 : RF_AGC_LEV[1:0] : RF-AGC Level Control 0 = AGC slow mode 1 = AGC normal mode 3 = AGC first mode Bit 0 : EN_RFAGC : RF-AGC ON/OFF 0 = AGC OFF 1 = AGC ON (Normal) 3 IF_AGC_LEV 2 1 RF_AGC_LEV[1:0] 0 EN_RFAGC No.A1990-18/23 LV23411V Register 1Ah - RADIO_CTRL3 - Radio control 3 (Read/Write) 7 DEEM_100 Bit 7 : 6 5 4 NA IF_AGC_CAP DEEM_100 : Additional De-emphasis (100μs) 0 = 0μs (Default setting) 1 = 100μs (DEEM = 1 : 75μS) 3 2 AM_WIDE_AGC_OFF Bit 6 : NA Bit 4 : IF_AGC_CAP 0 = OFF (Normal) 1 = ON Bit 3-2 : AM_WIDE_AGC_OFF[1:0] : AM WIDE AGC OFF Level Control 0 = First mode 3 = Slow mode Bit 1-0 : AM_WIDE_AGC_ON[1:0] : AM WIDE AGC ON Level Control 0 = WIDE AGC OFF 1 = First mode 3 = Slow mode 1 0 AM_WIDE_AGC_ON Register 1Ch - STEREO_CTRL1 - Stereo control 1 (Read/Write) 7 CRC[1:0] Bit 7-6 : 6 5 4 SS_SP2 Reserved CRC[1:0] : Capture Range Control 0 = Narrow mode 3 = Wide mode 3 Reserved Bit 5 : SS_SP2 : Stereo=ON sensitivity speed2 (First mode) 0 : First mode = OFF 1 : First mode = ON (Recommend) Bit 4 : Reserved : Fixed to “0” Bit 3 : Reserved : Fixed to “0 Bit 2 : PICAN_EN : PILOT signal Cancellation ON/OF 0 = OFF 1 = ON (Recommend) Bit 1 : FOSTEREO : Forced Stereo 0 = OFF (Normal) 1 = ON Bit 0 : ST_M : Mono/Stereo setting 0 = Stereo on (Normal) 1 = Stereo off (Forced mono) 2 PICAN_EN 1 FOSTEREO 0 ST_M No.A1990-19/23 LV23411V Register 1Dh - STEREO_CTRL2 - Stereo control 2 (Read/Write) 7 NA Bit 7-5 : 6 5 4 FOAMAGC 3 Reserved 2 OVER_MOD 1 CPAJ[2:0] 0 1 LEVSHIF 0 FO_SOFTT NA Bit 4 : FOAMAGC 0 : Forced - AGC = OFF 1 : Forced - AGC = ON Bit 3 : Reserved: Fixed to “0” Bit 2 : OVER_MOD : Over-modulation detector ON/OFF 0 = OFF 1 = ON Bit 1-0 : CPAJ[1:0] : Channel separation adjacent 0 = Minimum Sub-signal level 7 = Maximum Sub-signal level Register 1Eh - RADIO_CTRL4 - Radio control 4 (Read/Write) 7 6 5 4 3 SOFTST[2:0] SOFTMU[2:0] Bit 7-5 : SOFTST[2:0] : Soft Stereo Function (Stereo-Blend) 0 : Soft Stereo = OFF 7 : Soft Stereo = Lev7 (Max) Bit 4-2 : SOFTMU[2:0] : Soft Audio mute Function 0 : Soft mute = OFF 7 : Soft mute = Lev7 (Max) Bit 1 : LEVSHIF : Audio Line-out DC level shift 0 = Normal DC level (VCC = 5.0V) 1 = DC level is shifted (VCC =9.0V) Bit 0 : FO_SOFTST : Forced Soft Stereo Function 0 : ON (Normal) 1 : OFF 2 No.A1990-20/23 LV23411V Register 1Fh - RADIO_CTRL5 - Radio control 5 (Read/Write) 7 RF_SEL Bit 7 : 6 5 4 IFRIM nAGC_SPD SE_FM/AM RF_SEL : RF tuning range select 0 = Normal ( Japan/USA/Europe) 1 = OILT (65MHz to 74MHz) Bit 6 : IFRIM : IF OSC limit setting 0 : Max = 350kHz (FM mode) 1 : Max = 150kHz (AM mode) Bit 5 : nAGC_SPD : IF AGC speed setting 0 = High speed (FM mode) 1 = Normal (AM mode) Bit 4 : SE_FM/AM : AM/FM mode select 0 = FM mode 1 = AM mode Bit 3 : AMP_CTR : Audio Amp ON/OFF 0 = OFF 1 = ON Bit 2 : MUTE : Audio Mute ON/OFF 0 = ON 1 = OFF 3 AMP_CTR 2 MUTE 1 AM_CAL 0 PW_RAD Bit 1 : AM_CAL : AM Calibration (Antenna tuning mode) 0 = AM Receiving mode (Normal) 1 = AM Calibration mode (AM antenna tuning mode) Note : Set this bit to “1”, if ANT calibration frequency is measured. Bit 0 : PW_RAD: Radio Power 0 = Power OFF (power save mode) 1 = Power ON *1 : After the VCC voltage is impressed, PW_RAD is automatically set to "0" in 50ms. *2 : When the VCC voltage is dropped once, content of registers other than PW_RAD becomes irregular. No.A1990-21/23 LV23411V Test Circuit I2C_Bus X1 32.768Hz 18 16 VCC_Low AM_LCF SD OUT ST OUT VCC LV23411V 17 CLK IN NC SCL SDA 6 21 R OUT 5 Vref2(3V) L2 4 22 L OUT GND4 3 GND3 FLL CAP 2 23 GND2 GND5 1 24 L1 25 R1 4.7kΩ 20 19 AM AGC 26 MPX IN_OUT Vref3(4.3V) 27 Vref1(4.3V) 28 GND1 29 AM CAP 30 R3 open IF AGC CAP R2 4.7kΩ AM ref T1 50Ω C9 22μF BPF FM ANT 50Ω 50Ω L1 39nH AM ANT 50Ω L2 39nH NC C10 0.1μF 7 8 9 10 11 12 13 14 15 Dummy ANT C1 0.1μF C2 1μF C3 1μF C4 C5 1μF 1μF C6 0.047μF VCC=5V:short VCC=9V:open SD MPX IN_OUT GND Lout Rout C7 C8 0.1μF 22μF ST VCC=5V(9V) PS No.A1990-22/23 LV23411V Application Circuit Example I2C_Bus C9 22μF R2 4.7kΩ NC SCL SDA 18 16 VCC_Low AM_LCF SD OUT ST OUT VCC LV23411V 17 R OUT 6 Vref2(3V) 5 21 X1 32.768Hz L OUT 4 GND3 L2 3 22 R1 4.7kΩ 20 19 GND2 GND4 2 23 L1 FLL CAP 1 24 R3 open AM AGC GND5 MPX IN_OUT Vref3(4.3V) 25 Vref1(4.3V) 26 GND1 27 AM CAP 28 AM ref 29 AM ANT T1 30 FM ANT BPF CLK IN L1 39nH IF AGC CAP L2 39nH SD ADJ C10 0.1μF 7 8 9 10 11 12 13 14 15 L3 For AM Loop antenna AM CAP AM ref AM ANT GND C1 0.1μF C2 1μF C3 1μF C4 C5 1μF 1μF C6 0.047μF VCC=5V:short VCC=9V:open SD MPX IN_OUT GND Lout Rout C7 C8 0.1μF 22μF ST VCC=5V(9V) LO1 For AM Ferrite antenna SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of October, 2011. Specifications and information herein are subject to change without notice. PS No.A1990-23/23