Ordering number : ENA1699B LV24250LS Bi-CMOS LSI 1-Chip FM Tuner IC for Compact Portable Equipment http://onsemi.com Overview The LV24250LS is an I2C-controlled single-chip FM tuner IC that integrates external components which are necessary for tuning in a compact VQLP package with dimensions of only 3.5mm×3.5mm. Features FM FE FM IF MPX stereo decoder FLL Tuning Standby Specifications Absolute Maximum Ratings at Ta = 25C Parameter Symbol Conditions Unit VCC max VDD max Digital block supply voltage Maximum input voltage VIN1 max SCL, SDA, Int VIN2 max External_clk_in VDD+0.3 Allowable power dissipation Pd max Analog block supply voltage Ratings Maximum supply voltage Ta 70C * 5.0 V 4.0 V VDD+0.3 V 140 V mW Operating temperature Topr -20 to +70 C Storage temperature Tstg -40 to +125 C * : When mounted on the specified printed circuit board (40.0mm × 50.0 mm × 0.8mm), Four layers glass epoxy (2S2P) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Semiconductor Components Industries, LLC, 2013 June, 2013 60811 SY/60910 SY/42810 SY 201003265-S00003 No.A1699-1/18 LV24250LS Operating Conditions at Ta = 25C Parameter Recommended supply voltage Operating supply voltage range Symbol Conditions Ratings Unit VCC Analog block supply voltage 3.0 V VDD Digital block supply voltage 3.0 V 2.6 to 3.6 V 2.5 to 3.6 V 2.2 to 3.6 V VCC op VDD op VIO op Interface voltage Note : Supply voltage VIO equal VDD, or VIO ≤ VDD & VIO ≥ 2.2 V * Stabilize the service voltage so as not to cause the voltage change by the noise etc. Operating Characteristics at Ta = 25°C, VCC = 3.0V, VDD = 3.0V, Volume =15/16, Soft Mute = 1/Soft Stereo = off with the designated test circuit Output level set with Radio Control 1 of control register map (0Dh Bit0, Bit1,Bit5 set to ‘1’, ‘1’) Control 2 of control register map (0Dh Bit1 set to ‘1’) In addition, Set IF_OSC = 170kHz, IF_BW = 100% (Radio Control 1 : 0D Bit6, Bit7 set to ‘1’, ’1’) Parameter Symbol Conditions Ratings min typ Unit max Current drain ICCA Analog block at 60dBV EMF input 12 17 mA (in operation) ICCD Digital block at 60 dBV EMF input 0.3 0.8 mA Current drain ICCA Analog standby mode 3 30 A ICCD Digital standby mode (in standby) FM receive band F_range 30 A 108 MHz 3 Refer to PCB mounting conditions to cover 76 the FM receive band of 76M to 108MHz FM receive characteristics; MONO : fc = 80MHz, fm = 1kHz, 22.5kHzdev. Note that Soft_mute = 1, Soft_stereo function OFF, IHF-BPF used 3dB sensitivity -3dB LS 60dBV, 22.5kHzdev output standard, 5 17 dBV 8 16 dBV -3dB input. EMF Practical sensitivity 1 QS1 Input at S/N = 30dB Practical sensitivity 2 (Reference) QS2 Input at S/N = 26dB De-emphasis = 75s, SG open display EMF V 1.10 De-emphasis = 75s, SG terminal display Demodulation output Vo 60dBV EMF, pin 19 output 80 110 160 Channel balance CB 60dBV EMF, pin 18 output/pin 19 output -2 0 2 Signal-to-noise ratio S/N 60dBV EMF, pin 19 output 48 58 Total harmonic distortion 1 mVrms dB dB THD1 60dBV EMF, pin 19 output, 22.5kHz dev. 0.4 1.5 % THD2 60dBV EMF, pin 19 output, 75.0kHz dev. 1.3 3 % 10 20 dBV (MONO) Total harmonic distortion 2 (MONO) Field intensity display level FS Reg1Dh_bit0 = OFF 3 Input level at which Reg02h_bit1-3 change EMF from 1 to 2. Mute attenuation Mute-Att. 60dBV EMF, pin 19 output 60 70 dB FM receive characteristics ; STEREO characteristics : fc = 80MHz, fm = 1kHz, VIN = 60dBV EMF, Pilot = 10% (7.5kHzdev), MPX-Filter used Separation SEP L-mod, pin 19 / pin 18 output 20 35 dB L+R signals = 30% (22.5kHz dev.) Total harmonic distortion (Main) THD-ST1 Main-mod (for L + R input), 19 output 0.6 1.8 % IHF_BPF L+R signals = 30% (22.5kHzdev.) Interface block allowable operation range at Ta = -20 to +70C, VSS = 0V Parameter Symbol Conditions Supply voltage VDD Digital block input VIH High-level input voltage range VIL Low-level input voltage range IOL Output current at Low level VOL Output voltage at Low level IOL = 2mA Digital block output External clock operating frequency fclk_ext Ratings min typ 2.5 Clock frequency for external input max Unit 3.6 V 0.7VDD VDD V 0 0.1VDD 2.0 32k V mA 32.768k 0.6 V 20M Hz Note : External clock input (pin 12) allows also input of the sine wave signal. No.A1699-2/18 LV24250LS Package Dimensions unit : mm (typ) 3393 BOTTOM VIEW (0.1) 0.35 0.4 24 3.5 (0.054) 3.5 0.35 SIDE VIEW (0.75) TOP VIEW 2 1 (0.75) 0.85 MAX SIDE VIEW 0.0 NOM 0.2 SANYO : VQLP24J(3.5X3.5) VCC Vstabi NC FLL_LPF MPX_OUT Line_out_R Pin Assignment 18 17 16 15 14 13 12 Ext_CLK_IN Line_out_L 19 Package-GND 20 11 Package-GND Package-GND 21 10 Package-GND Package-GND 22 9 Package-GND Package-GND 23 8 Package-GND 1 2 3 4 5 6 FM_ANT2 VIO VDD INT SDA 7 SCL FM_ANT1 GND 24 Top view No.A1699-3/18 LV24250LS Line_out_R MPX_OUT FLL_LPF NC Vstabi V CC Block Diagram 18 17 16 15 14 13 Voltage Stabilizer Line_out_L 19 And Mute AMP Package_GND 20 FM Demodulator Package_GND 21 To Each Block Line SW Buffer 11 Package_GND Stereo De- Decorder emphasis FM Selectivity Package_GND 22 10 Package_GND Tuning System Filter FLL RF and FM Quadrature Mixer Package_GND 23 12 Ext_CLK_IN Tuning Power Manage ment Quadrature Oscillator Digital Interface I2C Conversion To Each Block GND 24 1 2 3 4 5 6 FM_ANT1 FM_ANT2 VIO VDD INT SDA To Each Block 9 Package_GND 8 Package_GND 7 SCL No.A1699-4/18 LV24250LS Pin Function Pin No. Pin name 1 FM-ANT1 Antenna input Description 2 FM-ANT2 For pin 1 single input, pin 2 is set Pin voltage Internal equivalent circuit 1V Mixer Vstabi to AC_GND via capacity ANT1 1 1V 1V Vstabi ANT2 1V 2 1V Mixer 3 VI/O Digital interface supply voltage VI/O VDD Power pin dedicated to the interface input/output elements V_I/O 3 4 VDD Digital supply voltage VDD VDD Power pin for digital block 5 INT to each interface block 4 Interrupt line VDD Output pin dedicated to interrupt (hardware output: used for SDA VIO INT 5 options) 6 to each logic block Digital interface DATA ine VDD Bidirectional data line. Pull up to VIO data Vio line with 3.3kΩ to 10kΩ resistor 6 7 SCL data Digital interface Clock line VDD SCL 7 8 Package-GND GND for package-shield VIO (GND) BND pin for package shield 9 10 11 12 Ext_CLK_IN Reference clock-source input VDD for measurement VIO External standard CLK input pin. 12 CLK Continued on next page. No.A1699-5/18 LV24250LS Continued from preceding page. Pin No. Pin name 13 VCC Description Analog supply voltage Pin voltage Supplement VCC VCC Power pin for analog (tuner) to each VCC block 26V Bias Regulater 13 block 14 Vstabi Stabilizer voltage 2.6V . VCC Local oscillator reference bias Vstabi. line for each block pin. NC pin to be used 2.6V Bias Regulater 14 VCC 13 OSC block 15 . NC 16 FLL_LPF Keep this open LPF for FLL Vstabi LPF pin for noise decrease when FLL operates. Capacity(0.47μF to 1.0μF) is added this pin and 16 between Vstabi pin of 14pin. NC pin to be used 17 MPX_OUT MPX-signal output 2.3V Vstabi Stereo decoder input monitor pin. NC pin to be used 17 18 LINE-OUT-R Radio Rch Line-output 1.2V Vstabi Audio R_ch output 19 LINE-OUT-L Radio Lch Line-output 1.2V Vstabi 19 18 Audio L_ch output 20 Package-GND GND for package-shield (GND) GND pin for package shield 21 22 23 24 GND GND (Analog and Digital GND) (GND) GND pin for analog (FM tuner) block and digital (control) block No.A1699-6/18 LV24250LS Format of Bus Transfers Bus transfers are primarily based on the I2C primitives Start condition Repeated start condition Stop condition Byte write Byte read Start, restart, and stop conditions are specified as shown in Table 1 below. Start Repeated start Stop SCL SCL SCL SDA SDA SDA Fig. 1 the I2C start, repeated start and stop conditions. For details, like timing, etc., refer to specifications of I2C. 8-bit write 8-bit data is sent from the master microcomputer to LV24250LS. Data bit consists of MSB first and LSB last. Data transmission is latched at the rising edge of SCL in synchronization with the SCL clock generated at the master IC. Do not change data while SCL remains HIGH. LV24250LS outputs the ACK bit between eighth and ninth falling edges of SCL SCL SDA D7 D6 D5 D4 D3 D2 D1 D0 Ack Fig. 2 Signal pattern of the I2C byte write Read is of the same form as write, only except that the data direction is opposite. Eight data bits are sent from LV24250LS to the master while Ack is sent from the master to LV24250LS. SCL SDA D7 D6 D5 D4 D3 D2 D1 D0 Ack Fig. 3 Signal pattern of the I2C byte read The serial clock SCL is supplied from the master side. It is essential that data bit is output from LV24250LS in synchronization with the falling edge while the master side performs latching at the rising edge. No.A1699-7/18 LV24250LS LV24250LS latches ACK at the rising edge. The sequence to write data D into the register A of LV24250LS is shown below. Start condition write the device address (C0h) write the register address, A write the target data, D stop condition start write device address SCL DA7 SDA Ack DA6...1 write register address A7 A6...1 write data byte Ack D7 stop Ack D6...0 Fig. 4 Register write through I2C When one or more data has been provided for writing, only the first data is allowed to be written. Read sequence start condition write the device address (C0h) write the register address, A repeated start condition (or stop + start in a single master network) write the device address + 1 (C1h) read the register contents D, transmit NACK (no more data to be read) stop condition start write device address write register address rep. SCL DA7 SDA start DA6...1 Ack write device address + 1 DA7 DA6...1 A7 A6...0 read data byte with NACK Ack D7 Ack stop D6...0 Fig. 5 Register read through I2C Interrupt Pin INT LV24250LS has the dedicated interrupt output pin. For the active level to the host, either LOW or HIGH can be selected. The INT output pin is kept floating while the PWRAD bit is cleared during initialization. Therefore, to avoid influence on the CPU side during initialization, it is recommended to secure the non-active state by means of the pull-up or pull-down resistor. This enables direct INT output connection to non-masking interruption of the host CPU. No.A1699-8/18 LV24250LS Digital interface specification (interface specification : reference) (1). Characteristics of SDA and SCL bus line relative to the I2C bus interface Repeated START START Condition Tf TLOW Tr THIGH SCL Tf Tr SDA THD;STA THD;DAT Parameter Symbol SCL clock frequency TSU;DAT TSU;STA Standard-mode min FSCL High_Speed-mode max min 100 0 400 Fall time of both SDA and SCL Tf 300 20+0.1Cb 300 ns Rise time of both SDA and SCL Tr 1000 20+0.1Cb 300 ns High time of SCL 0 unit max THIGH 4.0 kHz s 0.6 TLOW 4.7 1.3 s Hold time of STAT condition THD ; STA 4.0 0.6 s Hold time of Data THD ; DAT 0 Set-up time of STAT condition TSU ; STA 4.7 0.6 s Set-up time of STOP condition TSU ; STO 4.0 0.6 s Set-up time of Data TSU ; DAT 250 100 ns TBUF 4.7 1.3 s Low time of SCL Bus free time between a STOP and Capacitivie load for each bus line 3.45 Cb 0 400 0.9 400 s pF *Cb = Total capacitance of one bus line (2). Register map (On Register Map) Following is Sub address map of LV24250LS. Each register becomes 8-bit constitution. Address 00h Register Name CHIP_ID 02h RADIO_STAT 0Bh RFCAP Mode R/W R R/W Remark Chip ID Status of Radio Station RF Cap bank 0Dh RADIO_CTRL1 R/W Radio Control 1 0Eh RADIO_CTRL2 R/W Radio Control 2 0Fh RADIO_CTRL3 R/W Radio Control 3 10h TNPL R Tune Position Low 11h TNPH_STAT R Tune Position High and Status 19h REF_CLK_PRS R/W Reference clock pre-scalar 1Ah REF_CLK_DIV R/W Reference clock divider 1Bh REF_CLK_OFF R/W Reference clock offset 1Dh SCN_CTRL R/W Scan control 1Eh TARGET_VAL_L R/W Target value Low 1Fh TARGET_VAL_H R/W Target value High R : Read only register R/W : Read and Write register No.A1699-9/18 LV24250LS (3). Register description (ON Contents of each Register) Register 00h – CHIP_ID – Chip identify register (Read/Write) 7 6 5 4 3 2 1 2 1 0 ID [7 : 0] bit 7-0 : ID [7 : 0] : 8-bit chip ID. LV24250LS : 15h Note : To abort the command, write any value in this register. Register 02h – RADIO_STAT – Radio station status (Read-Only) 7 6 5 4 RAD_IF N/A N/A MO_ST bit 7 : 3 FS [2 : 0] 0 SF5DB RAD_IF : Radio interrupt flag. 0 = no interrupt 1 = interrupt Note : When status (field strength, stereo/mono) changes, this bit is set. If Interrupt of IRQ pin is enabled, Interrupt pin is set by following IPOL register condition. This bit is cleared by register read. In stand-by mode (PW_RAD = 0), this bit is 1 bit 6-5 : NA [1 : 0] : NA 0 fixed bit 4 : MO_ST : Mono/stereo indicator 0 = Forced monaural 1 = Normal (Receiving in stereo mode) bit 3-1 FS [2 : 0] : Fieldstrength : 0 = Low field strength … 7 = High field strength bit 0 : SF5DB : Fieldstrength +5dB : 0 = FS5dB no UP 1 = FS5dB UP For details, refer to Application note. Register 0Bh – RFCAP – RF Cap bank (Read/Write) 7 6 5 4 3 2 1 0 RFCAP [7 : 0] bit 7-0 : RFCAP [7 : 0] : RF Oscillator CAP bank No.A1699-10/18 LV24250LS Register 0Dh – RADIO_CTRL1 – Radio control 1 (Read/Write) 7 6 5 4 3 2 IF_SEL IFBWSEL AGC_SPD DEEM ST_M nMUTE bit 7 : 1 0 VOL [1 : 0] IF_SEL : IF Frequency Setting 0 = 150kHz 1 = 170kHz bit 6 : IFBWSEL : IF band width setting 0 = 50% 1 = 100% bit 5 : VOL_2 : Volume setting For details, refer to Bit0,1 for RADIO_CTRL1 bit 4 : DEEM : de-emphasis 0 = 50s : Korea, China, Europe, Japan 1 = 75s : USA bit 3 : ST_M : Stereo/mono setting 0 = Stereo enabled 1 = Stereo disabled (mono mode) bit 2 : nMUTE : Audio Mute 0 = Mute On 1 = Mute Off bit 1-0 : VOL [1 : 0] : Volume Setting * It controls by Bit5 of RADIO_CTRL1 and combination 4Bit with Bit1 of RADIO_CTRL2. Vol_3 Vol_2 Vol_1 Vol_0 0 0 0 0 : Minimum level 0 0 0 1 0 0 1 0 … 1 1 1 1 : Max level Register 0Eh – RADIO_CTRL2 – Radio control 2 (Read/Write) 7 6 5 4 SOFTST [2 : 0] bit 7-5 : 3 SOFTMU [2 : 0] 2 1 0 N/A STABI_BP SOFTST [2 : 0] : Soft Stereo setting 000b = Soft stereo level 3 001b = Disable soft stereo 010b = Soft stereo level 1 (*) 100b = Soft stereo level 2 Note : do not use without these value. (*) : recommended setting bit 4-2 : SOFTMU [2 : 0] : Soft audio mute setting 000b = Soft audio mute level 3 001b = Disable soft audio mute 010b = Soft audio mute level 1 100b = Soft audio mute level 2 (*) Note : do not use without these value. (*) : recommended setting bit 1 : VOL_3 : Volume setting For details, refer to Bit0,1 for RADIO_CTRL1 bit 0 : STABI_BP : Internal regulator by-pass bit 0 = Internal regulator operate (normal) 1 = Internal regulator by-pass No.A1699-11/18 LV24250LS Register 0Fh – RADIO_CTRL3 – Radio control 3 (Read/Write) 7 6 5 4 3 IPOL SM_IE RAD_IE SD_PM nIF_PM bit 7 : 2 1 EXT_CLK_CFG [1 : 0] 0 PW_RAD IPOL : Interrupt (IRQ) Polarity 0 = IRQ active high 1 = IRQ active low bit 6 : SM_IE : Command end interrupt 0 = Disable 1 = Enable bit 5 : RAD_IE : Radio Interrupt (field strength/stereo changes) 0 = Disable 1 = Enable bit 4 : SD_PM : Stereo decoder clock PLL mute 0 = SD PLL On (Normal Operation) 1 = SD PLL Off (Adjustment) bit 3 : nIF_PM : IF PLL mute 0 = IF PLL Off (Adjustment) 1 = IF PLL On (Normal Operation) bit 2-1 : EXT_CLK_CFG [1 : 0] : External Clock Setting EXT_CLK_CFG [1 : 0] Reference clock 00 Off 01 NA:Do not use 10 Oscillator clock source / 32 (for high frequency source) 11 Oscillator clock source (for low frequency source) bit 0 : PW_RAD : Radio Circuit Power 0 = Power Off (Stand-by). 1 = Power On Note : At the time of start, PW_RAD becomes 0 (Stand-by) Register 10h – TNPL – Tune position low (Read-Only) 7 6 5 4 3 2 1 0 TUNEPOS [7 : 0] bit 7-0 : TUNEPOS [7 : 0] : Current RF Frequency (Low 8bit) No.A1699-12/18 LV24250LS Register 11h – TNPH_STAT – Tune position high/status (Read-Only) 7 6 5 ERROR [2 : 0] bit 7-5 : bit 4 : 4 3 2 SM_IF TUNED NA 1 0 TUNEPOS [9 : 8] ERROR [2 : 0] : Error Code ERROR [2 : 0] Remark 0 OK, Command end (No Error) 1 Default value after or during reset 2 Band Limit Error 3 DAC Limit Error 6 Command forced End 7 Command busy SM_IF : Command End interrupt flag 0 = No Interrupt 1 = Interrupt This bit is set when the command is over. When the IRQ pin interrupt is allowed, the pin status is changed, Reading this register causes clearing. bit 3 : TUNED : Radio tuning Flag 0 = No tune 1 = Tuned Note : This flag is set when Tuned or a station search succeeded. This flag is cleared under 3 conditions as below. (1) PW_RAD = 0 (2) Tuning Frequency (3) FM station searching bit 2 : NA : 0 (Fix) bit 1 : 0 : TUNEPOS [9 : 8] : Current RF frequency (High 2 bit) Register 19h – REF_CLK_PRS – Reference clock prescaler (Read/Write) 7 6 5 4 3 REFPRE [2 : 0] bit [7 : 5] : 2 1 0 2 1 0 2 1 0 REFMOD [4 : 0] REFPRE [2 : 0] : Reference Clock pre- scaler 0=1:1 1=1:2 … 7 = 1:128 bit [4 : 0] : REFMOD [4 : 0] : 5-bit slope correction Register 1Ah – REF_CLK_DIV – Reference clock divider (Read/Write) 7 6 5 4 3 REFDIV [7 : 0] Bit 7-0 : REFDIV [7 : 0] : Reference Clock Divider 0 : Divider Value = 1 1 : Divider Value = 2 … 255 : Divider Value = 256 Register 1Bh –REF_CLK_OFF – Reference clock offset (Read/Write) 7 6 5 4 3 REFOFFS [7 : 0] Bit 7-0 : REFOFFS [7 : 0] : Offset register for the spread of reference clock No.A1699-13/18 LV24250LS Register 1Dh – SCN_CTRL – Scan control (Read/Write) 7 6 GRID [1 : 0] bit 7-6 : 5 4 FLL_ON FLL_MODE 3 2 1 FS [2 : 0] 0 SHF5DB GRID [1 : 0] : FM station search frequency interval : 0 = IFSD set 1 = 50kHz grid 2 = 100kHz grid 3 = 200kHz grid bit 5 : FLL_ON : FLL Control 0 = FLL OFF 1 = FLL ON During setting of the FM frequency and during seek, keep this OFF. Turn it ON after tuning. bit 4 : Reserved : 0 (Fix) However, '1' is set when capacity is added to 16pin, and it uses it as Smoothing Filter(FLL_LPF). bit 3-1 : FS [2 : 0] : Field strength setting at the time of FM station search and a frequency adjustment bit Set 1 for setting of IFSD. bit 0 : SHF5DB : Scan stop level +5dB Register1Eh – TARGET_VAL_L – Target Value Low Register (Read/Write) 7 6 5 4 3 2 1 0 1 0 TARGET [7 : 0] bit 7-0 : TARGET [7 : 0] : Target frequency low 8 bit : Tuning frequency or Limit Frequency for FM Station Search Register 1Fh – TARGET_VAL_H – Target Value High Register (Read/Write) 7 6 5 4 3 2 TARGET [15 : 8] bit 7-0 : TARGET [15 : 8] : Target frequency High 8 bit : Target value of oscillator calibration, Tuning frequency value or limit frequency value for station search Note : GRID [1 : 0] is not 0 TARGET [15 : 14] has different definition With radio power ON, lower eight bits of the target frequency are set. Then, set higher eight bits of the target frequency to this register. The command is executed. No.A1699-14/18 LV24250LS Test Circuit Line_out_R VCC + 19 VCC External_CLK_IN Voltage 12 Source 20 11 18 21 13 22 9 23 8 24 7 3 VIO 2 1000pF 4 SW 10 Top View 1 FM_ANT 14 5 Package GND SCL 6 SDA GND 15 INT Package GND 16 VDD Line_out_L 17 SW SW VDD Voltage Source Extenal CLK_IN SCL (CLOCK) VIO Voltage Source SDA (DATA) INT 1000pF I2C_Bus MPU No.A1699-15/18 LV24250LS Application Circuit Not necessary when the CD cut capacity is on the receive side Line_out_R + VCC Changeover of resistor possible depending on the state of power supply VCC 13 External_CLK_IN Voltage 12 Source 18 17 16 15 14 19 20 11 9 23 8 24 7 47pF R5 SW Changeover of resistor possible depending on the state of power supply Voltage for I2C interface pull-up SCL 6 R1 R2 27pF 120nH Winding type VDD Voltage Source 5 SDA (DATA) 100 to 1000pF 4 Package GND SDA 3 VIO 2 INT 1 FM_ANT INT GND 22 VDD Package GND 10 Top View R3 R4 Extenal CLK_IN 21 SCL (CLOCK) Line_out_L SW R6 I2C_Bus MPU Cautions for mounting of IC Note1 : For external part constant, the recommended value is described. Since the constant may differ during actual use with the set mounted, be sure to consider optimization. Note2 : The single input antenna application has been described. The difference input is also possible (The signal input from 1pin and 2pin: Refer to the application note for details). Note3 : If the spike noise between MPU and IC is large during communication, it is recommended to add limiting resistors R1, R2, and R3 between MPU and IC. 0 at 1.8V. Note4 : To reduce noise from power supply, add a capacitor between VCC - GND and between VDD - GND. Note5 : The I2C bus communication line requires pull-up resistors R5 and R6. The commonly-employed resistance value is 4.7k (4.7k to 10k). Set the pull-up voltage to the same one of VIO of LV24250LS. (Supply from the same source as VIO and VDD is recommended. Note6 : Please use the INT pin arbitrarily. Recommended to open when unused. The INT pin becomes unstable at IC startup. To protect MPU from any effects during startup, it is recommended to add either the pull-up or pull-down resistor to set the non-active mode. (This is not necessary when the MPU can be set to non-active by a software during initialization. No.A1699-16/18 LV24250LS PCB Mounting Conditions to cover the FM Receiving Area of 76M to 108MHz LV24250LS's PCB mounting conditions LV24250LS Printed Circuit Board X = 0mm LAYER LV24250LS has an inductor for local oscillator on the package bottom side. In order to cover the receiving frequency range of 76MHz to 108MHz, provide the GND layer to the first layer of Side A of PCB that is directly below the package bottom side, as shown in the figure. Recommended layout of PCB substrate 3.50 × 3.50 Y = 2.30 2.24 0.20 0.75 0.60 3.50 × 3.50 0.60 0.40 PCB GND Layer 0.57 0.79 0.55 X = 2.40 0.55 2.64 IC backside_LV24250LS IC directly-below_PCB recommended GND patten diagram With this SPL, the receiving frequency is measured under the following conditions : The X-value can be set freely between Min = 2.00mm and Max = 2.60mm with reference to IC. (The X-value for Our Demo Board is 2.4mm.) The Y-value can be set freely between Min = 1.00mm and Max = 2.40mm with reference to IC. (The Y-value for Our Demo Board is 2.30mm.) Avoid providing another wiring within 0.4mm of bottom layer of PCB_GND as much as possible. No.A1699-17/18 LV24250LS ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PS No.A1699-18/18