Ordering number : ENA1850 Bi-CMOS IC Fan Motor Driver LV8063TT Single-Phase Full-Wave Driver Overview The LV8063TT is the driver IC with BTL linear output for single-phase fan motor, and that drives at high efficiency, low power, and low noise by suppressing the reactive power. The BTL output can be combined with the PWM control by an external signal, which is optimum for the note PC, the CPU cooler, etc. that requires low power dissipation and low noise. Functions • Single-phase full-wave operating by BTL output (BTL amplifier gain : +43dB) • Speed control available by PWM pin • Hall bias output pin (VHB = 1.05V typ) • Built-in Quick Start circuit • FG(rotation signal) output pin (Open drain output) • Built-in thermal-shutdown (TSD) circuit • Built-in lock protection and automatic return circuit Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage OUT pin output current Symbol Conditions VCC max Ratings Unit 7 IOUT max1 In regular mode IOUT max2 In lock-detection mode V 0.7 A 1 A OUT pin output voltage handling VOUT max 7 V FG output voltage handling VFG max 7 V FG output current IFG max 5 mA HB output current IHB max 10 mA Allowable power dissipation Pd max1 Independent IC 0.2 W Pd max2 IC on board * 0.4 W Operating temperature Topr -30 to +95 °C Storage temperature Tstg -55 to +150 °C * Specified substrate : 20mm × 10mm × 0.8mm, Paper phenol Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 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O1310 SY 20100929-S00008 No.A1850-1/8 LV8063TT Recommended Operating Conditions at Ta = 25°C Parameter Symbol Supply voltage Hall input common-mode input voltage Conditions VCC opg Active at all circuit VCC min Start-up with PWM=H Ratings Unit 2.5 to 6.0 VICM V 2.2 to 6.0 V 0.3 to VCC-1.5 V range Electrical Characteristics at Ta = 25°C, VCC = 5V Parameter Symbol Ratings Conditions min Circuit current typ Unit max ICC Active 1.5 3.0 mA ICCO Stand-by 200 300 μA HB bias voltage VHB IHB = 5mA 1.05 1.2 V Hall input bias current IHIN 1 μA Output On voltage VO 0.25 0.35 V 6 mV 43 47 dB 0.9 IO = 250mA, source + sink Hall amplifier output offset voltage VINOFS -6 Hall amplifier voltage gain GH 39 PWM pin input Low level VPWML 0 0.7 V PWM pin input High level VPWMH 2.5 VCC V PWM input frequency fPWM Design guarantee * PWM input smallest pulse width TPWM Design guarantee * FG output low-level voltag VFG IFG = 3mA FG output leakage current IFGL VFG = 7V FG comparator hysteresis width ΔVHYS Output on time in Lock-detection TACT 20 50 kHz μs 5 0.3 V 10 μA ±5 ±15 ±20 mV 0.45 0.6 0.75 sec 4.5 6 7.5 sec 8 10 11 Output off time in Lock-detection TDET Output on/off ratio in Lock-detection TRTO TRTO=TDET/TACT Thermal shutdown operating temperature TSD Design guarantee * 180 °C Thermal shutdown hysteresis width ΔTSD Design guarantee * 40 °C * Design guarantee: Indicates a design target value. These parameters are not tested in the independent IC. Pin Assignment IN1 1 10 PWM HB 2 9 FG IN2 3 8 VCC SGND 4 7 OUT2 OUT1 5 6 PGND Top view No.A1850-2/8 LV8063TT Package Dimensions unit : mm (typ) 3297 Pd max -- Ta 0.5 3.0 0.5 3.0 4.9 Ambient temperature, Pd max -- W 6 10 1 0.5 0.2 0.125 (0.85) (0.5) 5 0.4 Specified board (20 × 10 × 0.8mm3, paper phenol) 0.3 0.2 Independent IC 0.18 0.1 1.1 max 0 --30 0.09 --10 10 30 50 70 90 110 0.08 Ambient temperature, Ta -- °C SANYO : MSOP10(150mil) Block Diagram LOCK DETECTION TSD IN1 1 10 PWM LEVEL SHIFT HB ENABLE OSC 2 9 FG 8 VCC 7 OUT2 6 PGND HB SGND 4 OUT1 5 CONTROL + - 3 + IN2 No.A1850-3/8 LV8063TT Sample Application Circuit *2 1 IN1 2 HB FG 3 IN2 VCC 8 4 SGND 5 OUT1 PWM 10 *3 H R1 *4 *5 9 Di OUT2 7 PGND 6 Cr *1 M *1 When the diode Di is used to prevent device destruction from reverse connection, the capacitor Cr must be inserted to assure a path for regenerative currents. Similarly, if there no nearby capacitors on the fan power supply line, the capacitor Cr is also required to increase reliability. *2 The Hall element is biased at a constant voltage of approximately 1.05Vfrom the HB pin. Thus LV8063TT provides a stable Hall output with excellent temperature characteristics. If the Hall output is needed to adjust the amplitude, use the resistor R1 as shown in the figure. *3 When the wiring from the Hall output to IC Hall input is long, noise may be carried through the wiring. In this case, insert the capacitor as shown in the figure. *4 This pin must be left open if unused. *5 When a PWM signal seems to be the open collector (a drain) output, please connect suitable pulling up resistance so that a H/L level is decided. No.A1850-4/8 LV8063TT Pin Description Pin No. Pin name 1 IN1 3 IN2 Pin voltage Description Equivalent circuit Hall input pin (+) - Hall input pin (-) 1 3 2 HB 1.05V (typ) Hall bias output pin 2 4 SGND 5 OUT1 7 OUT2 6 PGND 8 VCC 9 FG 0V Signal ground pin Motor drive output pin 5 - 7 0V Power ground pin 2.5V to 6.0V Voltage supply pin - FG pulse output pin 9 10 PWM - PWM control input pin 10 No.A1850-5/8 LV8063TT Timing Chart Stand-by/Start-up VCC TSLP TSLP PWM (Hi-Impedance) HB OUT1/OUT2 Stand-by Active Stand-by Active Active *TSLP=800μs(typ) *When PWM signal is input “L” level for continuousness TSLP, it becones the Stand-by mode by detecting above situation. *When “H” level is input, it becomes the Active mode at once. In Regular-Rotation HYS IN1-IN2 HYS PWM OUT1 OUT2 FG *Truth Table When Steady Rotation IN1 H L IN2 *PWM OUT1 OUT2 H H L L H FG Mode drive L L L L H L H L L L regeneration drive OFF regeneration No.A1850-6/8 LV8063TT In Motor-Lock Motor Lock Motor re-rotation IN1-IN2 OUT1 OUT2 FG TACT ( = 0.6S (typ)) TACT ( = 6S (typ)) Waiting for FG pulse Motor protection FG detection Release * When motor protection is activated, both OUT1 and OUT2 output low level. When the circuit operates making amends starting (PWM pin = H) VCC IN1-IN2 PWM OUT1 OUT2 FG When the power supply is turned on, the standby release (quick start), and the lock protection is released, the start amends operation is done. No.A1850-7/8 LV8063TT When the circuit operates making amends starting (PWM pin = PWM signal input) VCC IN1-IN2 PWM OUT1 OUT2 FG When the power supply is turned on, the standby release (quick start), and the lock protection is released, the start amends operation is done. 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of October, 2010. Specifications and information herein are subject to change without notice. PS No.A1850-8/8