SEMTECH SX8662

SX8662
Capacitive Button Matrix (up to 36) Controller
with Individual LED Drivers and Buzzer Output
ADVANCED COMMUNICATIONS & SENSING
GENERAL DESCRIPTION
KEY PRODUCT FEATURES
The SX8662 is an ultra low power, fully integrated
12-channel solution for capacitive touch-button
matrix applications (up to 36 keys). Unlike many
capacitive touch solutions, the SX8662 features
dedicated capacitive sense inputs (that requires no
external components) in addition to 8 general
purpose I/O ports (GPIO) which can be used to drive
up to 36 matrix LEDs (i.e. one per key). Each of the
on-chip GPIO/LED driver is equipped with
independent PWM source for enhanced visual effect
such as dimming, and breathing.
Complete Capacitive Touch-Button Solution
The SX8662 includes a capacitive 10 bit ADC analog
interface with automatic compensation up to 100pF.
The high resolution capacitive sensing supports a
wide variety of touch pad sizes and shapes and
allows capacitive buttons to be created using thick
overlay materials (up to 5mm) for an extremely
robust and ESD immune system design.
The SX8662 incorporates a versatile firmware that
was specially designed to simplify capacitive touch
solution design and offers reduced time-to-market.
Integrated
multi-time
programmable
memory
provides the ultimate flexibility to modify key firmware
parameters (gain, threshold, scan period, auto offset
compensation) in the field without the need for new
firmware development.
The SX8662 supports the 400 kHz I²C serial bus
data protocol and includes a field programmable
slave address. The tiny 5mm x 5mm footprint makes
it an ideal solution for portable, battery powered
applications where power and density are at a
premium.
o Up to 36 Matrix Buttons
o Up to 36 LEDs Control for individual Visual Feedback
with Auto Lightening
o Configurable Single or Continuous Fading Mode
o 256 steps PWM Linear and Logarithmic control
High Resolution Capacitive Sensing
o Up to 100pF of Offset Cap. Compensation at Full
Sensitivity
o Capable of Sensing up thru 5mm thick Overlay Materials
Support of buzzer for audible feedback
User-selectable Button Reporting Configuration
Extremely Low Power
o 8uA (typ) in Sleep Mode
o 100uA (typ) in Doze Mode (195ms)
o 460uA (typ) in Active Mode (30ms)
Programmable Scanning Period from 15ms to several seconds
Auto Offset Compensation
o Eliminates false triggers due to environmental factors
(temperature, humidity)
o Initiated on power-up and configurable intervals
Multi-Time In-Field Programmable Firmware Parameters
for Ultimate Flexibility
o On-chip user programmable memory for fast, self
contained start-up
No External Components per Sensor Input
Internal Clock Requires No External Components
Differential Sensor Sampling for Reduced EMI
Optional 400 KHz I²C Interface with Programmable Address
-40°C to +85°C Operation
APPLICATIONS
TYPICAL APPLICATION CIRCUIT
Home Automation
White Goods
buzzer
SX8662
cap2
cap11
analog sensor
interface
clock
generation
RC
Consumer Products, Instrumentation, Automotive
PWM LED
controller
gpio6
cap4
cap9
Mechanical Button Replacement
gpio5
cap5
power management
gpio4
cap7
cap6
cap6
Notebook/Netbook/Portable/Handheld computers
gnd
micro processor
GPIO controller
RAM
NVM
ROM
I2C
cap7
gpio3
gpio2
cap8
36 Matrix LEDs
cap3
Printers
gpio7
vdig
gnd
vana
cap1
cap10
cap8
cap3
cap2
cap1
ORDERING INFORMATION
Part Number
gpio1
Temperature
Range
cap5
gpio0
cap9
bottom plate
1
sda
scl
intb
cp
vdd
cn
cap10
Package
SX8662I08AWLTRT -40°C to +85°C Lead Free MLPQ-W32
cap4
cap11
cap0
36 Capacitive Matrix Buttons
resetb
cap0
1
HOST
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Rev5 4 August 2011
3000 Units/reel
* This device is RoHS/WEEE compliant and Halogen Free
© 2011 Semtech Corp.
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SX8662
Capacitive Button Matrix (up to 36) Controller
with Individual LED Drivers and Buzzer Output
ADVANCED COMMUNICATIONS & SENSING
Table of Contents
GENERAL DESCRIPTION ........................................................................................................................ 1
TYPICAL APPLICATION CIRCUIT ............................................................................................................ 1
KEY PRODUCT FEATURES..................................................................................................................... 1
APPLICATIONS....................................................................................................................................... 1
ORDERING INFORMATION...................................................................................................................... 1
1
GENERAL DESCRIPTION............................................................................................................... 4
1.1
1.2
1.3
1.4
1.5
2
Pin Diagram
Marking information
Pin Description
Simplified Block Diagram
Acronyms
4
4
5
6
6
ELECTRICAL CHARACTERISTICS ................................................................................................. 7
2.1
2.2
2.3
2.4
3
Absolute Maximum Ratings
Recommended Operating Conditions
Thermal Characteristics
Electrical Specifications
7
7
7
8
FUNCTIONAL DESCRIPTION ........................................................................................................ 10
3.1
Introduction
3.1.1
General
3.1.2
Parameters
3.1.3
Configuration
3.2
Scan Period
3.3
Operation modes
3.4
Sensors on the PCB
3.4.1
Matrix Keys/Buttons (MK)
3.4.2
Priority Key/Button (PK)
3.4.3
Schematics Requirements
3.5
Button Information (MK and PK)
3.6
Analog Sensing Interface
3.7
Offset Compensation
3.8
Processing
3.9
Configuration
3.10
Power Management
3.11
Clock Circuitry
3.12
I2C interface
3.13
Interrupt
3.13.1 Power up
3.13.2 Assertion
3.13.3 Clearing
3.13.4 Example
3.14
Reset
3.14.1 Power up
3.14.2 RESETB
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10
10
10
10
11
12
12
12
12
14
14
16
17
17
19
19
19
20
20
20
20
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21
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SX8662
Capacitive Button Matrix (up to 36) Controller
with Individual LED Drivers and Buzzer Output
ADVANCED COMMUNICATIONS & SENSING
3.14.3 Software Reset
3.15
General Purpose Input and Outputs
3.15.1 GPO
3.15.2 Fading Modes
3.15.3 Intensity index vs PWM pulse width
3.15.4 Tri-State Multiplexing (TSM)
4
22
23
23
25
26
27
PIN DESCRIPTIONS ..................................................................................................................... 28
4.1
4.2
4.3
4.4
4.5
5
Introduction
ASI pins
Host interface pins
Power management pins
General purpose IO pins
28
28
29
32
33
DETAILED CONFIGURATION DESCRIPTIONS .............................................................................. 34
5.1
5.2
5.3
5.4
5.5
5.6
6
Introduction
General Parameters
Capacitive Sensors Parameters
Buttons (MK and PK) Parameters
Buzzer Parameters
GPIO Parameters
34
37
38
40
43
44
I2C INTERFACE ........................................................................................................................... 47
6.1
6.2
6.3
6.4
6.5
6.6
I2C Write
I2C read
I2C Registers Overview
Status Registers
Control Registers
SPM Gateway Registers
6.6.1
SPM Write Sequence
6.6.2
SPM Read Sequence
6.7
NVM burn
47
48
49
50
52
53
54
55
56
7
APPLICATION INFORMATION ...................................................................................................... 57
8
REFERENCES ............................................................................................................................. 58
9
PACKAGING INFORMATION ........................................................................................................ 59
9.1
9.2
Package Outline Drawing
Land Pattern
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SX8662
Capacitive Button Matrix (up to 36) Controller
with Individual LED Drivers and Buzzer Output
ADVANCED COMMUNICATIONS & SENSING
1 GENERAL DESCRIPTION
cap1
cap0
vana
resetb
gnd
vdig
gpio7
gpio6
Pin Diagram
32
31
30
29
28
27
26
25
cap2
1
24
gnd
cap3
2
23
gpio5
cap4
3
22
gpio4
cap5
4
21
gpio3
cap6
5
20
gpio2
cap7
6
19
gnd
cap8
7
18
gpio1
cap9
8
17
gpio0
SX8662
Top View
9
10
11
12
13
14
15
16
cap11
cn
cp
vdd
intb
scl
sda
bottom ground pad
cap10
1.1
Figure 1 Pinout Diagram
1.2
Marking information
ASX08
yyww
xxxxxx
R08
yyww = Date Code
xxxxxx = Semtech lot number
R08 = Semtech Code
Figure 2 Marking Information
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SX8662
Capacitive Button Matrix (up to 36) Controller
with Individual LED Drivers and Buzzer Output
ADVANCED COMMUNICATIONS & SENSING
1.3
Pin Description
Number
Name
Type
Description
1
CAP2
Analog
Capacitive Sensor 2
2
CAP3
Analog
Capacitive Sensor 3
3
CAP4
Analog
Capacitive Sensor 4
4
CAP5
Analog
Capacitive Sensor 5
5
CAP6
Analog
Capacitive Sensor 6
6
CAP7
Analog
Capacitive Sensor 7
7
CAP8
Analog
Capacitive Sensor 8
8
CAP9
Analog
Capacitive Sensor 9
9
CAP10
Analog
Capacitive Sensor 10
10
CAP11
Analog
Capacitive Sensor 11
11
CN
Analog
Integration Capacitor, negative terminal (1nF between CN and CP)
12
CP
Analog
Integration Capacitor, positive terminal (1nF between CN and CP)
13
VDD
Power
Main input power supply
14
INTB
Digital Output
Interrupt, active LOW, requires pull up resistor (on host or external)
15
SCL
Digital Input
I2C Clock, requires pull up resistor (on host or external)
16
SDA
Digital Input/Output
I2C Data, requires pull up resistor (on host or external)
17
GPIO0
Digital Input/Output
General Purpose Input/Output 0
18
GPIO1
Digital Input/Output
General Purpose Input/Output 1
19
GND
Ground
Ground
20
GPIO2
Digital Input/Output
General Purpose Input/Output 2
21
GPIO3
Digital Input/Output
General Purpose Input/Output 3
22
GPIO4
Digital Input/Output
General Purpose Input/Output 4
23
GPIO5
Digital Input/Output
General Purpose Input/Output 5
24
GND
Ground
Ground
25
GPIO6
Digital Input/Output
General Purpose Input/Output 6
26
GPIO7
Digital Input/Output
General Purpose Input/Output 7
27
VDIG
Analog
Digital Core Decoupling, connect to a 100nF decoupling capacitor
28
GND
Ground
Ground
29
RESETB
Digital Input
Active Low Reset. Connect to VDD if not used.
30
VANA
Analog
Analog Core Decoupling, connect to a 100nF decoupling capacitor
31
CAP0
Analog
Capacitive Sensor 0
32
CAP1
Analog
Capacitive Sensor 1
Ground
Exposed pad connect to ground
Bottom Plate GND
Table 1 Pin description
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SX8662
Capacitive Button Matrix (up to 36) Controller
with Individual LED Drivers and Buzzer Output
ADVANCED COMMUNICATIONS & SENSING
1.4
Simplified Block Diagram
gpio6
gpio7
vdig
gnd
resetb
vana
cap0
cap1
The simplified block diagram of the SX8662 is illustrated in Figure 3.
SX8662
cap2
cap3
analog
sensor
interface
clock
generation
RC
PWM
LED
controller
gnd
gpio5
gpio4
cap4
power management
cap5
cap6
cap7
cap8
gpio3
micro
processor
GPIO
controller
RAM
NVM
ROM
I2C
gpio2
gnd
gpio1
gpio0
cap9
sda
scl
intb
vdd
cp
cn
cap11
cap10
bottom plate
Figure 3 Simplified block diagram of the SX8662
1.5
Acronyms
ASI
DCV
GPO
GPP
MTP
NVM
PWM
QSM
SPM
SPO
MK
PK
PS
TSM
Analog Sensor Interface
Digital Compensation Value
General Purpose Output
General Purpose PWM
Multiple Time Programmable
Non Volatile Memory
Pulse Width Modulation
Quick Start Memory
Shadow Parameter Memory
Special Purpose Output
Matrix Key
Priority Key
Proximity Sensor
Tri-State Multiplexing
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SX8662
Capacitive Button Matrix (up to 36) Controller
with Individual LED Drivers and Buzzer Output
ADVANCED COMMUNICATIONS & SENSING
2 ELECTRICAL CHARACTERISTICS
2.1
Absolute Maximum Ratings
Stresses above the values listed in “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these, or any other conditions beyond the “Recommended
Operating Conditions”, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Parameter
Symbol
Min.
Max.
Unit
Supply Voltage
VDD
-0.5
3.9
V
Input voltage (non-supply pins)
VIN
-0.5
3.9
V
Input current (non-supply pins)
IIN
10
mA
Operating Junction Temperature
TJCT
125
°C
Reflow temperature
TRE
260
°C
Storage temperature
TSTOR
-50
150
°C
ESDHBM
3
kV
ILU
± 100
mA
ESD HBM (Human Body model)
Latchup
(i)
(ii)
Table 2 Absolute Maximum Ratings
(i) Tested to JEDEC standard JESD22-A114
(ii) Tested to JEDEC standard JESD78
2.2
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Unit
Supply Voltage
VDD
2.7
3.6
V
100
mV
Supply Voltage Drop
(iii, iv, v)
VDDdrop
Supply Voltage for NVM programming
VDD
3.0
3.6
V
Ambient Temperature Range
TA
-40
85
°C
Table 3 Recommended Operating Conditions
(iii) Performance for 2.6V < VDD < 2.7V might be degraded.
(iv) Operation is not guaranteed below 2.6V. Should VDD briefly drop below this minimum value, then the SX8662 may
require;
- a hardware reset issued by the host using the RESETB pin
- a software reset issued by the host using the I2C interface
(v) In the event the host processor is reset or undergoes a power OFF/ON cycle, it is recommended that the host also resets
the SX8662 and assures that parameters are re-written into the SPM (should these differ to the parameters held in NVM).
2.3
Thermal Characteristics
Parameter
Thermal Resistance - Junction to Ambient
Symbol
(vi)
θJA
Min.
Max.
Unit
25
°C/W
Table 4 Thermal Characteristics
(vi) Static airflow
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SX8662
Capacitive Button Matrix (up to 36) Controller
with Individual LED Drivers and Buzzer Output
ADVANCED COMMUNICATIONS & SENSING
2.4
Electrical Specifications
All values are valid within the operating conditions unless otherwise specified.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Active mode, average
IOP,active
30ms scan period,
12 sensors enabled,
minimum sensitivity
460
uA
Doze mode, average
IOP,Doze
195ms scan period,
12 sensors enabled,
minimum sensitivity
100
uA
Sleep
IOP,sleep
I2C listening, sensors
disabled
8
Current consumption
17
uA
0.7*VDD
VDD + 0.3
V
VSS - 0.3
0.8
V
±1
uA
ResetB, SCL, SDA
Input logic high
VIH
Input logic low
VIL
VSS applied to GND pins
Input leakage current
LI
CMOS input
Pull up resistor
RPU
when enabled
660
kΩ
Pull down resistor
RPD
when enabled
660
kΩ
Output logic high
VOH
IOH<4mA
Output logic low
VOL
GPIO set as Output, INTB, SDA
VDD-0.4
V
IOL,GPIO<12mA
0.4
V
400
ms
IOL,SDA,INTB<4mA
Start-up
Power up time
tpor
time between rising edge
VDD and rising INTB
RESETB
ResetB pulse width
tres
50
ns
Recommended External components
capacitor between VDIG, GND
Cvdig
type 0402, tolerance +/-50%
100
nF
capacitor between VANA, GND
Cvana
type 0402, tolerance +/-50%
100
nF
capacitor between CP, CN
Cint
type 0402, COG, tolerance +/-5%
1
nF
capacitor between VDD, GND
Cvdd
type 0402, tolerance +/-50%
100
nF
Table 5 Electrical Specifications
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SX8662
Capacitive Button Matrix (up to 36) Controller
with Individual LED Drivers and Buzzer Output
ADVANCED COMMUNICATIONS & SENSING
Parameter
I2C Timing Specifications
Symbol
Conditions
Min.
Typ.
Max.
Unit
400
KHz
(i)
SCL clock frequency
fSCL
SCL low period
tLOW
1.3
us
SCL high period
tHIGH
0.6
us
Data setup time
tSU;DAT
100
ns
Data hold time
tHD;DAT
0
ns
Repeated start setup time
tSU;STA
0.6
us
Start condition hold time
tHD;STA
0.6
us
Stop condition setup time
tSU;STO
0.6
us
Bus free time between stop and start
tBUF
500
us
Input glitch suppression
tSP
50
ns
Table 6 I2C Timing Specification
Notes:
(i) All timing specifications, Figure 4 and Figure 5, refer to voltage levels (VIL, VIH, VOL) defined in Table 5.
The interface complies with slave F/S mode as described by NXP: “I2C-bus specification, Rev. 03 - 19 June 2007”
Figure 4 I2C Start and Stop timing
Figure 5 I2C Data timing
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SX8662
Capacitive Button Matrix (up to 36) Controller
with Individual LED Drivers and Buzzer Output
ADVANCED COMMUNICATIONS & SENSING
3 FUNCTIONAL DESCRIPTION
3.1
3.1.1
Introduction
General
The SX8662 is intended to be used in applications which require capacitive sensors covered by isolating overlay
material. A finger approaching the capacitive sensors will change the charge that can be loaded on the sensors.
The SX8662 measures the change of charge and converts that into digital values (ticks). The larger the charge on
the sensors, the larger the number of ticks will be. The charge to ticks conversion is done by the SX8662 Analog
Sensor Interface (ASI).
The ticks are further processed by the SX8662 and converted in a high level, easy to use information for the
user’s host.
The information between SX8662 and the host is passed through the I2C interface with an additional interrupt
signal indicating that the SX8662 has new information. For buttons this information is simply touched or released.
User feedback, done through the SX8662’s GPIOs, can be visual via LEDs and/or audio via a buzzer.
3.1.2
Parameters
The SX8662 has many low level built-in, fixed algorithms and procedures. To allow a lot of freedom for the user
and adapt the SX8662 for different applications these algorithms and procedures can be configured with a large
set of parameters which will be described in the following sections.
Sensitivity and detection thresholds of the sensors are part of these parameters. Assuming that overlay material
and sensors areas are identical then the sensitivities and thresholds will be the same for each sensor. In case
sensors are not of the same size then sensitivities or thresholds might be chosen individually per sensor.
So a smaller size sensor can have a larger sensitivity while a big size sensor may have the lower sensitivity.
3.1.3
Configuration
During a development phase the parameters can be determined and fine tuned by the users and downloaded
over the I2C in a dynamic way. The parameter set can be downloaded over the I2C by the host each time the
SX8662 boots up. This allows a flexible way of setting the parameters at the expense of I2C occupation.
In case the parameters are frozen they can be programmed in Multiple Time Programmable (MTP) Non Volatile
Memory (NVM) on the SX8662. The programming needs to be done once (over the I2C). The SX8662 will then
boot up from the NVM and additional parameters from the host are not required anymore.
In case the host desires to overwrite the boot-up NVM parameters (partly or even complete) this can be done by
additional I2C communications.
3.2
Scan Period
The basic operation Scan period of the SX8662 sensing interface can be split into three periods over time.
In the first period (Sensing) the SX8662 is sensing all enabled CAP inputs, from CAP0 towards CAP11.
In the second period (Processing) the SX8662 processes the sensor data, verifies and updates the GPIO and the
I2C.
In the third period (Timer) the SX8662 is set in a low power mode and waits until a new cycle starts.
Figure 6 shows the different SX8662 periods over time.
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SX8662
Capacitive Button Matrix (up to 36) Controller
with Individual LED Drivers and Buzzer Output
ADVANCED COMMUNICATIONS & SENSING
Figure 6 Scan Period
The scan period determines the minimum reaction time of the SX8662. The scan period can be configured by the
host from 15ms to values larger than a second.
The reaction time is defined as the interval between a touch on the sensor and the moment that the SX8662
generates the interrupt on the INTB pin. The shorter the scan period the faster the reaction time will be.
Very low power consumptions can be obtained by setting very long scan periods with the expense of having
longer reaction times.
All external events like GPIO, I2C and the interrupt are updated in the processing period, so once every scan
period.
3.3
Operation modes
The SX8662 has 3 operation modes. The main difference is found in the reaction time (corresponding to the scan
period) and power consumption.
Active mode offers fast scan periods. The typical reaction time is 30ms. All enabled sensors are scanned and
information data is processed within this interval.
Doze mode increases the scan period time which increases the reaction time to 195ms typical and at the same
time reduces the operating current.
Sleep mode turns the SX8662 OFF, except for the I2C peripheral, minimizing operating current while maintaining
the power supplies. In Sleep mode the SX8662 does not do any sensor scanning. The Sleep mode will be exited
by any I2C access.
The user can specify other scan periods for the Active and Doze mode and decide for other compromises
between reaction time and power consumption.
In most applications the reaction time needs to be fast when fingers are present, but can be slow when no person
uses the application. In case the SX8662 is not used for a specific time it will go from Active mode into Doze
mode and power will be saved. This time-out is determined by the Passive Timer which can be configured by the
user or turned OFF if not required.
To leave Doze mode and enter Active mode this can be done by a simple touch on any button.
The host can decide to force the operating mode by issuing commands over the I2C (using register
CompOpMode) and take fully control of the SX8662. The diagram in Figure 7 shows the available operation
modes and the possible transitions.
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SX8662
Capacitive Button Matrix (up to 36) Controller
with Individual LED Drivers and Buzzer Output
ADVANCED COMMUNICATIONS & SENSING
Figure 7 Operation modes
3.4
3.4.1
Sensors on the PCB
Matrix Keys/Buttons (MK)
In opposition to most of the other Semtech capacitive sensing products where 1 button = 1 sensor
(CAP0…CAP11)., the SX8662 requires sensors to be routed in matrix and each button is formed by the
intersection/concatenation of two sensors areas. The buttons are covered by isolating overlay material (typically
1mm...3mm). The area of a button is typically one square centimetre which corresponds about to the area of a
finger touching the overlay material.
Figure 8 Matrix buttons layout/connections (Red = Top; Brown = Inner1; Blue = Inner2)
IMPORTANT: Please note that while the matrix structure allows increasing dramatically the potential maximum
number of buttons (up to 36 with only 12 sensors) it also limits the operation to max one matrix button reported at
a time (ie single button touch operation). When several matrix buttons are touched only the first one is reported.
3.4.2
Priority Key/Button (PK)
When the priority key is enabled in BtnCfg[6], CAP11 can be routed outside the matrix to a separate standard
button sensor. Matrix size is then reduced to 6x5 keys (CAP0…CAP10). Priority key operation/reporting is
independent from the matrix and can be used for any “high priority” key (Power, Reset, etc) or “multi-touch”
function (Shift, Alt, etc).
3.4.3 Schematics Requirements
For each PK combination, a specific schematic must be followed on the board as illustrated in figure below.
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SX8662
Capacitive Button Matrix (up to 36) Controller
with Individual LED Drivers and Buzzer Output
ADVANCED COMMUNICATIONS & SENSING
MK
35
MK
34
MK
33
MK
32
MK
31
CAP11
MK
25
MK
24
MK
23
MK
22
MK
21
MK
30
CAP9
MK
25
MK
24
MK
23
MK
22
MK
21
MK
30
CAP9
MK
16
MK
15
MK
14
MK
13
MK
20
MK
29
CAP7
MK
16
MK
15
MK
14
MK
13
MK
20
MK
29
CAP7
MK
9
MK
8
MK
7
MK
12
MK
19
MK
28
CAP6
MK
9
MK
8
MK
7
MK
12
MK
19
MK
28
CAP6
MK
4
MK
3
MK
6
MK
11
MK
18
MK
27
CAP5
MK
4
MK
3
MK
6
MK
11
MK
18
MK
27
CAP5
MK
1
MK
2
MK
5
MK
10
MK
17
MK
26
CAP4
MK
1
MK
2
MK
5
MK
10
MK
17
MK
26
CAP4
CAP0
CAP1
CAP2
CAP3
CAP8
CAP10
CAP0
CAP1
CAP2
CAP3
CAP8
CAP10
MK
36
PK = ON (CAP11)
PK = OFF
Figure 9 Sensors Schematics Requirements vs Configuration
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3.5
Button Information (MK and PK)
The touch buttons have two simple states (see Figure 10): ON (touched by finger) and OFF (released and no
finger press).
Figure 10 Buttons
A finger touch is reported as soon as the ASI ticks of both sensors forming the button exceed their user-defined
threshold plus a hysteresis.
A finger release is reported as soon as the ASI ticks of one at least of the sensors forming the button goes below
its user-defined threshold minus a hysteresis.
The hysteresis around the threshold avoids rapid touch and release signalling during transients.
IMPORTANT: Please note that while the matrix structure allows increasing dramatically the potential maximum
number of buttons (up to 36 with only 12 sensors) it also limits the operation to max one matrix button reported at
a time (ie single button touch operation). When two matrix buttons are touched only the first one is reported.
3.6
Analog Sensing Interface
The Analog Sensing Interface (ASI) converts the charge on the sensors into ticks which will be further digitally
processed. The basic principle of the ASI will be explained in this section.
The ASI consists of a multiplexer selecting the sensor, analog switches, a reference voltage, an ADC sigma delta
converter, an offset compensation DAC and an external integration capacitor (see Figure 11).
Figure 11 Analog Sensor Interface
To get the ticks representing the charge on a specific sensor the ASI will execute several steps.
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The charge on a sensor cap (e.g CAP0) will be accumulated multiple times on the external integration capacitor,
Cint.
This results in an increasing voltage on Cint proportional to the capacitance on CAP0.
At this stage the offset compensation DAC is enabled. The compensation DAC generates a voltage proportional
to an estimation of the external capacitance. The estimation is obtained by the offset compensation procedure
executed e.g. at power-up.
The difference between the DAC output and the charge on Cint is the desired signal. In the ideal case the
difference of charge will be converted to zero ticks if no finger is present and the number of ticks becomes high in
case a finger is present.
The difference of charge on Cint and the DAC output will be transferred to the ADC (Sigma Delta Integrator).
After the charge transfer to the ADC the steps above will be repeated.
The larger the number the cycles are repeated the larger the signal out of the ADC with improved SNR. The
sensitivity is therefore directly related to the number of cycles.
The SX8662 allows setting the sensitivity for each sensor individually in applications which have a variety of
sensors sizes or different overlays or for fine-tuning performances. The optimal sensitivity is depending heavily on
the final application. If the sensitivity is too low the ticks will not pass the thresholds and user detection will not be
possible. In case the sensitivity is set too large, some power will be wasted and false touch information may be
output (i.e. for touch buttons => finger not touching yet).
Once the ASI has finished the first sensor, the ticks are stored and the ASI will start measuring the next sensor
until all (enabled) sensors pins have been treated.
In case some sensors are disabled then these result in lower power consumption simply because the ASI is active
for a shorter period and the following processing period will be shorter.
The ticks from the ASI will then be handled by the digital processing.
The ASI will shut down and wait until new sensing period will start.
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3.7
Offset Compensation
The capacitance at the CAP pins is determined by an intrinsic capacitance of the integrated circuit, the PCB
traces, ground coupling and the sensor planes. This capacitance is relatively large and might become easily some
tens of pF. This parasitic capacitance will vary only slowly over time due to environmental changes.
A finger touch is in the order of one pF. If the finger approaches the sensor this occurs typically fast.
The ASI has the difficult task to detect and distinguish a small, fast changing capacitance, from a large, slow
varying capacitance. This would require a very precise, high resolution ADC and complicated, power consuming,
digital processing.
The SX8662 features a 16 bit DAC which compensates for the large, slow varying capacitance already in front of
the ADC. In other words the ADC converts only the desired small signal. In the ideal world the ADC will put out
zero ticks even if the external capacitance is as high as 100pF.
At each power-up of the SX8662 the Digital Compensation Values (DCV) are estimated by the digital processing
algorithms. The algorithm will adjust the compensation values such that zero ticks will be generated by the ADC.
Once the correct compensation values are found these will be stored and used to compensate each CAP pin.
If the SX8662 is shut down the compensation values will be lost. At a next power-up the procedure starts all over
again. This assures that the SX8662 will operate under any condition. Powering up at e.g. different temperatures
will not change the performance of the SX8662 and the host does not have to do anything special.
The DCVs do not need to be updated if the external conditions remain stable.
However if e.g. temperature changes this will influence the external capacitance. The ADC ticks will drift then
slowly around zero values basically because of the mismatch of the compensation circuitry and the external
capacitance.
In case the average value of the ticks become higher than the positive noise threshold (configurable by user) or
lower than the negative threshold (configurable by user) then the SX8662 will initiate a compensation procedure
and find a new set of DCVs.
Compensation procedures can as well be initiated by the SX8662 on periodic intervals. Even if the ticks remain
within the positive and negative noise thresholds the compensation procedure will then estimate new sets of
DCVs.
Finally the host can initiate a compensation procedure by using the I2C interface. This is e.g. required after the
host changed the sensitivity of sensors.
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3.8
Processing
The first processing step of the raw ticks, coming out of the ASI, is low pass filtering to obtain an estimation of the
average capacitance: tick-ave (see Figure 12).
This slowly varying average is important in the detection of slowly changing environmental changes.
ASI
processing
SPM
processing
ticks (raw)
tick-diff
PWM LED
controller
tick-ave
GPIO
controller
low pass
I2C
compensation DCV
Figure 12 Processing
The difference of the tick average and the raw ticks, tick-diff, is a good estimation of rapid changing input
capacitances.
The tick-diff, tick-ave and the configuration parameters in the SPM are then processed and determines the sensor
information, I2C registers status and PWM control.
3.9
Configuration
Figure 13 shows the building blocks used for configuring the SX8662.
Figure 13 Configuration
The default configuration parameters of the SX8662 are stored in the Quick Start Memory (QSM). This
configuration data is setup to a very common application for the SX8662 with 8 buttons. Without any programming
or host interaction the SX8662 will start up in the Quick Start Application.
The QSM settings are fixed and cannot be changed by the user.
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In case the application needs different settings than the QSM settings then the SX8662 can be setup and/or
programmed over the I2C interface.
The configuration parameters of the SX8662 can be stored in the Multiple Time Programmable (MTP) Non
Volatile Memory (NVM). The NVM contains all those parameters that are defined and stable for the application.
Examples are the number of sensors enabled, sensitivity, active and Doze scan period. The details of these
parameters are described in the next chapters.
At power up the SX8662 checks if the NVM contains valid data. In that case the configuration parameter source
becomes the NVM. If the NVM is empty or non-valid then the configuration source becomes the QSM. In the next
step the SX8662 copies the configuration parameter source into the Shadow Parameter Memory (SPM). The
SX8662 is operational and uses the configuration parameters of the SPM.
During power down or reset event the SPM loses all content. It will automatically be reloaded following power up
or at the end of the reset event.
The host will interface with the SX8662 through the I2C bus and the analog output interface.
The I2C of the SX8662 consists of 16 registers. Some of these I2C registers are used to read the status and
information of the buttons. Other I2C registers allow the host to take control of the SX8662. The host can e.g.
decide to change the operation mode from active mode to Doze mode or go into sleep (according Figure 7).
Two additional modes allow the host to have an access to the SPM or indirect access to the NVM.
These modes are required during development, can be used in real time or in-field programming.
Figure 14 shows the Host SPM mode. In this mode the host can decide to overwrite the SPM. This is useful
during the development phases of the application where the configuration parameters are not yet fully defined and
as well during the operation of the application if some parameters need small deviations from the QSM or NVM
content.
Figure 14 Host SPM mode
The content of the SPM remains valid as long as the SX8662 is powered. After a power down the host needs to
re-write the SPM at the next power-up.
Figure 15 shows the Host NVM mode. In this mode the host will be able to write the NVM.
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Figure 15 Host NVM mode
The writing of the host towards the NVM is not done directly but done in 2 steps (Figure 15).
In the first step the host writes to the SPM (as in Figure 14). In the second step the host signals the SX8662 to
copy the SPM content into the NVM.
Initially the NVM memory is empty and it is required to determine a valid parameter set for the application. This
can be done during the development phase using dedicated evaluation hardware representing the final
application. This development phase uses probably initially the host SPM mode which allows faster iterations.
Once the parameter set is determined this can be written to the NVM over the I2C using the 2 steps approach by
the host or a dedicated programmer for large volumes production (as described in the paragraphs 6.6 and 6.7).
3.10 Power Management
The SX8662 uses on-chip voltage regulators which are controlled by the on-chip microprocessor. The regulators
need to be stabilized with an external capacitor between VANA and ground and between VDIG and ground (see
Table 5). Both regulators are designed to only drive the SX8662 internal circuitry and must not be loaded
externally.
3.11 Clock Circuitry
The SX8662 has its own internal clock generation circuitry that does not require any external components. The
clock circuitry is optimized for low power operation and is controlled by the on-chip microprocessor. The typical
operating frequency of the oscillating core is 16.7MHz from which all other lower frequencies are derived.
3.12 I2C interface
The I2C interface allows the communication between the host and the SX8662.
The I2C slave implemented on the SX8662 is compliant with the standard (100kb/s) and fast mode (400kb/s)
The default SX8662 I2C address equals 0b010 1011.
A different I2C address can be programmed by the user in the NVM.
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3.13 Interrupt
3.13.1 Power up
During power up the INTB is kept low. Once the power up sequence is terminated the INTB is cleared
autonomously. The SX8662 is then ready for operation.
Figure 16 Power Up vs. INTB
During the power on period the SX8662 stabilizes the internal regulators, RC clocks and the firmware initializes all
registers.
During the power up the SX8662 is not accessible and I2C communications are forbidden. The GPIOs set as
inputs with a pull up resistor.
As soon as the INTB rises the SX8662 will be ready for I2C communication. The GPIOs are then configured
according the parameters in the SPM.
The value of INTB before power up depends on the INTB pull up resistor supply voltage.
3.13.2 Assertion
INTB is updated in Active or Doze mode once every scan period.
The INTB will be asserted at the following events:
• if a Button event occurred (touch or release if enabled). I2C register CapStatKeys show the detailed status of
the Buttons,
• when actually entering Active or Doze mode via a host request (may be delayed by 1 scan period). I2C
register CompOpmode shows the current operation mode,
• once compensation procedure is completed either through automatic trigger or via host request (may be
delayed by 1 scan period),
• once SPM write is effective (may be delayed by 1 scan period),
• once NVM burn procedure is completed (may be delayed by 1 scan period),
• during reset (power up, hardware RESETB, software reset).
3.13.3 Clearing
The clearing of the INTB is done as soon as the host performs a read to any of the SX8662 I2C registers.
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3.13.4 Example
A typical example of the assertion and clearing of the INTB and the I2C communication is shown in Figure 17.
Figure 17 Interrupt and I2C
When a button is touched the SX8662 will assert the interrupt (1). The host will read the SX8662 status
information over the I2C (2) and this clears the interrupt.
If the finger releases the button the interrupt will be asserted (3), the host reads the status (4) which clears the
interrupt.
In case the host will not react to an interrupt then this will result in a missing touch.
3.14 Reset
The reset can be performed by 3 sources:
- power up,
- RESETB pin,
- software reset.
3.14.1 Power up
During power up the INTB is kept low. Once the power up sequence is terminated the INTB is released
autonomously. The SX8662 is then ready for operation.
Figure 18 Power Up vs. INTB
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During the power on period the SX8662 stabilizes the internal regulators, RC clocks and the firmware initializes all
registers.
During the power up the SX8662 is not accessible and I2C communications are forbidden.
As soon as the INTB rises the SX8662 will be ready for I2C communication.
3.14.2 RESETB
When RESETB is driven low the SX8662 will reset and start the power up sequence as soon as RESETB is
driven high or pulled high.
In case the user does not require a hardware reset control pin then the RESETB pin can be connected to VDD.
Figure 19 Hardware Reset
3.14.3 Software Reset
To perform a software reset the host needs to write 0xDE followed by 0x00 at the SoftReset register at address
0xB1.
Figure 20 Software Reset
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3.15 General Purpose Input and Outputs
The SX8662 offers eight General Purpose Input and Outputs (GPIO) pins which can be configured in any of these
modes:
- GPO (General Purpose Output) with Autoligth ON/OFF
- SPO (Special Purpose Output). GPIO7 only; in this mode the GPIO can be connected to an external buzzer.
The input state of the GPIO is only used during the initial phase of the power up period.
Each of these GPIO modes is described in more details in the following sections.
The polarity of the GPO pins is defined as in figure below, driving an LED as example. It has to be set accordingly
in SPM parameter GpioPolarity.
Figure 21 polarity = 1/Normal (a), polarity = 0/Inverted (b)
The PWM blocks used GPO modes are 8-bits based and clocked at 2MHz typ. hence offering 256 selectable
pulse width values with a granularity of 0.5us typ.
Figure 22 PWM definition, (a) small pulse width, (b) large pulse width
3.15.1 GPO
GPIOs configured as GPO will operate as digital outputs which can generate both standard low/high logic levels
and PWM low/high duty cycles levels. Typical application is LED ON/OFF control.
Transitions between ON and OFF states can be triggered either automatically (Autolight ON) or manually by the
host (Autolight OFF). This is illustrated in figures below.
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Figure 23 LED Control in GPO mode, Autolight OFF
Figure 24 LED Control in GPO mode, Autolight ON
Additionally these transitions can be configured to be done with or without fading following a logarithmic or linear
function. This is illustrated in figures below.
Figure 25 GPO ON transition (LED fade in), normal polarity, (a) linear, (b) logarithmic
Figure 26 GPO ON transition (LED fade in), inverted polarity, (a) linear, (b) logarithmic
The fading out (e.g. after a button is released) is identical to the fading in but an additional off delay can be added
before the fading starts (Figure 27 and Figure 28).
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Figure 27 GPO OFF transition (LED fade out), normal polarity, (a) linear, (b) logarithmic
Figure 28 GPO OFF transition (LED fade out), inverted polarity, (a) linear, (b) logarithmic
Please note that standard high/low logic signals are just a specific case of GPO mode and can also be generated
simply by setting inc/dec time to 0 (i.e. OFF) and programming intensity OFF/ON to 0x00 and 0xFF.
3.15.2 Fading Modes
The SX8662 supports two different fading modes, namely Single and Continuous. These fading modes can be
configured for each GPIO individually. Please see 5.6 “GPIO Parameters” for more information on how to
configure this feature.
i) Single Fading Mode:
The GPO pin fades in when the associated button is touched and it fades out when it is released. This is shown in
Figure 29
OFF
OFF
ON
ON intensity
OFF intensity
OFF intensity
fading-in
delay_off
fading-out
Figure 29 Single Fading Mode
ii) Continuous Fading Mode:
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The GPO pin fades in and fades out continuously when the associated button is touched. The fading in and out
stops when the button is released. This is shown in Figure 30.
OFF
ON
ON intensity
OFF intensity
OFF intensity
fading-in fading-out
Figure 30 Continuous Fading Mode
3.15.3 Intensity index vs PWM pulse width
Tables below are used to convert all intensity indexes parameters GpioIntensityOff, GpioIntensityOn and
GppIntensity but also to generate fading in GPO mode
During fading in(out), the index is automatically incremented(decremented) at every Inc(Dec)Time x
Inc(Dec)Factor until it reaches the programmed GpioIntensityOn(Off) value.
Index
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Lin/Log
0/0
2/0
3/0
4/0
5/0
6/2
7/2
8/2
9/2
10/2
11/2
12/2
13/2
14/2
15/3
16/3
17/3
18/3
19/3
20/3
21/3
22/3
23/3
24/4
25/4
26/4
27/4
28/4
29/4
30/4
31/4
32/5
Index
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Lin/Log
33/5
34/5
35/5
36/5
37/5
38/6
39/6
40/6
41/6
42/6
43/7
44/7
45/7
46/7
47/7
48/8
49/8
50/8
51/8
52/9
53/9
54/9
55/9
56/10
57/10
58/10
59/10
60/11
61/11
62/11
63/12
64/12
Index
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
Lin/Log
65/12
66/13
67/13
68/13
69/14
70/14
71/14
72/15
73/15
74/15
75/16
76/16
77/16
78/17
79/17
80/18
81/18
82/19
83/19
84/20
85/20
86/21
87/21
88/22
89/22
90/23
91/23
92/24
93/24
94/25
95/25
96/26
Index
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
Lin/Log
97/26
98/27
99/27
100/28
101/29
102/29
103/30
104/30
105/31
106/32
107/32
108/33
109/33
110/34
111/35
112/35
113/36
114/37
115/38
116/38
117/39
118/40
119/40
120/41
121/42
122/43
123/44
124/44
125/45
126/46
127/47
128/48
Index
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
Lin/Log
129/48
130/49
131/50
132/51
133/52
134/53
135/54
136/55
137/55
138/56
139/57
140/58
141/59
142/60
143/61
144/62
145/63
146/64
147/65
148/66
149/67
150/68
151/69
152/71
153/72
154/73
155/74
156/75
157/76
158/77
159/78
160/80
Index
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
Lin/Log
161/81
162/82
163/83
164/84
165/86
166/87
167/88
168/89
169/91
170/92
171/93
172/95
173/96
174/97
175/99
176/100
177/101
178/103
179/104
180/106
181/107
182/109
183/110
184/111
185/113
186/114
187/116
188/117
189/119
190/121
191/122
192/124
Index
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
Lin/Log
193/125
194/127
195/129
196/130
197/132
198/133
199/135
200/137
201/139
202/140
203/142
204/144
205/146
206/147
207/149
208/151
209/153
210/155
211/156
212/158
213/160
214/162
215/164
216/166
217/168
218/170
219/172
220/174
221/176
222/178
223/180
224/182
Index
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
Lin/Log
225/184
226/186
227/188
228/190
229/192
230/194
231/197
232/199
233/201
234/203
235/205
236/208
237/210
238/212
239/215
240/217
241/219
242/221
243/224
244/226
245/229
246/231
247/233
248/236
249/238
250/241
251/243
252/246
253/248
254/251
255/253
256/256
Lin/Log
64/131
63/129
Index
224
225
Lin/Log
32/72
31/70
Table 7 Intensity index vs. PWM pulse width (normal polarity)
Index
0
1
Lin/Log
256/256
255/256
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Index
32
33
Lin/Log
224/251
223/251
Rev5 4 August 2011
Index
64
65
Lin/Log
192/244
191/243
Index
96
97
Lin/Log
160/230
159/229
Index
128
129
Lin/Log
128/208
127/207
© 2011 Semtech Corp.
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Index
160
161
Lin/Log
96/175
95/174
Index
192
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2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
254/256
253/256
252/256
251/254
250/254
249/254
248/254
247/254
246/254
245/254
244/254
243/254
242/253
241/253
240/253
239/253
238/253
237/253
236/253
235/253
234/253
233/252
232/252
231/252
230/252
229/252
228/252
227/252
226/252
225/251
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
222/251
221/251
220/251
219/250
218/250
217/250
216/250
215/250
214/249
213/249
212/249
211/249
210/249
209/248
208/248
207/248
206/248
205/247
204/247
203/247
202/247
201/246
200/246
199/246
198/246
197/245
196/245
195/245
194/244
193/244
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
190/243
189/243
188/242
187/242
186/242
185/241
184/241
183/241
182/240
181/240
180/240
179/239
178/239
177/238
176/238
175/237
174/237
173/236
172/236
171/235
170/235
169/234
168/234
167/233
166/233
165/232
164/232
163/231
162/231
161/230
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
158/229
157/228
156/227
155/227
154/226
153/226
152/225
151/224
150/224
149/223
148/223
147/222
146/221
145/221
144/220
143/219
142/218
141/218
140/217
139/216
138/216
137/215
136/214
135/213
134/212
133/212
132/211
131/210
130/209
129/208
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
126/206
125/205
124/204
123/203
122/202
121/201
120/201
119/200
118/199
117/198
116/197
115/196
114/195
113/194
112/193
111/192
110/191
109/190
108/189
107/188
106/187
105/185
104/184
103/183
102/182
101/181
100/180
99/179
98/178
97/176
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
94/173
93/172
92/170
91/169
90/168
89/167
88/165
87/164
86/163
85/161
84/160
83/159
82/157
81/156
80/155
79/153
78/152
77/150
76/149
75/147
74/146
73/145
72/143
71/142
70/140
69/139
68/137
67/135
66/134
65/132
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
62/127
61/126
60/124
59/123
58/121
57/119
56/117
55/116
54/114
53/112
52/110
51/109
50/107
49/105
48/103
47/101
46/100
45/98
44/96
43/94
42/92
41/90
40/88
39/86
38/84
37/82
36/80
35/78
34/76
33/74
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
30/68
29/66
28/64
27/62
26/59
25/57
24/55
23/53
22/50
21/48
20/46
19/44
18/41
17/39
16/37
15/35
14/32
13/30
12/27
11/25
10/23
9/20
8/18
7/15
6/13
5/10
4/8
3/5
2/3
0/0
Table 8 Intensity index vs. PWM pulse width (inverted polarity)
3.15.4 Tri-State Multiplexing (TSM)
SX8662 can support up to 36 individual LEDs ie one per matrix key. To make this possible with the limited GPIOs
available a Tri-State Multiplexing driver has been implemented on chip and a specific LED matrix connection
must be followed for correct operation.
Figure 31 Tri-State Multiplexing Schematics (DMKx = LED of button MKx, Cf Figure 48)
Whenever set to GPO with Autolight ON, GPIO0-6 (GPIO0-5 if PK is enabled) are automatically configured for
TSM operation.
If PK is enabled the matrix is reduced to 6x5 LEDs, DMK31-36 can be removed and GPIO6 is automatically used
for PK independent LED feedback (if Autoligth ON, else can be controlled by the host).
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4 PIN DESCRIPTIONS
4.1
Introduction
This chapter describes briefly the pins of the SX8662, the way the pins are protected, if the pins are analog,
digital, require pull up or pull down resistors and show control signals if these are available.
4.2
ASI pins
CAP0, CAP1,...,CAP11
The capacitance sensor pins (CAP0, CAP1,..., CAP11) are connected directly to the ASI circuitry which converts
the sensed capacitance into digital values.
The capacitance sensor pins which are not used should be left open.
The enabled CAP pins need be connected directly to the sensors without significant resistance (typical below
some ohms, connection vias are allowed).
The capacitance sensor pins are protected to VANA and GROUND.
Figure 32 shows the simplified diagram of the CAP0, CAP1,...CAP11 pins.
SX8662
VANA
sensor
CAPx
CAP_INx
ASI
Note : x = 0, 1,2,…7
Figure 32 Simplified diagram of CAP0, CAP1,...,CAP11
CN, CP
The CN and the CP pins are connected to the ASI circuitry. A 1nF sampling capacitor between CP and CN needs
to be placed as close as possible to the SX8662.
The CN and CP are protected to VANA and GROUND.
Figure 33 shows the simplified diagram of the CN and CP pins.
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SX8662
VANA
CP
ASI
VANA
CN
Figure 33 Simplified diagram of CN and CP
4.3
Host interface pins
The host interface consists of the interrupt pin INTB, a reset pin RESETB and the standard I2C pins: SCL and
SDA.
INTB
The INTB pin is an open drain output that requires an external pull-up resistor (1..10 kOhm). The INTB pin is
protected to VDD using dedicated devices. The INTB pin has diode protected to GROUND.
Figure 34 shows a simplified diagram of the INTB pin.
VDD
SX8662
R_INT
INTB
to host
INT
Figure 34 Simplified diagram of INTB
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SCL
The SCL pin is a high impedance input pin. The SCL pin is protected to VDD, using dedicated devices, in order to
conform to standard I2C slave specifications. The SCL pin has diode protected to GROUND.
An external pull-up resistor (1..10 kOhm) is required on this pin.
Figure 35 shows the simplified diagram of the SCL pin.
VDD
SX8662
R_SCL
SCL
SCL _IN
from host
Figure 35 Simplified diagram of SCL
SDA
SDA is an IO pin that can be used as an open drain output pin with external pull-up resistor or as a high
impedance input pin. The SDA IO pin is protected to VDD, using dedicated devices, in order to conform to
standard I2C slave specifications. The SDA pin has diode protected to GROUND.
An external pull-up resistor (1..10 kOhm) is required on this pin.
Figure 36 shows the simplified diagram of the SDA pin.
VDD
SX8662
R_SDA
SDA
SDA_IN
from/to host
SDA_OUT
Figure 36 Simplified diagram of SDA
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RESETB
The RESETB pin is a high impedance input pin. The RESETB pin is protected to VDD using dedicated devices.
The RESETB pin has diode protected to GROUND.
Figure 37 shows the simplified diagram of the RESETB pin controlled by the host.
VDD
SX8662
R_RESETB
RESETB
RESETB_IN
from host
Figure 37 Simplified diagram of RESETB controlled by host
Figure 38 shows the RESETB without host control.
VDD
SX8662
RESETB
RESETB_IN
Figure 38 Simplified diagram of RESETB without host control
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4.4
Power management pins
The power management pins consist of the Power, Ground and Regulator pins.
VDD
VDD is a power pin and is the main power supply for the SX8662.
VDD has protection to GROUND.
Figure 39 shows a simplified diagram of the VDD pin.
SX8662
VDD
VDD
Figure 39 Simplified diagram of VDD
GND
The SX8662 has four ground pins all named GND. These pins and the package center pad need to be connected
to ground potential.
The GND has protection to VDD.
Figure 40 shows a simplified diagram of the GND pin.
SX8662
VDD
GND
GND
Figure 40 Simplified diagram of GND
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VANA, VDIG
The SX8662 has on-chip regulators for internal use (pins VANA and VDIG).
VANA and VDIG have protection to VDD and to GND.
The output of the regulators needs to be de-coupled with a small 100nF capacitor to ground.
Figure 41 shows a simplified diagram of the VANA and VDIG pin.
SX8662
VDD
VDIG
VDIG
Cvdig
GND
VDD
VANA
VANA
Cvana
GND
Figure 41 Simplified diagram of VANA and VDIG
4.5
General purpose IO pins
The SX8662 has 8 General purpose input/output (GPIO) pins.
All the GPIO pins have protection to VDD and GND.
Figure 42 shows a simplified diagram of the GPIO pins.
Figure 42 Simplified diagram of GPIO pins
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5 DETAILED CONFIGURATION DESCRIPTIONS
5.1
Introduction
The SX8662 configuration parameters are taken from the QSM or the NVM and loaded into the SPM as explained
in the chapter ‘functional description’.
This chapter describes the details of the configuration parameters of the SX8662.
The SPM is split by functionality into 5 configuration sections:
• General: operating modes,
• Capacitive Sensors: related to lower level capacitive sensing,
• Buttons (MK and PK): related to the conversion from sensor data towards button information,
• Buzzer: defining parameters for the buzzer
• GPIOs: related to the setup of the GPIO pins.
The total address space of the SPM and the NVM is 128 bytes, from address 0x00 to address 0x7F.
Two types of memory addresses, data are accessible to the user.
• ‘application data’: Application dependent data that need to be configured by the user.
• ‘reserved’: Data that need to be maintained by the user to the QSM default values (i.e. when NVM is burned).
The Table 9 and Table 10 resume the complete SPM address space and show the ‘application data’ and
‘reserved’ addresses, the functional split and the default values (loaded from the QSM).
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Address
Name
Default/QSM
value
Address
0x00
Reserved
0xxx
0x20
Reserved
0x00
0x01
Reserved
0xxx
0x21
Reserved
0x00
0x02
Reserved
0x42
0x22
BtnCfg
0x30
0x03
Reserved
Name
Default/QSM
value
BtnAvgThresh
0x50
0x2B
0x24
BtnCompNegThresh
0xA0
0x05
ActiveScanPeriod
0x02
0x25
BtnCompNegCntMax
0x01
DozeScanPeriod
0x0D
0x26
BtnHysteresis
0x0A
0x06
Buttons
0x23
I2CAddress
General
0xxx
0x04
PassiveTimer
0x00
0x27
BtnStuckAtTimeout
0x00
0x08
Reserved
0x00
0x28
Reserved
0x80
0x09
CapModeMisc
0x00
0x29
Reserved
0x00
0x0A
Reserved
0x55
0x2A
Reserved
0xFF
0x0B
Reserved
0x55
0x2B
Reserved
0x00
0x0C
Reserved
0x55
0x2C
Reserved
0x7D
0x0D
CapSensitivity0_1
0x44
0x2D
Reserved
0x00
0x0E
CapSensitivity2_3
0x44
0x2E
Reserved
0x0A
0x0F
CapSensitivity4_5
0x44
0x2F
Reserved
0x00
0x10
CapSensitivity6_7
0x44
0x30
Reserved
0x64
0x11
CapSensitivity8_9
0x44
0x31
Reserved
0x34
Capacitive Sensors
0x07
0x44
0x32
Reserved
0x50
0xA0
0x33
Reserved
0xA0
CapThresh1
0xA0
0x34
Reserved
0x01
CapThresh2
0xA0
0x35
Reserved
0x00
CapThresh3
0xA0
0x36
Reserved
0x00
0x17
CapThresh4
0xA0
0x37
BuzzerCfg
0xA4
0x18
CapThresh5
0xA0
0x38
BuzzerFreqPhase1
0x40
0x19
CapThresh6
0xA0
0x39
BuzzerFreqPhase2
0x20
0x1A
CapThresh7
0xA0
0x3A
Reserved
0x00
0x1B
CapThresh8
0xA0
0x3B
Reserved
0x00
0x1C
CapThresh9
0xA0
0x3C
Reserved
0x00
0x1D
CapThresh10
0xA0
0x3D
Reserved
0x00
0x1E
CapThresh11
0xA0
0x3E
Reserved
0x00
0x1F
CapPerComp
0x00
0x3F
Reserved
0x00
0x13
0x14
0x15
0x16
Buzzer
CapSensitivity10_11
CapThresh0
0x12
Table 9 SPM address map: 0x00…0x3F
Note
• ‘0xxx’:
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Address
Name
Default/QSM
value
Address
Name
Default/QSM
value
0x00
0x60
GpioDecTime7_6
0x44
Reserved
0x00
0x61
GpioDecTime5_4
0x44
0x42
Reserved
0x00
0x62
GpioDecTime3_2
0x44
0x43
GpioMode7_4
0x00
0x63
GpioDecTime1_0
0x44
0x44
GpioMode3_0
0x00
0x64
GpioOffDelay7_6
0x00
0x45
GpioIntensityOn0
0xFF
0x65
GpioOffDelay5_4
0x00
0x46
GpioIntensityOn1
0xFF
0x66
GpioOffDelay3_2
0x00
0x47
GpioIntensityOn2
0xFF
0x67
GpioOffDelay1_0
0x00
0x48
GpioIntensityOn3
0xFF
0x68
Reserved
0x00
0x49
GpioIntensityOn4
0xFF
0x69
Reserved
0x00
0x4A
GpioIntensityOn5
0xFF
0x6A
Reserved
0x00
0x4B
GpioIntensityOn6
0xFF
0x6B
Reserved
0x00
0x4C
GpioIntensityOn7
0xFF
0x6C
Reserved
0x00
0x4D
GpioIntensityOff0
0x00
0x6D
GpioFadingMode7_4
0x00
0x4E
GpioIntensityOff1
0x00
0x6E
GpioFadingMode3_0
0x00
0x4F
GpioIntensityOff2
0x00
0x6F
Reserved
0x50
0x50
GpioIntensityOff3
0x00
0x70
Reserved
0x74
GpioIntensityOff4
0x00
0x71
Reserved
0x10
GpioIntensityOff5
0x00
0x72
Reserved
0x45
0x53
GpioIntensityOff6
0x00
0x73
Reserved
0x02
0x54
GpioIntensityOff7
0x00
0x74
Reserved
0xFF
0x55
Reserved
0xFF
0x75
Reserved
0xFF
0x56
GpioOutPwrUp
0x00
0x76
Reserved
0xFF
0x57
GpioAutoLight
0xFF
0x77
Reserved
0xD5
0x58
GpoPolarity
0x7F
0x78
Reserved
0x55
0x59
GpioFunction
0x00
0x79
Reserved
0x55
0x5A
GpioIncFactor
0x00
0x7A
Reserved
0x7F
0x5B
GpioDecFactor
0x00
0x7B
Reserved
0x23
0x5C
GpioIncTime7_6
0x00
0x7C
Reserved
0x22
0x5D
GpioIncTime5_4
0x00
0x7D
Reserved
0x41
0x5E
GpioIncTime3_2
0x00
0x7E
Reserved
0xFF
0x51
0x52
GpioIncTime1_0
0x5F
0x00
0x7F
GPIOs
Reserved
0x41
GPIOs
0x40
SpmCrc
1
0xXX
Table 10 SPM address map: 0x40…0x7F
1
Note
• SpmCrc:
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5.2
General Parameters
General Parameters
Address
Name
Bits
Description
0x04
I2CAddress
7
Reserved (0)
6:0
Defines the I2C address.
The I2C address will be active after a reset.
Default: 0x2B
0x05
ActiveScanPeriod 7:0
Defines Active Mode Scan Period (Figure 6).
0x00: Reserved
0x01: 15ms
0x02: 30ms (default)
…
0xFF: 255 x 15ms
0x06
DozeScanPeriod
7:0
Defines Doze Mode Scan Period (Figure 6).
0x00: Reserved
0x01: 15ms
…
0x0D: 195ms (default)
…
0xFF: 255 x 15ms
0x07
PassiveTimer
7:0
Defines Passive Timer on Button Information (Figure 7).
0x00: OFF (default)
0x01: 1 second
…
0xFF: 255 seconds
0x08
Reserved
7:0
Reserved (0x00)
Table 11 General Parameters
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5.3
Capacitive Sensors Parameters
Capacitive Sensors Parameters
Address
Name
Bits Description
0x09
CapModeMisc
7:5 Reserved (000)
4:3 CapSenseProtect:
00: OFF (default)
01: ON. GPIOs activity is disabled during CAP11 sensing.
10: ON. GPIOs activity is disabled during CAP10-11 sensing.
11: ON. GPIOs activity is disabled during CAP0-11 sensing (i.e. all CAPx).
2:0 IndividualSensitivity Defines common sensitivity for all sensors or individual sensor
sensitivity.
000: Common sensitivity settings (CapSensitivity0_1[7:4]) (default)
100: Individual sensitivity settings (CapSensitivityx_x)
Else : Reserved
0x0A
Reserved
7:0 Reserved (0x55)
0x0B
Reserved
7:0 Reserved (0x55)
0x0C
Reserved
7:0 Reserved (0x55)
0x0D
CapSensitivity0_1
0x0E
CapSensitivity2_3
0x0F
CapSensitivity4_5
7:4 CAP0 Sensitivity - Common Sensitivity Defines the sensitivity.
0x0: Minimum
3:0 CAP1 Sensitivity
0x1: 1
…
7:4 CAP2 Sensitivity
0x4: 4 (default)
3:0 CAP3 Sensitivity
…
0x7: Maximum
7:4 CAP4 Sensitivity
0x8..0xF: Reserved
3:0 CAP5 Sensitivity
0x10
CapSensitivity6_7
7:4 CAP6 Sensitivity
3:0 CAP7 Sensitivity
0x11
CapSensitivity8_9
7:4 CAP8 Sensitivity
3:0 CAP9 Sensitivity
0x12
CapSensitivity10_1 7:4 CAP10 Sensitivity
1
3:0 CAP11 Sensitivity
0x13
CapThresh0
7:0 CAP0 Touch Threshold
0x14
CapThresh1
7:0 CAP1 Touch Threshold
0x15
CapThresh2
7:0 CAP2 Touch Threshold
0x16
CapThresh3
7:0 CAP3 Touch Threshold
0x17
CapThresh4
7:0 CAP4 Touch Threshold
0x18
CapThresh5
7:0 CAP5 Touch Threshold
0x19
CapThresh6
7:0 CAP6 Touch Threshold
0x1A
CapThresh7
7:0 CAP7 Touch Threshold
0x1B
CapThresh8
7:0 CAP8 Touch Threshold
0x1C
CapThresh9
7:0 CAP9 Touch Threshold
0x1D
CapThresh10
7:0 CAP10 Touch Threshold
0x1E
CapThresh11
7:0 CAP11 Touch Threshold
0x1F
CapPerComp
7:4 Reserved (0000)
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Defines the Touch Threshold ticks.
0x00: 0,
0x01: 4,
…
0xA0: 640 (default),
…
0xFF: 1020
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Capacitive Sensors Parameters
Address
Name
Bits Description
3:0 Periodic Offset Compensation
Defines the periodic offset compensation.
0x0: OFF (default)
0x1: 1 second
0x2: 2 seconds
…
0x7: 7 seconds
0x8: 16 seconds
0x9: 18 seconds
…
0xE: 28 seconds
0xF: 60 seconds
Table 12 Capacitive Sensors Parameters
CapSenseProtect
If needed, ASI activity can be protected against LED interference by automatically disabling GPIOs during
sensing periods. At the end of the sensing activity, GPIOs activity resume normally.
CapModeMisc
By default the ASI uses common sensitivity for all capacitive sensors in the case overlay material and sensors
sizes are about equal. The register bits CapSensitivity0_1[7:4] determine the sensitivity for all sensors in
common sensitivity mode.
The ASI can use an individual sensitivity for each CAP pin The individual sensitivity mode results in longer
sensing periods than required in common sensitivity mode.
CapSensitivity0_1,
CapSensitivity10_11
CapSensitivity2_3,
CapSensitivity4_5,
CapSensitivity6_7,
CapSensitivity8_9,
The sensitivity of the sensors can be set between 8 values. The higher the sensitivity is set the larger the value
of the ticks will be.
The minimum sensitivity can be used for thin overlay materials and large sensors, while the maximum
sensitivity is required for thicker overlay and smaller sensors.
The required sensitivity needs to be determined during a product development phase. Too low sensitivity
settings result in missing touches. Too high sensitivity settings will result in fault detection of fingers hovering
above the touch sensors.
The sensitivity is identical for all sensors in common sensitivity mode using the bits CapSensitivity0_1[7:4] and
can be set individually using register CapModeMisc[2:0].
CapThresh0, CapThresh1, CapThresh2, CapThresh3, CapThresh4, CapThresh5, CapThresh6, CapThresh7,
CapThresh8, CapThresh9, CapThresh10, CapThresh11:
For each CAP pin a threshold level can be set individually.
The threshold levels are used by the SX8662 for making touch and release decisions.
The details are explained in the sections for buttons.
CapPerComp
The SX8662 offers a periodic offset compensation for applications which are subject to substantial
environmental changes. The periodic offset compensation is done at a defined interval and only if buttons are
released.
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5.4
Buttons (MK and PK) Parameters
Buttons Parameters
Address
Name
0x22
BtnCfg
Bits Description
7
Reporting scheme:
0: report both MK and PK touches (multi MK touch is never allowed/reported)
(default)
1: report first/single MK or PK touch (ignore next touch until release of the first
one)
6
Priority key (PK):
0: OFF (default)
1: ON (CAP11)
5:4 Button events to be reported on NIRQ.
00 : None
01 : Touch
10 : Release
11 : Both (default)
3:2 Defines the number of samples at the scan period for determining a release of a
button.
00 : no debounce, use incoming sample (default)
01 : 2 samples debounce
10 : 3 samples debounce
11 : 4 samples debounce
1:0 Defines the number of samples at the scan period for determining a touch of a
button.
00 : no debounce, use incoming sample (default)
01 : 2 samples debounce
10 : 3 samples debounce
11 : 4 samples debounce
0x23
BtnAvgThresh
7:0 Defines the positive threshold for disabling the processing filter averaging.
If ticks are above the threshold, then the averaging is suspended.
0x00: 0
0x01: 4
…
0x50: 320 (default)
…
0xFF: 1020
0x24
BtnCompNegThresh
7:0 Defines the negative offset compensation threshold.
0x00: 0
0x01: 4
…
0xA0: 640 (default)
…
0xFF: 1020
0x25
BtnCompNegCntMax
7:0 Defines the number of ticks (below the negative offset compensation threshold)
which will initiate an offset compensation.
0x00: reserved
0x01: 1 sample (default)
…
0xFF: 255 samples
0x26
BtnHysteresis
7:0 Defines the button hysteresis corresponding to a percentage of the CAP
thresholds (defined in Table 12).
All buttons use the same hysteresis.
0x00: 0%
0x01: 1%
…
0x0A: 10% (default)
…
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Buttons Parameters
Address
Name
Bits Description
0x64: 100%
0x27
BtnStuckAtTimeout
7:0 Defines the stuck at timeout for buttons.
0x00: OFF (default)
0x01: 1 second
…
0xFF: 255 seconds
Table 13 Button Parameters
ticks_diff
A reliable button operation requires a coherent setting of the registers.
Figure 43 shows an example of a touch and a release. The ticks will vary slightly around the zero idle state.
When the touch occurs the ticks will rise sharply. At the release of the button the ticks will go down rapidly and
converge to the idle zero value.
Figure 43 Touch and Release Example
As soon as the ticks become larger than the CAP thresholds (see registers of the previous section) plus the
hysteresis (defined in register BtnHysteresis ) the debounce counter starts.
In the example of Figure 43 the touch is validated after 2 ticks (BtnCfg [2:0] = 1).
The release is detected immediately (BtnCfg [3] = 0) at the first tick which is below the threshold minus the
hysteresis.
BtnCfg
The user can select to have the interrupt signal (INTB) on touching a button, releasing a button or both.
In noisy environments it may be required to debounce the touch and release detection decision.
In case the debounce is enabled the SX8662 will count up to the number of debounce samples BtnCfg [1:0],
BtnCfg [3:2] before taking a touch or release decision. The sample period is identical to the scan period.
BtnAvgPosThresh
Small environmental and system noise cause the ticks to vary slowly around the zero idle mode value.
In case the ticks get slightly positive this is considered as normal operation. Very large positive tick values
indicate a valid touch. The averaging filter is disabled as soon as the average reaches the value defined by
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BtnAvgPosThresh. This mechanism avoids that a valid touch will be averaged and finally the tick difference
becomes zero.
In case three or more sensors reach the BtnAvgPosThresh value simultaneously then the SX8662 will start an
offset compensation procedure.
ticks_avg
Small environmental and system noise cause the ticks to vary slowly around the zero idle mode value.
In case the ticks get slightly negative this is considered as normal operation. However large negative values will
trigger an offset compensation phase and a new set of DCVs will be obtained.
The decision to trigger a compensation phase based on negative ticks is determined by the value in the register
BtnCompNegThresh and by the number of ticks below the negative thresholds defined in register
BtnCompNegCntMax. An example is shown in Figure 44.
Figure 44 Negative Ticks Offset Compensation Trigger
BtnCompNegThresh
Small negative ticks are considered as normal operation and will occur very often.
Larger negative ticks however need to be avoided and a convenient method is to trigger an offset
compensation phase. The new set of DCV will assure the idle ticks will be close to zero again.
A trade-off has to be found for the value of this register. A negative threshold too close to zero will trigger a
compensation phase very often. A very negative threshold will never trigger.
BtnCompNegCntMax
As soon as the ticks get smaller than the Negative Threshold the Negative Counter starts to count.
If the counter goes beyond the Negative Counter Max then the offset compensation phase is triggered.
The recommended value for this register is ‘1’ which means that the offset compensation starts on the first tick
below the negative threshold.
BtnHysteresis
The hysteresis percentage is identical for all buttons.
A touch is detected if the ticks are getting larger as the value defined by:
CapThreshold + CapThreshold * hysteresis.
A release is detected if the ticks are getting smaller as the value defined by:
CapThreshold - CapThreshold * hysteresis.
BtnStuckAtTimeout
The stuckat timer can avoid sticky buttons.
If the stuckat timer is set to one second then the touch of a finger will last only for one second and then a
compensation will be performed and button hence considered released, even if the finger remains on the
button for a longer time. After the actual finger release the button can be touched again and will be reported as
usual. In case the stuckat timer is not required it can be set to zero.
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5.5
Buzzer Parameters
Buzzer Parameters
Address
Name
Bits
Description
0x37
BuzzerCfg
7:6
Defines the phase 1 duration.
0x00: ~ 5ms
0x01: ~ 10ms
0x02: ~ 15ms (default)
0x03: ~ 30ms
5:4
Defines the phase 2 duration.
0x00: ~ 5ms
0x01: ~ 10ms
0x02: ~ 15ms (default)
0x03: ~ 30ms
3
Defines the buzzer idle level (BuzzerLevelIdle).
0x0: min level (0V), (default)
0x1: max level (VDD)
2:0
Defines the buzzer pwm prescaler value.
Default: 0x04
0x38
BuzzerFreqPhase1
7:0
Defines the frequency for the first phase of the buzzer.
freq ≈ 4MHz /(2^prescaler * BuzzerFreqPhase1)
Default: 0x40 (4KHz)
0x39
BuzzerFreqPhase2
7:0
Defines the frequency for the second phase of the buzzer.
freq ≈ 4MHz /(2^prescaler * BuzzerFreqPhase2)
Default: 0x20 (8KHz)
0x3A
Reserved
7:0
Reserved (0x00)
Table 14 Buzzer Parameters
The SX8662 has the ability to drive a buzzer (on GPIO7) to provide an audible indication that a button has been
touched. The buzzer is driven by a square signal for approximately 30ms (default). During the first phase (15ms)
the signal’s frequency is default 4KHz while in the second phase (15ms) the signal’s frequency default is 8KHz.
The buzzer is activated only once during any button touch and is not repeated for long touches. The user can
choose to enable or disable the buzzer by configuration and define the idle level, frequencies and phase
durations.
Figure 45 Buzzer behavior
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5.6
GPIO Parameters
GPIO Parameters
Address
Name
Bits Description
0x43
GpioMode7_4
7:6 GPIO[7] Mode Defines the GPIO mode.
00: GPO
5:4 GPIO[6] Mode 01: Reserved
3:2 GPIO[5] Mode 10: Reserved
11: SPO: Buzzer for GPIO[7],
1:0 GPIO[4] Mode
Reserved for GPIO[6..0]
Default GPO
7:6 GPIO[3] Mode
Default GPO
5:4 GPIO[2] Mode
Default GPO
3:2 GPIO[1] Mode
Default GPO
1:0 GPIO[0] Mode
Default GPO
0x44
GpioMode3_0
Default GPO
Default GPO
Default GPO
0x45
GpioIntensityOn0
0x46
GpioIntensityOn1
0x47
GpioIntensityOn2
0x48
GpioIntensityOn3
7:0 Defines the ON intensity index.
0x00: 0
7:0 0x01: 1
7:0 …
0xFF: 255 (default)
7:0
0x49
GpioIntensityOn4
7:0
0x4A
GpioIntensityOn5
7:0
0x4B
GpioIntensityOn6
7:0
0x4C
GpioIntensityOn7
7:0
0x4D
GpioIntensityOff0
0x4E
GpioIntensityOff1
0x4F
GpioIntensityOff2
0x50
GpioIntensityOff3
7:0 Defines the OFF intensity index.
0x00: 0 (default)
7:0 0x01: 1
7:0 …
0xFF: 255
7:0
0x51
GpioIntensityOff4
7:0
0x52
GpioIntensityOff5
7:0
0x53
GpioIntensityOff6
7:0
0x54
GpioIntensityOff7
7:0
0x56
GpioOutPwrUp
7:0 Defines the values of GPO pins after power up i.e. default values of I2C
parameters GpoCtrl.
Bits corresponding to GPO pins with Autolight ON should be left to 0.
Before being actually initialized GPIOs are shortly set as inputs with pull up.
0: OFF(default)
1: ON
0x57
GpioAutoLight
7:0 Enables Autolight in GPO mode.
0: OFF
1: ON (default). GPIO0-5 = MK(TSM); GPIO6 = MK(TSM) or PK if enabled
0x58
GpioPolarity
7:0 Defines the polarity of the GPO pins.
SPO pins require Normal Polarity.
0: Inverted
1: Normal
Default : 0x7F
0x59
GpioFunction
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7:0 Defines the intensity index vs PWM pulse width function.
0: Logarithmic (default)
1: Linear
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GPIO Parameters
Address
Name
Bits Description
0x5A
GpioIncFactor
7:0 Defines the fading increment factor.
0: intensity index incremented every increment time (default)
1: intensity index incremented every 16 increment times
0x5B
GpioDecFactor
7:0 Defines the fading decrement factor.
0: intensity index decremented every decrement time (default)
1: intensity index decremented every 16 decrement times
0x5C
GpioIncTime7_6
7:4 GPIO[7] Fading Increment Time
3:0 GPIO[6] Fading Increment Time
0x5D
GpioIncTime5_4
7:4 GPIO[5] Fading Increment Time
3:0 GPIO[4] Fading Increment Time
0x5E
GpioIncTime3_2
7:4 GPIO[3] Fading Increment Time
3:0 GPIO[2] Fading Increment Time
0x5F
GpioIncTime1_0
Defines the fading increment time.
0x0: OFF (default)
0x1: 0.5ms
0x2: 1ms
…
0xF: 7.5ms
The total fading in time will be:
GpioIncTime*GpioIncFactor*
(GpioIntensityOn – GpioIntensityOff)
7:4 GPIO[1] Fading Increment Time
3:0 GPIO[0] Fading Increment Time
0x60
GpioDecTime7_6
7:4 GPIO[7] Fading Decrement Time
3:0 GPIO[6] Fading Decrement Time
0x61
GpioDecTime5_4
7:4 GPIO[5] Fading Decrement Time
3:0 GPIO[4] Fading Decrement Time
0x62
GpioDecTime3_2
7:4 GPIO[3] Fading Decrement Time
3:0 GPIO[2] Fading Decrement Time
0x63
GpioDecTime1_0
7:4 GPIO[1] Fading Decrement Time
3:0 GPIO[0] Fading Decrement Time
0x64
GpioOffDelay7_6
7:4 GPIO[7] OFF Delay
3:0 GPIO[6] OFF Delay
0x65
GpioOffDelay5_4
7:4 GPIO[5] OFF Delay
3:0 GPIO[4] OFF Delay
0x66
GpioOffDelay3_2
7:4 GPIO[3] OFF Delay
3:0 GPIO[2] OFF Delay
0x67
GpioOffDelay1_0
7:4 GPIO[1] OFF Delay
Defines the fading decrement time.
0x0: OFF
0x1: 0.5ms
0x2: 1ms
…
0x4: 2.0ms (default)
…
0xF: 7.5ms
The total fading out time will be:
GpioDecTime*GpioDecFactor*
(GpioIntensityOn – GpioIntensityOff)
Defines the delay between release and start
of fading out (single fading)
0x0: instantaneous (default)
0x1: 200 ms
0x2: 400 ms
0x3: 600ms
…
0xA: 2s
0xB: 4s
…
0xF: 12s
3:0 GPIO[0] OFF Delay
0x68
Reserved
7:0 Reserved (0x00)
0x69
Reserved
7:0 Reserved (0x00)
0x6A
Reserved
7:0 Reserved (0x00)
0x6B
Reserved
7:0 Reserved (0x00)
0x6C
Reserved
7:0 Reserved (0x00)
0x6D
GpioFadingMode7_4
7:6 Fading mode for GPIO[7]
5:4 Fading mode for GPIO[6]
3:2 Fading mode for GPIO[5]
1:0 Fading mode for GPIO[4]
0x6E
GpioFadingMode3_0
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Defines the Fading mode for GPO[7:0].
00: Single (default)
01: Continuous
10: Reserved
11: Reserved
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GPIO Parameters
Address
Name
Bits Description
5:4 Fading mode for GPIO[2]
3:2 Fading mode for GPIO[1]
1:0 Fading mode for GPIO[0]
The fading modes are expected to be
defined at power up by the QSM or NVM.
In case the fading modes need to be
changed after power up this can be done
when the GPOs are all OFF.
Table 15 resumes the applicable SPM and I2C parameters for each GPIO mode.
SPM
I2C
1
GpioMode
GpioOutPwrUp
GpioAutolight
GPO
Autolight OFF
X
1
X
OFF
GpioPolarity
X
GpioIntensityOn
X
GpioIntensityOff
X
GpioFunction
GpioIncFactor
GpioDecFactor
GpioIncTime
GpioDecTime
GpioOffDelay
GpioFadingMode
GpoCtrl
X
X
X
X
X
X
X
X
GPO
Autolight ON
X
OFF
ON
TSM->Normal
else X
X
TSM->0%
else X
X
X
X
X
X
X
X
SPO
(Buzzer – GPIO7 only)
X
OFF
ON
Normal
Linear
GpioOutPwrUp must be set to OFF in Continuous Fading Mode
Grey = not applicable, with or without required setting
Table 15 Applicable (X) SPM/I2C Parameters vs. GPIO Mode
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6 I2C INTERFACE
The I2C implemented on the SX8662 is compliant with:
- standard (100kb/s), fast mode (400kb/s)
- slave mode
- 7 bit address (default 0x2B). The default address can be changed in the NVM at address 0x04.
The host can use the I2C to read and write data at any time. The effective changes will be applied at the next
processing phase (section 3.2).
Three types of registers are considered:
- status (read). These registers give information about the status of the capacitive buttons, GPIs, operation modes
etc…
- control (read/write). These registers control the soft reset, operating modes, GPIOs and offset compensation.
- SPM gateway (read/write). These registers are used for the communication between host and the SPM. The
SPM gateway communication is done typically at power up and is not supposed to be changed when the
application is running. The SPM needs to be re-stored each time the SX8662 is powered down.
The SPM can be stored permanently in the NVM memory of the SX8662. The SPM gateway communication over
the I2C at power up is then not required.
The I2C will be able to read and write from a start address and then perform read or writes sequentially, and the
address increments automatically.
The supported I2C access formats are described in the next sections.
6.1
I2C Write
The format of the I2C write is given in Figure 46.
After the start condition [S], the slave address (SA) is sent, followed by an eighth bit (‘0’) indicating a Write. The
SX8662 then acknowledges [A] that it is being addressed, and the master sends an 8 bit Data Byte consisting of
the SX8662 Register Address (RA). The slave acknowledges [A] and the master sends the appropriate 8 bit Data
Byte (WD0). Again the slave acknowledges [A]. In case the master needs to write more data, a succeeding 8 bit
Data Byte will follow (WD1), acknowledged by the slave [A]. This sequence will be repeated until the master
terminates the transfer with the Stop condition [P].
Figure 46 I2C write
The register address is incremented automatically when successive register data (WD1...WDn) is supplied by the
master.
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6.2
I2C read
The format of the I2C read is given in Figure 47.
After the start condition [S], the slave address (SA) is sent, followed by an eighth bit (‘0’) indicating a Write. The
SX8662 then acknowledges [A] that it is being addressed, and the master responds with an 8 bit data consisting
of the Register Address (RA). The slave acknowledges [A] and the master sends the Repeated Start Condition
[Sr]. Once again, the slave address (SA) is sent, followed by an eighth bit (‘1’) indicating a Read.
The SX8662 responds with acknowledge [A] and the Read Data byte (RD0). If the master needs to read more
data it will acknowledge [A] and the SX8662 will send the next read byte (RD1). This sequence can be repeated
until the master terminates with a NACK [N] followed by a stop [P].
Figure 47 I2C read
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6.3
I2C Registers Overview
Address
Name
R/W
Description
0x00
IrqSrc
read
Interrupt Source
0x01
CapStatKeys
read
Cap Status
0x02
Reserved
0x03
Reserved
0x04
Reserved
0x05
Reserved
0x06
Reserved
0x07
Reserved
0x08
SpmStat
read
SPM Status
0x09
CompOpMode
read/write
Compensation and
Operating Mode
0x0A
GpoCtrl
0x0B
Reserved
0x0C
Reserved
0x0D
SpmCfg
read/write
SPM Configuration
0x0E
SpmBaseAddr
read/write
SPM Base Address
0x0F
Reserved
0xAC
SpmKeyMsb
read/write
SPM Key MSB
0xAD
SpmKeyLsb
read/write
SPM Key LSB
0xB1
SoftReset
read/write
Software Reset
Table 16 I2C Registers Overview
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6.4
Status Registers
Address
0x00
Name
Bits
Description
7
Reserved
6
NVM burn interrupt flag
5
SPM write interrupt flag
4
Reserved
3
Reserved
2
Sensors interrupt flag
1
Compensation interrupt flag
0
Operating Mode interrupt flag
IrqSrc
Interrupt source flags
0: Inactive (default)
1: Active
INTB goes low if any of
these bits is set.
More than one bit can be
set.
Reading IrqSrc clears it
together with INTB.
Table 17 Interrupt Source
The delay between the actual event and the flags indicating the interrupt source may be one scan period.
IrqSrc[6] is set once NVM burn procedure is completed.
IrqSrc[5] is set once SPM write is effective.
IrqSrc[2] is set if a sensor event occurred. CapStatKeys show the detailed status of the sensors.
IrqSrc[1] is set once compensation procedure is completed either through automatic trigger or via host request.
IrqSrc[0] is set when actually entering Active or Doze mode via host request. CompOpmode shows the current
operation mode.
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Address
Name
Bits Description
7
0x01
CapStatKeys
Reserved
Priority Key Status
6 0 : not touched.
1 : touched.
Matrix Keys Status
0x00: no touch on matrix
0x01: key1 (MK1) is touched
0x02: key2 (MK2) is touched
5:0 …
0x24: key36 (MK36) is touched
If several matrix buttons are touched only the first one is reported.
Cf figure below for MK mapping/numbering vs CAPx pins
Table 18 I2C Cap status
Figure 48 Matrix Keys Mapping
Address
0x08
Name
Bits
SpmStat 7:4
3
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Description
reserved
NvmValid
Indicates if the current NVM is valid.
0: No – QSM is used
1: Yes – NVM is used
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Address
Name
Bits
Description
2:0
Indicates the number of times NVM has been burned:
0: None – QSM is used (default)
1: Once – NVM is used if NvmValid = 1, else QSM.
NvmCount
2: Twice – NVM is used if NvmValid = 1, else QSM.
3: Three times – NVM is used if NvmValid = 1, else QSM.
4: More than three times – QSM is used
Table 19 I2C SPM status
6.5
Control Registers
Address Name
Bits
Description
7:3
Reserved*, write only ‘00000’
2
0x09
Compensation
Indicates/triggers compensation procedure
0: Compensation completed (default)
1: read -> compensation running ; write -> trigger
compensation
Operating Mode
Indicates/programs** operating mode
00: Active mode (default)
01: Doze mode
10: Sleep mode
11: Reserved
CompOpMode
1:0
* The reading of these reserved bits will return varying values.
** After the operating mode change (Active/Doze) the host should wait for INTB or 300ms before
performing any I2C read access.
Table 20 I2C compensation, operation modes
Address Name
0x0A
GpoCtrl
Bits
7:0
Description
GpoCtrl[7:0]
Triggers ON/OFF state of GPOs when Autolight is OFF
0: OFF (i.e. go to IntensityOff)
1: ON (i.e. go to IntensityOn)
Default is set by SPM parameter GpioOutPwrUp
Bits of non-GPO pins are ignored.
Table 21 I2C GPO Control
Address
0xB1
Name
Bits
Description
SoftReset
7:0
Writing 0xDE followed by 0x00 will reset the chip.
Table 22 I2C Soft Reset
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6.6
SPM Gateway Registers
The SX8662 I2C interface offers two registers for exchanging the SPM data with the host.
• SpmCfg
• SpmBaseAddr
Address
0x0D
Name
Bits
Description
7:6
00: Reserved
5:4
Defines the normal operation or SPM mode
00: I2C in normal operation mode (default)
01: I2C in SPM mode
10: Reserved
11: Reserved
3
Defines r/w direction of SPM
0: SPM write access (default)
1: SPM read access
2:0
000: Reserved
SpmCfg
Table 23 SPM access configuration
Address
Name
Bits
Description
0x0E
SpmBaseAddr
7:0
SPM Base Address (modulo 8).
The lowest address is 0x00 (default)
The highest address is 0x78.
Table 24 SPM Base Address
The exchange of data, read and write, between the host and the SPM is always done in bursts of eight bytes.
The base address of each burst of eight bytes is a modulo 8 number, starting at 0x00 and ending at 0x78.
The registers SpmKeyMsb and SpmKeyLsb are required for NVM programming as described in section 6.7.
Address
0xAC
Name
Bits
Description
SpmKeyMsb
7:0
SPM to NVM burn Key MSB
Unlock requires writing data: 0x62
Table 25 SPM Key MSB at I2C register address 0xAC
Address
0xAD
Name
Bits
Description
SpmKeyLsb
7:0
SPM to NVM burn Key LSB
Unlock requires writing data: 0x9D
Table 26 SPM Key LSB
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6.6.1
SPM Write Sequence
The SPM must always be written in blocks of 8 bytes. The sequence is described below:
1. Set the I2C in SPM mode by writing “01” to SpmCfg[5:4] and SPM write access by writing ‘0’ to SpmCfg[3].
2. Write the SPM base address to SpmBaseAddr (The base address needs to be a value modulo 8).
3. Write the eight consecutive bytes to I2C address 0, 1, 2, …7
4. Terminate by writing “000” to SpmCfg[5:3].
Figure 49 SPM write sequence
The complete SPM can be written by repeating 16 times the cycles shown in Figure 49 using base addresses
0x00, 0x08, 0x10,…0x70, 0x78.
Once the SPM write sequence is actually applied, the INTB pin will be asserted. The host clears the interrupt by
reading any I2C register. At the same time the bit GenStatMsb[6], indicating the SPM write is done, will be
cleared.
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6.6.2
SPM Read Sequence
The SPM must always be read in blocks of 8 bytes. The sequence is described below:
1. Set the I2C in SPM mode by writing “01” to SpmCfg[5:4] and SPM read access by writing ‘1’ to SpmCfg[3].
2. Write the SPM base address to SpmBaseAddr (The base address needs to be a value modulo 8).
3. Read the eight consecutive bytes from I2C address 0, 1, 2, …7
4. Terminate by writing “000” to SpmCfg[5:3].
Figure 50 SPM Read Sequence
The complete SPM can be read by repeating 16 times the cycles shown in Figure 50 using base addresses 0x00,
0x08, 0x10,…0x70, 0x78.
Once the SPM read sequence is actually applied, the INTB pin will be asserted. The host clears the interrupt by
reading any I2C register. At the same time the bit GenStatMsb[6], indicating the SPM write is done, will be
cleared.
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6.7
NVM burn
The content of the SPM can be copied permanently (burned) into the NVM to be used as the new default
parameters. The burning of the NVM can be done up to three times and must be done only when the SPM is
completely written with the desired data.
The number of times the NVM has been burned can be monitored by reading NvmCycle from the I2C register
GenStatLsb[7:5].
Figure 51 Simplified Diagram NvmCycle
Figure 51 shows the simplified diagram of the NvmCycle counter. The SX8662 is delivered with empty NVM and
NvmCycle set to zero. The SPM points to the QSM.
Each NVM burn will increase the NvmCycle. At the fourth NVM burn the SX8662 switches definitely to the QSM.
The burning of the SPM into the NVM is done by executing a special sequence of four I2C commands.
1. Write the data 0x62 to the I2C register I2CKeyMsb.
2. Write the data 0x9D to the I2C register I2CKeyLsb.
3. Write the data 0xA5 to the I2C register I2CSpmBaseAddr.
4. Write the data 0x5A to the I2C register I2CSpmBaseAddr.
Terminate the I2C write by a STOP.
Terminate the I2C write by a STOP.
Terminate the I2C write by a STOP.
Terminate the I2C write by a STOP.
This is illustrated in Figure 52.
1)
S
SA
0
A
0xAC
A
0x62
A
P
2)
S
SA
0
A
0xAD
A
0x9D
A
P
3)
S
SA
0
A
0x0E
A
0xA5
A
P
4)
S
SA
0
A
0x0E
A
0x5A
A
P
S
SA
A
P
: Start condition
: Slave address
: Slave acknowledge
: Stop condition
From master to slave
From slave to master
Figure 52: NVM burn procedure
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7 APPLICATION INFORMATION
A typical application schematic is shown in figure below.
buzzer
SX8662
cap2
analog sensor
interface
clock
generation
RC
PWM LED
controller
gpio6
cap4
cap9
gnd
gpio5
cap5
power management
gpio4
cap7
cap6
cap6
micro processor
GPIO controller
cap7
gpio3
gpio2
cap8
RAM
NVM
ROM
I2C
36 Matrix LEDs
cap3
cap11
gpio7
vdig
gnd
vana
cap1
cap10
cap8
cap3
cap2
cap1
cap0
36 Capacitive Matrix Buttons
resetb
cap0
gpio1
cap5
gpio0
cap9
bottom plate
sda
scl
intb
vdd
cp
cn
cap10
cap11
cap4
HOST
Figure 53 Typical Application
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8 REFERENCES
[1] Capacitive Touch Sensing Layout guidelines on www.semtech.com
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SX8662
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9 PACKAGING INFORMATION
9.1
Package Outline Drawing
SX8662 is assembled in a MLPQ-W32 package as shown in figure below
Figure 54 Package Outline Drawing
9.2
Land Pattern
The land pattern of MLPQ-W32 package, 5 mm x 5 mm is shown in figure below.
Figure 55 Land Pattern
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© Semtech 2011
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Contact Information
Semtech Corporation
Advanced Communications and Sensing Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
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