CAT25C01, CAT25C02, CAT25C04 1K/2K/4K SPI Serial CMOS EEPROM FEATURES DESCRIPTION ■ 10 MHz SPI compatible The CAT25C01/02/04 is a 1K/2K/4K Bit SPI Serial CMOS EEPROM internally organized as 128x8/256x8/ 512x8 bits. Catalyst’s advanced CMOS Technology substantially reduces device power requirements. The CAT25C01/02/04 features a 16-byte page write buffer. The device operates via the SPI bus serial interface and is enabled though a Chip Select (CS). In addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C01/ 02/04 is designed with software and hardware write protection features including Block Write protection. The device is available in 8-pin DIP, 8-pin SOIC and 8-pin TSSOP packages. ■ 1.8 to 5.5 volt operation ■ 16-byte page write buffer ■ Hardware and software protection ■ Block write protection – Protect 1/4, 1/2 or all of EEPROM array ■ Low power CMOS technology ■ SPI modes (0,0 & 1,1) ■ Industrial temperature range d e ■ 1,000,000 program/erase cycles ■ 100 year data retention ■ Self-timed write cycle ■ RoHS compliant “ ”&“ ” 8-pin PDIP, SOIC and TSSOP packages it n o PIN CONFIGURATION PDIP (L) SOIC (V) TSSOP (Y) i D c s CS 1 8 SO 2 7 WP 3 6 VSS 4 5 u n FUNCTIONAL SYMBOL VCC SO VCC SI HOLD CS SCK WP SI CAT25C01 CAT25C02 CAT25C04 SO HOLD SCK PIN FUNCTIONS Pin Name a P s t r Function VSS Serial Data Output SCK Serial Clock WP Write Protect VCC +1.8V to +5.5V Power Supply VSS Ground CS Chip Select SI Serial Data Input HOLD Suspends Serial Input © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1105, Rev. B CAT25C01, CAT25C02, CAT25C04 ABSOLUTE MAXIMUM RATINGS* Storage Temperature -65°C to +150°C Voltage on Any Pin with Respect to Ground(1) -0.5 V to +6.5 V * Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. RELIABILITY CHARACTERISTICS(2) s t r Symbol Parameter Min Units NEND(*) Endurance 1,000,000 Program/ Erase Cycles 100 Years TDR Data Retention (*) Page Mode, VCC = 5 V, 25°C D.C. OPERATING CHARACTERISTICS d e VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified. Symbol Parameter Test Conditions ICC Supply Current Read or Write at 5 MHz ISB Standby Current All I/O Pins at GND or VCC, CS = VCC IL I/O Pin Leakage VIL Input Low Voltage VIH Input High Voltage VOL1 Output Low Voltage VCC > 2.5 V, IOL = 3.0 mA 0.4 V VOL2 Output Low Voltage VCC > 1.8 V, IOL = 1.0 mA 0.2 V Max Units it n o c s u n Min a P Max Units 1 mA 2 µA 2 µA VCC x 0.3 V VCC x 0.7 VCC + 0.5 V Pin at GND or VCC -0.5 PIN IMPEDANCE CHARACTERISTICS i D TA = 25°C, f = 1 MHz, VCC = 5 V Symbol CIN (2) Parameter Conditions Min SDA I/O Pin Capacitance VIN = 0 V 8 pF CIN(2) Input Capacitance (other pins) VIN = 0 V 6 pF ZWPL WP Input Low Impedance VIN < 0.5 V 70 kΩ ILWPH WP Input High Leakage VIN > VCC x 0.7 2 µA 5 Note: (1) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. (2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. Doc. No. 1105, Rev. B 2 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C01, CAT25C02, CAT25C04 A.C. CHARACTERISTICS CAT25CXX-1.8 1.8V-5.5V SYMBOL PARAMETER Min. CAT25CXX 2.5V-5.5V Max. Min. Max. 4.5V-5.5V Min. Max. Test UNITS Conditions tSU Data Setup Time 50 20 20 ns tH Data Hold Time 50 20 20 ns tWH SCK High Time 250 75 40 ns tWL SCK Low Time 250 75 40 ns fSCK Clock Frequency DC tLZ HOLD to Output Low Z 50 tRI(1) Input Rise Time tFI(1) Input Fall Time tHD HOLD Setup Time 100 40 tCD HOLD Hold Time 100 40 tWC(4) Write Cycle Time tV Output Valid from Clock Low tHO Output Hold Time tDIS Output Disable Time tHZ HOLD to Output High Z tCS CS High Time tCSS CS Setup Time tCSH CS Hold Time tWPS WP Setup Time tWPH WP Hold Time i D Symbol tPUR tPUW DC 5 10 MHz 50 50 ns 2 2 2 µs 2 2 2 µs u n 0 250 it n o 500 500 150 40 40 5 250 0 DC d e 5 500 c s Power-Up Timing(1)(3) 1 150 100 150 75 a P ns s t r ns 5 ms CL = 50pF 40 ns (note 2) 0 ns 75 75 ns 50 50 ns 100 ns 100 100 ns 100 100 ns 50 50 ns 50 50 ns Parameter Max. Units Power-up to Read Operation 1 ms Power-up to Write Operation 1 ms NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) AC Test Conditions: Input Pulse Voltages: 0.3VCC to 0.7VCC Input rise and fall times: ≤10ns Input and output reference voltages: 0.5VCC Output load: current source IOL max/IOH max; CL=50pF (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. (4) tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle. © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 3 Doc. No. 1105, Rev. B CAT25C01, CAT25C02, CAT25C04 FUNCTIONAL DESCRIPTION PIN DESCRIPTION The CAT25C01/02/04 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT25C01/02/04 to interface directly with many of today’s popular microcontrollers. The CAT25C01/02/04 contains an 8-bit instruction register. (The instruction set and the operation codes are detailed in the instruction set table) SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses, and data to be written to the CAT25010/20/40. Input data is latched on the rising edge of the serial clock for SPI modes (0, 0 & 1, 1). SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the CAT25C01/02/04. During a read cycle, data is shifted out on the falling edge of the serial clock for SPI modes (0,0 & 1,1). After the device is selected with CS going low, the first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define the operation to be performed. Figure 1. Sychronous Data Timing VIH d e CS VIL tCSS VIH tWH SCK VIL tH tSU VIH it n o VALID IN SI VIL VOH SO HI-Z VOL Note: Dashed Line= mode (1, 1) – – – – – c s INSTRUCTION SET Instruction i D WREN WRDI RDSR WRSR READ WRITE u n tWL tRI tFI tV tHO a P s t r tCS tCSH tDIS HI-Z Opcode Operation 0000 0110 Enable Write Operations 0000 0100 Disable Write Operations 0000 0101 Read Status Register 0000 0001 Write Status Register 0000 X011(1) Read Data from Memory 0000 X010(1) Write Data to Memory Note: (1) X=0 for CAT25C01, CAT25C02. X=A8 for CAT25C04. Doc. No. 1105, Rev. B 4 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C01, CAT25C02, CAT25C04 When WP is tied low and the WPEN bit in the status register is set to “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit is set to 0. Figure 10 illustrates the WP timing sequence during a write operation. SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchronize the communication between the microcontroller and the CAT25C01/02/04. Opcodes, byte addresses, or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK for SPI modes (0,0 & 1,1) . CS CS: Chip Select CS is the Chip select pin. CS low enables the CAT25C01/ 02/04 and CS high disables the CAT25C01/02/04. CS high takes the SO output pin to high impedance and forces the devices into a Standby Mode (unless an internal write operation is underway) The CAT25C01/ 02/04 draws ZERO current in the Standby mode. A high to low transition on CS is required prior to any sequence being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle. HOLD HOLD: Hold WP WP: Write Protect WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. STATUS REGISTER 7 6 5 4 WPEN 1 1 1 it n o BLOCK PROTECTION BITS Status Register Bits BP1 BP0 0 0 0 1 c s 1 i D 1 0 1 s t r The HOLD pin is used to pause transmission to the CAT25C01/20/40 while in the middle of a serial sequence without having to re-transmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high directly to VCC or tied to VCC through a resistor. Figure 9 illustrates hold timing sequence. d e u n 3 BP1 a P 2 1 0 BP0 WEL RDY Array Address Protected Protection None CAT25C01: 60-7F CAT25C02: C0-FF CAT25C04: 180-1FF CAT25C01: 40-7F CAT25C02: 80-FF CAT25C04: 100-1FF CAT25C01: 00-7F CAT25C02: 00-FF CAT25C04: 000-1FF No Protection Quarter Array Protection Half Array Protection Full Array Protection WRITE PROTECT ENABLE OPERATION WPEN 0 WP X WEL 0 Protected Blocks Protected Unprotected Blocks Protected Status Register Protected 0 X 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected X High 0 Protected Protected Protected X High 1 Protected Writable Writable © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 5 Doc. No. 1105, Rev. B CAT25C01, CAT25C02, CAT25C04 to the status register, (including the block protect bits and the WPEN bit) and the block protected sections in the memory array when the chip is hardware write protected. Only the sections of the memory array that are not block protected can be written. Hardware write protection is disabled when either WP pin is high or the WPEN bit is zero. STATUS REGISTER The Status Register indicates the status of the device. The RDY (Ready) bit indicates whether the CAT25C01/ 02/04 is busy with a write operation. When set to 1 a write cycle is in progress and when set to 0 the device indicates it is ready. This bit is read only. The WEL (Write Enable) bit indicates the status of the write enable latch. When set to 1, the device is in a Write Enable state and when set to 0 the device is in a Write Disable state. The WEL bit can only be set by the WREN instruction and can be reset by the WRDI instruction. DEVICE OPERATION The BP0 and BP1 (Block Protect) bits indicate which blocks are currently protected. These bits are set by the user issuing the WRSR instruction. The user is allowed to protect quarter of the memory, half of the memory or the entire memory by setting these bits. Once protected, the user may only read from the protected portion of the array. These bits are non-volatile. d e it n o CS SCK c s SI i D SO 0 0 0 0 a P READ Sequence The part is selected by pulling CS low. The 8-bit read instruction is transmitted to the CAT25C01/02/04, followed by the 8-bit address for CAT25C01/02/04 (for the CAT25C04, bit 3 of the read data instruction contains address A8). The WPEN (Write Protect Enable) is an enable bit for the WP pin. The WP pin and WPEN bit in the status register control the programmable hardware write protect feature. Hardware write protection is enabled when WP is low and WPEN bit is set to high. The user cannot write Figure 2. WREN Instruction Timing s t r Write Enable and Disable The CAT25C01/02/04 contains a write enable latch. This latch must be set before any write operation. The device powers up in a write disable state when VCC is applied. WREN instruction will enable writes (set the latch) to the device. WRDI instruction will disable writes (reset the latch) to the device. Disabling writes will protect the device against inadvertent writes. u n 0 1 1 0 HIGH IMPEDANCE Note: Dashed Line = mode (1, 1) Figure 3. WRDI Instruction Timing CS SCK 0 SI 0 0 0 0 1 0 0 HIGH IMPEDANCE SO Note: Dashed Line = mode (1, 1) Doc. No. 1105, Rev. B 6 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C01, CAT25C02, CAT25C04 Write enable state by pulling the CS low and then clocking the WREN instruction into CAT25C01/02/04. The CS must be brought high after the WREN instruction to enable writes to the device. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Also, for a successful write operation the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block protection level. After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by pulling the CS high. To read the status register, RDSR instruction should be sent. The contents of the status register are shifted out on the SO line. The status register may be read at any time even during a write cycle. Read sequece is illustrated in Figure 4. Reading status register is illustrated in Figure 5. WRITE Sequence The CAT25C01/02/04 powers up in a Write Disable state. Prior to any write instructions, the WREN instruction must be sent to CAT25C01/02/04. The device goes into d e Figure 4. Read Instruction Timing CS 0 1 2 3 4 5 6 7 8 0 0 0 0 X* 0 1 1 A7 A6 A5 HIGH IMPEDANCE SO 11 12 13 BYTE ADDRESS OPCODE 0 u n 10 it n o SK SI 9 c s s t r Byte Write Once the device is in a Write Enable state, the user may proceed with a write sequence by setting the CS low, issuing a write instruction via the SI line, followed by the 8-bit address for CAT25C01/02/04 (for the 25C04, bit 3 of the read data instruction contains address A8). Programming will start after the CS is brought high. Figure 6 illustrates byte write sequence. A4 A3 A2 14 15 16 17 a P 18 19 20 21 22 A1 A0 DATA OUT D7 D6 D5 D4 D3 D2 D1 D0 MSB *Please check the instruction set table for address X=0 for 25010, 25020 ; X=A8 for 25040 i D Note: Dashed line = mode (1,1)---- Figure 5. RDSR Instruction Timing CS 0 1 2 3 4 5 6 7 1 0 1 8 9 10 11 7 6 5 4 12 13 14 2 1 SCK SI 0 OPCODE 0 0 0 0 DATA OUT SO HIGH IMPEDANCE 3 0 MSB Note: Dashed Line= mode (1, 1) – – – – – © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 7 Doc. No. 1105, Rev. B CAT25C01, CAT25C02, CAT25C04 During an internal write cycle, all commands will be ignored except the RDSR (Read Status Register) instruction. address will remain constant. The only restriction is that the X (X=16 for CAT25C01/02/04) bytes must reside on the same page. If the address counter reaches the end of the page and clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written. The CAT25C01/02/04 is automatically returned to the write disable state at the completion of the write cycle. Figure 8 illustrates the page write sequence. The Status Register can be read to determine if the write cycle is still in progress. If Bit 0 of the Status Register is set at 1, write cycle is in progress. If Bit 0 is set at 0, the device is ready for the next instruction. Page Write The CAT25C01/02/04 features page write capability. After the initial byte, the host may continue to write up to 16 bytes of data to the CAT25C01/02/04. After each byte of data received, lower order address bits are internally incremented by one; the high order bits of Figure 6. Write Instruction Timing d e CS 0 1 2 3 4 5 6 7 8 0 SI 0 0 0 it n o 1 A7 0 HIGH IMPEDANCE SO Note: Dashed Line= mode (1, 1) – – – – – *X=0 for 25010, 25020 ; X=A8 for 25040 c s Figure 7. WRSR Timing CS i D 0 SCK SI 0 SO 1 2 u n BYTE ADDRESS 0X* 0 3 4 5 6 DATA IN A0 D7 D6 D5 D4 D3 D2 D1 D0 7 8 9 10 11 1 7 6 5 4 OPCODE 0 0 0 0 a P 13 14 15 16 17 18 19 20 21 22 23 SK OPCODE s t r To write to the status register, the WRSR instruction should be sent. Only Bit 2, Bit 3 and Bit 7 of the status register can be written using the WRSR instruction. Figure 7 illustrates the sequence of writing to status register. 12 13 14 15 2 1 0 DATA IN 0 0 3 MSB HIGH IMPEDANCE Note: Dashed Line= mode (1, 1) – – – – – Doc. No. 1105, Rev. B 8 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C01, CAT25C02, CAT25C04 DESIGN CONSIDERATIONS ming is continued. On power up, SO is in a high impedance. If an invalid op code is received, no data will be shifted into the CAT25C01/02/04, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. The CAT25C01/02/04 powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued to perform any writes to the device after power up. Also,on power up CS should be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write, the CAT25C01/02/04 goes into a write disable mode. CS must be set high after the proper number of clock cycles to start an internal write cycle. Access to the array during an internal write cycle is ignored and program- When powering down, the supply should be taken down to 0V, so that the CAT25C01/02/04 will be reset when power is ramped back up. If this is not possible, then, following a brown-out episode, the CAT25C01/02/04 can be reset by refreshing the contents of the Status Register (See Application Note AN10). Figure 8. Page Write Instruction Timing CS 0 1 2 3 4 5 6 7 8 13 14 15 16-23 SI 0 0 0 0 0 X* DATA IN BYTE ADDRESS 0 1 0 A7 A0 Data Byte 1 u n HIGH IMPEDANCE SO Note: Dashed Line= mode (1, 1) – – – – – CS tCD SCK Data Byte 3 Data Byte N 0 7..1 *X=0 for CAT25C01, CAT25C02; X=A8 for CAT25C04 it n o Figure 9. HOLD Timing Data Byte 2 a P 16+(N-1)x8-1..16+(N-1)x8 16+Nx8-1 d e SK OPCODE 24-31 s t r tCD tHD c s HOLD i D SO tHD tHZ HIGH IMPEDANCE tLZ Note: Dashed Line= mode (1, 1) – – – – – Figure 10. WP Timing t WPS t WPH CS SCK WP WP Note: Dashed Line= mode (1, 1) – – – – – © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 9 Doc. No. 1105, Rev. B CAT25C01, CAT25C02, CAT25C04 8-LEAD 300 MIL WIDE PLASTIC DIP (L) E1 E D A2 A A1 e b2 b SYMBOL MIN A A1 A2 b b2 D D2 E E1 e eB L 0.120 0.015 0.115 0.014 0.045 0.355 0.300 0.300 0.240 it n o NOM i D c s 0.115 MAX 0.210 0.130 0.018 0.060 0.365 0.310 0.250 0.100 BSC 0.130 0.195 0.022 0.070 0.400 0.325 0.325 0.280 d e L u n 0.430 0.150 a P s t r eB 24C02_8-LEAD_DIP_(300P).eps Notes: 1. Complies with JEDEC Standard MS001. 2. All dimensions are in inches. 3. Dimensioning and tolerancing per ANSI Y14.5M-1982 Doc. No. 1105, Rev. B 10 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C01, CAT25C02, CAT25C04 8-LEAD 150 MIL WIDE SOIC (V) E1 E D d e A θ1 e A1 b it n o SYMBOL MIN A1 A2 b C D E E1 e f θ1 0.0040 0.0532 0.013 0.0075 0.1890 02284 0.149 c s i D 0.0099 0° NOM MAX 0.0098 0.0688 0.020 0.0098 0.1968 0.2440 0.1574 u n a P s t r C L 0.050 BSC 0.0196 8° 24C02_8-LEAD_SOIC.eps Notes: 1. Complies with JEDEC specification MS-012 dimensions. 2. All linear dimensions in millimeters. © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 11 Doc. No. 1105, Rev. B CAT25C01, CAT25C02, CAT25C04 8-LEAD TSSOP (Y) D 5 8 SEE DETAIL A s t r c E E1 E/2 d e 4 1 PIN #1 IDENT. θ1 A2 A it n o e A1 b SYMBOL MIN c s A A1 A2 b c D E E1 e L θ1 i D 0.05 0.80 0.19 0.09 2.90 6.30 4.30 0.50 0.00 NOM 0.90 3.00 6.4 4.40 0.65 BSC 0.60 u n L a P GAGE PLANE 0.25 SEATING PLANE SEE DETAIL A MAX 1.20 0.15 1.05 0.30 0.20 3.10 6.50 4.50 0.75 8.00 Notes: 1. All dimensions in millimeters. Doc. No. 1105, Rev. B 12 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice CAT25C01, CAT25C02, CAT25C04 ORDERING INFORMATION Prefix Device # Suffix 25C04 CAT Optional Company ID Product Number 25C04: 4K 25C02: 2K 25C01: 1K -1.8 I V Temperature Range I = Industrial (-40°C to +85°C) Package L: PDIP (Lead-free, Halogen-free, NiPdAu lead plating) V: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating) Y: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating) TE13 s t r Tape & Reel a P Operating Voltage Blank (VCC = 2.5V to 5.5V) 1.8 (VCC = 1.8V to 5.5V) d e Notes: (1) The device used in the above example is a CAT25C04VI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage, Tape & Reel) it n o u n c s i D © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 13 Doc. No. 1105, Rev. B CAT25C01, CAT25C02, CAT25C04 PACKAGE MARKING 8-Lead PDIP 8-Lead SOIC VV 25C04LI YYWWC VV 25C04VI YYWWC CSI 25C04L I YY WW C VV = Catalyst Semiconductor, Inc. = Device Code = Temperature Range = Production Year = Production Week = Product Revision = Voltage Range 1.8V - 5.5V = 18 2.5V - 5.5V = Blank it n o 8-Lead TSSOP YMCV 25Y04 Y M C 25Y04 I V CSI 25C04V I YY WW C VV d e u n a P s t r = Catalyst Semiconductor, Inc. = Device Code = Temperature Range = Production Year = Production Week = Product Revision = Voltage Range 1.8V - 5.5V = 18 2.5V - 5.5V = Blank c s = Production Year = Production Month = Die Revision = Device Code = Industrial Temperature Range = Voltage Range 1.8V - 5.5V = 8 2.5V - 5.5V = Blank i D Notes: (1) The circle on the package marking indicates the location of Pin 1. Doc. No. 1105, Rev. B 14 © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice REVISION HISTORY Date Rev. Reason 10/13/05 A Initial Issue u n d e a P s t r Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ MiniPot™ it n o Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. c s Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. i D Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 1105 B 12/23/05