MICROCHIP 25AA020AT-I/MC

25AA020A/25LC020A
2K SPI Bus Serial EEPROM
Device Selection Table
Part Number
VCC Range
Page Size
Temp. Ranges
Packages
25AA020A
1.8-5.5V
16 Bytes
I
P, MS, SN, ST, MC, OT
25LC020A
2.5-5.5V
16 Bytes
I, E
P, MS, SN, ST, MC, OT
Features:
Description:
• 10 MHz max. clock frequency
• Low-power CMOS technology:
- Max. Write Current: 5 mA at 5.5V, 10 MHz
- Read Current: 5 mA at 5.5V, 10 MHz
- Standby Current: 5 μA at 5.5V
• 256 x 8-bit organization
• Write Page mode (up to 16 bytes)
• Sequential Read
• Self-timed Erase and Write cycles (5 ms max.)
• Block Write protection:
- Protect none, 1/4, 1/2 or all of array
• Built-in Write protection:
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• High reliability:
- Endurance: 1,000,000 Erase/Write cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• Temperature ranges supported:
- Industrial (I):
-40°C to +85°C
- Automotive (E):
-40°C to +125°C
The Microchip Technology Inc. 25XX020A* is a 2 Kbit
Serial Electrically Erasable Programmable Read-Only
Memory (EEPROM). The memory is accessed via a
simple Serial Peripheral Interface™ (SPI) compatible
serial bus. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO)
lines. Access to the device is controlled through a Chip
Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts.
The 25XX020A is available in standard packages
including 8-lead PDIP and SOIC, and advanced
packages including 8-lead MSOP, 8-lead TSSOP and
rotated TSSOP, 8-lead 2x3 DFN, and 6-lead SOT-23.
Package Types (not to scale)
PDIP/SOIC
TSSOP/MSOP
(P, SN)
(ST, MS)
CS
SO
WP
VSS
8
7
6
5
1
2
3
4
VCC
HOLD
SCK
SI
CS
SO
1
2
8
7
VCC
HOLD
WP
3
6
SCK
VSS
4
5
SI
• Pb-Free packages available
Name
Function
Chip Select Input
SO
Serial Data Output
WP
Write-Protect
VSS
Ground
SI
Serial Data Input
SCK
Serial Clock Input
VCC
(MC)
(OT)
CS
HOLD
DFN
SOT-23
Pin Function Table
SCK
1
6
VSS
2
5
SI
3
4
8 VCC
CS
CS 1
SO 2
SO
WP 3
6 SCK
VSS 4
5 SI
VDD
7 HOLD
X-Rotated TSSOP
(X/ST)
HOLD
VCC
CS
SO
1
2
3
4
8
7
6
5
SCK
SI
VSS
WP
Hold Input
Supply Voltage
*25XX020A is used in this document as a generic part number for the
25AA020A and the 25LC020A.
© 2006 Microchip Technology Inc.
Preliminary
DS21833C-page 1
25AA020A/25LC020A
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias ...............................................................................................................-40°C to 125°C
ESD protection on all pins ..........................................................................................................................................4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
DC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
TA = -40°C to +85°C
TA = -40°C to +125°C
Industrial (I):
Automotive (E):
Min.
Max.
Units
D001
VIH1
High-level Input
Voltage
0.7 VCC
VCC +1
V
D002
VIL1
-0.3
0.3 VCC
V
D003
VIL2
Low-level Input
Voltage
D004
VOL
D005
VOL
D006
VCC = 1.8V to 5.5V
VCC = 2.5V to 5.5V
Test Conditions
VCC ≥ 2.7V (Note 1)
-0.3
0.2 VCC
V
VCC < 2.7V (Note 1)
Low-level Output
Voltage
—
0.4
V
IOL = 2.1 mA
—
0.2
V
IOL = 1.0 mA, VCC < 2.5V
VOH
High-level Output
Voltage
VCC -0.5
—
V
IOH = -400 μA
D007
ILI
Input Leakage
Current
—
±1
μA
CS = VCC, VIN = VSS TO VCC
D008
ILO
Output Leakage
Current
—
±1
μA
CS = VCC, VOUT = VSS TO VCC
D009
CINT
Internal Capacitance
(all inputs and
outputs)
—
7
pF
TA = 25°C, CLK = 1.0 MHz,
VCC = 5.0V (Note 1)
D010
ICC Read
—
5
mA
—
2.5
mA
VCC = 5.5V; FCLK = 10.0 MHz;
SO = Open
VCC = 2.5V; FCLK = 5.0 MHz;
SO = Open
—
—
5
3
mA
mA
VCC = 5.5V
VCC = 2.5V
—
5
μA
—
1
μA
CS = VCC = 5.5V, Inputs tied to VCC or
VSS, TA = +125°C
CS = VCC = 2.5V, Inputs tied to VCC or
VSS, TA = +85°C
Operating Current
D011
ICC Write
D012
ICCS
Standby Current
Note:
This parameter is periodically sampled and not 100% tested.
DS21833C-page 2
Preliminary
© 2006 Microchip Technology Inc.
25AA020A/25LC020A
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Param.
Sym.
No.
Characteristic
Industrial (I):
Automotive (E):
TA = -40°C to +85°C
TA = -40°C to +125°C
VCC = 1.8V to 5.5V
VCC = 2.5V to 5.5V
Min.
Max.
Units
Test Conditions
—
—
—
10
5
3
MHz
MHz
MHz
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
1
FCLK
Clock Frequency
2
TCSS
CS Setup Time
50
100
150
—
—
—
ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
3
TCSH
CS Hold Time
100
200
250
—
—
—
ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
4
TCSD
CS Disable Time
50
—
ns
—
5
Tsu
Data Setup Time
10
20
30
—
—
—
ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
6
THD
Data Hold Time
20
40
50
—
—
—
ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
7
TR
CLK Rise Time
—
2
μs
(Note 1)
8
TF
CLK Fall Time
—
2
μs
(Note 1)
9
THI
Clock High Time
0.05
0.1
0.15
1000
1000
1000
μs
μs
μs
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
10
TLO
Clock Low Time
0.05
0.1
0.15
1000
1000
1000
μs
μs
μs
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
11
TCLD
Clock Delay Time
50
—
ns
—
12
TCLE
Clock Enable Time
50
—
ns
—
13
TV
Output Valid from Clock
Low
—
—
—
50
100
160
ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
14
THO
Output Hold Time
0
—
ns
(Note 1)
15
TDIS
Output Disable Time
—
—
—
40
80
160
ns
ns
ns
4.5V ≤ VCC < 5.5V (Note 1)
2.5V ≤ VCC < 4.5V (Note 1)
1.8V ≤ VCC < 2.5V (Note 1)
16
THS
HOLD Setup Time
20
40
80
—
—
—
ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from our web site:
www.Microchip.com.
3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.
© 2006 Microchip Technology Inc.
Preliminary
DS21833C-page 3
25AA020A/25LC020A
TABLE 1-2:
AC CHARACTERISTICS (CONTINUED)
Param.
Sym.
No.
TA = -40°C to +85°C
TA = -40°C to +125°C
Industrial (I):
Automotive (E):
AC CHARACTERISTICS
Characteristic
Min.
Max.
Units
VCC = 1.8V to 5.5V
VCC = 2.5V to 5.5V
Test Conditions
17
THH
HOLD Hold Time
20
40
80
—
—
—
ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
18
THZ
HOLD Low to Output
High-Z
30
60
160
—
—
—
ns
ns
ns
4.5V ≤ VCC < 5.5V (Note 1)
2.5V ≤ VCC < 4.5V (Note 1)
1.8V ≤ VCC < 2.5V (Note 1)
19
THV
HOLD High to Output
Valid
30
60
160
—
—
—
ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ VCC < 4.5V
1.8V ≤ VCC < 2.5V
20
TWC
Internal Write Cycle Time
(byte or page)
—
5
ms
(Note 3)
21
—
Endurance
1M
—
E/W (NOTE 2)
Cycles
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from our web site:
www.Microchip.com.
3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.
TABLE 1-3:
AC TEST CONDITIONS
AC Waveform:
VLO = 0.2V
VHI
= VCC - 0.2V
VHI = 4.0V
—
(Note 1)
(Note 2)
CL = 100 pF
—
Timing Measurement Reference Level
Input
0.5 VCC
Output
0.5 VCC
Note 1: For VCC ≤ 4.0V
2: For VCC > 4.0V
DS21833C-page 4
Preliminary
© 2006 Microchip Technology Inc.
25AA020A/25LC020A
FIGURE 1-1:
HOLD TIMING
CS
17
16
17
16
SCK
18
SO
n+2
SI
n+2
n+1
19
high-impedance
n
n
5
don’t care
n+1
n-1
n
n
n-1
HOLD
FIGURE 1-2:
SERIAL INPUT TIMING
4
CS
2
12
11
7
8
Mode 1,1
3
SCK Mode 0,0
5
SI
6
MSB in
LSB in
high-impedance
SO
FIGURE 1-3:
SERIAL OUTPUT TIMING
CS
9
3
10
Mode 1,1
SCK
Mode 0,0
13
14
SO
MSB out
SI
© 2006 Microchip Technology Inc.
15
ISB out
don’t care
Preliminary
DS21833C-page 5
25AA020A/25LC020A
2.0
FUNCTIONAL DESCRIPTION
2.1
Principles of Operation
The 25XX020A is a 256-byte Serial EEPROM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller
families,
including
Microchip’s
PICmicro® microcontrollers. It may also interface with
microcontrollers that do not have a built-in SPI port by
using discrete I/O lines programmed properly in
software to match the SPI protocol.
The 25XX020A contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
After setting the write enable latch, the user may
proceed by driving CS low, issuing a WRITE instruction,
followed by the remainder of the address, and then the
data to be written. Up to 16 bytes of data can be sent to
the device before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page. Additionally, a page address begins with
XXXX 0000 and ends with XXXX 1111. If the internal
address counter reaches XXXX 1111 and clock signals
continue to be applied to the chip, the address counter
will roll back to the first address of the page and overwrite any data that previously existed in those
locations.
Note:
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSb first, LSb last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25XX020A in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
2.2
Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 25XX020A followed by an 8-bit address. See Figure 2-1 for more
details.
After the correct READ instruction and address are sent,
the data stored in the memory at the selected address
is shifted out on the SO pin. Data stored in the memory
at the next address can be read sequentially by
continuing to provide clock pulses to the slave. The
internal Address Pointer automatically increments to
the next higher address after each byte of data is
shifted out. When the highest address is reached
(FFh), the address counter rolls over to address 00h
allowing the read cycle to be continued indefinitely. The
read operation is terminated by raising the CS pin
(Figure 2-1).
2.3
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and, end at addresses that are
integer multiples of page size – 1. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is driven
high at any other time, the write operation will not be
completed. Refer to Figure 2-2 and Figure 2-3 for more
detailed illustrations on the byte write sequence and
the page write sequence respectively. While the write is
in progress, the STATUS register may be read to check
the status of the WIP, WEL, BP1 and BP0 bits
(Figure 2-6). Attempting to read a memory array
location will not be possible during a write cycle. Polling
the WIP bit in the STATUS register is recommended in
order to determine if a write cycle is in progress. When
the write cycle is completed, the write enable latch is
reset.
Write Sequence
Prior to any attempt to write data to the 25XX020A, the
write enable latch must be set by issuing the WREN
instruction (Figure 2-4). This is done by setting CS low
and then clocking out the proper instruction into the
25XX020A. After all eight bits of the instruction are
transmitted, CS must be driven high to set the write
enable latch. If the write operation is initiated immediately after the WREN instruction without CS driven high,
data will not be written to the array since the write
enable latch was not properly set.
DS21833C-page 6
Preliminary
© 2006 Microchip Technology Inc.
25AA020A/25LC020A
BLOCK DIAGRAM
STATUS
Register
HV Generator
Memory
Control
Logic
I/O Control
Logic
EEPROM
Array
X
Dec
Page Latches
SI
SO
Y Decoder
CS
SCK
Sense Amp.
R/W Control
HOLD
WP
VCC
VSS
TABLE 2-1:
INSTRUCTION SET
Instruction Name
Instruction Format
Description
READ
0000 x011
Read data from memory array beginning at selected address
WRITE
0000 x010
Write data to memory array beginning at selected address
WRDI
0000 x100
Reset the write enable latch (disable write operations)
WREN
0000 x110
Set the write enable latch (enable write operations)
RDSR
0000 x101
Read STATUS register
WRSR
0000 x001
Write STATUS register
x = don’t care
FIGURE 2-1:
READ SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
SI
0
0
0
0
0
Address byte
0
1
1 A7 A6 A5 A4 A3 A2 A1 A0
data out
high-impedance
7
SO
© 2006 Microchip Technology Inc.
Preliminary
6
5
4
3
2
1
0
DS21833C-page 7
25AA020A/25LC020A
FIGURE 2-2:
BYTE WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Twc
SCK
Instruction
SI
0
0
0
0
0
Address byte
0
data byte
0 A7 A6 A5 A4 A3 A2 A1 A0
1
7
6
5
4
3
2
1
0
high-impedance
SO
FIGURE 2-3:
PAGE WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Address byte
Instruction
SI
0
0
0
0
0
0 1
data byte 1
0 A7 A6 A5 A4 A3 A2 A1 A0 7
6
5
4
3
2
1
0
CS
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
data byte 2
SI
7
DS21833C-page 8
6
5
4
3
data byte 3
2
1
0
7
6
5
4
3
data byte n (16 max)
2
Preliminary
1
0
7
6
5
4
3
2
1
0
© 2006 Microchip Technology Inc.
25AA020A/25LC020A
2.4
Write Enable (WREN) and Write
Disable (WRDI)
The following is a list of conditions under which the
write enable latch will be reset:
•
•
•
•
•
The 25XX020A contains a write enable latch. See
Table 2-4 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
FIGURE 2-4:
Power-up
WRDI instruction successfully executed
WRSR instruction successfully executed
WRITE instruction successfully executed
WP pin is brought low
WRITE ENABLE SEQUENCE (WREN)
CS
0
1
2
3
4
5
6
7
SCK
0
SI
0
0
0
0
1
1
0
high-impedance
SO
FIGURE 2-5:
WRITE DISABLE SEQUENCE (WRDI)
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
0
high-impedance
SO
© 2006 Microchip Technology Inc.
Preliminary
DS21833C-page 9
25AA020A/25LC020A
2.5
Read Status Register Instruction
(RDSR)
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘1’, the latch allows writes to the array, when set to a
‘0’, the latch prohibits writes to the array. The state of
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 2-4 and Figure 2-5.
The Read Status Register instruction (RDSR) provides
access to the STATUS register. See Figure 2-6 for the
RDSR timing sequence. The STATUS register may be
read at any time, even during a write cycle. The
STATUS register is formatted as follows:
TABLE 2-2:
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction, which
is shown in Figure 2-7. These bits are nonvolatile and
are described in more detail in Table 2-3.
STATUS REGISTER
7
6 5 4
3
2
1
–
– – – W/R W/R
R
X
X X X BP1 BP0 WEL
W/R = writable/readable. R = read-only.
0
R
WIP
The Write-In-Process (WIP) bit indicates whether the
25XX020A is busy with a write operation. When set to
a ‘1’, a write is in progress, when set to a ‘0’, no write
is in progress. This bit is read-only.
FIGURE 2-6:
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
instruction
SI
0
0
0
0
0
1
0
1
data from STATUS register
high-impedance
SO
DS21833C-page 10
7
Preliminary
6
5
4
3
2
© 2006 Microchip Technology Inc.
25AA020A/25LC020A
2.6
TABLE 2-3:
Write Status Register Instruction
(WRSR)
The Write Status Register instruction (WRSR) allows
the user to write to the nonvolatile bits in the STATUS
register as shown in Table 2-2. See Figure 2-7 for the
WRSR timing sequence. Four levels of protection for
the array are selectable by writing to the appropriate
bits in the STATUS register. The user has the ability to
write-protect none, one, two, or all four of the
segments of the array as shown in Table 2-3.
FIGURE 2-7:
ARRAY PROTECTION
BP1
BP0
Array Addresses
Write-Protected
0
0
none
0
1
upper 1/4
(C0h-FFh)
1
0
upper 1/2
(80h-FFh)
1
1
all
(00h-FFh)
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
instruction
SI
0
0
0
0
data to STATUS register
0
0
0
1
7
6
5
4
3
2
high-impedance
SO
Note:
An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register
sequence.
© 2006 Microchip Technology Inc.
Preliminary
DS21833C-page 11
25AA020A/25LC020A
2.7
Data Protection
2.8
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write or STATUS register
write, the write enable latch is reset
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
TABLE 2-4:
Power-On State
The 25XX020A powers on in the following state:
• The device is in low-power Standby mode
(CS = 1)
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS is required to
enter active state
WRITE-PROTECT FUNCTIONALITY MATRIX
WP
(pin 3)
WEL
(SR bit 1)
Protected Blocks
Unprotected Blocks
STATUS Register
0 (low)
x
Protected
Protected
Protected
1 (high)
0
Protected
Protected
Protected
1 (high)
1
Protected
Writable
Writable
x = don’t care
DS21833C-page 12
Preliminary
© 2006 Microchip Technology Inc.
25AA020A/25LC020A
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
3.5
TABLE 3-1:
The SCK is used to synchronize the communication
between a master and the 25XX020A. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
PIN FUNCTION TABLE
PDIP, SOIC,
MSOP,
Name
TSSOP,
DFN
Rotated SOTTSSOP
23
Function
CS
1
3
5
Chip Select Input
SO
2
4
4
Serial Data Output
WP
3
5
—
Write-Protect Pin
VSS
4
6
2
Ground
SI
5
7
3
Serial Data Input
SCK
6
8
1
Serial Clock Input
HOLD
7
1
—
Hold Input
VCC
8
2
6
Supply Voltage
3.1
Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low to high transition on CS after a valid write
sequence initiates an internal write cycle. After powerup, a low level on CS is required prior to any sequence
being initiated.
3.2
3.6
Serial Clock (SCK)
Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25XX020A while in the middle of a serial sequence
without having to retransmit the entire sequence again.
It must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-tolow transition. The 25XX020A must remain selected
during this sequence. The SI, SCK and SO pins are in
a high-impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD must be brought
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
Serial Output (SO)
The SO pin is used to transfer data out of the
25XX020A. During a read cycle, data is shifted out on
this pin after the falling edge of the serial clock.
3.3
Write-Protect (WP)
The WP pin is a hardware write-protect input pin.
When it is low, all writes to the array or STATUS register are disabled, but any other operations function
normally. When WP is high, all functions, including
nonvolatile writes operate normally. At any time, when
WP is low, the write enable reset latch will be reset
and programming will be inhibited. However, if a write
cycle is already in progress, WP going low will not
change or disable the write cycle. See Table 2-4 for
the Write-Protect Functionality Matrix.
3.4
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
© 2006 Microchip Technology Inc.
Preliminary
DS21833C-page 13
25AA020A/25LC020A
4.0
PACKAGING INFORMATION
4.1
Package Marking Information
Example:
8-Lead PDIP
XXXXXXXX
T/XXXNNN
YYWW
25AA020A
I/P e3 1L7
0627
8-Lead SOIC
Example:
XXXXXXXT
XXXXYYWW
NNN
25AA02AI
SN e3 0627
1L7
8-Lead TSSOP
Example:
XXXX
TYWW
NNN
5A2A
I627
1L7
8-Lead MSOP (150 mil)
Example:
5L2AI
6271L7
XXXXXT
YWWNNN
1st Line Marking Codes
Part Number
TSSOP
Standard Rotated
25AA020A
25LC020A
5A2A
A2AX
5A2AT
SOT-23
I Temp. E Temp.
—
22NN
5L2A
L2AX
5L2AT
25NN
Note: T = Temperature grade (I, E)
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS21833C-page 14
MSOP
26NN
DFN
I Temp.
E Temp.
—
411
414
415
NN = Alphanumeric traceability code
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Preliminary
© 2006 Microchip Technology Inc.
25AA020A/25LC020A
Package Marking Information (continued)
8-Lead 2X3 DFN
Example:
XXX
YWW
NN
411
627
L7
6-Lead SOT-23
Example:
XXNN
© 2006 Microchip Technology Inc.
22L7
Preliminary
DS21833C-page 15
25AA020A/25LC020A
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
p
eB
B
Units
Dimension Limits
n
p
INCHES*
NOM
8
.100
.155
.130
MAX
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MAX
Number of Pins
Pitch
Top to Seating Plane
A
.140
.170
4.32
Molded Package Thickness
A2
.115
.145
3.68
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.313
.325
8.26
Molded Package Width
E1
.240
.250
.260
6.60
Overall Length
D
.360
.373
.385
9.78
Tip to Seating Plane
L
.125
.130
.135
3.43
c
Lead Thickness
.008
.012
.015
0.38
Upper Lead Width
B1
.045
.058
.070
1.78
Lower Lead Width
B
.014
.018
.022
0.56
Overall Row Spacing
§
eB
.310
.370
.430
10.92
α
Mold Draft Angle Top
5
10
15
15
β
Mold Draft Angle Bottom
5
10
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS21833C-page 16
MIN
Preliminary
MIN
© 2006 Microchip Technology Inc.
25AA020A/25LC020A
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
INCHES*
NOM
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
.009
.017
12
12
Preliminary
MAX
MILLIMETERS
NOM
8
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
6.02
3.71
3.91
4.80
4.90
0.25
0.38
0.48
0.62
0
4
0.20
0.23
0.33
0.42
0
12
0
12
MAX
Number of Pins
Pitch
Overall Height
A
.053
.069
1.75
Molded Package Thickness
A2
.052
.061
1.55
Standoff
§
.004
.010
0.25
A1
Overall Width
E
.228
.244
6.20
Molded Package Width
E1
.146
.157
3.99
Overall Length
D
.189
.197
5.00
Chamfer Distance
h
.010
.020
0.51
Foot Length
L
.019
.030
0.76
φ
Foot Angle
0
8
8
c
Lead Thickness
.008
.010
0.25
Lead Width
B
.013
.020
0.51
α
Mold Draft Angle Top
0
15
15
β
Mold Draft Angle Bottom
0
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
© 2006 Microchip Technology Inc.
MIN
A1
MIN
DS21833C-page 17
25AA020A/25LC020A
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
β
φ
L
Units
Dimension Limits
A2
A1
MILLIMETERS*
INCHES
MIN
NOM
MAX
MIN
NOM
MAX
Pitch
n
p
Overall Height
A
.039
.041
.043
1.00
1.05
1.10
Molded Package Thickness
A2
.033
.035
.037
0.85
0.90
0.95
Number of Pins
8
8
.026
0.65
Standoff
A1
.002
.004
.006
0.05
0.10
0.15
Overall Width
E
.246
.251
.256
6.25
6.38
6.50
Molded Package Width
E1
.169
.173
.177
4.30
4.40
4.50
Molded Package Length
D
.114
.118
.122
2.90
3.00
3.10
Foot Length
L
φ
.020
.024
.028
0.50
0.60
0.70
Foot Angle
Lead Thickness
c
.004
.006
.008
0.09
0.15
0.20
Lead Width
B
α
.007
.010
.012
0.19
0.25
0.30
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0°
4°
8°
0°
4°
8°
0°
5°
10°
0°
5°
10°
0°
5°
10°
0°
5°
10°
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
DS21833C-page 18
Revised 07-21-05
Preliminary
© 2006 Microchip Technology Inc.
25AA020A/25LC020A
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
B
n
1
α
c
φ
L
F
A2
A
A1
β
Units
Dimension Limits
INCHES
MILLIMETERS*
NOM
MIN
MAX
NOM
MIN
MAX
Number of Pins
n
Pitch
p
Overall Height
A
-
-
.043
-
-
1.10
Molded Package Thickness
A2
.030
.033
.037
0.75
0.85
0.95
Standoff
A1
.000
-
.006
0.00
-
0.15
Overall Width
E
.193 BSC
4.90 BSC
Molded Package Width
E1
.118 BSC
3.00 BSC
Overall Length
D
.118 BSC
Foot Length
L
0.60
0.80
Footprint (Reference)
Foot Angle
F
φ
Lead Thickness
c
.003
.006
.009
0.08
-
0.23
Lead Width
B
.009
.012
.016
0.22
-
0.40
Mold Draft Angle Top
α
5°
-
15°
5°
-
15°
Mold Draft Angle Bottom
β
5°
-
15°
5°
-
15°
8
8
.026 BSC
.016
0.65 BSC
3.00 BSC
.024
.031
0.40
.037 REF
0°
0.95 REF
-
8°
0°
-
8°
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tolerance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent: MO-187
Drawing No. C04-111
© 2006 Microchip Technology Inc.
Preliminary
Revised 07-21-05
DS21833C-page 19
25AA020A/25LC020A
8-Lead Plastic Dual-Flat, No-Lead Package (MC) 2x3x0.9 mm Body (DFN) – Saw Singulated
b
D
p
n
L
K
E2
E
EXPOSED
METAL
PAD
(NOTE 2)
PIN 1
ID INDEX
AREA
(NOTE 1)
2
DETAIL
ALTERNATE
CONTACT
CONFIGURATION
TOP VIEW
A1
MIN
n
MILLIMETERS*
INCHES
Units
Number of Pins
BOTTOM VIEW
EXPOSED
TIE BAR
(NOTE 3)
A
A3
Dimension Limits
1
D2
MAX
NOM
MIN
MAX
NOM
8
8
Pitch
e
Overall Height
A
.031
.035
.039
0.80
0.90
1.00
Standoff
A1
.000
.001
.002
0.00
0.02
0.05
Contact Thickness
A3
.008 REF.
0.20 REF.
Overall Length
D
.079 BSC
2.00 BSC
Overall Width
E
.118 BSC
0.50 BSC
.020 BSC
3.00 BSC
Exposed Pad Length
D2
.051
–
.069
1.30**
–
Exposed Pad Width
E2
.059
–
.075
1.50**
–
L
.012
Contact Length §
Contact-to-Exposed Pad
Contact Width
§
K
.008
b
.008
.016
.020
–
.010
–
.012
* Controlling Parameter
** Not within JEDEC parameters
§ Significant Characteristic
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Exposed pad may vary according to die attach paddle size.
3. Package may have one or more exposed tie bars at ends.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tolerance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent MO-229 VCED-2
DWG No. C04-123
DS21833C-page 20
Preliminary
0.30
0.20
0.20
0.40
–
0.25
1.75
1.90
0.50
–
0.30
Revised 09-12-05
© 2006 Microchip Technology Inc.
25AA020A/25LC020A
6-Lead Plastic Small Outline Transistor (CH or OT) (SOT-23)
E
E1
B
p1
n
D
1
α
c
φ
β
A
A1
L
INCHES*
Units
Dimension Limits
A2
MIN
MILLIMETERS
NOM
MAX
MIN
NOM
MAX
Pitch
n
p
.038 BSC
Outside lead pitch
p1
.075 BSC
Overall Height
A
.035
.046
.057
0.90
1.18
Molded Package Thickness
A2
.035
.043
.051
0.90
1.10
1.30
Standoff
A1
.000
.003
.006
0.00
0.08
0.15
Overall Width
E
.102
.110
.118
2.60
2.80
3.00
Molded Package Width
E1
.059
.064
.069
1.50
1.63
1.75
Overall Length
D
.110
.116
.122
2.80
2.95
3.10
Foot Length
L
φ
.014
.022
0.35
Foot Angle
Lead Thickness
c
.004
Lead Width
B
α
.014
Mold Draft Angle Top
Mold Draft Angle Bottom
β
Number of Pins
6
0.95 BSC
1.90 BSC
.018
0
6
5
.006
.017
10
1.45
0.45
0
0.55
5
.008
0.09
0.15
.020
0.35
0.43
10
0.20
0.50
0
5
10
0
5
10
0
5
10
0
5
10
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
JEITA (formerly EIAJ) equivalent: SC-74A
Revised 09-12-05
Drawing No. C04-120
© 2006 Microchip Technology Inc.
Preliminary
DS21833C-page 21
25AA020A/25LC020A
APPENDIX A:
REVISION HISTORY
Revision B
Corrections to Section 1.0, Electrical Characteristics.
Revision C
Added Packages SOT-23, DFN and X-rotated TSSOP;
Revised AC Char., Params. 9, 10; Revised Package
Legend.
DS21833C-page 22
Preliminary
© 2006 Microchip Technology Inc.
25AA020A/25LC020A
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
© 2006 Microchip Technology Inc.
Preliminary
DS21833C-page 21
25AA020A/25LC020A
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
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RE:
Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
Device: 25AA020A/25LC020A
N
Literature Number: DS21833C
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21833C-page 22
Preliminary
© 2006 Microchip Technology Inc.
25AA020A/25LC020A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
Device
Tape & Reel
–
X
Temperature
/XX
Package
Examples:
a)
b)
Device:
25AA020A
25LC020A
2k-Bit, 1.8V, 16 Byte Page, SPI Serial EEPROM
2k-Bit, 2.5V, 16 Byte Page, SPI Serial EEPROM
c)
Tape & Reel:
Blank
T
=
=
Standard packaging
Tape & Reel
d)
Temperature
Range:
I
E
=
=
-40°C to+85°C
-40°C to+125°C
e)
Package:
MS
P
SN
ST
MC
OT
=
=
=
=
=
=
Plastic MSOP (Micro Small Outline), 8-lead
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (150 mil body), 8-lead
TSSOP, 8-lead
2x3 DFN, 8-lead
SOT-23, 6-lead (Tape and Reel only)
25AA020A-I/MS = 2k-bit, 16-byte page, 1.8V
Serial EEPROM, Industrial temp., MSOP
package
25AA020AT-I/SN = 2k-bit, 16-byte page, 1.8V
Serial EEPROM, Industrial temp., Tape & Reel,
SOIC package
25LC020AT-I/SN = 2k-bit, 16-byte page, 2.5V
Serial EEPROM, Industrial temp., Tape & Reel,
SOIC package
25LC020AT-I/ST = 2k-bit, 16-byte page, 2.5V
Serial EEPROM, Industrial temp., Tape & Reel,
TSSOP package
25LC020AT-E/SN = 2k-bit, 16-byte page, 2.5V
serial EEPROM, Extended temp., Tape & Reel,
SOIC Package
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
© 2006 Microchip Technology Inc.
Preliminary
DS21833C-page 23
25AA020A/25LC020A
NOTES:
DS21833C-page 24
Preliminary
© 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip devices in life support and/or safety
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all damages, claims, suits, or expenses resulting from such
use. No licenses are conveyed, implicitly or otherwise, under
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Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Linear Active Thermistor,
MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,
PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,
PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and Zena are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2006 Microchip Technology Inc.
Preliminary
DS21833C-page 25
WORLDWIDE SALES AND SERVICE
AMERICAS
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10/31/05
DS21833C-page 26
Preliminary
© 2006 Microchip Technology Inc.