STMICROELECTRONICS PSD4235F1V-B-12MI

PSD4235G2
Flash In-System Programmable (ISP) Peripherals
For 16-bit MCUs (5V Supply)
PRELIMINARY DATA
FEATURES SUMMARY
PSD provides an integrated solution to 16-bit MCU
based applications that includes configurable
memories, PLD logic and I/O:
■ Dual Bank Flash Memories
■
Programmable power management
■
High Endurance:
– 100,000 Erase/Write Cycles of Flash Memory
– 1,000 EraseWrite Cycles of PLD
– 4 Mbit of Primary Flash Memory (8 uniform
sectors, 32K x 16)
– 15 Year Data Retention
– 256 Kbit Secondary Flash Memory with 4
sectors
■
– Concurrent operation: read from one memory
while erasing and writing the other
■
■
64 Kbit SRAM (Battery Backed)
■
PLD with macrocells
Single Supply Voltage
– 5V ±10%
Memory Speed
– 70ns Flash memory and SRAM access time
Figure 1. Packages
– Over 3000 Gates of PLD: CPLD and DPLD
– CPLD with 16 Output Macrocells (OMCs) and
24 Input Macrocells (IMCs)
– DPLD – user defined internal chip select decoding
■
Seven l/O Ports with 52 I/O pins
– 52 individually configurable I/O port pins that
can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function l/Os
– l/O ports may be configured as open-drain
outputs
■
TQFP80 (U)
In-System Programming (ISP) with JTAG
– Built-in JTAG compliant serial port allows fullchip In-System Programmability
– Efficient manufacturing allow easy product
testing and programming
– Use low cost FlashLINK cable with PC
■
Page Register
– Internal page register that can be used to expand the microcontroller address space by a
factor of 256
December 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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PSD4235G2
TABLE OF CONTENTS
Summary Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
In-System Programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
In-Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PSDsoft Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSD Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
MCU Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ISP via JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
In-System Programming (ISP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
In-Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Development System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PSD Register Description and Address Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Detailed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reading Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Erasing Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Flash Memory Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Memory Select Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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PSD4235G2
Memory ID Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Decode PLD (DPLD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
MCU Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Ports A, B and C – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Port D – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Port E – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Port F – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Port G – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PLD Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Power On Reset, Warm Reset and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Programming In-Circuit using the JTAG Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
AC/DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table. CPLD Combinatorial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table. CPLD Macrocell Synchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table. CPLD Macrocell Asynchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table. Input Macrocell Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table. Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table. Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table. Port F Peripheral Data Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table. Port F Peripheral Data Mode Write Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table. Reset (Reset)Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table. VSTBYON Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table. Program, Write and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table. ISC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table. Power-down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
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PSD4235G2
Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table. TQFP80 - 80 lead Plastic Quad Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table. Pin Assignments – TQFP80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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PSD4235G2
SUMMARY DESCRIPTION
The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability
(ISP) to Flash memory and programmable logic.
The result is a simple and flexible solution for embedded designs. PSD devices combine many of
the peripheral functions found in MCU based applications.
PSD devices integrate an optimized Macrocell logic architecture. The Macrocell was created to address the unique requirements of embedded
system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication
between the MCU and other supporting devices.
Figure 2. Logic Diagram
VCC
8
PA0-PA7
8
PB0-PB7
3
8
CNTL0CNTL2
Table 1. Pin Names
PC0-PC7
4
PA0-PA7
Port-A
PB0-PB7
Port-B
PC0-PC7
Port-C
PD0-PD3
Port-D
PE0-PE7
Port-E
PF0-PF7
Port-F
PG0-PG7
Port-G
AD0-AD15
Address/Data
CNTL0-CNTL2
Control
RESET
Reset
VCC
Supply Voltage
VSS
Ground
PD0-PD3
PSD4xxxGx
8
16
PE0-PE7
AD0-AD15
The PSD family offers two methods to program the
PSD Flash memory while the PSD is soldered to
the circuit board: In-System Programming (ISP)
via JTAG, and In-Application Programming (IAP).
In-System Programming (ISP) via JTAG
An IEEE 1149.1 compliant JTAG In-System Programming (ISP) interface is included on the PSD
enabling the entire device (Flash memories, PLD,
configuration) to be rapidly programmed while soldered to the circuit board. This requires no MCU
participation, which means the PSD can be programmed anytime, even when completely blank.
The innovative JTAG interface to Flash memories
is an industry first, solving key problems faced by
designers and manufacturing houses, such as:
8
PF0-PF7
RESET
8
PG0-PG7
VSS
AI04916
First time programming. How do I get firmware
into the Flash memory the very first time? JTAG is
the answer. Program the blank PSD with no MCU
involvement.
Inventory build-up of pre-programmed devices. How do I maintain an accurate count of preprogrammed Flash memory and PLD devices
based on customer demand? How many and what
version? JTAG is the answer. Build your hardware
with blank PSDs soldered directly to the board and
then custom program just before they are shipped
to the customer. No more labels on chips, and no
more wasted inventory.
Expensive sockets. How do I eliminate the need
for expensive and unreliable sockets? JTAG is the
answer. Solder the PSD directly to the circuit
board. Program first time and subsequent times
with JTAG. No need to handle devices and bend
the fragile leads.
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PSD4235G2
61 PB0
62 PB1
63 PB2
64 PB3
65 PB4
66 PB5
67 PB6
69 VCC
68 PB7
70 GND
71 PE0
72 PE1
73 PE2
74 PE3
75 PE4
76 PE5
77 PE6
78 PE7
79 PD0
80 PD1
Figure 3. TQFP Connections
42 PC1
AD15 20
41 PC0
CNTL2 40
43 PC2
AD14 19
RESET 39
44 PC3
AD13 18
PF7 38
45 PC4
AD12 17
PF6 37
46 PC5
AD11 16
PF5 36
47 PC6
AD10 15
PF4 35
48 PC7
AD9 14
PF3 34
AD8 13
PF2 33
49 GND
PF1 32
50 GND
AD7 12
PF0 31
51 PA0
AD6 11
GND 30
52 PA1
AD5 10
PG7 28
53 PA2
VCC 9
VCC 29
54 PA3
GND 8
PG6 27
55 PA4
AD4 7
PG5 26
56 PA5
AD3 6
PG4 25
57 PA6
AD2 5
PG3 24
58 PA7
AD1 4
PG2 23
59 CNTL0
AD0 3
PG1 22
60 CNTL1
PD3 2
PG0 21
PD2 1
AI04943
In-Application Programming (IAP)
Two independent Flash memory arrays are included so that the MCU can execute code from one
while erasing and programming the other. Robust
product firmware updates in the filed are possible
over any communication channel (CAN, Ethernet,
UART, J1850, etc) using this unique architecture.
Designers are relieved of these problems:
Simultaneous read and write to Flash memory. How can the MCU program the same memory
from which it executing code? It cannot. The PSD
allows the MCU to operate the two Flash memory
blocks concurrently, reading code from one while
erasing and programming the other during IAP.
Complex memory mapping. How can I map
these two memories efficiently? A programmable
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Decode PLD (DPLD) is embedded in the PSD.
The concurrent PSD memories can be mapped
anywhere in MCU address space, segment by
segment with extermely high address resolution.
As an option, the secondary Flash memory can be
swapped out of the system memory map when
IAP is complete. A built-in page register breaks the
MCU address limit.
Separate Program and Data space. How can I
write to Flash memory while it resides in Program
space during field firmware updates? My
80C51XA will not allow it. The PSD provides
means to reclassify Flash memory as Data space
during IAP, then back to Program space when
complete.
PG0 – PG7
CLKIN
PORT
G
PROG.
PORT
PORT
F
PROG.
PORT
ADIO
PORT
PROG.
MCU BUS
INTRF.
CLKIN
82
8
CSIOP
GLOBAL
CONFIG. &
SECURITY
CLKIN
PLD, CONFIGURATION
& FLASH MEMORY
LOADER
JTAG
SERIAL
CHANNEL
PORT A ,B & C
24 INPUT MACROCELLS
PORT A & B
16 OUTPUT MACROCELLS
8 EXT CS TO PORT C or F
PORT F
64 KBIT BATTERY
BACKUP SRAM
256 KBIT SECONDARY
FLASH MEMORY
(BOOT OR DATA)
4 SECTORS
16 SECTORS
4 MBIT PRIMARY
FLASH MEMORY
RUNTIME CONTROL
AND I/O REGISTERS
PERIP I/O MODE SELECTS
SRAM SELECT
SECTOR
SELECTS
FLASH ISP CPLD
(CPLD)
FLASH DECODE
PLD (DPLD)
SECTOR
SELECTS
EMBEDDED
ALGORITHM
MACROCELL FEEDBACK OR PORT INPUT
82
PAGE
REGISTER
PORT
E
PROG.
PORT
PORT
D
PROG.
PORT
PORT
C
PROG.
PORT
PORT
B
PROG.
PORT
PORT
A
PROG.
PORT
POWER
MANGMT
UNIT
PE0 – PE7
PD0 – PD3
PC0 – PC7
PB0 – PB7
PA0 – PA7
VSTDBY
(PE6 )
PSDsoft Express
PSDsoft Express, a software development tool
from ST, guides you through the design process
step-by-step making it possible to complete an
embedded MCU design capable of ISP/IAP in just
hours. Select your MCU and PSDsoft Express
takes you through the remainder of the design with
point and click entry, covering PSD selection, pin
PF0 – PF7
AD0 – AD15
CNTL0,
CNTL1,
CNTL2
PLD
INPUT
BUS
ADDRESS/DATA/CONTROL BUS
PSD4235G2
definitions, programmable logic inputs and outpus,
MCU memory map definition, ANSI-C code generation for your MCU, and merging your MCU firmware with the PSD design. When complete, two
different device programmers are supported directly from PSDsoft Express: FlashLINK (JTAG)
and PSDpro.
Figure 4. PSD Block Diagram
Note: Additional address lines can be brought in to the device via Port A, B, C, D or F.
AI04990
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PSD4235G2
PSD ARCHITECTURAL OVERVIEW
PSD devices contain several major functional
blocks. Figure 4 shows the architecture of the PSD
device family. The functions of each block are described briefly in the following sections. Many of
the blocks perform multiple functions and are user
configurable.
Memory
Each of the memory blocks is briefly discussed in
the following paragraphs. A more detailed discussion can be found in the section entitled “Memory
Blocks“ on page 20.
The 4 Mbit primary Flash memory is the main
memory of the PSD. It is divided into 8 equallysized sectors that are individually selectable.
The 256 Kbit secondary Flash memory is divided
into 4 equally-sized sectors. Each sector is individually selectable.
The 64 Kbit SRAM is intended for use as a
scratch-pad memory or as an extension to the
MCU SRAM. If an external battery is connected to
the PSD’s Voltage Stand-by (VSTBY, PE6) signal,
data is retained in the event of power failure.
Each memory block can be located in a different
address space as defined by the user. The access
times for all memory types includes the address
latching and DPLD decoding time.
PLDs
The device contains two PLD blocks, the Decode
PLD (DPLD) and the Complex PLD (CPLD), as
shown in Table 2, each optimized for a different
function. The functional partitioning of the PLDs
reduces power consumption, optimizes cost/performance, and eases design entry.
The DPLD is used to decode addresses and to
generate Sector Select signals for the PSD internal memory and registers. The DPLD has combinatorial outputs, while the CPLD can implement
more general user-defined logic functions. The
CPLD has 16 Output Macrocells (OMC) and 8
combinatorial outputs. The PSD also has 24 Input
Macrocells (IMC) that can be configured as inputs
to the PLDs. The PLDs receive their inputs from
the PLD Input Bus and are differentiated by their
output destinations, number of product terms, and
Macrocells.
The PLDs consume minimal power. The speed
and power consumption of the PLD is controlled
by the Turbo bit in PMMR0 and other bits in
PMMR2. These registers are set by the MCU at
run-time. There is a slight penalty to PLD propagation time when not in the Turbo mode.
I/O Ports
The PSD has 52 I/O pins divided among seven
ports (Port A, B, C, D, E, F and G). Each I/O pin
can be individually configured for different func8/89
tions. Ports can be configured as standard MCU I/
O ports, PLD I/O, or latched address outputs for
MCUs using multiplexed address/data buses
The JTAG pins can be enabled on Port E for InSystem Programming (ISP).
Table 2. PLD I/O
Inputs
Outputs
Product
Terms
Decode PLD (DPLD)
82
17
43
Complex PLD (CPLD)
82
24
150
Name
MCU Bus Interface
The PSD easily interfaces easily with most 16-bit
MCUs, either with multiplexed or non-multiplexed
address/data buses. The device is configured to
respond to the MCU’s control pins, which are also
used as inputs to the PLDs.
ISP via JTAG Port
In-System Programming (ISP) can be performed
through the JTAG signals on Port E. This serial interface allows complete programming of the entire
PSD device. A blank device can be completely
programmed. The JTAG signals (TMS, TCK,
TSTAT, TERR, TDI, TDO) can be multiplexed with
other functions on Port E. Table 3 indicates the
JTAG pin assignments.
In-System Programming (ISP)
Using the JTAG signals on Port E, the entire PSD
device (memory, logic, configuration) can be programmed or erased without the use of the MCU.
Table 3. JTAG SIgnals on Port E
Port E Pins
JTAG Signal
PE0
TMS
PE1
TCK
PE2
TDI
PE3
TDO
PE4
TSTAT
PE5
TERR
In-Application Programming (IAP)
The primary Flash memory can also be programmed, or re-programmed, in-system by the
MCU executing the programming algorithms out of
the secondary Flash memory, or SRAM. The secondary Flash memory can be programmed the
same way by executing out of the primary Flash
memory. Table 4 indicates which programming
methods can program different functional blocks
of the PSD.
PSD4235G2
Page Register
The 8-bit Page Register expands the address
range of the MCU by up to 256 times. The paged
address can be used as part of the address space
to access external memory and peripherals, or internal memory and I/O. The Page Register can
also be used to change the address mapping of
the Flash memory blocks into different memory
spaces for IAP.
Power Management Unit (PMU)
The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consumption.
The PSD also has some bits that are configured at
run-time by the MCU to reduce power consumption of the CPLD. The Turbo bit in PMMR0 can be
reset to 0 and the CPLD latches its outputs and
goes to Stand-by mode until the next transition on
its inputs.
Additionally, bits in PMMR2 can be set by the
MCU to block signals from entering the CPLD to
reduce power consumption. See the section entitled “Power Management” on page 59 for more details.
Table 4. Methods of Programming Different Functional Blocks of the PSD
Functional Block
JTAG-ISP
Device Programmer
IAP
Primary Flash Memory
Yes
Yes
Yes
Secondary Flash memory
Yes
Yes
Yes
PLD Array (DPLD and CPLD)
Yes
Yes
No
PSD Configuration
Yes
Yes
No
9/89
PSD4235G2
DEVELOPMENT SYSTEM
The PSD family is supported by PSDsoft Express,
a Windows-based software development tool
(Windows-95, Windows-98, Windows-2000, Windows-NT). A PSD design is quickly and easily produced in a point and click environment. The
designer does not need to enter Hardware Description Language (HDL) equations, unless desired, to define PSD pin functions and memory
map information. The general design flow is
shown in Figure 5. PSDsoft Express is available
from our web site (the address is given on the back
page of this data sheet) or other distribution channels.
PSDsoft Express directly supports two low cost
device programmers form ST: PSDpro and
FlashLINK (JTAG). Both of these programmers
may be purchased through your local distributor/
representative, or directly from our web site using
a credit card. The PSD is also supported by thid
party device programmers. See our web site for
the current list.
Figure 5. PSDsoft Express Development Tool
Choose MCU and PSD
Automatically configures MCU
bus interface and other
PSD attributes
Define PSD Pin and
Node Functions
Point and click definition of
PSD pin functions, internal nodes,
and MCU system memory map
Define General Purpose
Logic in CPLD
C Code Generation
Point and click definition of combinatorial and registered logic in CPLD.
Access HDL is available if needed
GENERATE C CODE
SPECIFIC TO PSD
FUNCTIONS
Merge MCU Firmware
with PSD Configuration
A composite object file is created
containing MCU firmware and
PSD configuration
MCU FIRMWARE
HEX OR S-RECORD
FORMAT
USER'S CHOICE OF
MICROCONTROLLER
COMPILER/LINKER
*.OBJ FILE
PSD Programmer
PSDPro, or
FlashLINK (JTAG)
*.OBJ FILE
AVAILABLE
FOR 3rd PARTY
PROGRAMMERS
(CONVENTIONAL or
JTAG-ISC)
AI04919
10/89
PSD4235G2
PIN DESCRIPTION
Table 5 describes the signal names and signal
functions of the PSD. Those that have multiple
names or functions are defined using PSDsoft Express.
Table 5. Pin Description (for the TQFP package)
Pin Name
ADIO0ADIO7
ADIO8ADIO15
CNTL0
CNTL1
Pin
3-7
10-12
13-20
59
60
Type
Description
I/O
This is the lower Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
1. If your MCU has a multiplexed address/data bus where the data is multiplexed with
the lower address bits, connect AD0-AD7 to this port.
2. If your MCU does not have a multiplexed address/data bus, connect A0-A7 to this
port.
3. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this
port.
ALE or AS latches the address. The PSD drives data out only if the read signal is active
and one of the PSD functional blocks has been selected. The addresses on this port
are passed to the PLDs.
I/O
This is the upper Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
1. If your MCU has a multiplexed address/data bus where the data is multiplexed with
the upper address bits, connect A8-A15 to this port.
2. If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this
port.
3. If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this
port.
ALE or AS latches the address. The PSD drives data out only if the read signal is active
and one of the PSD functional blocks has been selected. The addresses on this port
are passed to the PLDs.
I
The following control signals can be connected to this pin, based on your MCU:
1. WR – active Low, Write Strobe input.
2. R_W – active High, read/active Low write input.
3. WRL – active Low, Write to Low-byte.
This pin is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equations.
I
The following control signals can be connected to this pin, based on your MCU:
1. RD – active Low, Read Strobe input.
2. E – E clock input.
3. DS – active Low, Data Strobe input.
4. LDS – active Low, Strobe for low data byte.
This pin is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equations.
CNTL2
40
I
Read or other Control input pin, with multiple configurations. Depending on the MCU
interface selected, this pin can be:
1. PSEN – Program Select Enable, active Low in code fetch bus cycle (80C51XA
mode).
2. BHE – High-byte enable, 16-bit data bus.
3. UDS – active Low, Strobe for high data byte, 16-bit data bus mode.
4. SIZ0 – Byte enable input.
5. LSTRB – Low Strobe input.
This pin is also connected to the PLDs.
Reset
39
I
Active Low input. Resets I/O Ports, PLD Macrocells and some of the Configuration
Registers and JTAG registers. Must be Low at Power-up. Reset also aborts any Flash
memory Program or Erase cycle that is currently in progress.
11/89
PSD4235G2
Pin Name
PA0-PA7
PB0-PB7
PC0-PC7
PD0
PD1
PD2
PD3
PE0
PE1
PE2
12/89
Pin
Type
Description
51-58
I/O
CMOS
or
Open
Drain
These pins make up Port A. These port pins are configurable and can have the
following functions:
1. MCU I/O – standard output or input port.
2. CPLD Macrocell (McellA0-McellA7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above).
61-68
I/O
CMOS
or
Open
Drain
These pins make up Port B. These port pins are configurable and can have the
following functions:
1. MCU I/O – standard output or input port.
2. CPLD Macrocell (McellB0-McellB7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above).
41-48
I/O
CMOS
or
Slew
Rate
These pins make up Port C. These port pins are configurable and can have the
following functions:
1. MCU I/O – standard output or input port.
2. External Chip Select (ECS0-ECS7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address
A16 and above).
79
I/O
CMOS
or
Open
Drain
PD0 pin of Port D. This port pin can be configured to have the following functions:
1. ALE/AS input – latches address on ADIO0-ADIO15.
2. AS input – latches address on ADIO0-ADIO15 on the rising edge.
3. MCU I/O – standard output or input port.
4. Transparent PLD input (can also be PLD input for address A16 and above).
80
I/O
CMOS
or
Open
Drain
PD1 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Transparent PLD input (can also be PLD input for address A16 and above).
3. CLKIN – clock input to the CPLD Macrocells, the APD Unit’s Power-down counter,
and the CPLD AND Array.
1
I/O
CMOS
or
Open
Drain
PD2 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Transparent PLD input (can also be PLD input for address A16 and above).
3. PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and
I/O. When High, the PSD memory blocks are disabled to conserve power. The falling
edge of this signal can be used to get the device out of Power-down mode.
2
I/O
CMOS
or
Open
Drain
PD3 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Transparent PLD input (can also be PLD input for address A16 and above).
3. WRH – for 16-bit data bus, write to high byte, active low.
71
I/O
CMOS
or
Open
Drain
PE0 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TMS Input for the JTAG Serial Interface.
72
I/O
CMOS
or
Open
Drain
PE1 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TCK Input for the JTAG Serial Interface.
73
I/O
CMOS
or
Open
Drain
PE2 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TDI input for the JTAG Serial Interface.
PSD4235G2
Pin Name
Pin
Type
Description
74
I/O
CMOS
or
Open
Drain
PE3 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TDO output for the JTAG Serial Interface.
75
I/O
CMOS
or
Open
Drain
PE4 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TSTAT output for the JTAG Serial Interface.
4. Ready/Busy output for parallel In-System Programming (ISP).
76
I/O
CMOS
or
Open
Drain
PE5 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TERR active Low output for the JTAG Serial Interface.
77
I/O
CMOS
or
Open
Drain
PE6 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. VSTBY – SRAM stand-by voltage input for SRAM battery backup.
78
I/O
CMOS
or
Open
Drain
PE7 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. Battery-on Indicator (VBATON). Goes High when power is being drawn from the
external battery.
31-38
I/O
CMOS
or
Open
Drain
These pins make up Port F. These port pins are configurable and can have the following
functions:
1. MCU I/O – standard output or input port.
2. External Chip Select (ECS0-ECS7) outputs, or inputs to CPLD.
3. Latched address outputs.
4. Address A1-A3 inputs in 80C51XA mode (PF0 is grounded)
5. Data bus port (D0-D7) in a non-multiplexed bus configuration.
6. Peripheral I/O mode.
7. MCU reset mode.
PG0-PG7
21-28
I/O
CMOS
or
Open
Drain
These pins make up Port G. These port pins are configurable and can have the
following functions:
1. MCU I/O – standard output or input port.
2. Latched address outputs.
3. Data bus port (D8-D15) in a non-multiplexed bus configuration.
4. MCU reset mode.
VCC
9, 29,
69
Supply Voltage
GND
8, 30,
49,
50, 70
Ground pins
PE3
PE4
PE5
PE6
PE7
PF0-PF7
13/89
PSD4235G2
PSD REGISTER DESCRIPTION AND ADDRESS OFFSETS
Table 6 shows the offset addresses to the PSD
Table 6 provides brief descriptions of the registers
registers relative to the CSIOP base address. The
in CSIOP space. The following sections give a
CSIOP space is the 256 bytes of address that is almore detailed description.
located by the user to the internal PSD registers.
Table 6. Register Address Offset
Register Name
Data In
Port Port Port Port Port Port Port
Other1
A
B
C
D
E
F
G
00
01
10
11
Control
Description
30
40
41
Reads Port pin as input, MCU I/O input mode
32
42
43
Selects mode between MCU I/O or Address
Out
Data Out
04
05
14
15
34
44
45
Stores data for output to Port pins, MCU I/O
output mode
Direction
06
07
16
17
36
46
47
Configures Port pin as input or output
Drive Select
08
09
18
19
38
48
49
Configures Port pins as either CMOS or
Open Drain on some pins, while selecting
high slew rate on other pins.
Input Macrocell
0A
0B
Enable Out
0C
0D
Output
Macrocells A
20
Output
Macrocells B
Mask
Macrocells A
Mask
Macrocells B
1A
1C
Reads Input Macrocells
Reads the status of the output enable to the
I/O Port driver
4C
Read – reads output of Macrocells A
Write – loads Macrocell Flip-flops
Read – reads output of Macrocells B
Write – loads Macrocell Flip-flops
21
22
Blocks writing to the Output Macrocells A
23
Blocks writing to the Output Macrocells B
Flash Memory
Protection
C0
Read only – Primary Flash Sector Protection
Flash Boot
Protection
C2
Read only – PSD Security and Secondary
Flash memory Sector Protection
JTAG Enable
C7
Enables JTAG Port
PMMR0
B0
Power Management Register 0
PMMR2
B4
Power Management Register 2
Page
E0
Page Register
VM
E2
Places PSD memory areas in Program and/
or Data space on an individual basis.
Memory_ID0
F0
Read only – SRAM and Primary memory
size
Memory_ID1
F1
Read only – Secondary memory type and
size
Note: 1. Other registers that are not part of the I/O ports.
14/89
PSD4235G2
REGISTER BIT DEFINITION
All the registers of the PSD are included here, for
reference. Detailed descriptions of these registers
can be found in the following sections.
Table 7. Data-In Registers – Ports A, B, C, D, E, F, G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Note: Bit Definitions (Read-only registers):
Read Port pin status when Port is in MCU I/O input mode.
Table 8. Data-Out Registers – Ports A, B, C, D, E, F, G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Note: Bit Definitions:
Latched data for output to Port pin when pin is configured in MCU I/O output mode.
Table 9. Direction Registers – Ports A, B, C, D, E, F, G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Note: Bit Definitions:
Port pin 0 = Port pin is configured in Input mode (default).
Port pin 1 = Port pin is configured in Output mode.
Table 10. Control Registers – Ports E, F, G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Note: Bit Definitions:
Port pin 0 = Port pin is configured in MCU I/O mode (default).
Port pin 1 = Port pin is configured in Latched Address Out mode.
Table 11. Drive Registers – Ports A, B, D, E, G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Note: Bit Definitions:
Port pin 0 = Port pin is configured for CMOS Output driver (default).
Port pin 1 = Port pin is configured for Open Drain output driver.
Table 12. Drive Registers – Ports C, F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Note: Bit Definitions:
Port pin 0 = Port pin is configured for CMOS Output driver (default).
Port pin 1 = Port pin is configured in Slew Rate mode.
15/89
PSD4235G2
Table 13. Enable-Out Registers – Ports A, B, C, F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Note: Bit Definitions (Read-only registers):
Port pin 0 = Port pin is in tri-state driver (default).
Port pin 1 = Port pin is enabled.
Table 14. Input Macrocells – Ports A, B, C
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IMcell 7
IMcell 6
IMcell 5
IMcell 4
IMcell 3
IMcell 2
IMcell 1
IMcell 0
Note: Bit Definitions (Read-only registers):
Read Input Macrocell (IMC7-IMC0) status on Ports A, B and C.
Table 15. Output Macrocells A Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcella 7
Mcella 6
Mcella 5
Mcella 4
Mcella 3
Mcella 2
Mcella 1
Mcella 0
Note: Bit Definitions:
Write Register: Load MCellA7-MCellA0 with 0 or 1.
Read Register: Read MCellA7-MCellA0 output status.
Table 16. Output Macrocells B Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcellb 7
Mcellb 6
Mcellb 5
Mcellb 4
Mcellb 3
Mcellb 2
Mcellb 1
Mcellb 0
Note: Bit Definitions:
Write Register: Load MCellB7-MCellB0 with 0 or 1.
Read Register: Read MCellB7-MCellB0 output status.
Table 17. Mask Macrocells A Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcella 7
Mcella 6
Mcella 5
Mcella 4
Mcella 3
Mcella 2
Mcella 1
Mcella 0
Note: Bit Definitions:
McellA_Prot 0 = Allow MCellA flip-flop to be loaded by MCU (default).
McellA_Prot 1 = Prevent MCellA flip-flop from being loaded by MCU.
Table 18. Mask Macrocells B Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcellb 7
Mcellb 6
Mcellb 5
Mcellb 4
Mcellb 3
Mcellb 2
Mcellb 1
Mcellb 0
Note: Bit Definitions:
McellB_Prot 0 = Allow MCellB flip-flop to be loaded by MCU (default).
McellB_Prot 1 = Prevent MCellB flip-flop from being loaded by MCU.
Table 19. Flash Memory Protection Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec7_Prot
Sec6_Prot
Sec5_Prot
Sec4_Prot
Sec3_Prot
Sec2_Prot
Sec1_Prot
Sec0_Prot
Note: Bit Definitions (Read-only register):
Sec_Prot 1 = Primary Flash memory Sector is write protected.
Sec_Prot 0 = Primary Flash memory Sector is not write protected.
16/89
PSD4235G2
Table 20. Flash Boot Protection Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Security_Bit
not used
not used
not used
Sec3_Prot
Sec2_Prot
Sec1_Prot
Sec0_Prot
Note: Bit Definitions:
Sec_Prot 1 = Secondary Flash memory Sector is write protected.
Sec_Prot 0 = Secondary Flash memory Sector is not write protected.
Security_Bit 0 = Security Bit in device has not been set.
Security_Bit 1 = Security Bit in device has been set.
Table 21. JTAG Enable Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
not used
not used
not used
not used
not used
not used
JTAGEnable
Note: Bit Definitions:
JTAGEnable 1 = JTAG Port is enabled.
JTAGEnable 0 = JTAG Port is disabled.
Table 22. Page Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PGR 7
PGR 6
PGR 5
PGR 4
PGR 3
PGR 2
PGR 1
PGR 0
Note: Bit Definitions:
Configure Page input to PLD. Default is PGR7-PGR0=0.
17/89
PSD4235G2
Table 23. PMMR0 Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to 0)
not used
(set to 0)
PLD
MCells CLK
PLD
Array CLK
PLD
Turbo
not used
(set to 0)
APD
Enable
not used
(set to 0)
Note: The bits of this register are cleared to zero following Power-up. Subsequent Reset (Reset) pulses do not clear the registers.
Note: Bit Definitions:
APD Enable
0 = Automatic Power-down (APD) is disabled.
1 = Automatic Power-down (APD) is enabled.
PLD Turbo
0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
PLD Array CLK 0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off.
1 = CLKIN to the PLD AND array is disconnected, saving power.
PLD MCells CLK 0 = CLKIN to the PLD Macrocells is connected.
1 = CLKIN to the PLD Macrocells is disconnected, saving power.
Table 24. PMMR2 Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to 0)
PLD
Array WRH
PLD
Array ALE
PLD Array
CNTL2
PLD Array
CNTL1
PLD Array
CNTL0
not used
(set to 0)
PLD
Array Addr
Note: For Bit 4, Bit 3, Bit 2: See Table 34 for the signals that are blocked on pins CNTL0-CNTL2.
Note: Bit Definitions:
PLD Array Addr 0 = Address A7-A0 are connected to the PLD array.
1 = Address A7-A0 are blocked from the PLD array, saving power.
(Note: in XA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4)
PLD Array CNTL2 0 = CNTL2 input to the PLD AND array is connected.
1 = CNTL2 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL1 0 = CNTL1 input to the PLD AND array is connected.
1 = CNTL1 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL0 0 = CNTL0 input to the PLD AND array is connected.
1 = CNTL0 input to the PLD AND array is disconnected, saving power.
PLD Array ALE 0 = ALE input to the PLD AND array is connected.
1 = ALE input to the PLD AND array is disconnected, saving power.
PLD Array WRH 0 = WRH/DBE input to the PLD AND array is connected.
1 = WRH/DBE input to the PLD AND array is disconnected, saving power.
Table 25. VM Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Peripheral
mode
not used
(set to 0)
not used
(set to 0)
FL_data
Boot_data
FL_code
Boot_code
SR_code
Note: On reset, Bit1-Bit4 are loaded to configurations that are selected by the user in PSDsoft Express. Bit0 and Bit7 are always cleared on
reset. Bit0-Bit4 are active only when the device is configured in Philips 80C51XA mode.
Note: Bit Definitions:
SR_code
0 = PSEN cannot access SRAM in 80C51XA modes.
1 = PSEN can access SRAM in 80C51XA modes.
Boot_code
0 = PSEN cannot access Secondary NVM in 80C51XA modes.
1 = PSEN can access Secondary NVM in 80C51XA modes.
FL_code
0 = PSEN cannot access Primary Flash memory in 80C51XA modes.
1 = PSEN can access Primary Flash memory in 80C51XA modes.
Boot_data
0 = RD cannot access Secondary NVM in 80C51XA modes.
1 = RD can access Secondary NVM in 80C51XA modes.
FL_data
0 = RD cannot access Primary Flash memory in 80C51XA modes.
1 = RD can access Primary Flash memory in 80C51XA modes.
Peripheral mode 0 = Peripheral mode of Port F is disabled.
1 = Peripheral mode of Port F is enabled.
18/89
PSD4235G2
Table 26. Memory_ID0 Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
S_size 3
S_size 2
S_size 1
S_size 0
F_size 3
F_size 2
F_size 1
F_size 0
Note: Bit Definitions:
F_size[3:0]
S_size[3:0]
0h = There is no Primary Flash memory
1h = Primary Flash memory size is 256 Kbit
2h = Primary Flash memory size is 512 Kbit
3h = Primary Flash memory size is 1 Mbit
4h = Primary Flash memory size is 2 Mbit
5h = Primary Flash memory size is 4 Mbit
6h = Primary Flash memory size is 8 Mbit
0h = There is no SRAM
1h = SRAM size is 16 Kbit
2h = SRAM size is 32 Kbit
3h = SRAM size is 64 Kbit
4h = SRAM size is 128 Kbit
5h = SRAM size is 256 Kbit
Table 27. Memory_ID1 Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to 0)
not used
(set to 0)
B_type 1
B_type 0
B_size 3
B_size 2
B_size 1
B_size 0
Note: Bit Definitions:
B_size[3:0]
B_type[1:0]
0h = There is no Secondary NVM
1h = Secondary NVM size is 128 Kbit
2h = Secondary NVM size is 256 Kbit
3h = Secondary NVM size is 512 Kbit
0h = Secondary NVM is Flash memory
1h = Secondary NVM is EEPROM
19/89
PSD4235G2
DETAILED OPERATION
As shown in Figure 4, the PSD consists of six major types of functional blocks:
■ Memory Blocks
■
PLD Blocks
■
MCU Bus Interface
■
I/O Ports
■
Power Management Unit (PMU)
■
JTAG-ISP Interface
The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.
Memory Blocks
The PSD has the following memory blocks:
– Primary Flash memory
– Secondary Flash memory
– SRAM
The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are userdefined in PSDsoft Express.
Table 28 sumamarizes the sizes and organisations of the memory blocks.
Table 28. Memory Block Size and Organization
Primary Flash Memory
Secondary Flash Memory
SRAM
Sector
Number
Sector Size
(x16)
Sector Select
Signal
Sector Size
(x16)
Sector Select
Signal
SRAM Size
(x16)
SRAM Select
Signal
0
32K
FS0
4K
CSBOOT0
4K
RS0
1
32K
FS1
4K
CSBOOT1
2
32K
FS2
4K
CSBOOT2
3
32K
FS3
4K
CSBOOT3
4
32K
FS4
5
32K
FS5
6
32K
FS6
7
32K
FS7
Totals
512KByte
8 Sectors
32KByte
4 Sectors
20/89
8KByte
PSD4235G2
Primary Flash Memory and Secondary Flash
memory Description. The primary Flash memory is divided evenly into 8 sectors. The secondary
Flash memory is divided evenly into 4 sectors.
Each sector of either memory block can be separately protected from Program and Erase cycles.
Flash memory may be erased on a sector-by-sector basis, and programmed word-by-word. Flash
sector erasure may be suspended while data is
read from other sectors of the block and then resumed after reading.
During a Program or Erase cycle in Flash memory,
the status can be output on the Ready/Busy pin
(PE4). This pin is set up using PSDsoft Express.
Memory Block Select Signals. The DPLD generates the Select signals for all the internal memory blocks (see the section entitled “PLDs”, on page
31). Each of the sectors of the primary Flash memory has a Select signal (FS0-FS7) which can contain up to three product terms. Each of the sectors
of the secondary Flash memory has a Select signal (CSBOOT0-CSBOOT3) which can contain up
to three product terms. Having three product terms
for each Select signal allows a given sector to be
mapped in different areas of system memory.
When using a MCU with separate Program and
Data space (80C51XA), these flexible Select signals allow dynamic re-mapping of sectors from
one memory space to the other before and after
IAP. The SRAM block has a single Select signal
(RS0).
Ready/Busy (PE4). This signal can be used to
output the Ready/Busy status of the PSD. The out-
put is a 0 (Busy) when a Flash memory block is being written to, or when a Flash memory block is
being erased. The output is a 1 (Ready) when no
Write or Erase cycle is in progress.
Memory Operation. The primary Flash memory
and secondary Flash memory are addressed
through the MCU Bus Interface. The MCU can access these memories in one of two ways:
■ The MCU can execute a typical bus Write or
Read operation just as it would if accessing a
RAM or ROM device using standard bus cycles.
■
The MCU can execute a specific instruction that
consists of several Write and Read operations.
This involves writing specific data patterns to
special addresses within the Flash memory to
invoke an embedded algorithm. These
instructions are summarized in Table 29.
Typically, the MCU can read Flash memory using
Read operations, just as it would read a ROM device. However, Flash memory can only be erased
and programmed using specific instructions. For
example, the MCU cannot write a single byte directly to Flash memory as one would write a byte
to RAM. To program a word into Flash memory,
the MCU must execute a Program instruction, then
test the status of the Programming event. This status test is achieved by a Read operation or polling
Ready/Busy (PE4).
Flash memory can also be read by using special
instructions to retrieve particular Flash device information (sector protect status and ID).
21/89
PSD4235G2
Table 29. Instructions
FS0-FS7 or
CSBOOT0CSBOOT3
Cycle 1
Read5
1
“Read”
RD @ RA
Read Main Flash ID6
1
Read Sector
Protection6,8,13
Instruction14
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
AAh@
XAAAh
55h@
X554h
90h@
XAAAh
Read ID
@ XX02h
1
AAh@
XAAAh
55h@
X554h
90h@
XAAAh
Read 00h
or 01h @
XX04h
Program a Flash
Word13
1
AAh@
XAAAh
55h@
X554h
A0h@
XAAAh
PD@ PA
Flash Sector Erase7,13
1
AAh@
XAAAh
55h@
X554h
80h@
XAAAh
AAh@
XAAAh
55h@
X554h
30h@
SA
30h7@
next SA
Flash Bulk Erase13
1
AAh@
XAAAh
55h@
X554h
80h@
XAAAh
AAh@
XAAAh
55h@
X554h
10h@
XAAAh
Suspend Sector
Erase11
1
B0h@
XXXXh
Resume Sector
Erase12
1
30h@
XXXXh
Reset6
1
F0h@
XXXXh
Unlock Bypass
1
AAh@
XAAAh
55h@
X554h
20h@
XAAAh
Unlock Bypass
Program9
1
A0h@
XXXXh
PD@ PA
Unlock Bypass
Reset10
1
90h@
XXXXh
00h@
XXXXh
Note: 1. All bus cycles are write bus cycles, except the ones with the “Read” label
2. All values are in hexadecimal:
X = Don’t Care. Addresses of the form XXXXh, in this table, must be even addresses
RA = Address of the memory location to be read
RD = Data read from location RA during the Read cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0).
PA is an even address for PSD in word programming mode.
PD = Data word to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR , CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to be
erased, or verified, must be Active (High).
3. Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active High, and are defined in PSDsoft Express.
4. Only address bits A11-A0 are used in instruction decoding.
5. No Unlock or instruction cycles are required when the device is in the Read mode
6. The Reset instruction is required to return to the Read mode after reading the Flash ID, or after reading the Sector Protection Status,
or if the Error Flag (DQ5/DQ13) bit goes High.
7. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80 µs.
8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
(A1,A0)=(1,0)
9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass
mode.
11. The system may perform Read and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status
when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle.
12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is
intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status
of the primary Flash memory.
14. All write bus cycles in an instruction are byte write to an even address (XA4Ah or X554h). A Flash memory Program bus cycle writes
a word to an even address.
22/89
PSD4235G2
Instructions
An instruction consists of a sequence of specific
operations. Each received byte is sequentially decoded by the PSD and not executed as a standard
Write operation. The instruction is executed when
the correct number of bytes are properly received
and the time between two consecutive bytes is
shorter than the time-out period. Some instructions are structured to include Read operations after the initial Write operations.
The instruction must be followed exactly. Any invalid combination of instruction bytes or time-out
between two consecutive bytes while addressing
Flash memory resets the device logic into Read
mode (Flash memory is read like a ROM device).
The PSD supports the instructions summarized in
Table 29:
■ Erase memory by chip or sector
■
Suspend or resume sector erase
■
Program a Word
■
Reset to Read mode
■
Read primary Flash Identifier value
■
Read Sector Protection Status
■
Bypass
These instructions are detailed in Table 29. For efficient decoding of the instructions, the first two
bytes of an instruction are the coded cycles and
are followed by an instruction byte or confirmation
byte. The coded cycles consist of writing the data
AAh to address XAAAh during the first cycle and
data 55h to address X554h during the second cycle (unless the Bypass instruction feature is used,
as described later). Address signals A15-A12 are
Don’t Care during the instruction Write cycles.
However, the appropriate Sector Select signal
(FS0-FS7, or CSBOOT0-CSBOOT3) must be selected.
The primary and secondary Flash memories have
the same instruction set (except for Read Primary
Flash Identifier). The Sector Select signals determine which Flash memory is to receive and execute the instruction. The primary Flash memory is
selected if any one of its Sector Select signals
(FS0-FS7) is High, and the secondary Flash memory is selected if any one of its Sector Select signals (CSBOOT0-CSBOOT3) is High.
Power-up Condition. The PSD internal logic is
reset upon Power-up to the Read mode. Sector
Select (FS0-FS7 and CSBOOT0-CSBOOT3)
must be held Low, and Write Strobe (WR/WRL,
CNTL0) High, during Power-up for maximum security of the data contents and to remove the possibility of data being written on the first edge of
Write Strobe (WR/WRL, CNTL0). Any Write cycle
initiation is locked when VCC is below V LKO.
Reading Flash Memory
Under typical conditions, the MCU may read the
primary Flash memory, or secondary Flash memory, using Read operations just as it would a ROM
or RAM device. Alternately, the MCU may use
Read operations to obtain status information
about a Program or Erase cycle that is currently in
progress. Lastly, the MCU may use instructions to
read special data from these memory blocks. The
following sections describe these Read functions.
Read Memory Contents. Primary Flash memory
and secondary Flash memory are placed in the
Read mode after Power-up, chip reset, or a Reset
Flash instruction (see Table 29). The MCU can
read the memory contents of the primary Flash
memory, or the secondary Flash memory by using
Read operations any time the Read operation is
not part of an instruction.
Read Primary Flash Identifier. The
primary
Flash memory identifier is read with an instruction
composed of 4 operations: 3 specific Write operations and a Read operation (see Table 29). The
identifier for the primary Flash memory is E8h. The
secondary Flash memory does not support this instruction.
Read Memory Sector Protection Status. The
Flash memory Sector Protection Status is read
with an instruction composed of four operations:
three specific Write operations and a Read operation (see Table 29). The Read operation produces
01h if the Flash memory sector is protected, or 00h
if the sector is not protected.
The sector protection status for all NVM blocks
(primary Flash memory, or secondary Flash memory) can be read by the MCU accessing the Flash
Protection and Flash Boot Protection registers in
PSD I/O space. See the section entitled “Flash
Memory Sector Protect”, on page 27, for register
definitions.
Reading the Erase/Program Status Bits. The
PSD provides several status bits to be used by the
MCU to confirm the completion of an Erase or Program cycle of Flash memory. These status bits
minimize the time that the MCU spends performing these tasks and are defined in Table 30. The
status byte resides in an even location, and can be
read as many times as needed. Also note that
DQ15-DQ8 is an even byte for Motorola MCUs
with a 16-bit data bus.
For Flash memory, the MCU can perform a Read
operation to obtain these status bits while an
Erase or Program instruction is being executed by
the embedded algorithm. See the section entitled
“Programming Flash Memory”, on page 25, for details.
23/89
PSD4235G2
Table 30. Status Bits
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Data Polling
Toggle Flag
Error Flag
X
Erase Timeout
X
X
X
Table 31. Status Bits for Motorola
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
Data Polling
Toggle Flag
Error Flag
X
Erase Timeout
X
X
X
Note: 1. X = Not guaranteed value, can be read either 1 or 0.
2. DQ15-DQ0 represent the Data Bus bits, D15-D0.
3. FS0-FS7/CSBOOT0-CSBOOT3 are active High.
Data Polling (DQ7) – DQ15 for Motorola.
When erasing or programming in Flash memory,
the Data Polling (DQ7/DQ15) bit outputs the complement of the bit being entered for programming/
writing on the DQ7/DQ15 bit. Once the Program
instruction or the Write operation is completed, the
true logic value is read on the Data Polling (DQ7/
DQ15) bit (in a Read operation).
■ Data Polling is effective after the fourth Write
pulse (for a Program instruction) or after the
sixth Write pulse (for an Erase instruction). It
must be performed at the address being
programmed or at an address within the Flash
memory sector being erased.
■
During an Erase cycle, the Data Polling (DQ7/
DQ15) bit outputs a 0. After completion of the
cycle, the Data Polling (DQ7/DQ15) bit outputs
the last bit programmed (it is a 1 after erasing).
■
If the location to be programmed is in a
protected Flash memory sector, the instruction
is ignored.
■
If all the Flash memory sectors to be erased are
protected, the Data Polling (DQ7/DQ15) bit is
reset to 0 for about 100 µs, and then returns to
the value from the previously addressed
location. No erasure is performed.
Toggle Flag (DQ6) – DQ14 for Motorola. The
PSD offers another way for determining when the
Flash memory Program cycle is completed. During
the internal Write operation and when either FS0FS7 or CSBOOT0-CSBOOT3 is true, the Toggle
Flag (DQ6/DQ14) bit toggles from 0 to 1 and 1 to
0 on subsequent attempts to read any word of the
memory.
When the internal cycle is complete, the toggling
stops and the data read on the Data Bus D0-D7 is
the value from the addressed memory location.
The device is now accessible for a new Read or
24/89
Write operation. The cycle is finished when two
successive Reads yield the same output data.
■ The Toggle Flag (DQ6/DQ14) bit is effective
after the fourth Write pulse (for a Program
instruction) or after the sixth Write pulse (for an
Erase instruction).
■
If the location to be programmed belongs to a
protected Flash memory sector, the instruction
is ignored.
■
If all the Flash memory sectors selected for
erasure are protected, the Toggle Flag (DQ6/
DQ14) bit toggles to 0 for about 100 µs and then
returns to the value from the previously
addressed location.
Error Flag (DQ5) – DQ13 for Motorola. During
a normal Program or Erase cycle, the Error Flag
(DQ5/DQ13) bit is reset to 0. This bit is set to 1
when there is a failure during a Flash memory Program, Sector Erase, or Bulk Erase cycle.
In the case of Flash memory programming, the Error Flag (DQ5/DQ13) bit indicates the attempt to
program a Flash memory bit, or bits, from the programmed state, 0, to the erased state, 1, which is
not a valid operation. The Error Flag (DQ5/DQ13)
bit may also indicate a Time-out condition while attempting to program a word.
In case of an error in a Flash memory Sector Erase
or Word Program cycle, the Flash memory sector
in which the error occurred or to which the programmed location belongs must no longer be
used. Other Flash memory sectors may still be
used. The Error Flag (DQ5/DQ13) bit is reset after
a Reset instruction. A Reset instruction is required
after detecting an error on the Error Flag (DQ5/
DQ13) bit.
Erase Time-out Flag (DQ3) – DQ11 for Motorola. The Erase Time-out Flag (DQ3/DQ11) bit reflects the time-out period allowed between two
consecutive Sector Erase instructions. The Erase
Time-out Flag (DQ3/DQ11) bit is reset to 0 after a
PSD4235G2
Sector Erase cycle for a period of 100 µs + 20%
unless an additional Sector Erase instruction is decoded. After this period, or when the additional
Sector Erase instruction is decoded, the Erase
Time-out Flag (DQ3/DQ11) bit is set to 1.
Programming Flash Memory
Flash memory must be erased prior to being programmed. The MCU may erase Flash memory all
at once or by-sector. Although erasing Flash memory occurs on a sector or device basis, programming Flash memory occurs on a word basis.
The primary and secondary Flash memories require the MCU to send an instruction to program a
word or to erase sectors (see Table 29).
Once the MCU issues a Flash memory Program or
Erase instruction, it must check the status bits for
completion. The embedded algorithms that are invoked inside the PSD support several means to
provide status to the MCU. Status may be checked
using any of three methods: Data Polling, Data
Toggle, or Ready/Busy (PE4) signal.
Data Polling. Polling on the Data Polling (DQ7/
DQ15) bit is a method of checking whether a Program or Erase cycle is in progress or has completed. Figure 6 shows the Data Polling algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location of the word to be programmed in Flash memory to check the status.
The Data Polling (DQ7/DQ15) bit becomes the
complement of the corresponding bit of the original
data word to be programmed. The MCU continues
to poll this location, comparing data and monitoring the Error Flag (DQ5/DQ13) bit. When the Data
Polling (DQ7/DQ15) bit matches the corresponding bit of the original data, and the Error Flag
(DQ5/DQ13) bit remains 0, the embedded algorithm is complete. If the Error Flag (DQ5/DQ13) bit
is 1, the MCU should test the Data Polling (DQ7/
DQ15) bit again since the Data Polling (DQ7/
DQ15) bit may have changed simultaneously with
the Error Flag (DQ5/DQ13) bit (see Figure 6).
The Error Flag (DQ5/DQ13) bit is set if either an internal time-out occurred while the embedded algorithm attempted to program the location or if the
MCU attempted to program a 1 to a bit that was not
erased (not erased is logic 0).
It is suggested (as with all Flash memories) to read
the location again after the embedded programming algorithm has completed, to compare the
word that was written to the Flash memory with the
word that was intended to be written.
When using the Data Polling method during an
Erase cycle, Figure 6 still applies. However, the
Data Polling (DQ7/DQ15) bit is 0 until the Erase
cycle is complete. A 1 on the Error Flag (DQ5/
DQ13) bit indicates a time-out condition on the
Erase cycle, a 0 indicates no error. The MCU can
read any even location within the sector being
erased to get the Data Polling (DQ7/DQ15) bit and
the Error Flag (DQ5/DQ13) bit.
PSDsoft Express generates ANSI C code functions that implement these Data Polling algorithms.
Figure 6. Data Polling Flowchart
START
READ DQ5 and DQ7
(DQ13 and DQ15)
at Valid Even Address
DQ7
(DQ15)
=
Data7
(Data15)
Yes
No
No
DQ5
(DQ13)
=1
Yes
READ DQ7
(DQ15)
DQ7
(DQ15)
=
Data7
(Data15)
Yes
No
Program
or Erase
Cycle failed
Program
or Erase
Cycle is
complete
Issue RESET
instruction
AI04920
Data Toggle. Checking the Toggle Flag (DQ6/
DQ14) bit is another method of determining whether a Program or Erase cycle is in progress or has
completed. Figure 7 shows the Data Toggle algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location to be programmed in
Flash memory to check the status. The Toggle
Flag (DQ6/DQ14) bit toggles each time the MCU
25/89
PSD4235G2
reads this location until the embedded algorithm is
complete. The MCU continues to read this location, checking the Toggle Flag (DQ6/DQ14) bit
and monitoring the Error Flag (DQ5/DQ13) bit.
When the Toggle Flag (DQ6/DQ14) bit stops toggling (two consecutive reads yield the same value), and the Error Flag (DQ5/DQ13) bit remains 0,
the embedded algorithm is complete. If the Error
Flag (DQ5/DQ13) bit is 1, the MCU should test the
Toggle Flag (DQ6/DQ14) bit again, since the Toggle Flag (DQ6/DQ14) bit may have changed simultaneously with the Error Flag (DQ5/DQ13) bit (see
Figure 7).
Figure 7. Data Toggle Flowchart
START
READ DQ5 and DQ6
(DQ13 and DQ14)
at Valid Even Address
DQ6
(DQ14)
=
Toggle
No
Yes
No
DQ5
(DQ13)
=1
Yes
READ DQ6
(DQ14)
DQ6
(DQ14)
=
Toggle
No
Yes
Program
or Erase
Cycle failed
Program
or Erase
Cycle is
complete
Issue RESET
instruction
AI04921
The Error Flag (DQ5/DQ13) bit is set if either an internal time-out occurred while the embedded algorithm attempted to program, or if the MCU
26/89
attempted to program a 1 to a bit that was not
erased (not erased is logic 0).
It is suggested (as with all Flash memories) to read
the location again after the embedded programming algorithm has completed, to compare the
word that was written to Flash memory with the
word that was intended to be written.
When using the Data Toggle method after an
Erase cycle, Figure 7 still applies. the Toggle Flag
(DQ6/DQ14) bit toggles until the Erase cycle is
complete. A 1 on the Error Flag (DQ5/DQ13) bit indicates a time-out condition on the Erase cycle, a
0 indicates no error. The MCU can read any even
location within the sector being erased to get the
Toggle Flag (DQ6/DQ14) bit and the Error Flag
(DQ5/DQ13) bit.
PSDsoft Express generates ANSI C code functions which implement these Data Toggling algorithms.
Unlock Bypass. The Unlock Bypass instruction
allows the system to program words to the Flash
memories faster than using the standard Program
instruction. The Unlock Bypass mode is entered
by first initiating two Unlock cycles. This is followed
by a third Write cycle containing the Unlock Bypass command, 20h (as shown in Table 29). The
Flash memory then enters the Unlock Bypass
mode.
A two-cycle Unlock Bypass Program instruction is
all that is required to program in this mode. The
first cycle in this instruction contains the Unlock
Bypass Program command, A0h. The second cycle contains the program address and data. Additional data is programmed in the same manner.
This mode dispense with the initial two Unlock cycles required in the standard Program instruction,
resulting in faster total programming time.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset instructions are valid.
To exit the Unlock Bypass mode, the system must
issue the two-cycle Unlock Bypass Reset instruction. The first cycle must contain the data 90h; the
second cycle the data 00h. Addresses are Don’t
Care for both cycles. The Flash memory then returns to Read mode.
Erasing Flash Memory
Flash Bulk Erase. The Flash Bulk Erase instruction uses six Write operations followed by a Read
operation of the status register, as described in
Table 29. If any byte of the Bulk Erase instruction
is wrong, the Bulk Erase instruction aborts and the
device is reset to the Read Memory mode.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag (DQ5/DQ13)
bit, the Toggle Flag (DQ6/DQ14) bit, and the Data
Polling (DQ7/DQ15) bit, as detailed in the section
PSD4235G2
entitled “Programming Flash Memory”, on page
25. The Error Flag (DQ5/DQ13) bit returns a 1 if
there has been an Erase Failure (maximum number of Erase cycles have been executed).
It is not necessary to program the memory with
00h because the PSD automatically does this before erasing to 0FFh.
During execution of the Bulk Erase instruction, the
Flash memory does not accept any instructions.
Flash Sector Erase. The Sector Erase instruction uses six Write operations, as described in Table 29. Additional Flash Sector Erase confirm
commands and Flash memory sector addresses
can be written subsequently to erase other Flash
memory sectors in parallel, without further coded
cycles, if the additional commands are transmitted
in a shorter time than the time-out period of about
100 µs. The input of a new Sector Erase command
restarts the time-out period.
The status of the internal timer can be monitored
through the level of the Erase Time-out Flag (DQ3/
DQ11) bit. If the Erase Time-out Flag (DQ3/DQ11)
bit is 0, the Sector Erase instruction has been received and the time-out period is counting. If the
Erase Time-out Flag (DQ3/DQ11) bit is 1, the
time-out period has expired and the PSD is busy
erasing the Flash memory sector(s). Before and
during Erase time-out, any instruction other than
Suspend Sector Erase and Resume Sector Erase,
abort the cycle that is currently in progress, and reset the device to Read mode. It is not necessary to
program the Flash memory sector with 00h as the
PSD does this automatically before erasing.
During a Sector Erase, the memory status may be
checked by reading the Error Flag (DQ5/DQ13)
bit, the Toggle Flag (DQ6/DQ14) bit, and the Data
Polling (DQ7/DQ15) bit, as detailed in the section
entitled “Programming Flash Memory”, on page
25.
During execution of the Erase cycle, the Flash
memory accepts only Reset and Suspend Sector
Erase instructions. Erasure of one Flash memory
sector may be suspended, in order to read data
from another Flash memory sector, and then resumed.
Suspend Sector Erase. When a Sector Erase
cycle is in progress, the Suspend Sector Erase instruction can be used to suspend the cycle by writing 0B0h to any even address when an
appropriate
Sector
Select
(FS0-FS7
or
CSBOOT0-CSBOOT3) is High. (See Table 29).
This allows reading of data from another Flash
memory sector after the Erase cycle has been
suspended. Suspend Sector Erase is accepted
only during the Flash Sector Erase instruction execution and defaults to Read mode. A Suspend
Sector Erase instruction executed during an Erase
time-out period, in addition to suspending the
Erase cycle, terminates the time out period.
The Toggle Flag (DQ6/DQ14) bit stops toggling
when the PSD internal logic is suspended. The
status of this bit must be monitored at an address
within the Flash memory sector being erased. The
Toggle Flag (DQ6/DQ14) bit stops toggling between 0.1 µs and 15 µs after the Suspend Sector
Erase instruction has been executed. The PSD is
then automatically set to Read mode.
If an Suspend Sector Erase instruction was executed, the following rules apply:
– Attempting to read from a Flash memory sector
that was being erased outputs invalid data.
– Reading from a Flash memory sector that was
not being erased is valid.
– The Flash memory cannot be programmed, and
only responds to Resume Sector Erase and Reset instructions (Read is an operation and is allowed).
– If a Reset instruction is received, data in the
Flash memory sector that was being erased is
invalid.
Resume Sector Erase. If a Suspend Sector
Erase instruction was previously executed, the
Erase cycle may be resumed with this instruction.
The Resume Sector Erase instruction consists of
writing 030h to any even address while an appropriate Sector Select (FS0-FS7 or CSBOOT0CSBOOT3) is High. (See Table 29.)
Flash Memory Sector Protect
Each sector of Primary or Secondary Flash memory can be separately protected against Program
and Erase cycles. Sector Protection provides additional data security because it disables all Program or Erase cycles. This mode can be activated
(or deactivated) through the JTAG-ISP Port or a
Device Programmer.
Sector protection can be selected for each sector
using the PSDsoft Express program. This automatically protects selected sectors when the device is programmed through the JTAG Port or a
Device Programmer. Flash memory sectors can
be unprotected to allow updating of their contents
using the JTAG Port or a Device Programmer. The
MCU can read (but cannot change) the sector protection bits.
Any attempt to program or erase a protected Flash
memory sector is ignored by the device. The Verify
operation results in a read of the protected data.
This allows a guarantee of the retention of the Protection status.
The sector protection status can be read by the
MCU through the Flash memory protection and
Secondary Flash memory protection registers (in
27/89
PSD4235G2
the CSIOP block) or use the Read Sector Protection instruction. See Table 19 to Table 20.
Reset
The Reset instruction consists of one Write cycle
(see Table 29). It can also be optionally preceded
by the standard two write decoding cycles (writing
AAh to AAAh, and 55h to 554h).
The Reset instruction must be executed after:
– Reading the Flash Protection Status or Flash ID
– An Error condition has occurred (and the device
has set the Error Flag (DQ5/DQ13) bit to 1) during a Flash memory Program or Erase cycle.
The Reset instruction immediately puts the Flash
memory back into normal Read mode. However, if
there is an error condition (with the Error Flag
(DQ5/DQ13) bit set to 1) the Flash memory will return to the Read mode in 25 µs after the Reset instruction is issued.
The Reset instruction is ignored when it is issued
during a Program or Bulk Erase cycle of the Flash
memory. The Reset instruction aborts any on-going Sector Erase cycle, and returns the Flash
memory to the normal Read mode in 25 µs.
Reset (RESET) Pin. A pulse on the Reset (RESET) pin aborts any cycle that is in progress, and
resets the Flash memory to the Read mode. When
the reset occurs during a Program or Erase cycle,
the Flash memory takes up to 25 µs to return to
the Read mode. It is recommended that the Reset
(RESET) pulse (except for Power On Reset, as
described on page 62) be at least 25 µs so that the
Flash memory is always ready for the MCU to
fetch the bootstrap instructions after the Reset cycle is complete.
SRAM
The SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to three product terms, allowing flexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
to the Voltage Stand-by (VSTBY, PE6) line. If you
have an external battery connected to the PSD,
the contents of the SRAM are retained in the event
of a power loss. The contents of the SRAM are retained so long as the battery voltage remains at
2 V or greater. If the supply voltage falls below the
battery voltage, an internal power switch-over to
the battery occurs.
PE7 can be configured as an output that indicates
when power is being drawn from the external battery. This Battery-on Indicator (VBATON, PE7)
signal is High when the supply voltage falls below
the battery voltage and the battery on Voltage
Stand-by (VSTBY, PE6) is supplying power to the
internal SRAM.
28/89
SRAM Select (RS0), Voltage Stand-by (VSTBY,
PE6) and Battery-on Indicator (VBATON, PE7)
are all configured using PSDsoft Express.
Memory Select Signals
The Primary Flash Memory Sector Select (FS0FS7), Secondary Flash Memory Sector Select
(CSBOOT0-CSBOOT3) and SRAM Select (RS0)
signals are all outputs of the DPLD. They are defined using PSDsoft Express. The following rules
apply to the equations for these signals:
1. Primary Flash memory and secondary Flash
memory Sector Select signals must not be larger than the physical sector size.
2. Any primary Flash memory sector must not be
mapped in the same memory space as another
Flash memory sector.
3. A secondary Flash memory sector must not be
mapped in the same memory space as another
secondary Flash memory sector.
4. SRAM, I/O, and Peripheral I/O spaces must not
overlap.
5. A secondary Flash memory sector may overlap
a primary Flash memory sector. In case of overlap, priority is given to the secondary Flash
memory sector.
6. SRAM, I/O, and Peripheral I/O spaces may
overlap any other memory sector. Priority is given to the SRAM, I/O, or Peripheral I/O.
Figure 8. Priority Level of Memory and I/O
Components
Highest Priority
Level 1
SRAM, I /O, or
Peripheral I /O
Level 2
Secondary
Non-Volatile Memory
Level 3
Primary Flash Memory
Lowest Priority
AI02867D
Example. FS0 is valid when the address is in the
range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to
87FFh. Any address in the range of RS0 always
accesses the SRAM. Any address in the range of
CSBOOT0 greater than 87FFh (and less than
9FFFh) automatically addresses secondary Flash
memory segment 0. Any address greater than
9FFFh accesses the primary Flash memory seg-
PSD4235G2
ment 0. You can see that half of the primary Flash
memory segment 0 and one-fourth of secondary
Flash memory segment 0 cannot be accessed in
this example. Also note that an equation that defined FS1 to anywhere in the range of 8000h to
BFFFh would not be valid.
Figure 8 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must
not overlap. Level 1 has the highest priority and
level 3 has the lowest.
Memory Select Configuration for MCUs with
Separate Program and Data Spaces. The
80C51XA and compatible family of MCUs, can be
configured to have separate address spaces for
Program memory (selected using Program Select
Enable (PSEN, CNTL2)) and Data memory (selected using Read Strobe (RD, CNTL1)). Any of
the memories within the PSD can reside in either
space or both spaces. This is controlled through
manipulation of the VM register that resides in the
CSIOP space.
The VM register is set using PSDsoft Express to
have an initial value. It can subsequently be
changed by the MCU so that memory mapping
can be changed on-the-fly.
For example, you may wish to have SRAM and primary Flash memory in the Data space at Boot-up,
and secondary Flash memory in the Program
space at Boot-up, and later swap the secondary
Flash memory and primary Flash memory. This is
easily done with the VM register by using PSDsoft
Express to configure it for Boot-up and having the
MCU change it when desired.
Table 25 describes the VM Register.
Separate Space Modes. Program space is separated from Data space. For example, Program
Select Enable (PSEN, CNTL2) is used to access
the program code from the primary Flash memory,
while Read Strobe (RD, CNTL1) is used to access
data from the secondary Flash memory, SRAM
and I/O Port blocks. This configuration requires
the VM register to be set to 0Ch (see Figure 9).
Figure 9. 8031 Memory Modules – Separate Space
DPLD
RS0
Primary
Flash
Memory
Secondary
Flash
Memory
SRAM
CSBOOT0-3
FS0-FS7
CS
CS
OE
CS
OE
OE
PSEN
RD
AI02869C
Combined Space Modes. The Program and
Data spaces are combined into one memory
space that allows the primary Flash memory, secondary Flash memory, and SRAM to be accessed
by either Program Select Enable (PSEN, CNTL2)
or Read Strobe (RD, CNTL1). For example, to
configure the primary Flash memory in Combined
space, bits 2 and 4 of the VM register are set to 1
(see Figure 10).
80C51XA Memory Map Example. See the Application Notes for examples.
29/89
PSD4235G2
Figure 10. 8031 Memory Modules – Combined Space
DPLD
RD
SRAM
Secondary
Flash
Memory
Primary
Flash
Memory
RS0
CSBOOT0-3
FS0-FS7
CS
CS
OE
CS
OE
OE
VM REG BIT 3
VM REG BIT 4
PSEN
VM REG BIT 1
RD
VM REG BIT 2
VM REG BIT 0
AI02870C
Page Register
The 8-bit Page Register increases the addressing
capability of the MCU by a factor of up to 256. The
contents of the register can also be read by the
MCU. The outputs of the Page Register (PGR0PGR7) are inputs to the DPLD decoder and can be
included in the Sector Select (FS0-FS7,
CSBOOT0-CSBOOT3), and SRAM Select (RS0)
equations.
If memory paging is not needed, or if not all eight
page register bits are needed for memory paging,
these bits may be used in the CPLD for general
logic. See Application Note AN1154.
Table 22 and Figure 11 show the Page Register.
The eight flip-flops in the register are connected to
the internal data bus (D0-D7). The MCU can write
to or read from the Page Register. The Page Register can be accessed at address location CSIOP
+ E0h.
Figure 11. Page Register
RESET
D0
D0 - D7
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
PGR0
INTERNAL
SELECTS
AND LOGIC
PGR1
PGR2
PGR3
PGR4
DPLD
AND
CPLD
PGR5
PGR6
PGR7
R/ W
PAGE
REGISTER
30/89
PLD
AI02871B
PSD4235G2
Memory ID Registers
The 8-bit read-only Memory Status Registers are
included in the CSIOP space. The user can determine the memory configuration of the PSD device
by reading the Memory ID0 and Memory ID1 registers. The content of the registers is defined as
shown in Table 26 and Table 27.
PLDs
The PLDs bring programmable logic functionality
to the PSD. After specifying the logic for the PLDs
using PSDsoft Express, the logic is programmed
into the device and available upon Power-up.
Table 32. DPLD and CPLD Inputs
Input Source
Input Name
Number
of
Signals
MCU Address Bus1
A15-A0
16
MCU Control Signals
CNTL0-CNTL2
3
Reset
RST
1
Power-down
PDN
1
Port A Input
Macrocells
PA7-PA0
8
Port B Input
Macrocells
PB7-PB0
8
Port C Input
Macrocells
PC7-PC0
8
Port D Inputs
PD3-PD0
4
Port F Inputs
PF7-PF0
8
Page Register
PGR7-PGR0
8
Macrocell A Feedback
MCELLA.FB7-FB0
8
Macrocell B Feedback
MCELLB.FB7-FB0
8
Flash memory
Program Status Bit
Ready/Busy
1
The PSD contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD). The PLDs
are briefly discussed in the next few paragraphs,
and in more detail in the following sections. Figure
12 shows the configuration of the PLDs.
The DPLD performs address decoding for internal
components, such as memory, registers, and I/O
ports Select signals.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state machines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 24 Input Macrocells
(IMC), and the AND Array. The CPLD can also be
used to generate External Chip Select (ECS0ECS2) signals.
The AND Array is used to form product terms.
These product terms are specified using PSDsoft
Express. An Input Bus consisting of 82 signals is
connected to the PLDs. The signals are shown in
Table 32.
The Turbo Bit in PSD. The
PLDs
in
the
PSD4235G2 can minimize power consumption by
switching to standby when inputs remain unchanged for an extended time of about 70 ns. Resetting the Turbo bit to 0 (Bit 3 of the PMMR0
register) automatically places the PLDs into standby if no inputs are changing. Turning the Turbo
mode off increases propagation delays while reducing power consumption. See the section entitled “Power Management”, on page 59, on how to
set the Turbo bit.
Additionally, five bits are available in the PMMR2
register to block MCU control signals from entering
the PLDs. This reduces power consumption and
can be used only when these MCU control signals
are not used in PLD logic equations.
Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.
Note: 1. The address inputs are A19-A4 in 80C51XA mode.
31/89
32/89
16
1
2
1
3
4
8
CPLD
PT
ALLOC.
OUTPUT MACROCELL FEEDBACK
DECODE PLD
PAGE
REGISTER
24 INPUT MACROCELL
(PORT A,B,C)
INPUT MACROCELL & INPUT PORTS
PORT D and PORT F INPUTS
24
12
MACROCELL
ALLOC.
8
8
MCELLB
TO PORT B
EXTERNAL CHIP SELECTS
TO PORT C or PORT F
8
MCELLA
TO PORT A
DIRECT MACROCELL ACCESS FROM MCU DATA BUS
JTAG SELECT
PERIPHERAL SELECTS
CSIOP SELECT
SRAM SELECT
SECONDARY NON-VOLATILE MEMORY SELECTS
PRIMARY FLASH MEMORY SELECTS
16 OUTPUT
MACROCELL
DIRECT MACROCELL INPUT TO MCU DATA BUS
82
82
8
I/O PORTS
DATA
BUS
AI05737
PSD4235G2
Figure 12. PLD Diagram
PLD INPUT BUS
PSD4235G2
DECODE PLD (DPLD)
The DPLD, shown in Figure 13, is used for decoding the address for internal and external components. The DPLD can be used to generate the
following decode signals:
■ 8 Sector Select (FS0-FS7) signals for the
primary Flash memory (three product terms
each)
■
4 Sector Select (CSBOOT0-CSBOOT3) signals
for the secondary Flash memory (three product
terms each)
■
1 internal SRAM Select (RS0) signal (three
product terms)
■
1 internal CSIOP Select (PSD Configuration
Register) signal
■
1 JTAG Select signal (enables JTAG-ISP on
Port E)
■
2 internal Peripheral Select signals
(Peripheral I/O mode).
Figure 13. DPLD Logic Array
(INPUTS)
I /O PORTS (PORT A,B,F)
3
CSBOOT 0
3
CSBOOT 1
3
CSBOOT 2
3
CSBOOT 3
3
FS0
(32)
3
MCELLAB.FB [7:0] (FEEDBACKS)
FS1
(8)
3
MCELLBC.FB [7:0] (FEEDBACKS)
FS2
(8)
3
PGR0 -PGR7
FS3
(8)
3
A[15:0] *
(16)
3
PD[3:0] (ALE,CLKIN,CSI)
(4)
PDN (APD OUTPUT)
(1)
FS5
3
FS6
3
CNTRL[2:0] (READ/WRITE CONTROL SIGNALS)
(3)
RESET
(1)
RD_BSY
(1)
8 PRIMARY FLASH
MEMORY SECTOR SELECTS
FS4
FS7
3
RS0
1
CSIOP
1
PSEL0
1
PSEL1
1
JTAGSEL
SRAM SELECT
I/O DECODER
SELECT
PERIPHERAL I/O MODE
SELECT
AI05738
Note: 1. The address inputs are A19-A4 when in 80C51XA mode
2. Additional address lines can be brought ino the PSD via Port A, B, C, D, or F.
33/89
PSD4235G2
COMPLEX PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate eight External Chip Select (ECS0-ECS7), routed to Port C or Port F.
Although External Chip Select (ECS0-ECS7) can
be produced by any Output Macrocell (OMC),
these eight External Chip Select (ECS0-ECS7) on
Port C or Port F do not consume any Output Macrocells (OMC).
As shown in Figure 12, the CPLD has the following
blocks:
■ 24 Input Macrocells (IMC)
■
16 Output Macrocells (OMC)
■
Product Term Allocator
■
AND Array capable of generating up to 196
product terms
■
Four I/O Ports.
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the MCU. This
enables the MCU software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC).
This feature allows efficient implementation of system logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
Figure 14. Macrocell and I/O Port
PLD INPUT BUS
PRODUCT TERMS
FROM OTHER
MACROCELLS
MCU ADDRESS / DATA BUS
CPLD MACROCELLS
I/O PORTS
DATA
LOAD
CONTROL
PT PRESET
MCU DATA IN
PRODUCT TERM
ALLOCATOR
LATCHED
ADDRESS OUT
DATA
MCU LOAD
I/O PIN
D
Q
MUX
POLARITY
SELECT
MUX
AND ARRAY
WR
UP TO 10
PRODUCT TERMS
CPLD OUTPUT
PR DI LD
D/T
MUX
PT
CLOCK
PLD INPUT BUS
MACROCELL
OUT TO
MCU
GLOBAL
CLOCK
SELECT
Q
D/T/JK FF
SELECT
COMB.
/REG
SELECT
PDR
INPUT
CK
CL
CLOCK
SELECT
Q
DIR
REG.
D
WR
PT CLEAR
PT OUTPUT ENABLE (OE)
MACROCELL FEEDBACK
INPUT MACROCELLS
MUX
I/O PORT INPUT
ALE/AS
MUX
PT INPUT LATCH GATE/CLOCK
Q D
Q D
G
AI04945
34/89
PSD4235G2
Output Macrocell (OMC). Eight of the Output
Macrocells (OMC) are connected to Ports A pins
and are named as McellA0-McellA7. The other
eight Macrocells are connected to Ports B pins
and are named as McellB0-McellB7.
The Output Macrocell (OMC) architecture is
shown in Figure 15. As shown in the figure, there
are native product terms available from the AND
Array, and borrowed product terms available (if
unused) from other Output Macrocells (OMC). The
polarity of the product term is controlled by the
XOR gate. The Output Macrocell (OMC) can implement either sequential logic, using the flip-flop
element, or combinatorial logic. The multiplexer
selects between the sequential or combinatorial
logic outputs. The multiplexer output can drive a
port pin and has a feedback path to the AND Array
inputs.
The flip-flop in the Output Macrocell (OMC) block
can be configured as a D, T, JK, or SR type in the
PSDsoft Express program. The flip-flop’s clock,
preset, and clear inputs may be driven from a
product term of the AND Array. Alternatively, the
external CLKIN (PD1) signal can be used for the
clock input to the flip-flop. The flip-flop is clocked
on the rising edge of CLKIN (PD1). The preset and
clear are active High inputs. Each clear input can
use up to two product terms.
Table 33. Output Macrocell Port and Data Bit Assignments
Output
Macrocell
Port
Assignment
Native Product
Terms
Maximum
Borrowed
Product Terms
Data Bit for
Loading or
Reading
Motorola 16-Bit
MCU for Loading or
Reading
McellA0
Port A0
3
6
D0
D8
McellA1
Port A1
3
6
D1
D9
McellA2
Port A2
3
6
D2
D10
McellA3
Port A3
3
6
D3
D11
McellA4
Port A4
3
6
D4
D12
McellA5
Port A5
3
6
D5
D13
McellA6
Port A6
3
6
D6
D14
McellA7
Port A7
3
6
D7
D15
McellB0
Port B0
4
5
D8
D0
McellB1
Port B1
4
5
D9
D1
McellB2
Port B2
4
5
D10
D2
McellB3
Port B3
4
5
D11
D3
McellB4
Port B4
4
6
D12
D4
McellB5
Port B5
4
6
D13
D5
McellB6
Port B6
4
6
D14
D6
McellB7
Port B7
4
6
D15
D7
35/89
PSD4235G2
Figure 15. CPLD Output Macrocell
MASK
REG.
MACROCELL CS
INTERNAL DATA BUS
RD
PT
ALLOCATOR
WR
DIRECTION
REGISTER
ENABLE (.OE)
AND ARRAY
PLD INPUT BUS
PRESET(.PR)
COMB/REG
SELECT
PT
PT
DIN PR
MUX
PT
LD
POLARITY
SELECT
IN
CLEAR (.RE)
PORT
DRIVER
CLR
PROGRAMMABLE
FF (D/T/JK /SR)
PT CLK
CLKIN
I/O PIN
Q
MUX
FEEDBACK (.FB)
PORT INPUT
INPUT
MACROCELL
AI04946
Product Term Allocator. The CPLD has a Product Term Allocator. PSDsoft Express, uses the
Product Term Allocator to borrow and place product terms from one Macrocell to another. The following list summarizes how product terms are
allocated:
■ McellA0-McellA7 all have three native product
terms and may borrow up to six more
■
McellB0-McellB3 all have four native product
terms and may borrow up to five more
■
McellB4-McellB7 all have four native product
terms and may borrow up to six more.
Each Macrocell may only borrow product terms
from certain other Macrocells. Product terms already in use by one Macrocell are not available for
another Macrocell.
If an equation requires more product terms than
are available to it, then “external” product terms
are required, which consume other Output Macrocells (OMC). If external product terms are used,
extra delay is added for the equation that required
the extra product terms. This is called product term
expansion. PSDsoft Express performs this expansion as needed.
36/89
Loading and Reading the Output Macrocells
(OMC). The Output Macrocells (OMC) block occupies a memory location in the MCU address
space, as defined by the CSIOP (see the section
entitled “I/O Ports”, on page 50). The flip-flops in
each of the 16 Output Macrocells (OMC) can be
loaded from the data bus by a MCU. Loading the
Output Macrocells (OMC) with data from the MCU
takes priority over internal functions. As such, the
preset, clear, and clock inputs to the flip-flop can
be overridden by the MCU. The ability to load the
flip-flops and read them back is useful in such applications as loadable counters and shift registers,
mailboxes, and handshaking protocols.
Data is loaded to the Output Macrocells (OMC) on
the trailing edge of Write Strobe (WR/WRL,
CNTL0).
The OMC Mask Register. There is one Mask
Register for each of the two groups of eight Output
Macrocells (OMC). The Mask Registers can be
used to block the loading of data to individual Output Macrocells (OMC). The default value for the
Mask Registers is 00h, which allows loading of the
Output Macrocells (OMC). When a given bit in a
Mask Register is set to a 1, the MCU is blocked
from writing to the associated Output Macrocells
PSD4235G2
(OMC). For example, suppose McellA0-McellA3
are being used for a state machine. You would not
want a MCU write to McellA to overwrite the state
machine registers. Therefore, you would want to
load the Mask Register for McellA (Mask Macrocell A) with the value 0Fh.
The Output Enable of the OMC. The
Output
Macrocells (OMC) can be connected to an I/O port
pin as a PLD output. The output enable of each
port pin driver is controlled by a single product
term from the AND Array, ORed with the Direction
Register output. The pin is enabled upon Powerup if no output enable equation is defined and if
the pin is declared as a PLD output in PSDsoft Express.
If the Output Macrocell (OMC) output is declared
as an internal node and not as a port pin output in
the PSDabel file, then the port pin can be used for
other I/O functions. The internal node feedback
can be routed as an input to the AND Array.
Input Macrocells (IMC). The CPLD has 24 Input
Macrocells (IMC), one for each pin on Ports A, B,
and C. The architecture of the Input Macrocells
(IMC) is shown in Figure 16. The Input Macrocells
(IMC) are individually configurable, and can be
used as a latch, register, or to pass incoming Port
signals prior to driving them onto the PLD input
bus. The outputs of the Input Macrocells (IMC) can
be read by the MCU through the internal data bus.
The enable for the latch and clock for the register
are driven by a multiplexer whose inputs are a
product term from the CPLD AND Array or the
MCU Address Strobe (ALE/AS). Each product
term output is used to latch or clock four Input
Macrocells (IMC). Port inputs 3-0 can be controlled by one product term and 7-4 by another.
Configurations for the Input Macrocells (IMC) are
specified by PSDsoft Express (see Application
Note AN1171). Outputs of the Input Macrocells
(IMC) can be read by the MCU via the IMC buffer.
See the section entitled “I/O Ports”, on page 50.
Input Macrocells (IMC) can use Address Strobe
(ALE/AS, PD0) to latch address bits higher than
A15. Any latched addresses are routed to the
PLDs as inputs.
Input Macrocells (IMC) are particularly useful with
handshaking communication applications where
two processors pass data back and forth through
a common mailbox. Figure 18 shows a typical configuration where the Master MCU writes to the Port
A Data Out Register. This, in turn, can be read by
the Slave MCU via the activation of the “SlaveRead” output enable product term.
The Slave can also write to the Port A Input Macrocells (IMC) and the Master can then read the Input Macrocells (IMC) directly.
Note that the “Slave-Read” and “Slave-Wr” signals
are product terms that are derived from the Slave
MCU inputs Read Strobe (RD, CNTL1), Write
Strobe (WR/WRL, CNTL0), and Slave_CS.
37/89
PSD4235G2
Figure 16. Input Macrocell
INTERNAL DATA BUS
INPUT MACROCELL _ RD
DIRECTION
REGISTER
ENABLE ( .OE )
OUTPUT
MACROCELLS A
AND
MACROCELLS B
PLD INPUT BUS
AND ARRAY
PT
I/O PIN
PT
PORT
DRIVER
MUX
Q
D
PT
MUX
ALE/AS
D FF
FEEDBACK
D
Q
G
LATCH
INPUT MACROCELL
AI04926
External Chip Select. The CPLD also provides
eight External Chip Select (ECS0-ECS7) outputs
that can be used to select external devices. Each
External Chip Select (ECS0-ECS7) consists of
one product term that can be configured active
High or Low.
The output enable of the pin is controlled by either
the output enable product term or the Direction
Register. (See Figure 17.)
Figure 17. External Chip Select Signal
CPLD AND ARRAY
PLD INPUT BUS
Port C or Port F
ENABLE (.OE) PT
ECS
To Port C or F
ECS PT
DIRECTION
REGISTER
PORT PIN
POLARITY
BIT
AI04927
38/89
PSD4235G2
Figure 18. Handshaking Communication Using Input Macrocells
PSD
SLAVE – CS
RD
WR
SLAVE – READ
PORT A
DATA OUT
REGISTER
MCU -RD
MASTER
MCU
D [ 7:0]
CPLD
D
Q
SLAVE
MCU
PORT A
MCU - WR
MCU -WR
SLAVE – WR
D [ 7:0]
PORT A
INPUT
MACROCELL
Q
D
MCU - RD
AI02877C
39/89
PSD4235G2
MCU BUS INTERFACE
The “no-glue logic” MCU Bus Interface block can
be directly connected to most popular MCUs and
their control signals. Key 16-bit MCUs, with their
bus types and control signals, are shown in Table
34. The MCU interface type is specified using the
PSDsoft Express.
PSD Interface to a Multiplexed Bus. Figure 19
shows an example of a system using a MCU with
a 16-bit multiplexed bus and a PSD4235G2. The
ADIO port on the PSD is connected directly to the
MCU address/data bus. Address Strobe (ALE/AS,
PD0) latches the address signals internally.
Latched addresses can be brought out to Port E, F
or G. The PSD drives the ADIO data bus only
when one of its internal resources is accessed and
Read Strobe (RD, CNTL1) is active. Should the
system address bus exceed sixteen bits, Ports A,
B, C, or F may be used as additional address inputs.
PSD Interface to a Non-Multiplexed 8-Bit Bus.
Figure 20 shows an example of a system using a
MCU with a 16-bit non-multiplexed bus and a
PSD4235G2. The address bus is connected to the
ADIO Port, and the data bus is connected to Ports
F and G. Ports F and G are in tri-state mode when
the PSD is not accessed by the MCU. Should the
system address bus exceed sixteen bits, Ports A,
B, or C may be used for additional address inputs.
Table 34. MCUs and their Control Signals
MCU
CNTL0
CNTL1
CNTL2
PD02
PD3
ADIO0
PF3-PF0
68302, 68306, MMC2001
R/W
LDS
UDS
(Note 1)
AS
—
(Note 1)
68330, 68331, 68332, 68340
R/W
DS
SIZ0
(Note 1)
AS
A0
(Note 1)
68LC302, MMC2001
WEL
OE
—
WEH
AS
—
(Note 1)
68HC16
R/W
DS
SIZ0
(Note 1)
AS
A0
(Note 1)
68HC912
R/W
E
LSTRB
DBE
E
A0
(Note 1)
68HC812 3
R/W
E
LSTRB
(Note 1)
(Note 1)
A0
(Note 1)
80196
WR
RD
BHE
(Note 1)
ALE
A0
(Note 1)
80196SP
WRL
RD
(Note 1)
WRH
ALE
A0
(Note 1)
80186
WR
RD
BHE
(Note 1)
ALE
A0
(Note 1)
80C161, 80C164-80C167
WR
RD
BHE
(Note 1)
ALE
A0
(Note 1)
80C51XA
WRL
RD
PSEN
WRH
ALE
A4/D0
A3-A1
H8/300
WRL
RD
(Note 1)
WRH
AS
A0
—
M37702M2
R/W
E
BHE
(Note 1)
ALE
A0
(Note 1)
Note: 1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PD3-PD0, PF3-PF0) can be configured for other I/O functions.
2. ALE/AS input is optional for MCUs with a non-multiplexed bus
40/89
PSD4235G2
Figure 19. An Example of a Typical 16-bit Multiplexed Bus Interface
PSD
MCU
AD [ 7:0]
ADIO
PORT
AD[ 15:8]
WR
WR (CNTRL0)
RD
RD (CNTRL1)
BHE (CNTRL2)
BHE
RST
ALE
A [ 7: 0]
PORT
F
(OPTIONAL)
PORT
G
(OPTIONAL)
PORT
A, B
or C
(OPTIONAL)
A [ 15: 8]
A [ 23:16]
ALE (PD0)
PORT D
RESET
AI04928
Figure 20. An Example of a Typical 16-bit Non-Multiplexed Bus Interface
PSD
MCU
D [ 15:0]
ADIO
PORT
PORT
F
D [ 7:0]
A [ 15:0]
PORT
G
WR
WR (CNTRL0)
RD
RD (CNTRL1)
BHE (CNTRL2)
BHE
RST
ALE
PORT
A, B
or C
D[ 15:8]
A [ 23:16]
(OPTIONAL)
ALE (PD0)
PORT D
RESET
AI04929
41/89
PSD4235G2
Data Byte Enable Reference. MCUs have different data byte orientations. Table 35 to Table 38
show how the PSD4235G2 interprets byte/word
operations in different bus write configurations.
Even-byte refers to locations with address A0
equal to 0, and odd byte as locations with A0 equal
to 1.
Table 35. 16-Bit Data Bus with BHE
BHE
A0
D15-D8
D7-D0
0
0
Odd Byte
Even Byte
0
1
Odd Byte
1
0
—
WRH
WRL
D15-D8
D7-D0
0
0
Odd Byte
Even Byte
0
1
Odd Byte
—
1
0
—
Even Byte
Table 37. 16-Bit Data Bus with SIZ0, A0
(Motorola MCU)
SIZ0
A0
—
0
0
Even Byte
Odd Byte
Even Byte
1
0
Even Byte
—
1
1
—
Odd Byte
MCU Bus Interface Examples. Figure 21 to Figure 26 show examples of the basic connections
between the PSD4235G2 and some popular
MCUs. The PSD4235G2 Control input pins are labeled as to the MCU function for which they are
configured. The MCU bus interface is specified using PSDsoft Express. The Voltage Stand-by (VSTBY, PE6) line should be held at Ground if not in
use.
42/89
Table 36. 16-Bit Data Bus with WRH and WRL
D15-D8
D7-D0
Table 38. 16-Bit Data Bus with LDS, UDS
(Motorola MCU)
WRH
WRL
D15-D8
D7-D0
0
0
Even Byte
Odd Byte
1
0
Even Byte
—
0
1
—
Odd Byte
PSD4235G2
Figure 21. Interfacing the PSD with an 80C196
A19-A16
A[ 19:16]
AD15-AD0
AD[ 15:0 ]
VCC
80C196NT
19
18
32
49
6
48
44
45
46
47
58
59
60
61
62
63
64
65
36
37
38
39
40
41
42
43
57
56
55
54
53
52
51
50
PSD
X1
X2
P3.0/AD0
P3.1/AD1
P3.2/AD2
P3.3/AD3
P3.4/AD4
P3.5/AD5
P3.6/AD6
P3.7/AD7
3
4
5
6
7
10
11
12
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
5
6
7
10
11
12
P4.0/AD8
P4.1/AD9
P4.2/AD10
P4.3/AD11
P4.4/AD12
P4.5/AD13
P4.6/AD14
P4.7/AD15
13
14
15
16
17
18
19
20
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
13
14
15
16
17
18
19
20
EP.0/A16
EP.1/A17
EP.2/A18
EP.3/A19
14
13
12
11
9
WR
59
7
RD
60
8
BHE
40
4
ALE
79
80
1
2
NMI
VREF
VPP
ANGND
ACH4/P0.4/PMD.0
ACH5/P0.5/PMD.1
ACH6/P0.6/PMD.2
ACH7/P0.7/PMD.3
P6.0/EPA8
P6.1/EPA9
P6.2/T1CLK
P6.3/T1DIR
P6.4/SC0
P6.5/SD0
P6.6/SC1
P6.7/SD1
WR/WRL/P5.2
RD/P5.3
BHE/WRH/P5.5
P2.0/TX/PVR
P2.1/RXD/PALE
P2.2/EXINT/PROG
P2.3/INTB
P2.4/INTINTOUT
P2.5/HLD
P2.6/HLDA/CPVER
P2.7/CLKOUT/PAC
ALE/ADV/P5.0
EA
P1.5/EPA5
P1.6/EPA6
P1.7/EPA7
33
31
P1.0/EPA0/T2CLK
P1.1/EPA1
P1.2/EPA2/T2DIR
P1.3/EPA3
BUSWIDTH/P5.7
P1.4/EPA4
INST/P5.1
SLPINT/P5.4
29
69
VCC
VCC
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
A16
A17
A18
A19
RESET
READY/P5.6
9
VCC
2
10
3
1
RESET
39
71
72
73
74
75
76
77
78
CNTL1 (RD)
CNTL2 (BHE)
PD0 (ALE)
PD1 (CLKIN)
PD2 (CSI)
PD3 (WRH)
80C196 and 80C186. In Figure 21, the Intel
80C196 MCU, which has a 16-bit multiplexed address/data bus, is shown connected to a
PSD4235G2. The Read Strobe (RD, CNTL1), and
Write Strobe (WR/WRL, CNTL0) signals are connected to the CNTL pins. When BHE is not used,
the PSD can be configured to receive WRL and
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
RESET
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
GND
GND
GND
GND
GND
8
RESET
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
CNTL0 (WR)
30
49
50
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
31
32
33
34
35
36
37
38
21
22
23
24
25
26
27
28
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
A16
A17
A18
A19
70
AI04930
Write Enable High-byte (WRH/DBE, PD3) from the
MCU. Higher address inputs (A16-A19) can be
routed to Ports A, B, or C as input ot the PLD.
The AMD 80186 family has the same bus connection to the PSD as the 80C196.
43/89
PSD4235G2
Figure 22. Interfacing the PSD with an MC68331
D[15:0]
D[15:0]
A[23:0]
A[23:0]
69
9
PSD
29
VCC_BAR
89
88
77
76
75
74
73
72
71
D8
D9
D10
D11
D12
D13
D14
D15
DSACK0
DSACK1
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19_CS6/
A20_CS7/
A21_CS8/
A22_CS9/
A23_CS10/
27
30
31
32
33
35
36
37
38
41
42
121
122
123
124
125
A8
A9
A10
A11
A12
A13
A14
A15
13
14
15
16
17
18
19
20
A16
A17
A18
A19
A20
A21
A22
A23
79
R_W 85
DS 81
SIZ0
AS
RESET
SIZ1
CLKOUT
CSBOOT/
BR_CS0/
BG_CS1/
BGACK_CS2/
FC0_CS3/
FC1_CS4/
FC2_CS5/
R/W\
DS\
59
60
SIZ0
40
AS
79
80
1
2
RESET\
39
82
68
80
66
112
113
114
115
118
119
120
71
72
73
74
75
76
77
78
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
Vcc
A0
A1
A2
A3
A4
A5
A6
A7
Vcc
A0
A1
A2
A3
A4
A5
A6
A7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
CNTL0(R/W)
CNTL1(DS)
CNTL2 (SIZ0)
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
RESET
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0 (AS)
PD1 (CLKIN)
PD2 (CSI)
PD3
31
32
33
34
35
36
37
38
D0
D1
D2
D3
D4
D5
D6
D7
21
22
23
24
25
26
27
28
D8
D9
D10
D11
D12
D13
D14
D15
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
A16
A17
A18
A19
GND
GND
GND
GND
GND
D8 100
D9 99
D10 98
D11 97
D12 94
D13 93
D14 92
D15 91
D0
D1
D2
D3
D4
D5
D6
D7
3
4
5
6
7
10
11
12
8
30
49
50
70
D0
D1
D2
D3
D4
D5
D6
D7
90
20
21
22
23
24
25
26
Vcc
MC68331
111
110
109
108
105
104
103
102
RESET\
AI04951b
MC683xx and MC68HC16. Figure 22 shows a
MC68331 with a 16-bit non-multiplexed data bus
and 24-bit address bus. The data bus from the
MC68331 is connected to Port F (D0-D7) and Port
G (D8-D15). The SIZ0 and A0 inputs determine
44/89
the high/low byte selection. The R/W, DS and SIZ0
signals are connected to the CNTL0-CNTL2 pins.
The MC68HC16, and other members of the
MC683xx family, has the same bus connection to
the PSD as the MC68331 shown in Figure 22.
PSD4235G2
Figure 23. Interfacing the PSD with an 80C51XA-G3
D[15:0]
D[15:0]
A[3:1]
VCC_BAR
CRYSTAL
20
11
13
6
7
9
8
16
RESET\
10
14
15
35
17
XTAL1
XTAL2
RXD0
TXD0
RXD1
TXD1
T2EX
T2
T0
RST
INT0
INT1
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12D8
A13D9
A14D10
A15D11
A16D12
A17D13
A18D14
A19D15
A3
A2
A1
A0/WRH
WRL
RD
PSEN
EA/WAIT
ALE
43
42
41
40
39
38
37
36
3
A4D0
4
A5D1
A6D2
5
6
A7D3
A8D4
7
A9D5 10
A10D6 11
A11D7 12
24
25
26
27
28
29
30
31
A12D8 13
A13D9 14
A14D10 15
A15D11 16
A16D12 17
A17D13 18
A18D14 19
A19D15 20
5
4
3
2
18
19
A3
A2
A1
WRH\
WRL\
RD\
59
60
32
PSEN\
40
33
ALE
79
80
1
2
BUSW
VCC_BAR
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
69
Vcc
21
U3
Vcc
9
XA-G3
Vcc
PSD
29
A[3:1]
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
CNTL0(WR)
CNTL1(RD)
CNTL2(PSEN)
RESET
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
31
32
33
34
35
36
37
38
A1
A2
A3
21
22
23
24
25
26
27
28
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
8
30
49
50
70
GND
GND
GND
GND
GND
71
72
73
74
75
76
77
78
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PD0 (ALE)
PD1 (CLKIN)
PD2 (CSI)
PD3 (WRH)
RESET\
39
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
AI04952b
80C51XA. The Philips 80C51XA MCU has a 16bit multiplexed bus with burst cycles. Address bits
(A3-A1) are not multiplexed, while (A19-A4) are
multiplexed with data bits (D15-D0).
The PSD4235G2 supports the 80C51XA burst
mode. The WRH signal is connected to PD3, and
WHL is connected to CNTL0. The RD and PSEN
signals are connected to the CNTL1 and CNTL2
pins. Figure 23 shows the schematic diagram.
The 80C51XA improves bus throughput and performance by issuing burst cycles to fetch codes
from memory. In burst cycles, address A19-A4 are
latched internally by the PSD, while the 80C51XA
drives the A3-A1 signals to fetch sequentially up to
16 bytes of code. The PSD access time is then
measured from address A3-A1 valid to data in valid. The PSD bus timing requirement in a burst cycle is identical to the normal bus cycle, except the
address setup and hold time with respect to Address Strobe (ALE/AS, PD0) is not required.
45/89
PSD4235G2
Figure 24. Interfacing the PSD with an H83/2350
D[15:0]
D[15:0]
A[23:0]
A[23:0]
78
PD0/D8
PD1/D9
PD2/D10
PD3/D11
PD4/D12
PD5/D13
PD6/D14
PD7/D15
EXTAL
U3
CRYSTAL
77
29
30
31
32
55
53
57
56
54
58
90
89
91
88
87
86
74
71
70
69
68
67
66
65
64
60
61
62
63
113
114
115
80
XTAL
CS7/IRQ3
CS6/IRQ2
IRQ1
IRQ0
RXD0
TXD0
SCK0
RXD1
TXD1
SCK1
RXD2
TXD2
SCK2
PF0/BREQ
PF1/BACK
PF2/LCAS/WAIT/B
NMI
PO0/TIOCA3
PO1/TIOCB3
PO2/TIOCC3/TMRI
PO3/TIOCD3/TMCI
PO4/TIOCA4/TMRI
PO5/TIOCB4/TMRC
PO6/TIOCA5/TMRO
PO7/TIOCB5/TMRO
DREQ/CS4
TEND0/CS5
DREQ1
TEND1
MOD0
MOD1
MOD2
PF0/PHI0
PB0/A8
PB1/A9
PB2/A10
PB3/A11
PB4/A12
PB5/A13
PB6/A14
PB7/A15
PA0/A16
PA1/A17
PA2/A18
PA3/A19
PA4/A20/IRQ4
PA5/A21/IRQ5
PA6/A22/IRQ6
PA7/A23/IRQ7
LWR
RD
AS
HWR
RESET
WDTOVF
STBY
PO8/TIOCA0/DACK
PO9/TIOCB0/DACK
PO10/TIOCC0/TCL
PO11/TIOCD0/TCL
PO12/TIOCA1
PO13/TIOCB1/TCL
PO14/TIOCA2
PO15/TIOCB2/TCL
AN0
AN1
AN2
AN3
AN4
AN5
AN6/DA0
AN7/DA1
ADTRG
PG0/CAS/OE
PG1/CS3
PG2/CS2
PG3/CS1
PG4/CS0
11
12
13
14
16
17
18
19
20
21
22
23
25
26
27
28
85
83
A8
A9
A10
A11
A12
A13
A14
A15
13
14
15
16
17
18
19
20
WRL\
RD\
AS
84
WRH\
73
72
75
112
111
110
109
108
107
106
105
59
60
40
82
RESET\
79
80
1
2
39
71
72
73
74
75
76
77
78
69
9
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
CNTL0(WRL)
CNTL1(RD)
CNTL2
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
RESET
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0 (AS)
PD1 (CLKIN)
PD2 (CSI)
PD3 (WRH)
31
32
33
34
35
36
37
38
D0
D1
D2
D3
D4
D5
D6
D7
21
22
23
24
25
26
27
28
D8
D9
D10
D11
D12
D13
D14
D15
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
A16
A17
A18
A19
95
96
97
98
99
100
101
102
92
116
117
118
119
120
RESET\
H8/300. Figure 24 shows an Hitachi H8/2350 with
a 16-bit non-multiplexed data bus, and a 24-bit address bus. The H8 data bus is connected to Port F
(D0-D7) and Port G (D8-D15).
46/89
A16
A17
A18
A19
A20
A21
A22
A23
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
Vcc
3
4
5
6
7
10
11
12
Vcc
43
44
45
46
48
49
50
51
PC0/A0
PC1/A1
PC2/A2
PC3/A3
PC4/A4
PC5/A5
PC6/A6
PC7/A7
A0
A1
A2
A3
A4
A5
A6
A7
GND
GND
GND
GND
GND
D8
D9
D10
D11
D12
D13
D14
D15
PE0/D0
PE0/D1
PE0/D2
PE0/D3
PE0/D4
PE0/D5
PE0/D6
PE0/D7
PSD
2
3
4
5
7
8
9
10
8
30
49
50
70
34
35
36
37
39
40
41
42
Vcc
H8S/2655
D0
D1
D2
D3
D4
D5
D6
D7
29
VCC_BAR
AI04953b
The WRH signal is connected to PD3, and WHL is
connected to CNTL0. The RD signal is connected
to CNTL1. The connection to the Address Strobe
(AS) signal is optional, and is required if the addresses are to be latched.
PSD4235G2
Figure 25. Interfacing the PSD with an MMC2001
A[19:16]
A[19:16]
AD[15:0]
VCC_BAR
19
20
21
22
23
24
25
26
9
10
11
12
13
14
15
16
P5.0/AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5
P5.6/AN6
P5.7/AN7
P5.8/AN8
P5.9/AN9
P5.10/AN10/T6UED
P5.11/AN11/T5UED
P5.12/AN12/T6IN
P5.13/AN13/T5IN
P5.14/AN14/T4UED
P5.15/AN15/T2UED
P4.0/A16
A17
A18
A19
A20
A21
A22
P4.7/A23
WR/WRL
RD
P3.12/BHE/WRH
ALE
EA
P1H7
P1H6
P1H5
P1H4
P1H3
P1H2
P1H1
P1H0
P1L7
P1L6
P1L5
P1L4
P1L3
P1L2
P1L1
P1L0
P6.0/!CS0
P6.1/!CS1
P6.2/!CS2
P6.3/!CS3
P6.4/!CS4
P6.5/!HOLD
P6.6/!HLDA
P6.7/!BREQ
P7.0/POUT0
P7.1/POUT1
P7.2/POUT2
P7.3/POUT3
P7.4/CC28IO
P7.5/CC29IO
P7.6/CC30IO
P7.7/CC31IO
P8.0/CC16IO
P8.1/CC17IO
P8.2/CC18IO
P8.3/CC19IO
P8.4/CC20IO
P8.5/CC21IO
P8.6/CC22IO
P8.7/CC23IO
P2.0/CC0IO
P2.1/CC1IO
P2.2/CC2IO
P2.3/CC3IO
P2.4/CC4IO
P2.5/CC5IO
P2.6/CC6IO
P2.7/CC7IO
P2.8/CC8IO/EX0IN
P2.9/CC9IO/EX1IN
P2.10/CC10IO/EX2IN
P2.11/CC11IO/EX3IN
P2.12/CC12IO/EX4IN
P2.13/CC13IO/EX5IN
P2.14/CC14IO/EX6IN
P2.15/CC15IO/EX7IN
Vref
READY
143
139
127
110
94
Vss
Vss
Vss
Vss
Vss
37
97
P3.13/SCLK
P3.15/CLKOUT
RSTIN
RSTOUT
NMI
108
111
112
113
114
115
116
117
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
13
14
15
16
17
18
19
20
85
86
87
88
89
90
91
92
96
95
79
98
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
9
29
69
Vcc
3
4
5
6
7
10
11
12
Vcc
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
A16
A17
A18
A19
WR\
RD\
BHE\
ALE
99
135
134
133
132
131
130
129
128
125
124
123
122
121
120
119
118
RESET\
59
60
40
79
80
1
2
39
71
72
73
74
75
76
77
78
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
CNTL0(WR)
CNTL1(RD)
CNTL2(BHE)
RESET
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0 (ALE)
PD1 (CLKIN)
PD2 (CSI)
PD3 (WRH)
31
32
33
34
35
36
37
38
21
22
23
24
25
26
27
28
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
A16
A17
A18
A19
GND
GND
GND
GND
GND
1
2
3
4
5
6
7
8
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
Agnd
27
28
29
30
31
32
33
34
35
36
39
40
41
42
43
44
P3.0/T0IN
P3.1/T6OUT
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3EUD
P3.5/T4IN
P3.6/T3IN
P3.7/T2IN
P3.8/MRST
P3.9/MTSR
P3.10/TXD0
P3.11/RXD0
100
101
102
103
104
105
106
107
47
48
49
50
51
52
53
54
57
58
59
60
61
62
63
64
140
141
142
38
80
81
XTAL2
Vss
Vss
Vss
Vss
Vss
65
66
67
68
69
70
73
74
75
76
77
78
83
71
55
45
18
137
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Vcc
82
72
56
46
17
U3
CRYSTAL
ADIO[15:0]
8
30
49
50
70
XTAL1
PSD
Vcc
Vcc
Vcc
Vcc
Vcc
138
Vcc
Vcc
Vcc
Vcc
Vcc
Infineon C167CR
144
136
126
109
93
VCC_BAR
RESET\
MMC2001. The Motorola MCORE MMC2001
MCU has a MOD input pin that selects interal or
external boot ROM. The PSD can be configured
as the external flash boot ROM or as extension to
the internal ROM.
The MMC2001 has a 16-bit external data bus and
20 address lines with external chip select signals.
The Chip Select Control Registers allow the user
to customize the bus interface and timing to fit the
individual system requirement. A typical interface
AI04954b
configuaration to the PSD is shown in Figure 25.
The MMC2001’s R/W signal is conneced to the
CNTL0 pin, while EB0 and EB1 (enable byte-0 and
enable byte-1) are connected to the CNTL1 (UDS)
and CNTL2 (LDS) pins. The WEN bit in the Chip
Select Control Register should be set to 1 to terminate the EB0-EB1 earlier to provide the wrtie data
hold time for the PSD. The WSC and WWS bits in
the Control Register are set to wait states that
meet the PSD access time requirement.
47/89
PSD4235G2
Another option is to configure the EB0 and EB1 as
WRL and WRH signals. In this case, the PSD control setting will be: OE, WRL, WRH where OE is
the read signal for the MMC2001.
C16x Family. The PSD supports Infineon’s C16X
family of MCUs (C161-C167) in both the multiplexed and non-multiplexed bus configuration. In
Figure 26, the C167CR is shown connected to the
48/89
PSD in a multiplexed bus configuration. The control signals from the MCU are WR, RD, BHE and
ALE, and are routed to the corresponding PSD
pins.
The C167 has another control signal setting (RD,
WRL, WRH, ALE) which is also supported by the
PSD.
PSD4235G2
Figure 26. Interfacing the PSD with a C167CR
A19-A16
A[ 19:16]
AD15-AD0
Vcc
144136129109 93 82 72 56 46 17
VccVccVccVccVccVccVccVccVccVcc
138
65
66
67
68
69
70
73
74
75
76
77
78
79
80
100
101
102
103
104
105
106
107
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
5
6
7
10
11
12
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
108
111
112
113
114
115
116
117
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
13
14
15
16
17
18
19
20
XTAL1
81
27
28
29
30
31
32
33
34
35
36
39
40
41
42
43
44
1
2
3
4
5
6
7
8
19
20
21
22
23
24
25
26
9
10
11
12
13
14
15
16
37
97
XTAL2
P3.0/T0IN
P3.1/T6OUT
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3UED
P3.5/T4IN
P3.6/T3IN
P3.7/T2IN
P3.8/MRST
P3.9/MTSR
P3.10/TXD0
P3.11/RXD0
P3.12
P3.13/SCLK
85
86
87
88
89
90
91
92
P5.0/AN0
WR/WRL
P5.1/AN1
P5.2/AN2
RD
P5.3/AN3
P312/BHE/WRH
P5.4/AN4
P5.5/AN5
ALE
P5.6/AN6
P5.7/AN7
EA
P5.8/AN8
P5.9/AN9
P1H7
P5.10/AN10/T6UED
P1H6
P5.11/AN11/T5UED
P1H5
P5.12/AN12/T6IN
P1H4
P5.13/AN13
P1H3
P5.14/AN14/T4UED
P1H2
P5.15/AN15/T2UED
P1H1
P1H0
P6.0/!CS0
P1L7
P6.1/!CS1
P1L6
P6.2/!CS2
P1L5
P6.3/!CS3
P1L4
P6.4/!CS4
P1L3
P6.5/!HOLD
P1L2
P1L1
P6.6/!HLDA
P1L0
P6.7/!BREQ
96
WR
59
95
RD
60
79
BHE
40
98
ALE
79
80
P3.15/CLKOUT
P7.0/POUT0
P7.1/POUT1
P7.2/POUT2
P7.3/POUT3
P7.4/CC28IO
P7.5/CC29IO
P7.6/CC30IO
P7.7/CC31IO
P8.0/CC16IO
P8.1/CC17IO
P8.2/CC18IO
P8.3/CC19IO
P8.4/CC20IO
P8.5/CC21IO
P8.6/CC22IO
P8.7/CC23IO
Vref
99
135
134
133
132
131
130
129
128
125
124
123
122
121
120
119
118
9
VCC
29
69
VCC
VCC
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
A16
A17
A18
A19
P4.0/A16
P4.1/A17
P4.2/A18
P4.3/A19
P4.4/A20
P4.5/A21
P4.6/A22
P4.7/A23
1
2
RESET
39
71
72
73
74
75
76
77
78
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
CNTL0 (WR)
CNTL1 (RD)
CNTL2 (BHE)
PD0 (ALE)
PD1 (CLKIN)
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PD2 (CSI)
PD3 (WRH)
RESET
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
GND
GND
GND
GND
GND
8
30
49
50
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
31
32
33
34
35
36
37
38
21
22
23
24
25
26
27
28
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
A16
A17
A18
A19
70
47
48
49
50
51
52
53
54
57
58
59
60
61
62
63
64
P2.0/CC0IO
P2.1/CC1IO
P2.2/CC2IO
P2.3/CC3IO
P2.4/CC4IO
P2.5/CC5IO
P2.6/CC6IO
P2.7/CC7IO
P2.8/CC8IO/EX0IN
P2.9/CC9IO/EX1IN
P2.10/CC10IO/EX2IN
P2.11/CC11IO/EX3IN
P2.12/CC12IO/EX4IN
P2.13/CC13IO/EX5IN
P2.14/CC14IO/EX6IN
P2.15/CC15IO/EX7IN
140
RSTIN
RSTOUT
141
NMI
AGND
VssVssVssVssVssVssVssVssVssVss
READY
143139127110 94 83 71 55 45 18
RESET
PSD
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
C167CR
137
AD[ 15:0 ]
VCC
142
38
AI04955
49/89
PSD4235G2
I/O PORTS
There are seven programmable I/O ports: Ports A,
B, C, D, E, F and G. Each port pin is individually
user configurable, thus allowing multiple functions
per port. The ports are configured using PSDsoft
Express or by the MCU writing to on-chip registers
in the CSIOP space.
The topics discussed in this section are:
■ General Port architecture
available for other purposes. Exceptions are noted.
As shown in Figure 27, the ports contain an output
multiplexer whose select signals are driven by the
configuration bits in the Control Registers (Ports E,
F and G only) and PSDsoft Express Configuration.
Inputs to the multiplexer include the following:
■ Output data from the Data Out register
■
Port operating modes
■
Latched address outputs
■
Port Configuration Registers (PCR)
■
CPLD Macrocell output
■
Port Data Registers
■
External Chip Select from the CPLD.
■
Individual Port functionality.
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connected to the Internal
Data Bus for feedback and can be read by the
MCU. The Data Out and Macrocell outputs, Direction Register and Control Register, and port pin input are all connected to the Port Data Buffer
(PDB).
General Port Architecture. The general architecture of the I/O Port block is shown in Figure 27.
Individual Port architectures are shown in Figure
29 to Figure 31. In general, once the purpose for a
port pin has been defined, that pin is no longer
Figure 27. General I/O Port Architecture
DATA OUT
REG.
D
Q
D
Q
DATA OUT
WR
ADDRESS
ALE
ADDRESS
PORT PIN
OUTPUT
MUX
G
MACROCELL OUTPUTS
EXT CS
INTERNAL DATA BUS
READ MUX
P
OUTPUT
SELECT
D
DATA IN
B
CONTROL REG.
D
Q
ENABLE OUT
WR
DIR REG.
D
Q
WR
ENABLE PRODUCT TERM (.OE)
INPUT
MACROCELL
CPLD - INPUT
AI02885
50/89
PSD4235G2
The Port pin’s tri-state output driver enable is controlled by a two input OR gate whose inputs come
from the CPLD AND Array enable product term
and the Direction Register. If the enable product
term of any of the Array outputs are not defined
and that port pin is not defined as a CPLD output
in the PSDabel file, the Direction Register has sole
control of the buffer that drives the port pin.
The contents of these registers can be altered by
the MCU. The Port Data Buffer (PDB) feedback
path allows the MCU to check the contents of the
registers.
Ports A, B, and C have embedded Input Macrocells (IMC). The Input Macrocells (IMC) can be
configured as latches, registers, or direct inputs to
the PLDs. The latches and registers are clocked
by Address Strobe (ALE/AS, PD0) or a product
term from the PLD AND Array. The outputs from
the Input Macrocells (IMC) drive the PLD input bus
and can be read by the MCU. See the section entitled “Input Macrocell”, on page 38.
Port Operating Modes
The I/O Ports have several modes of operation.
Some modes can be defined using PSDsoft Express, some by the MCU writing to the registers in
CSIOP space, and some by both. The modes that
can only be defined using PSDsoft Express must
be programmed into the device and cannot be
changed unless the device is reprogrammed. The
modes that can be changed by the MCU can be
done so dynamically at run-time. The PLD I/O,
Data Port, Address Input, Peripheral I/O and MCU
Reset modes are the only modes that must be defined before programming the device. All other
modes can be changed by the MCU at run-time.
See Application Note AN1171 for more detail.
Table 39 summarizes which modes are available
on each port. Table 40 shows how and where the
different modes are configured. Each of the port
operating modes are described in the following
sections.
MCU I/O Mode. In the MCU I/O mode, the MCU
uses the PSD Ports to expand its own I/O ports. By
setting up the CSIOP space, the ports on the PSD
are mapped into the MCU address space. The addresses of the ports are listed in Table 6.
A port pin can be put into MCU I/O mode by writing
a 0 to the corresponding bit in the Control Register
(for Ports E, F and G). The MCU I/O direction may
be changed by writing to the corresponding bit in
the Direction Register, or by the output enable
product term. See the section entitled “Port Operating Modes”, on page 51. When the pin is configured as an output, the content of the Data Out
Register drives the pin. When configured as an input, the MCU can read the port input through the
Data In buffer. See Figure 27.
Ports A, B and C do not have Control Registers,
and are in MCU I/O mode by default. They can be
used for PLD I/O if they are specified in PSDsoft
Express.
PLD I/O Mode. The PLD I/O Mode uses a port as
an input to the CPLD’s Input Macrocells (IMC),
and/or as an output from the CPLD’s Output Macrocells (OMC). The output can be tri-stated with a
control signal. This output enable control signal
can be defined by a product term from the PLD, or
by resetting the corresponding bit in the Direction
Register to 0. The corresponding bit in the Direction Register must not be set to 1 if the pin is defined for a PLD input signal in PSDsoft Express.
The PLD I/O mode is specified in PSDsoft Express
by declaring the port pins, and then specifying an
equation in PSDsoft Express.
Address Out Mode. For MCUs with a multiplexed address/data bus, Address Out mode can
be used to drive latched addresses onto the port
pins. These port pins can, in turn, drive external
devices. Either the output enable or the corresponding bits of both the Direction Register and
Control Register must be set to a 1 for pins to use
Address Out mode. This must be done by the
MCU at run-time. See Table 41 for the address
output pin assignments on Ports E, F and G for
various MCUs.
Note: Do not drive address signals with Address
Out Mode to an external memory device if it is intended for the MCU to Boot from the external device. The MCU must first Boot from PSD memory
so the Direction and Control register bits can be
set.
51/89
PSD4235G2
Table 39. Port Operating Modes
Port Mode
Port A
Port B
Port C
Port D
Port E
Port F
Port G
MCU I/O
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PLD I/O
McellA Outputs
McellB Outputs
Additional Ext. CS Outputs
PLD Inputs
Yes
No
No
Yes
Yes
Yes
No
Yes
No
No
Yes
Yes
No
No
No
Yes
No
No
No
No
No
No
Yes
Yes
No
No
No
No
Address Out
No
No
No
No
Yes (A7 – 0)
Yes (A7 – 0)
Yes (A7 – 0)
or (A15 – 8)
Address In
Yes
Yes
Yes
Yes
No
Yes
No
Data Port
No
No
No
No
No
Yes
Yes
Peripheral I/O
Yes
No
No
Yes
No
Yes
No
JTAG ISP
No
No
No
No
Yes1
No
No
MCU Reset Mode2
No
No
No
No
No
Yes
Yes
Note: 1. Can be multiplexed with other I/O functions.
2. Available to Motorola 16-bit 683xx and HC16 families of MCUs.
Table 40. Port Operating Mode Settings
Mode
Control
Register
Setting
Defined in PSDsoft
Express
Direction
Register
Setting
VM Register
Setting
JTAG Enable
MCU I/O
Declare pins only
0 (Note 4)
1 = output,
0 = input
(Note 2)
N/A
N/A
PLD I/O
Declare pins and
Logic equations
N/A
(Note 2)
N/A
N/A
Data Port (Port F, G)
Selected for MCU
with non-multiplexed
bus
N/A
N/A
N/A
N/A
Address Out
(Port E, F, G)
Declare pins only
1
1 (Note 2)
N/A
N/A
Address In
(Port A, B, C, D, F)
Declare pins or Logic
equation for Input
Macrocells
N/A
N/A
N/A
N/A
Peripheral I/O
(Port F)
Logic equations
(PSEL0 and PSEL1)
N/A
N/A
PIO bit = 1
N/A
JTAG ISP 3
Declare pins only
N/A
N/A
N/A
JTAG_Enable
MCU Reset Mode
Specific pin logic level N/A
N/A
N/A
N/A
Note: 1. N/A = Not Applicable
2. The direction of the Port A,B,C, and F pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND Array.
3. Any of these three methods enables the JTAG pins on Port E.
4. Control Register setting is not applicable to Ports A, B and C.
52/89
PSD4235G2
Table 41. I/O Port Latched Address Output Assignments
MCU
80C51XA
All Other
MCU with Multiplexed Bus
Port E
(PE3-PE0)
Port E
(PE7-PE4)
Port F
(PF3-PF0)
Port F
(PF7-PF4)
Port G
(PG3-PG0)
Port G
(PG7-PG4)
N/A1
Address
a7-a4
N/A
Address
a7-a4
Address
a11-a8
Address
a15-a12
Address
a3-a0
Address
a7-a4
Address
a3-a0
Address
a7-a4
Address
a11-a8
Address
a15-a12
Note: 1. N/A = Not Applicable.
Address In Mode. For MCUs that have more
than 16 address signals, the higher addresses can
be connected to Port A, B, C, D or F, and are routed as inputs to the PLDs. The address input can
be latched in the Input Macrocell (IMC) by Address
Strobe (ALE/AS, PD0). Any input that is included
in the DPLD equations for the primary Flash memory, secondary Flash memory or SRAM is considered to be an address input.
Data Port Mode. Ports F and G can be used as a
data bus port for a MCU with a non-multiplexed
address/data bus. The Data Port is connected to
the data bus of the MCU. The general I/O functions are disabled in Ports F and G if the ports are
configured as a Data Port. Data Port mode is automatically configured in PSDsoft Express when a
non-multiplexed bus MCU is selected.
Peripheral I/O Mode. Peripheral I/O mode can
be used to interface with external 8-bit peripherals.
In this mode, all of Port F serves as a tri-state, bidirectional data buffer for the MCU. Peripheral I/O
mode is enabled by setting bit 7 of the VM Register
to a 1. Figure 28 shows how Port A acts as a bidirectional buffer for the MCU data bus if Peripheral I/O mode is enabled. An equation for PSEL0
and/or PSEL1 must be specified in PSDsoft Express. The buffer is tri-stated when PSEL0 or
PSEL1 is not active.
JTAG In-System Programming (ISP). Port E is
JTAG compliant, and can be used for In-System
Programming (ISP). You can multiplex JTAG operations with other functions on Port E because InSystem Programming (ISP) is not performed during normal system operation. For more information
on the JTAG Port, see the section entitled “Reset
(RESET) Timing”, on page 63.
MCU Reset Mode. Ports F and G can be configured to operate in MCU Reset mode. This mode is
available when PSD is configured for the Motorola
16-bit 683xx and HC16 family and is active only
during reset.
At the rising edge of the Reset input, the MCU
reads the logic level on the data bus (D15-D0)
pins. The MCU then configures some of its I/O pin
functions according to the logic level input on the
data bus lines. Two dedicated buffers are usually
enabled during reset to drive the data bus lines to
the desired logic level.
The PSD can replace the two buffers by configuring Ports F and G to operate in MCU Reset mode.
In this mode, the PSD will drive the pre-defined
logic level or data pattern on to the MCU data bus
when Reset is active and there is no ongoing bus
cycle. After reset, Ports F and G return to the normal Data Port mode.
The MCU Reset mode is enabled and configured
in PSDsoft Express. The user defines the logic level (data pattern) that will be drive out from Ports F
and G during reset.
Port Configuration Registers (PCR). Each Port
has a set of Port Configuration Registers (PCR)
used for configuration. The contents of the registers can be accessed by the MCU through normal
read/write bus cycles at the addresses given in Table 6. The addresses in Table 6 are the offsets in
hexadecimal from the base of the CSIOP register.
The pins of a port are individually configurable and
each bit in the register controls its respective pin.
For example, bit 0 in a register refers to bit 0 of its
port. The three Port Configuration Registers
(PCR), shown in Table 42, are used for setting the
Port configurations. The default Power-up state for
each register in Table 42 is 00h.
Table 42. Port Configuration Registers (PCR)
Register Name
Port
MCU Access
Control
E, F, G
Write/Read
Direction
A, B, C, D, E, F, G
Write/Read
Drive Select1
A, B, C, D, E, F, G
Write/Read
Note: 1. See Table 46 for Drive Register bit definition.
Control Register. Any bit reset to 0 in the Control
Register sets the corresponding port pin to MCU I/
O mode, and a 1 sets it to Address Out mode. The
default mode is MCU I/O. Only Ports E, F and G
have an associated Control Register.
53/89
PSD4235G2
Figure 28. Peripheral I/O Mode
RD
PSEL0
PSEL
PSEL1
D0 - D7
DATA BUS
VM REGISTER BIT 7
PA0 - PA7
WR
AI02886
Direction Register. The Direction Register controls the direction of data flow in the I/O Ports. Any
bit set to 1 in the Direction Register causes the
corresponding pin to be an output, and any bit set
to 0 causes it to be an input. The default mode for
all port pins is input.
Table 43. Port Pin Direction Control, Output
Enable P.T. Not Defined
Direction Register Bit
Port Pin Mode
0
Input
1
Output
Table 44. Port Pin Direction Control, Output
Enable P.T. Defined
Direction
Register Bit
Output Enable
P.T.
Port Pin Mode
0
0
Input
0
1
Output
1
0
Output
1
1
Output
Table 45. Port Direction Assignment Example
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
1
1
54/89
Figure 29 and Figure 31 show the Port Architecture diagrams for Ports A/B/C and E/F/G, respectively. The direction of data flow for Ports A, B, C
and F are controlled not only by the direction register, but also by the output enable product term
from the PLD AND Array. If the output enable
product term is not active, the Direction Register
has sole control of a given pin’s direction.
An example of a configuration for a Port with the
three least significant bits set to output and the remainder set to input is shown in Table 45. Since
Port D only contains four pins, the Direction Register for Port D has only the four least significant
bits active.
Drive Select Register. The Drive Select Register
configures the pin driver as Open Drain or CMOS
for some port pins, and controls the slew rate for
the other port pins. An external pull-up resistor
should be used for pins configured as Open Drain.
A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register is set to a
1. The default pin drive is CMOS.
(The slew rate is a measurement of the rise and
fall times of an output. A higher slew rate means a
faster output response and may create more electrical noise. A pin operates in a high slew rate
when the corresponding bit in the Drive Register is
set to 1. The default rate is slow slew.)
Table 46 shows the Drive Register for Ports A, B,
C, D, E, F and G. It summarizes which pins can be
configured as Open Drain outputs and which pins
the slew rate can be set for.
PSD4235G2
Table 46. Drive Register Pin Assignment
Drive
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port A
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port B
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port C
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port D
NA1
NA1
NA1
NA1
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port E
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port F
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port G
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Note: 1. NA = Not Applicable.
Table 47. Port Data Registers
Register Name
Port
MCU Access
Data In
A, B, C, D, E, F, G Read – input on pin
Data Out
A, B, C, D, E, F, G Write/Read
Output Macrocell
A, B
Read – outputs of Macrocells
Write – loading Macrocells Flip-flop
Mask Macrocell
A, B
Write/Read – prevents loading into a given
Macrocell
Input Macrocell
A, B, C
Read – outputs of the Input Macrocells
Enable Out
A, B, C, F
Read – the output enable control of the port driver
Port Data Registers. The Port Data Registers,
shown in Table 47, are used by the MCU to write
data to or read data from the ports. Table 47
shows the register name, the ports having each
register type, and MCU access for each register
type. The registers are described next.
Data In. Port pins are connected directly to the
Data In buffer. In MCU I/O Input mode, the pin input is read through the Data In buffer.
Data Out Register. Stores output data written by
the MCU in the MCU I/O Output mode. The contents of the Register are driven out to the pins if the
Direction Register or the output enable product
term is set to 1. The contents of the register can
also be read back by the MCU.
Output Macrocells (OMC). The CPLD Output
Macrocells (OMC) occupy a location in the MCU’s
address space. The MCU can read the output of
the Output Macrocells (OMC). If the Mask Macrocell Register bits are not set, writing to the Macrocell loads data to the Macrocell flip-flops. See the
section entitled “Macrocell and I/O Port”, on page
34.
Mask Macrocell Register. Each Mask Macrocell
Register bit corresponds to an Output Macrocell
(OMC) flip-flop. When the Mask Macrocell Register bit is set to a 1, loading data into the Output
Macrocell (OMC) flip-flop is blocked. The default
value is 0, or unblocked.
Input Macrocells (IMC). The Input Macrocells
(IMC) can be used to latch or store external inputs.
The outputs of the Input Macrocells (IMC) are routed to the PLD input bus, and can be read by the
MCU. See the section entitled “Input Macrocells
(IMC)”, on page 37.
55/89
PSD4235G2
Figure 29. Port A, B and C Structure
DATA OUT
Register
D
DATA OUT
Q
WR
PORT Pin
OUTPUT
MUX
MCELL7-MCELL0 (Port A)
MCELLB7-MCELLB0 (Port B)
Ext.CS (Port C)
INTERNAL DATA BUS
READ MUX
P
OUTPUT
SELECT
D
DATA IN
B
ENABLE OUT
DIR Register
D
Q
WR
ENABLE PRODUCT TERM (.OE)
INPUT
MACROCELL
CPLD - INPUT
AI04936
Enable Out. The Enable Out register can be read
by the MCU. It contains the output enable values
for a given port. A 1 indicates the driver is in output
mode. A 0 indicates the driver is in tri-state and the
pin is in input mode.
Ports A, B and C – Functionality and Structure
Ports A, B and C have similar functionality and
structure, as shown in Figure 29. The ports can be
configured to perform one or more of the following
functions:
■ MCU I/O Mode
56/89
■
CPLD Output – Macrocells McellA7-McellA0
can be connected to Port A. McellB7-McellB0
can be connected to Port B. External Chip
Select (ECS7-ECS0) can be connected to Port
C or Port F.
■
CPLD Input – Via the Input Macrocells (IMC).
■
Address In – Additional high address inputs
using the Input Macrocells (IMC).
■
Open Drain/Slew Rate – pins PC7-PC0 can be
configured to fast slew rate. Pins PA7-PA0 can
be configured to Open Drain mode.
PSD4235G2
Figure 30. Port D Structure
DATA OUT
Register
DATA OUT
D
Q
WR
PORT D PIN
OUTPUT
MUX
INTERNAL DATA BUS
READ MUX
OUTPUT
SELECT
P
D
DATA IN
B
DIR Register
D
Q
WR
CPLD - INPUT
AI04937
Port D – Functionality and Structure
Port D has four I/O pins. See Figure 30. Port D can
be configured to perform one or more of the following functions:
■ MCU I/O mode
■
■
■
In-System Programming (ISP) – JTAG port can
be enabled for programming/erase of the PSD
device. (See the section entitled “Reset
(RESET) Timing”, on page 63, for more
information on JTAG programming.)
■
Open Drain – pins can be configured in Open
Drain Mode
■
Battery Backup features
CPLD Input – direct input to the CPLD, no Input
Macrocells (IMC)
Port D pins can be configured in PSDsoft Express as input pins for other dedicated functions:
Address Strobe (ALE/AS, PD0)
■
CLKIN (PD1) as input to the Macrocells Flipflops and APD counter
■
PSD Chip Select Input (CSI, PD2). Driving this
signal High disables the Flash memory, SRAM
and CSIOP.
■
Port E – Functionality and Structure
Port E can be configured to perform one or more
of the following functions (see Figure 31):
■ MCU I/O Mode
Write Enable High-byte (WRH, PD3) input, or as
DBE input from a MC68HC912.
– PE6 can be configured for a battery input supply, Voltage Stand-by (VSTBY).
– PE7 can be configured as a Battery-on Indicator (VBATON), indicating when VCC is less
than VBAT.
■
Latched Address output – Provide latched
address output.
57/89
PSD4235G2
Figure 31. Port E, F and G Structure
DATA OUT
Register
D
Q
D
Q
DATA OUT
WR
ADDRESS
ALE
ADDRESS
PORT Pin
A[ 7:0] OR A[15:8]
G
OUTPUT
MUX
Ext. CS (Port F)
INTERNAL DATA BUS
READ MUX
P
OUTPUT
SELECT
D
DATA IN
B
CONTROL Register
D
ENABLE OUT
Q
WR
DIR Register
D
Q
WR
ENABLE PRODUCT TERM (.OE)
CPLD - INPUT (Port F)
ISP or Battery Back-Up (Port E)
Configuration Bit
AI04938
Port F – Functionality and Structure
Port F can be configured to perform one or more
of the following functions:
■ MCU I/O Mode
■
MCU Reset Mode – for 16-bit Motorola 683xx
and HC16 MCUs
Port G – Functionality and Structure
Port G can be configured to perform one or more
of the following functions:
■ MCU I/O Mode
■
CPLD Output – External Chip Select (ECS7ECS0) can be connected to Port F or Port C.
■
CPLD Input – direct input to the CPLD, no Input
Macrocells (IMC)
■
Latched Address output – Provide latched
address output as per Table 41.
■
Latched Address output – Provide latched
address output as per Table 41.
■
Open Drain – pins can be configured in Open
Drain Mode
■
Slew Rate – pins can be configured for fast Slew
Rate
■
■
Data Port – connected to D7-D0 when Port F is
configured as Data Port for a non-multiplexed
bus
Data Port – connected to D15-D8 when Port G
is configured as Data Port for a non-multiplexed
bus
■
MCU Reset Mode – for 16-bit Motorola 683xx
and HC16 MCUs
■
Peripheral Mode
58/89
PSD4235G2
POWER MANAGEMENT
The PSD device offers configurable power saving
options. These options may be used individually or
in combinations, as follows:
■ All memory blocks in a PSD (primary Flash
memory, secondary Flash memory, and SRAM)
are built with power management technology. In
addition to using special silicon design
methodology, power management technology
puts the memories into standby mode when
address/data inputs are not changing (zero DC
current). As soon as a transition occurs on an
input, the affected memory “wakes up”,
changes and latches its outputs, then goes back
to standby. The designer does not have to do
anything special to achieve memory Stand-by
mode when no inputs are changing—it happens
automatically.
■
The PLD sections can also achieve Stand-by
mode when its inputs are not changing, as described for the Power Management Mode Registers (PMMR), later.
The Automatic Power Down (APD) block allows
the PSD to reduce to stand-by current
automatically. The APD Unit also blocks MCU
address/data signals from reaching the
memories and PLDs. This feature is available
on all PSD devices. The APD Unit is described
in more detail in the section entitled “APD Unit”,
on page 60.
Built in logic monitors the Address Strobe of the
MCU for activity. If there is no activity for a certain period (the MCU is asleep), the APD Unit
initiates Power-down mode (if enabled). Once in
Power-down mode, all address/data signals are
blocked from reaching the PSD memories and
PLDs, and the memories are deselected internally. This allows the memories and PLDs to remain in Stand-by mode even if the address/data
signals are changing state externally (noise,
other devices on the MCU bus, etc.). Keep in
■
■
mind that any unblocked PLD input signals that
are changing states keeps the PLD out of
Stand-by mode, but not the memories.
PSD Chip Select Input (CSI, PD2) can be used
to disable the internal memories, placing them
in Stand-by mode even if inputs are changing.
This feature does not block any internal signals
or disable the PLDs. This is a good alternative
to using the APD Unit, especially if your MCU
has a chip select output. There is a slight
penalty in memory access time when PSD Chip
Select Input (CSI, PD2) makes its initial
transition from deselected to selected.
The Power Management Mode Registers
(PMMR) can be written by the MCU at run-time
to manage power. All PSD devices support
“blocking bits” in these registers that are set to
block designated signals from reaching both
PLDs. Current consumption of the PLDs is
directly related to the composite frequency of
the changes on their inputs (see Figure 35).
Significant power savings can be achieved by
blocking signals that are not used in DPLD or
CPLD logic equations at run-time. PSDsoft Express creates a fuse map that automatically
blocks the low address byte (A7-A0) or the control signals (CNTL0-CNTL2, ALE and Write Enable High-byte (WRH/DBE, PD3)) if none of
these signals are used in PLD logic equations.
PSD devices have a Turbo bit in PMMR0. This
bit can be set to turn the Turbo mode off (the default is with Turbo mode turned on). While Turbo
mode is off, the PLDs can achieve Stand-by current when no PLD inputs are changing (zero DC
current). Even when inputs do change, significant power can be saved at lower frequencies
(AC current), compared to when Turbo mode is
on. When the Turbo mode is on, there is a significant DC current component, and the AC
component is higher.
59/89
PSD4235G2
Figure 32. APD Unit
APD EN
PMMR0 BIT 1=1
TRANSITION
DETECTION
DISABLE BUS
INTERFACE
ALE
CLR
Secondary Flash
Memory Select
Primary Flash
Memory Select
APD
COUNTER
RESET
CSI
PD
EDGE
DETECT
PD
PLD
CLKIN
SRAM Select
POWER DOWN
(PDN) Select
DISABLE Primary and Secondary
FLASH Memory and SRAM
AI04939
Automatic Power-down (APD) Unit and Powerdown Mode. The APD Unit, shown in Figure 32,
puts the PSD into Power-down mode by monitoring the activity of Address Strobe (ALE/AS, PD0).
If the APD Unit is enabled, as soon as activity on
Address Strobe (ALE/AS, PD0) stops, a four bit
counter starts counting. If Address Strobe (ALE/
AS, PD0) remains inactive for fifteen clock periods
of CLKIN (PD1), Power-down (PDN) goes High,
and the PSD enters Power-down mode, as discussed next.
■
If Address Strobe (ALE/AS, PD0) starts pulsing
again, the PSD returns to normal operation. The
PSD also returns to normal operation if either
PSD Chip Select Input (CSI, PD2) is Low or the
Reset (RESET) input is High.
■
The MCU address/data bus is blocked from all
memory and PLDs.
■
Various signals can be blocked (prior to Powerdown mode) from entering the PLDs by setting
the appropriate bits in the Power Management
Mode Registers (PMMR). The blocked signals
include MCU control signals and the common
CLKIN (PD1). Note that blocking CLKIN (PD1)
from the PLDs does not block CLKIN (PD1)
from the APD Unit.
■
All PSD memories enter Stand-by mode and are
drawing Stand-by current. However, the PLDs
and I/O ports blocks do not go into Stand-by
mode because you do not want to have to wait
for the logic and I/O to “wake-up” before their
outputs can change. See Table 48 for Powerdown mode effects on PSD ports.
■
Typical Stand-by current is or the order of µA.
This Stand-by current value assumes that there
are no transitions on any PLD input.
Table 48. Effect of Power-down Mode on Ports
Port Function
Pin Level
MCU I/O
No Change
PLD Out
No Change
Address Out
Undefined
Data Port
Tri-State
Peripheral I/O
Tri-State
Power-down Mode. By default, if you enable the
APD Unit, Power-down mode is automatically enabled. The device enters Power-down mode if Address Strobe (ALE/AS, PD0) remains inactive for
fifteen periods of CLKIN (PD1).
The following should be kept in mind when the
PSD is in Power-down mode:
Table 49. PSD Timing and Stand-by Current during Power-down Mode
Mode
Power-down
PLD Propagation Delay
Normal tPD (Note 1)
Memory Access
Time
Access Recovery Time to
Normal Access
Typical Stand-by
Current
No Access
tLVDV
ISB (Note 2)
Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo bit.
2. Typical current consumption, see Table 60, assuming no PLD inputs are changing state and the PLD Turbo bit is 0.
60/89
PSD4235G2
Figure 33. Enable Power-down Flow Chart
RESET
Enable APD
Set PMMR0 Bit 1 = 1
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 0 to 6.
No
ALE/AS idle
for 15 CLKIN
clocks?
Yes
PSD in Power
Down Mode
AI04940
Other Power Saving Options. The PSD offers
other reduced power saving options that are independent of the Power-down mode. Except for the
SRAM Stand-by and PSD Chip Select Input (CSI,
PD2) features, they are enabled by setting bits in
PMMR0 and PMMR2 (as summarised in Table 23
and Table 24).
PLD Power Management
The power and speed of the PLDs are controlled
by the Turbo bit (bit 3) in PMMR0. By setting the
bit to 1, the Turbo mode is off and the PLDs consume the specified Stand-by current when the inputs are not switching for an extended time of
70 ns. The propagation delay time is increased after the Turbo bit is set to 1 (turned off) when the inputs change at a composite frequency of less than
15 MHz. When the Turbo bit is reset to 0 (turned
on), the PLDs run at full power and speed. The
Turbo bit affects the PLD’s DC power, AC power,
and propagation delay. See the AC and DC characteristics tables for PLD timing values (Table 67).
Blocking MCU control signals with the PMMR2 bits
can further reduce PLD AC power consumption.
SRAM Stand-by Mode (Battery Backup). The
PSD supports a battery backup mode in which the
contents of the SRAM are retained in the event of
a power loss. The SRAM has Voltage Stand-by
(VSTBY, PE6) that can be connected to an external battery. When VCC becomes lower than V STBY
then the PSD automatically connects to Voltage
Stand-by (VSTBY, PE6) as a power source to the
SRAM. The SRAM Stand-by current (I STBY) is typically 0.5 µA. The SRAM data retention voltage is
2 V minimum. The Battery-on Indicator (VBATON)
can be routed to PE7. This signal indicates when
the VCC has dropped below V STBY, and that the
SRAM is running on battery power.
PSD Chip Select Input (CSI, PD2)
PD2 of Port D can be configured in PSDsoft Express as PSD Chip Select Input (CSI). When Low,
the signal selects and enables the internal primary
Flash memory, secondary Flash memory, SRAM,
and I/O blocks for Read or Write operations involving the PSD. A High on PSD Chip Select Input
(CSI, PD2) disables the primary Flash memory,
secondary Flash memory, and SRAM, and reduces the PSD power consumption. However, the
PLD and I/O signals remain operational when PSD
Chip Select Input (CSI, PD2) is High.
There may be a timing penalty when using PSD
Chip Select Input (CSI, PD2) depending on the
speed grade of the PSD that you are using. See
the timing parameter tSLQV in Table 67.
Input Clock. The PSD provides the option to turn
off CLKIN (PD1) to the PLD to save AC power consumption. CLKIN (PD1) is an input to the PLD
AND Array and the Output Macrocells (OMC).
During Power-down mode, or, if CLKIN (PD1) is
not being used as part of the PLD logic equation,
the clock should be disabled to save AC power.
CLKIN (PD1) is disconnected from the PLD AND
Array or the Macrocells block by setting bits 4 or 5
to a 1 in PMMR0.
Table 50. APD Counter Operation
APD Enable Bit
ALE PD Polarity
ALE Level
APD Counter
0
X
X
Not Counting
1
X
Pulsing
Not Counting
1
1
1
Counting (Generates PDN after 15 Clocks)
1
0
0
Counting (Generates PDN after 15 Clocks)
61/89
PSD4235G2
Input Control Signals. The PSD provides the
option to turn off the address input (A7-A0) and input control signals (CNTL0, CNTL1, CNTL2, Address Strobe (ALE/AS, PD0) and Write Enable
High-byte (WRH/DBE, PD3)) to the PLD to save
AC power consumption. These signals are inputs
to the PLD AND Array. During Power-down mode,
or, if any of them are not being used as part of the
PLD logic equation, these control signals should
be disabled to save AC power. They are disconnected from the PLD AND Array by setting bits 0,
2, 3, 4, 5 and 6 to a 1 in PMMR2.
Power On Reset, Warm Reset and Power-down
Power On Reset. Upon Power-up, the PSD requires a Reset (RESET) pulse of duration tNLNHPO (minimum 1 ms) after VCC is steady. During
this period, the device loads internal configurations, clears some of the registers and sets the
Flash memory into Operating mode. After the rising edge of Reset (RESET), the PSD remains in
the Reset mode for an additional period, t OPR
(maximum 120 ns), before the first memory access is allowed.
The PSD Flash memory is reset to the Read mode
upon Power-up. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must all be Low, Write
Strobe (WR/WRL, CNTL0) High, during Power On
Reset for maximum security of the data contents
and to remove the possibility of data being written
on the first edge of Write Strobe (WR/WRL,
CNTL0). Any Flash memory Write cycle initiation
is prevented automatically when V CC is below VLKO.
Warm Reset. Once the device is up and running,
the device can be reset with a pulse of a much
shorter duration, tNLNH (minimum 150 ns). The
same t OPR period is needed before the device is
operational after warm reset. Figure 34 shows the
timing of the Power-up and warm reset.
I/O Pin, Register and PLD Status at Reset. Table 51 shows the I/O pin, register and PLD status
during Power On Reset, warm reset and Powerdown mode. PLD outputs are always valid during
warm reset, and they are valid in Power On Reset
once the internal PSD Configuration bits are loaded. This loading of PSD is completed typically long
before the VCC ramps up to operating level. Once
the PLD is active, the state of the outputs are determined by equations specified in PSDsoft Express.
Reset of Flash Memory Erase and Program Cycles. An external Reset (RESET) also resets the
internal Flash memory state machine. During a
Flash memory Program or Erase cycle, Reset
(RESET) terminates the cycle and returns the
Flash memory to the Read mode within a period of
tNLNH-A (minimum 25 µs).
Table 51. Status During Power-On Reset, Warm Reset and Power-down Mode
Port Configuration
Power-On Reset
Warm Reset
Power-down Mode
MCU I/O
Input mode
Input mode
Unchanged
PLD Output
Valid after internal PSD
configuration bits are
loaded
Valid
Depends on inputs to PLD
(addresses are blocked in
PD mode)
Address Out
Tri-stated
Tri-stated
Not defined
Data Port
Tri-stated
Tri-stated
Tri-stated
Peripheral I/O
Tri-stated
Tri-stated
Tri-stated
Register
Power-On Reset
Warm Reset
Power-down Mode
PMMR0 and PMMR2
Cleared to 0
Unchanged
Unchanged
Macrocells Flip-flop status
Cleared to 0 by internal
Power-On Reset
Depends on .re and .pr
equations
Depends on .re and .pr
equations
Initialized, based on the
selection in PSDsoft
Express
Configuration menu
Initialized, based on the
selection in PSDsoft
Express
Configuration menu
Unchanged
Cleared to 0
Cleared to 0
Unchanged
VM
Register1
All other registers
Note: 1. The SR_code and Peripheral Mode bits in the VM Register are always cleared to 0 on Power-On Reset or Warm Reset.
62/89
PSD4235G2
Figure 34. Reset (RESET) Timing
VCC
VCC(min)
tNLNH-PO
tNLNH
tNLNH-A
tOPR
Power-On Reset
tOPR
Warm Reset
RESET
AI02866b
Programming In-Circuit using the JTAG Serial
Interface
The JTAG Serial Interface on the PSD can be enabled on Port E (see Table 52). All memory blocks
(primary Flash memory and secondary Flash
memory), PLD logic, and PSD Configuration bits
may be programmed through the JTAG-ISC Serial
Interface. A blank device can be mounted on a
printed circuit board and programmed using JTAG
In-System Programming (ISP).
The standard JTAG signals (IEEE 1149.1) are
TMS, TCK, TDI, and TDO. Two additional signals,
TSTAT and TERR, are optional JTAG extensions
used to speed up Program and Erase cycles.
By default, on a blank PSD (as shipped from the
factory, or after erasure), four pins on Port E are
enabled for the basic JTAG signals TMS, TCK,
TDI, and TDO .
See Application Note AN1153 for more details on
JTAG In-System Programming (ISP).
Standard JTAG Signals. The standard JTAG
signals (TMS, TCK, TDI, and TDO) can be enabled by any of three different conditions that are
logically ORed. When enabled, TDI, TDO, TCK,
and TMS are inputs, waiting for a serial command
from an external JTAG controller device (such as
FlashLINK or Automated Test Equipment). When
the enabling command is received from the external JTAG controller device, TDO becomes an output and the JTAG channel is fully functional inside
the PSD. The same command that enables the
JTAG channel may optionally enable the two additional JTAG pins, TSTAT and TERR.
The following symbolic logic equation specifies the
conditions enabling the four basic JTAG pins
(TMS, TCK, TDI, and TDO) on their respective
Port E pins. For purposes of discussion, the logic
label JTAG_ON is used. When JTAG_ON is true,
the four pins are enabled for JTAG. When
JTAG_ON is false, the four pins can be used for
general PSD I/O.
JTAG_ON = PSDsoft Express_enabled +
/* An NVM configuration bit inside the
PSD is set by the designer in the
PSDsoft Express Configuration utility.
This dedicates the pins for JTAG at all
times (compliant with IEEE 1149.1 */
Microcontroller_enabled +
/* The microcontroller can set a bit at
run-time
by
writing
to
the
PSD
register, JTAG Enable. This register
is located at address CSIOP + offset
C7h. Setting the JTAG_ENABLE bit in
this register will enable the pins for
JTAG use. This bit is cleared by a PSD
reset or the microcontroller. See
Table 21 for bit definition. */
PSD_product_term_enabled;
/* A dedicated product term (PT) inside
the PSD can be used to enable the JTAG
pins. This PT has the reserved name
JTAGSEL. Once defined as a node in
PSDabel, the designer can write an
equation for JTAGSEL. This method is
used when the Port E JTAG pins are
multiplexed with other I/O signals. It
is recommended to tie logically the
node JTAGSEL to the JEN\ signal on the
Flashlink cable when multiplexing JTAG
signals. See Application Note 1153 for
details. */
The state of the PSD Reset (RESET) signal does
not interrupt (or prevent) JTAG operations if the
JTAG pins are dedicated by an NVM configuration
bit (via PSDsoft Express). However, Reset (RESET) will prevent or interrupt JTAG operations if
the JTAG Enable Register (as shown in Table 21)
is used to enable the JTAG pins.
The PSD supports JTAG In-System-Programmability (ISP) commands, but not Boundary Scan.
ST’s PSDsoft Express software tool and
FlashLINK JTAG programming cable implement
the JTAG In-System-Programmability (ISP) commands.
Table 52. JTAG Port Signals
Port E Pin
JTAG Signals
Description
PE0
TMS
Mode Select
PE1
TCK
Clock
PE2
TDI
Serial Data In
PE3
TDO
Serial Data Out
63/89
PSD4235G2
Port E Pin
JTAG Signals
Description
PE4
TSTAT
Status
PE5
TERR
Error Flag
JTAG Extensions. TSTAT and TERR are two
JTAG extension signals enabled by a JTAG command received over the four standard JTAG pins
(TMS, TCK, TDI, and TDO). They are used to
speed Program and Erase cycles by indicating
status on PSD pins instead of having to scan the
status out serially using the standard JTAG channel. See Application Note AN1153.
TERR indicates if an error has occurred when
erasing a sector or programming in Flash memory.
This signal goes Low (active) when an Error condition occurs, and stays Low until a specific JTAG
command is executed or a Reset (RESET) pulse
is received after an “ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy (PE4)
described in the section entitled “Ready/Busy
(PE4)”, on page 21. TSTAT is High when the
PSD4235G2 device is in Read mode (primary
Flash memory and secondary Flash memory contents can be read). TSTAT is Low when Flash
memory Program or Erase cycles are in progress,
INITIAL DELIVERY STATE
When delivered from ST, the PSD device has all
bits in the memory and PLDs set to 1. The PSD
Configuration Register bits are set to 0. The code,
configuration, and PLD logic are loaded using the
64/89
and also when data is being written to the secondary Flash memory .
TSTAT and TERR can be configured as opendrain type signals with a JTAG command.
Note: The state of Reset (Reset) does not interrupt
(or prevent) JTAG operations if the JTAG signals
are dedicated by an NVM Configuration bit (via
PSDsoft Express). However, Reset (Reset) prevents or interrupts JTAG operations if the JTAG
Enable Register (as shown in Table 21) is used to
enable the JTAG signals.
Security and Flash memory Protection. When
the security bit is set, the device cannot be read on
a Device Programmer or through the JTAG Port.
When using the JTAG Port, only a Full Chip Erase
command is allowed.
All other Program, Erase and Verify commands
are blocked. Full Chip Erase returns the device to
a non-secured blank state. The Security Bit can be
set in PSDsoft Express.
All primary Flash memory and secondary Flash
memory sectors can individually be sector protected against erasure. The sector protect bits can be
set in PSDsoft Express.
programming procedure. Information for programming the device is available directly from ST.
Please contact your local sales representative.
PSD4235G2
AC/DC PARAMETERS
These tables describe the AD and DC parameters
of the PSD4235G2:
❏ DC Electrical Specification
❏ AC Timing Specification
■ PLD Timing
– Combinatorial Timing
– Synchronous Clock Mode
– Asynchronous Clock Mode
– Input Macrocell Timing
■
– Power-down and Reset Timing
The following are issues concerning the parameters presented:
■ In the DC specification the supply current is
given for different modes of operation. Before
calculating the total power consumption,
determine the percentage of time that the PSD
is in each mode. Also, the supply power is
considerably different if the Turbo bit is 0.
■
The AC power component gives the PLD, Flash
memory, and SRAM mA/MHz specification.
Figure 35 show the PLD mA/MHz as a function
of the number of Product Terms (PT) used.
■
In the PLD timing parameters, add the required
delay when Turbo bit is 0.
MCU Timing
– Read Timing
– Write Timing
– Peripheral Mode Timing
Figure 35. PLD ICC /Frequency Consumption
110
100
Vcc = 5V
90
80
TURBO ON (100%)
70
Icc - (mA)
TURBO OFF
60
50
TURBO ON (25%)
40
30
20
PT 100%
PT 25%
TURBO OFF
10
0
0
5
10
15
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
AI05739
65/89
PSD4235G2
Table 53. Example of PSD Typical Power Calculation at VCC = 5.0 V (with Turbo Mode On)
Conditions
Highest Composite PLD input frequency
(Freq PLD)
MCU ALE frequency (Freq ALE)
= 8 MHz
= 4 MHz
% Flash memory
Access
= 80%
% SRAM access
= 15%
% I/O access
= 5% (no additional power above base)
Operational Modes
% Normal
= 10%
% Power-down Mode
= 90%
Number of product terms used
Turbo Mode
(from fitter report)
= 45 PT
% of total product terms
= 45/193 = 23.3%
= ON
Calculation (using typical values)
ICC total
= Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE
+ %SRAM x 1.5 mA/MHz x Freq ALE
+ % PLD x 2 mA/MHz x Freq PLD
+ #PT x 400 µA/PT)
= 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz
+ 0.15 x 1.5 mA/MHz x 4 MHz
+ 2 mA/MHz x 8 MHz
+ 45 x 0.4 mA/PT)
= 45 µA + 0.1 x (8 + 0.9 + 16 + 18 mA)
= 45 µA + 0.1 x 42.9
= 45 µA + 4.29 mA
= 4.34 mA
This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based on IOUT
= 0 mA.
66/89
PSD4235G2
Table 54. Example of PSD Typical Power Calculation at VCC = 5.0 V (with Turbo Mode Off)
Conditions
Highest Composite PLD input frequency
(Freq PLD)
MCU ALE frequency (Freq ALE)
= 8 MHz
= 4 MHz
% Flash memory
Access
= 80%
% SRAM access
= 15%
% I/O access
= 5% (no additional power above base)
Operational Modes
% Normal
= 10%
% Power-down Mode
= 90%
Number of product terms used
Turbo Mode
(from fitter report)
= 45 PT
% of total product terms
= 45/193 = 23.3%
= Off
Calculation (using typical values)
ICC total
= Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE
+ %SRAM x 1.5 mA/MHz x Freq ALE
+ % PLD x (from graph using Freq PLD))
= 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz
+ 0.15 x 1.5 mA/MHz x 4 MHz
+ 24 mA)
= 45 µA + 0.1 x (8 + 0.9 + 24)
= 45 µA + 0.1 x 32.9
= 45 µA + 3.29 mA
= 3.34 mA
This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based on IOUT
= 0 mA.
67/89
PSD4235G2
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 55. Absolute Maximum Ratings
Symbol
Parameter
TSTG
Storage Temperature
TLEAD
Lead Temperature during Soldering (20 seconds max.)1
Max.
Unit
–65
125
°C
235
°C
VIO
Input and Output Voltage (Q = VOH or Hi-Z)
–0.6
7.0
V
VCC
Supply Voltage
–0.6
7.0
V
VPP
Device Programmer Supply Voltage
–0.6
14.0
V
VESD
Electrostatic Discharge Voltage (Human Body model) 2
–2000
2000
V
Note: 1. IPC/JEDEC J-STD-020A
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
68/89
Min.
PSD4235G2
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC
and AC Characteristic tables that follow are derived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parameters.
Table 56. Operating Conditions
Symbol
VCC
Parameter
Min.
Max.
Unit
Supply Voltage
4.5
5.5
V
Ambient Operating Temperature (industrial)
–40
85
°C
0
70
°C
TA
Ambient Operating Temperature (commercial)
Table 57. AC Symbols for PLD Timing
Signal Letters
Signal Behavior
A
Address Input
t
Time
C
CEout Output
L
Logic Level Low or ALE
D
Input Data
H
Logic Level High
E
E Input
V
Valid
G
Internal WDOG_ON signal
X
No Longer a Valid Logic Level
I
Interrupt Input
Z
Float
L
ALE Input
N
Reset Input or Output
P
Port Signal Output
Q
Output Data
R
WR, UDS, LDS, DS, IORD, PSEN Inputs
S
Chip Select Input
T
R/W Input
W
Internal PDN Signal
B
VSTBY Output
M
Output Macrocell
PW
Pulse Width
Example: tAVLX – Time from Address Valid to ALE Invalid.
69/89
PSD4235G2
Table 58. AC Measurement Conditions
Symbol
CL
Parameter
Min.
Load Capacitance
Max.
30
Unit
pF
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Table 59. Capacitance
Symbol
Parameter
Test Condition
Typ.2
Max.
Unit
CIN
Input Capacitance (for input pins)
VIN = 0V
4
6
pF
COUT
Output Capacitance (for input/
output pins)
VOUT = 0V
8
12
CVPP
Capacitance (for CNTL2/VPP)
VPP = 0V
18
25
pF
pF
Note: 1. Sampled only, not 100% tested.
2. Typical values are for T A = 25°C and nominal supply voltages.
Figure 36. AC Measurement I/O Waveform
Figure 37. AC Measurement Load Circuit
2.01 V
195 Ω
3.0V
Test Point
1.5V
Device
Under Test
0V
CL = 30 pF
(Including Scope and
Jig Capacitance)
AI03103b
AI03104b
Figure 38. Switching Waveforms – Key
WAVEFORMS
INPUTS
OUTPUTS
STEADY INPUT
STEADY OUTPUT
MAY CHANGE FROM
HI TO LO
WILL BE CHANGING
FROM HI TO LO
MAY CHANGE FROM
LO TO HI
WILL BE CHANGING
LO TO HI
DON'T CARE
CHANGING, STATE
UNKNOWN
OUTPUTS ONLY
CENTER LINE IS
TRI-STATE
AI03102
70/89
PSD4235G2
Table 60. DC Characteristics
Symbol
Parameter
Test Condition
(in addition to those in
Table 56)
Min.
Typ.
Max.
Unit
VIH
Input High Voltage
4.5 V < VCC < 5.5 V
2
VCC +0.5
V
VIL
Input Low Voltage
4.5 V < VCC < 5.5 V
–0.5
0.8
V
VIH1
Reset High Level Input Voltage
(Note 1)
0.8VCC
VCC +0.5
V
VIL1
Reset Low Level Input Voltage
(Note 1)
–0.5
0.2VCC –0.1
V
VHYS
Reset Pin Hysteresis
0.3
VLKO
VCC (min) for Flash Erase and
Program
2.5
VOL
V
V
IOL = 20 µA, VCC = 4.5 V
0.01
0.1
V
IOL = 8 mA, VCC = 4.5 V
0.25
0.45
V
Output Low Voltage
Output High Voltage Except
VSTBY On
VOH
IOH = –20 µA, VCC = 4.5 V
4.4
4.49
V
IOH = –2 mA, VCC = 4.5 V
2.4
3.9
V
IOH1 = 1 µA
VSTBY – 0.8
VOH1
Output High Voltage VSTBY On
VSTBY
SRAM Stand-by Voltage
ISTBY
SRAM Stand-by Current
IIDLE
Idle Current (VSTBY input)
VDF
SRAM Data Retention Voltage
ISB
Stand-by Supply Current
for Power-down Mode
CSI >VCC –0.3 V (Notes 2,3)
ILI
Input Leakage Current
VSS < VIN < VCC
ILO
Output Leakage Current
0.45 < VOUT < VCC
PLD Only
ICC (DC)
(Note 5)
Operating
Supply
Current
Flash memory
SRAM
V
2.0
VCC = 0 V
0.5
VCC > VSTBY
–0.1
Only on VSTBY
2
ICC (AC)
(Note 5)
VCC
V
1
µA
0.1
µA
V
100
200
µA
–1
±0.1
1
µA
–10
±5
10
µA
PLD_TURBO = Off,
f = 0 MHz (Note 5)
0
PLD_TURBO = On,
f = 0 MHz
400
700
µA/PT
During Flash memory Write/
Erase Only
15
30
mA
Read Only, f = 0 MHz
0
0
mA
f = 0 MHz
0
0
mA
µA/PT
note 4
PLD AC Adder
Note: 1.
2.
3.
4.
4.2
Flash memory AC Adder
2.5
3.5
mA/
MHz
SRAM AC Adder
1.5
3.0
mA/
MHz
Reset (Reset) has hysteresis. VIL1 is valid at or below 0.2VCC –0.1. VIH1 is valid at or above 0.8VCC .
CSI deselected or internal Power-down mode is active.
PLD is in non-Turbo mode, and none of the inputs are switching.
Please see Figure 35 for the PLD current calculation.
71/89
PSD4235G2
Table 61. CPLD Combinatorial Timing
-70
Symbol
Parameter
-90
Conditions
Min
Max
Min
Max
tPD
CPLD Input Pin/
Feedback to CPLD
Combinatorial Output
20
25
tEA
CPLD Input to CPLD
Output Enable
21
tER
CPLD Input to CPLD
Output Disable
tARP
CPLD Register Clear
or Preset Delay
tARPW
CPLD Register Clear
or Preset Pulse Width
tARD
CPLD Array Delay
Fast
Turbo Slew
PT
Off
rate1
Aloc
+ 12
–2
ns
26
+ 12
–2
ns
21
26
+ 12
–2
ns
21
26
+ 12
–2
ns
10
+2
20
Any
Macrocell
Unit
+ 12
11
16
+2
Max
Fast
PT
Aloc
ns
ns
Note: 1. Fast Slew Rate output available on Port C and Port F.
Table 62. CPLD Macrocell Synchronous Clock Mode Timing
-70
Symbol
Parameter
Min
fMAX
-90
Conditions
Max
Min
Turbo Slew
Off
rate1
Unit
Maximum Frequency
External Feedback
1/(tS+tCO)
34.4
30.30
MHz
Maximum Frequency
Internal Feedback
(fCNT)
1/(tS+tCO–10)
52.6
43.48
MHz
Maximum Frequency
Pipelined Data
1/(tCH+tCL)
83.3
50.00
MHz
tS
Input Setup Time
14
15
tH
Input Hold Time
0
0
ns
tCH
Clock High Time
Clock Input
6
10
ns
tCL
Clock Low Time
Clock Input
6
10
ns
tCO
Clock to Output
Delay
Clock Input
15
18
tARD
CPLD Array Delay
Any Macrocell
11
16
tMIN
Minimum Clock
Period 2
tCH+tCL
12
Note: 1. Fast Slew Rate output available on Port C and Port F.
2. CLKIN (PD1) t CLCL = tCH + tCL .
72/89
20
+2
+ 12
ns
–2
+2
ns
ns
ns
PSD4235G2
Table 63. CPLD Macrocell Asynchronous Clock Mode Timing
-70
Symbol
Parameter
Min
fMAXA
-90
Conditions
Max
Min
Max
PT Turbo Slew
Aloc
Off
Rate
Unit
Maximum
Frequency
External
Feedback
1/(tSA+tCOA)
38.4
26.32
MHz
Maximum
Frequency
Internal
Feedback
(fCNTA)
1/(tSA+tCOA–10)
62.5
35.71
MHz
1/(tCHA+tCLA)
47.6
37.03
MHz
Maximum
Frequency
Pipelined Data
tSA
Input Setup
Time
6
8
tHA
Input Hold Time
7
12
tCHA
Clock Input
High Time
9
12
+ 12
ns
tCLA
Clock Input Low
Time
12
15
+ 12
ns
tCOA
Clock to Output
Delay
tARDA
CPLD Array
Delay
tMINA
Minimum Clock
Period
Any Macrocell
1/fCNTA
16
+2
ns
ns
21
30
11
16
28
+ 12
+ 12
+2
–2
ns
ns
ns
73/89
PSD4235G2
Figure 39. Input to Output Disable / Enable
INPUT
tER
tEA
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
Figure 40. Asynchronous Reset / Preset
tARPW
RESET/PRESET
INPUT
tARP
REGISTER
OUTPUT
AI02864
Figure 41. Synchronous Clock Mode Timing – PLD
tCH
tCL
CLKIN
tS
tH
INPUT
tCO
REGISTERED
OUTPUT
AI02860
Figure 42. Asynchronous Clock Mode Timing (product term clock)
tCHA
tCLA
CLOCK
tSA
tHA
INPUT
tCOA
REGISTERED
OUTPUT
AI02859
74/89
PSD4235G2
Table 64. Input Macrocell Timing
-70
Symbol
Parameter
-90
Conditions
Min
Max
Min
Max
PT
Aloc
Turbo
Off
Unit
tIS
Input Setup Time
(Note 1)
0
0
tIH
Input Hold Time
(Note 1)
15
20
tINH
NIB Input High Time
(Note 1)
9
12
ns
tINL
NIB Input Low Time
(Note 1)
9
12
ns
tINO
NIB Input to Combinatorial
Delay
(Note 1)
34
ns
+ 12
46
+2
+ 12
ns
ns
Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to t AVLX and tLXAX .
Figure 43. Input Macrocell Timing (product term clock)
t INH
t INL
PT CLOCK
t IS
t IH
INPUT
OUTPUT
t INO
AI03101
75/89
PSD4235G2
Table 65. Read Timing
-70
Symbol
Parameter
Min
tLVLX
ALE or AS Pulse Width
tAVLX
Address Setup Time
tLXAX
-90
Conditions
Max
Min
Max
Turbo
Off
Unit
15
20
ns
(Note 3)
4
6
ns
Address Hold Time
(Note 3)
7
8
ns
tAVQV
Address Valid to Data Valid
(Note 3)
tSLQV
CS Valid to Data Valid
70
90
+ 12
ns
75
100
ns
RD to Data Valid 8-Bit Bus
(Note 5)
24
32
ns
RD or PSEN to Data Valid
8-Bit Bus, 8031, 80251
(Note 2)
31
38
ns
tRHQX
RD Data Hold Time
(Note 1)
0
0
ns
tRLRH
RD Pulse Width
(Note 1)
27
32
ns
tRHQZ
RD to Data High-Z
(Note 1)
tEHEL
E Pulse Width
27
32
ns
tTHEH
R/W Setup Time to Enable
6
10
ns
tELTL
R/W Hold Time After Enable
0
0
ns
tAVPV
Address Input Valid to
Address Output Delay
tRLQV
Note: 1.
2.
3.
4.
5.
76/89
(Note 4)
20
25
20
RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
RD and PSEN have the same timing.
Any input used to select an internal PSD function.
In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
RD timing has the same timing as DS, LDS, and UDS signals.
25
ns
ns
PSD4235G2
Figure 44. Read Timing
tAVLX
1
tLXAX
ALE /AS
tLVLX
A /D
MULTIPLEXED
BUS
ADDRESS
VALID
DATA
VALID
tAVQV
ADDRESS
NON-MULTIPLEXED
BUS
ADDRESS
VALID
DATA
NON-MULTIPLEXED
BUS
DATA
VALID
tSLQV
CSI
tRLQV
tRHQX
tRLRH
RD
(PSEN, DS)
tRHQZ
tEHEL
E
tTHEH
tELTL
R/W
tAVPV
ADDRESS OUT
AI02895
Note: 1. tAVLX and tLXAX are not required for 80C251 in Page Mode or 80C51XA in Burst Mode.
77/89
PSD4235G2
Table 66. Write Timing
-70
Symbol
Parameter
Unit
Min
tLVLX
ALE or AS Pulse Width
tAVLX
Address Setup Time
tLXAX
Address Hold Time
tAVWL
Address Valid to Leading
Edge of WR
tSLWL
-90
Conditions
Max
Min
Max
15
20
ns
(Note 1)
4
6
ns
(Note 1)
7
8
ns
(Notes 1,3)
8
15
ns
CS Valid to Leading Edge of WR
(Note 3)
12
15
ns
tDVWH
WR Data Setup Time
(Note 3)
25
35
ns
tWHDX
WR Data Hold Time
(Note 3,7)
4
5
ns
tWLWH
WR Pulse Width
(Note 3)
28
35
ns
tWHAX1
Trailing Edge of WR to Address Invalid
(Note 3)
6
8
ns
tWHAX2
Trailing Edge of WR to DPLD Address
Invalid
(Note 3,6)
0
0
ns
tWHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
tDVMV
(Note 3)
27
30
ns
Data Valid to Port Output Valid
Using Macrocell Register
Preset/Clear
(Notes 3,5)
42
55
ns
tAVPV
Address Input Valid to Address
Output Delay
(Note 2)
20
25
ns
tWLMV
WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear
(Notes 3,4)
48
55
ns
Note: 1.
2.
3.
4.
5.
6.
7.
78/89
Any input used to select an internal PSD function.
In multiplexed mode, latched address generated from ADIO delay to address output on any port.
WR has the same timing as E, DS, LDS, UDS, WRL, and WRH signals.
Assuming data is stable before active write signal.
Assuming write is active before data becomes valid.
tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
tWHAX is 6 ns when writing to the Output Macrocell Registers AB and BC.
PSD4235G2
Figure 45. Write Timing
tAVLX
t LXAX
ALE / AS
t LVLX
A/D
MULTIPLEXED
BUS
ADDRESS
VALID
DATA
VALID
tAVWL
ADDRESS
NON-MULTIPLEXED
BUS
ADDRESS
VALID
DATA
NON-MULTIPLEXED
BUS
DATA
VALID
tSLWL
CSI
tDVWH
t WLWH
WR
(DS)
t WHDX
t WHAX
t EHEL
E
t THEH
t ELTL
R/ W
t WLMV
tAVPV
t WHPV
ADDRESS OUT
STANDARD
MCU I/O OUT
AI02896
79/89
PSD4235G2
Table 67. Port F Peripheral Data Mode Read Timing
-70
-90
Unit
Max
Turbo
Off
30
35
+ 12
ns
25
35
+ 12
ns
21
32
ns
RD to Data Valid 8031 Mode
31
38
ns
tDVQV–PF
Data In to Data Out Valid
22
30
ns
tQXRH–PF
RD Data Hold Time
tRLRH–PF
RD Pulse Width
(Note 1)
tRHQZ–PF
RD to Data High-Z
(Note 1)
Symbol
Parameter
Conditions
Min
tAVQV–PF
Address Valid to Data
Valid
tSLQV–PF
CSI Valid to Data Valid
tRLQV–PF
(Note 3)
(Notes 1,4)
RD to Data Valid
Max
Min
0
0
ns
27
32
ns
23
25
ns
Figure 46. Peripheral I/O Read Timing
ALE /AS
A/D BUS
ADDRESS
DATA VALID
tAVQV (PF)
tSLQV (PF)
CSI
tRLQV (PF)
RD
tQXRH (PF)
tRHQZ (PF)
tRLRH (PF)
tDVQV (PF)
DATA ON PORT F
AI05740
80/89
PSD4235G2
Table 68. Port F Peripheral Data Mode Write Timing
-70
Symbol
Parameter
-90
Conditions
Unit
Min
Max
Min
Max
tWLQV–PF
WR to Data Propagation Delay
(Note 2)
25
35
ns
tDVQV–PF
Data to Port F Data Propagation Delay
(Note 5)
22
30
ns
tWHQZ–PF
WR Invalid to Port F Tri-state
(Note 2)
20
25
ns
Note: 1.
2.
3.
4.
5.
RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
Any input used to select Port F Data Peripheral mode.
Data is already stable on Port F.
Data stable on ADIO pins to data on Port F.
Figure 47. Peripheral I/O Write Timing
ALE /AS
A / D BUS
ADDRESS
DATA OUT
tWLQV
tWHQZ (PF)
(PF)
WR
tDVQV (PF)
PORT F
DATA OUT
AI05741
81/89
PSD4235G2
Table 69. Reset (Reset)Timing
Symbol
Parameter
tNLNH
RESET Active Low Time 1
tNLNH–PO
Conditions
Min
Max
Unit
150
ns
Power On Reset Active Low Time
1
ms
tNLNH–A
Warm Reset 2
25
µs
tOPR
RESET High to Operational Device
120
ns
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in Read mode.
Figure 48. Reset (RESET) Timing
VCC
VCC(min)
tNLNH-PO
tNLNH
tNLNH-A
tOPR
Power-On Reset
tOPR
Warm Reset
RESET
AI02866b
Table 70. VSTBYON Timing
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tBVBH
VSTBY Detection to VSTBYON Output High
(Note 1)
20
µs
tBXBL
VSTBY Off Detection to VSTBYON Output
Low
(Note 1)
20
µs
Note: 1. VSTBYON timing is measured at VCC ramp rate of 2 ms.
Table 71. Program, Write and Erase Times
Symbol
Parameter
Min.
Flash Program
Typ.
8.5
Flash Bulk Erase1 (pre-programmed)
3
Flash Bulk Erase (not pre-programmed)
10
tWHQV3
Sector Erase (pre-programmed)
1
tWHQV2
Sector Erase (not pre-programmed)
2.2
tWHQV1
Byte Program
14
Program / Erase Cycles (per Sector)
tWHWLO
tQ7VQV
30
s
s
30
s
s
1200
µs
cycles
100
Polling)2
Note: 1. Programmed to all zero before erase.
2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.
3. DQ7 is DQ15 for Motorola MCU with 16-bit data bus.
82/89
Unit
s
100,000
Sector Erase Time-Out
DQ7 Valid to Output (DQ7-DQ0) Valid (Data
Max.
µs
30
ns
PSD4235G2
Table 72. ISC Timing
-70
Symbol
Parameter
-90
Conditions
Unit
Min
Max
Min
Max
tISCCF
Clock (TCK, PC1) Frequency (except for
PLD)
(Note 1)
tISCCH
Clock (TCK, PC1) High Time (except for
PLD)
(Note 1)
23
26
ns
tISCCL
Clock (TCK, PC1) Low Time (except for
PLD)
(Note 1)
23
26
ns
tISCCFP
Clock (TCK, PC1) Frequency (PLD only)
(Note 2)
tISCCHP
Clock (TCK, PC1) High Time (PLD only)
(Note 2)
240
240
ns
tISCCLP
Clock (TCK, PC1) Low Time (PLD only)
(Note 2)
240
240
ns
tISCPSU
ISC Port Set Up Time
6
8
ns
tISCPH
ISC Port Hold Up Time
5
5
ns
tISCPCO
ISC Port Clock to Output
21
23
ns
tISCPZV
ISC Port High-Impedance to Valid Output
21
23
ns
tISCPVZ
ISC Port Valid Output to
High-Impedance
21
23
ns
20
18
2
2
MHz
MHz
Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For Program or Erase PLD only.
Figure 49. ISC Timing
t ISCCH
TCK
t ISCCL
t ISCPSU
t ISCPH
TDI/TMS
t ISCPZV
t ISCPCO
ISC OUTPUTS/TDO
t ISCPVZ
ISC OUTPUTS/TDO
AI02865
83/89
PSD4235G2
Table 73. Power-down Timing
-70
Symbol
Parameter
Unit
Min
tLVDV
ALE Access Time from Power-down
tCLWH
Maximum Delay from
APD Enable to Internal PDN Valid
Signal
Note: 1. tCLCL is the period of CLKIN (PD1).
84/89
-90
Conditions
Max
Min
80
Using CLKIN
(PD1)
15 * tCLCL1
Max
90
ns
µs
PSD4235G2
PACKAGE MECHANICAL
TQFP80 - 80 lead Plastic Quad Flatpack
D
D1
D2
A2
e
E2 E1 E
Ne
b
N
1
A
Nd
CP
L1
c
A1
QFP-A
α
L
Note: Drawing is not to scale.
TQFP80 - 80 lead Plastic Quad Flatpack
Symb.
mm
Typ.
Min.
A
inches
Max.
Typ.
Min.
1.200
Max.
0.0472
A1
0.050
0.150
0.0020
0.0059
A2
0.950
1.050
0.0374
0.0413
α
3.5°
0.0°
7.0°
3.5°
0.0°
7.0°
b
0.220
0.170
0.270
0.0087
0.0067
0.0106
0.090
0.200
0.0035
0.0079
—
—
—
—
c
D
14.000
0.5512
D1
12.000
0.4724
D2
9.500
E
14.000
E1
12.000
E2
9.500
e
0.500
L
0.600
L1
1.000
CP
0.080
—
—
0.3740
0.5512
0.4724
—
—
0.3740
—
—
0.0197
—
—
0.450
0.750
0.0236
0.0177
0.0295
0.0394
0.0031
N
80
80
Nd
20
20
Ne
20
20
85/89
PSD4235G2
Table 74. Pin Assignments – TQFP80
Pin No.
Pin
Assign
ments
Pin No.
Pin
Assign
ments
Pin No.
Pin
Assign
ments
Pin No.
Pin
Assign
ments
1
PD2
21
PG0
41
PC0
61
PB0
2
PD3
22
PG1
42
PC1
62
PB1
3
AD0
23
PG2
43
PC2
63
PB2
4
AD1
24
PG3
44
PC3
64
PB3
5
AD2
25
PG4
45
PC4
65
PB4
6
AD3
26
PG5
46
PC5
66
PB5
7
AD4
27
PG6
47
PC6
67
PB6
8
GND
28
PG7
48
PC7
68
PB7
9
VCC
29
VCC
49
GND
69
VCC
10
AD5
30
GND
50
GND
70
GND
11
AD6
31
PF0
51
PA0
71
PE0
12
AD7
32
PF1
52
PA1
72
PE1
13
AD8
33
PF2
53
PA2
73
PE2
14
AD9
34
PF3
54
PA3
74
PE3
15
AD10
35
PF4
55
PA4
75
PE4
16
AD11
36
PF5
56
PA5
76
PE5
17
AD12
37
PF6
57
PA6
77
PE6
18
AD13
38
PF7
58
PA7
78
PE7
19
AD14
39
RESET
59
CNTL0
79
PD0
20
AD15
40
CNTL2
60
CNTL1
80
PD1
86/89
PSD4235G2
PART NUMBERING
Table 75. Ordering Information Scheme
Example:
PSD42 3
5 G
2
V
– 90 U
I
T
Device Type
PSD42 = Flash PSD for 16-bit MCUs (with CPLD)
SRAM Size
0 = none
1 = 16 Kbit
2 = 32 Kbit
3 = 64 Kbit
4 = 128 Kbit
5 = 256 Kbit
Flash Memory Size
1 = 256 Kbit
2 = 512 Kbit
3 = 1 Mbit
4 = 2 Mbit
5 = 4 Mbit
6 = 8 Mbit
I/O Count
F = 27 I/O
G = 52 I/O
2nd Non Volatile
Memory
1 = 256 Kbit EEPROM
2 = 256 Kbit Flash memory
3 = none
6 = 512 Kbit Flash memory
Operating Voltage
blank = VCC = 4.5 to 5.5V
V1 = VCC = 3.0 to 3.6V
Speed
70 = 70 ns
90 = 90 ns
12 = 120 ns
15 = 150 ns
20 = 200 ns
Package
U = TQFP80
Temperature Range
blank = 0 to 70 °C (commercial)
I = –40 to 85 °C (industrial)
Option
T = Tape & Reel Packing
Note: 1. The 3.3V±10% devices are not covered by this data sheet, but by the PSD4235G2V data sheet.
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Office.
87/89
PSD4235G2
REVISION HISTORY
Table 76. Document Revision History
Date
Rev.
01-May-2001
1.0
Initial release as a WSI document
01-Aug-2001
1.1
Timing parameters updated
12-Sep-2001
2.0
Document rewritten using the ST template
14-Dec-2001
2.1
Information on the 3.3V±10% range removed to a separate data sheet
88/89
Description of Revision
PSD4235G2
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2001 STMicroelectronics - All Rights Reserved
STMicroelectronics group of companies Austalia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.
www.st.com
89/89

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