PIC16C64X & PIC16C66X
8-Bit EPROM Microcontrollers with Analog Comparators
Devices included in this data sheet:
•
•
•
•
Pin Diagrams
PDIP, SOIC, Windowed CERDIP
PIC16C641
PIC16C642
PIC16C661
PIC16C662
High Performance RISC CPU:
• Only 35 instructions to learn
• All single-cycle instructions (200 ns), except for
program branches which are two-cycle
• Operating speed:
- DC - 20 MHz clock input
- DC - 200 ns instruction cycle
Device
Data
Memory x8
PIC16C641
2K
128
PIC16C642
4K
176
PIC16C661
2K
128
PIC16C662
4K
176
• Interrupt capability
• 8-level deep hardware stack
• Direct, Indirect and Relative addressing modes
Peripheral Features:
• Up to 33 I/O pins with individual direction control
• High current sink/source for direct LED drive
• Analog comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
(VREF) module
- Programmable input multiplexing from device
inputs and internal voltage reference
- Comparator outputs can be output signals
• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
Special Microcontroller Features:
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Brown-out Reset
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• Serial in-circuit programming (via two pins)
1996 Microchip Technology Inc.
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7
RC6
RC5
RC4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PDIP, Windowed CERDIP
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
RA5
RE0/RD
RE1/WR
RE2/CS
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0
RC1
RC2
RC3
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC16C66X
Program
Memory x14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIC16C64X
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
RA5
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0
RC1
RC2
RC3
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7
RC6
RC5
RC4
RD3/PSP3
RD2/PSP2
• Four user programmable ID locations
• Program Memory Parity Error checking circuitry
with Parity Error Reset (PER)
• CMOS Technology:
• Low-power, high-speed CMOS EPROM technology
• Fully static design
• Wide operating voltage range: 3.0V to 6.0V
• Commercial, Industrial and Automotive
temperature ranges
• Low power consumption
- < 2.0 mA @ 5.0V, 4.0 MHz
- 15 µA typical @ 3.0V, 32 kHz
- < 1.0 µA typical standby current @ 3.0V
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 1
PIC16C64X & PIC16C66X
Pin Diagrams (Cont.’d)
RC6
RC5
RC4
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3
RC2
RC1
NC
TQFP
44 43 42 41 40 39 38 37 36 35 34
RC7
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3
1
2
3
4
5
6
7
8
9
10
11
PIC16C66X
33
32
31
30
29
28
27
26
25
24
23
NC
RC0
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
RE2/CS
RE1/WR
RE0/RD
RA5
RA4/T0CKI
12 1314 15 16 17 1819 20 21 22
RA3/AN3
RA2/AN2/VREF
RA1/AN1
RA0/AN0
MCLR/VPP
RB7
RB6
RB5
RB4
NC
NC
RA3/AN3
RA2/AN2/VREF
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
PLCC
RA4/T0CKI
RA5
RE0/RD
RE1/WR
RE2/CS
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0
NC
6 5 4 3 2 1 44 43 42 4140
39
38
37
36
35
34
33
32
31
30
16
29
17
18 19 20 21 2223 24 2526 27 28
7
8
9
10
11
12
13
14
15
PIC16C66X
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7
NC
RC6
RC5
RC4
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3
RC2
RC1
DS30559A-page 2
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
Table of Contents
1.0
General Description .......................................................................................................................................... 5
2.0
PIC16C64X & PIC16C66X Device Varieties .................................................................................................... 7
3.0
Architectural Overview...................................................................................................................................... 9
4.0
Memory Organization ..................................................................................................................................... 17
5.0
I/O Ports.......................................................................................................................................................... 29
6.0
Timer0 Module................................................................................................................................................ 41
7.0
Comparator Module ........................................................................................................................................ 47
8.0
Voltage Reference Module ............................................................................................................................. 53
9.0
Special Features of the CPU .......................................................................................................................... 55
10.0
Instruction Set Summary ................................................................................................................................ 73
11.0
Development Support ..................................................................................................................................... 87
12.0
Electrical Specifications .................................................................................................................................. 91
13.0
Device Characterization Information............................................................................................................. 103
14.0
Packaging Information .................................................................................................................................. 105
Appendix A: Enhancements...................................................................................................................................... 115
Appendix B: Compatibility ......................................................................................................................................... 115
Appendix C: What’s New .......................................................................................................................................... 116
Appendix D: What’s Changed ................................................................................................................................... 116
Appendix E: PIC16/17 Microcontrollers ..................................................................................................................... 117
Pin Compatibility ......................................................................................................................................................... 125
Index ........................................................................................................................................................................... 127
List of Examples.......................................................................................................................................................... 129
List of Figures.............................................................................................................................................................. 129
List of Tables............................................................................................................................................................... 130
On-Line Support.......................................................................................................................................................... 131
Reader Response ....................................................................................................................................................... 132
PIC16C64X & PIC16C66X Product Identification System .......................................................................................... 135
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional
amount of time to ensure that these documents are correct. However, we realize that we may have missed a few
things. If you find any information that is missing or appears in error, please use the reader response form in the
back of this data sheet to inform us. We appreciate your assistance in making this a better document.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 3
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 4
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
1.0
GENERAL DESCRIPTION
PIC16C64X & PIC16C66X devices are 28-pin and
40-pin EPROM-based members of the versatile
PIC16CXXX family of low-cost, high-performance,
CMOS, fully-static, 8-bit microcontrollers.
All PIC16/17 microcontrollers employ an advanced
RISC architecture. The PIC16CXXX family has
enhanced core features, eight-level deep stack, and
multiple internal and external interrupt sources. The
separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two-stage instruction
pipeline allows all instructions to execute in a single-cycle, except for program branches (which require
two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set
gives some of the architectural innovations used to
achieve a very high performance.
PIC16CXXX microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in its class.
The PIC16C641 has 128 bytes of RAM and the
PIC16C642 has 176 bytes of RAM. Both devices have
22 I/O pins, and an 8-bit timer/counter with an 8-bit programmable prescaler. In addition, they have two analog
comparators with a programmable on-chip voltage reference module. Program Memory has internal parity
error detection circuitry with a Parity Error Reset. The
comparator module is ideally suited for applications
requiring a low-cost analog interface (e.g., battery
chargers,
threshold
detectors,
white
goods
controllers, etc.).
The PIC16C661 has 128 bytes of RAM and the
PIC16C662 has 176 bytes of RAM. Both devices have
33 I/O pins, and an 8-bit timer/counter with an 8-bit programmable prescaler. They also have an 8-bit Parallel
Slave Port. In addition, the devices have two analog
comparators with a programmable on-chip voltage reference module. Program Memory has internal parity
error detection circuitry with a Parity Error Reset. The
comparator module is ideally suited for applications
requiring a low-cost analog interface (e.g., battery
chargers,
threshold
detectors,
white
goods
controllers, etc.).
A highly reliable Watchdog Timer (WDT) with its own
on-chip RC oscillator provides protection against software lock-up.
A UV-erasable CERDIP-packaged version is ideal for
code development while the cost-effective One-Time
Programmable (OTP) version is suitable for production
in any volume.
The PIC16CXXX series fit perfectly in applications
ranging from battery chargers to low-power remote
sensors.
The
EPROM
technology
makes
customization of application programs (detection
levels, pulse generation, timers, etc.) extremely fast
and convenient. The small footprint packages make
this microcontroller series perfect for all applications
with space limitations. Low-cost, low-power,
high-performance, ease of use, and I/O flexibility make
the PIC16C64X & PIC16C66X very versatile.
1.1
Family and Upward Compatibility
Those users familiar with the PIC16C5X family of
microcontrollers will realize that this is an enhanced
version of the PIC16C5X architecture. Please refer to
Appendix A for a detailed list of enhancements. Code
written for PIC16C5X can be easily ported to the
PIC16C64X & PIC16C66X (Appendix B).
1.2
Development Support
PIC16C64X & PIC16C66X devices are supported by
the complete line of Microchip Development tools,
including:
• MPLAB Integrated Development Environment
including MPLAB-Simulator.
• MPASM Universal Assembler and MPLAB-C Universal C compiler.
• PRO MATE II and PICSTART Plus device programmers.
• PICMASTER In-circuit Emulator System
• fuzzyTECH-MP Fuzzy Logic Development Tools
• DriveWay Visual Programming Tool
Please refer to Section 11.0 for more details about
these and other Microchip development tools.
PIC16CXXX devices have special features to reduce
external components, thus reducing cost, enhancing
system reliability and reducing power consumption.
There are four oscillator options, of which the single pin
RC oscillator provides a low-cost solution, the LP
oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for High Speed crystals.
The SLEEP (power-down) mode offers power saving.
The user can wake-up the chip from SLEEP through
several external and internal interrupts and resets.
1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 5
DS30559A-page 6
Preliminary
4K
2K
20
20
20
PIC16C642
PIC16C661
PIC16C662
E
M
176
128
176
128
O
PR
Da
o
ta
Pr
Ti
TMR0
TMR0
TMR0
TMR0
er
m
(b
2
2
2
2
M
Yes
Yes
Yes
Yes
m
Co
t
In
al
Yes
Pa
l
le
5
5
4
4
l
ra
t
In
33
33
22
22
3.0-6.0
3.0-6.0
3.0-6.0
R
Br
Pa
t
se
e
tR
ou
wn
o
ge
an
)
lts
o
(V
a
ck
ge
s
Features
Yes
Yes
40-pin PDIP, Windowed CDIP;
44-pin PLCC, TQFP
40-pin PDIP, Windowed CDIP;
44-pin PLCC, TQFP
Yes 28-pin PDIP, SOIC, Windowed CDIP
Yes 28-pin PDIP, SOIC, Windowed CDIP
e
g
lta
Vo
3.0-6.0
Pi
ns
es
rc
u
So
I/O
pt
P
ru
er
ve
a
Sl
t
or
ge
ta
l
Vo
Peripherals
e
nc
e
er
f
Re
Yes
-
-
n
er
)
(s
or
t
ra
pa
s)
e(
l
du
o
s)
o
em
M
e
yt
am
y
or
em
M
(M
r
og
n
io
Memory
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and high I/O current
capability.
All PIC16CXXX Family devices use serial programming with clock pin RB6 and data pin RB7.
4K
2K
20
PIC16C641
a
M
um
xim
en
qu
e
Fr
cy
p
fO
at
er
ry
TABLE 1-1:
)
Hz
Clock
PIC16C64X & PIC16C66X
PIC16C64X & PIC16C66X DEVICE FEATURES
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
2.0
PIC16C64X & PIC16C66X
DEVICE VARIETIES
2.3
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements the proper device option can be selected
using the information in the Product Identification System page at the end of this data sheet. When placing
orders, please use that page of the data sheet to specify the correct part number.
2.1
UV Erasable Devices
The UV erasable version, offered in CERDIP package
is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the oscillator modes.
Microchip's PICSTART Plus and PRO MATE II
programmers both support programming of the
PIC16C64X & PIC16C66X.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need flexibility for frequent code
updates and small volume applications. In addition to
the program memory, the configuration bits must also
be programmed.
1996 Microchip Technology Inc.
Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the
OTP devices but with all EPROM locations and configuration options already programmed by the factory.
Certain code and prototype verification procedures
apply before production shipments are available.
Please contact your Microchip Technology sales office
for more details.
2.4
Serialized Quick-TurnaroundProduction (SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 7
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 8
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16C64X &
PIC16C66X devices can be attributed to a number of
architectural features commonly found in RISC microprocessors. To begin with, the PIC16C64X &
PIC16C66X use a Harvard architecture in which program and data are accessed from separate memories
using separate buses. This improves bandwidth over
traditional von Neumann architecture where program
and data are fetched from the same memory. Separating program and data memory further allows instructions to be sized differently than an 8-bit wide data
word. Instruction opcodes are 14-bits wide making it
possible to have all single word instructions. A 14-bit
wide program memory access bus fetches a 14-bit
instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently,
all instructions (35) execute in a single cycle (200 ns @
20 MHz) except for program branches, which require
two cycles.
The PIC16C641 and PIC16C661 both address 2K x 14
on-chip program memory while the PIC16C642 and
PIC16C662 address 4K x 14. All program memory is
internal.
PIC16C64X & PIC16C66X devices contain an 8-bit
ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and
any register file.
The ALU is 8-bits wide and capable of addition,
subtraction, shift, and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a Borrow and Digit Borrow out bit,
respectively, bit in subtraction. See the SUBLW and
SUBWF instructions for examples.
PIC16C64X & PIC16C66X devices can directly or indirectly address their register files or data memory. All
special function registers including the program
counter are mapped in the data memory. These
devices have an orthogonal (symmetrical) instruction
set that makes it possible to carry out any operation on
any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’
make programming with the PIC16C64X & PIC16C66X
simple yet efficient. In addition, the learning curve is
reduced significantly.
1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 9
PIC16C64X & PIC16C66X
FIGURE 3-1:
PIC16C641/642 BLOCK DIAGRAM
PIC16C641 has 2K x 14 Program Memory and 128 x 8 RAM
PIC16C642 has 4K x 14 Program Memory and 176 x 8 RAM
13
8
Data Bus
Program Counter
Voltage
Reference
EPROM
Program
Memory
Program
Bus
8 Level Stack
(13-bit)
RAM
Comparator
File
Registers
RA0/AN0
RA1/AN1
+
14
Instruction reg
7
RA3/AN3
+
Addr MUX
8
Direct Addr
RA2/AN2/VREF
9
RAM Bank
Select
Indirect
Addr
FSR reg
Timer0
STATUS reg
RA4/T0CKI
3
MUX
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
Oscillator
Start-up Timer
Power-on
Reset
ALU
PORTA
W reg
Watchdog
Timer
RA5
Brown-out
Reset
Parity Error
Reset
MCLR
PORTB
RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7
VDD, VSS
PORTC
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
DS30559A-page 10
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
FIGURE 3-2:
PIC16C661/662 BLOCK DIAGRAM
PIC16C661 has 2K x 14 Program Memory and 128 x 8 RAM
PIC16C662 has 4K x 14 Program Memory and 176 x 8 RAM
13
8
Data Bus
Program Counter
Voltage
Reference
EPROM
Program
Memory
Program
Bus
RAM
8 Level Stack
(13-bit)
Comparator
File
Registers
RA0/AN0
RA1/AN1
+
14
Instruction reg
Direct Addr
RA2/AN2/VREF
9
RAM Bank
Select
7
8
RA3/AN3
+
Addr MUX
Indirect
Addr
FSR reg
Timer0
STATUS reg
RA4/T0CKI
3
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MUX
Power-up
Timer
PORTA
ALU
Oscillator
Start-up Timer
Power-on
Reset
W reg
Watchdog
Timer
RA5
Brown-out
Reset
Parity Error
Reset
MCLR
PORTB
VDD, VSS
RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7
Parallel
Slave
Port
PORTC
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
PORTE
RE0/RD
RE1/WR
PORTD
RE2/CS
1996 Microchip Technology Inc.
Preliminary
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
DS30559A-page 11
PIC16C64X & PIC16C66X
TABLE 3-1:
PIC16C641/642 PINOUT DESCRIPTION
Pin #
I/O/P
Type
OSC1/CLKIN
OSC2/CLKOUT
9
10
I
O
MCLR/VPP
1
I/P
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
2
3
4
5
6
I/O
I/O
I/O
I/O
I/O
RA5
7
I/O
RB0/INT
21
I/O
RB1
RB2
RB3
RB4
RB5
RB6
22
23
24
25
26
27
I/O
I/O
I/O
I/O
I/O
I/O
TTL/ST(2)
Interrupt on change pin.
Interrupt on change pin.
Interrupt on change pin. Serial programming clock.
RB7
28
I/O
TTL/ST(2)
Interrupt on change pin. Serial programming data.
Name
Buffer
Type
Description
ST/CMOS Oscillator crystal input or external clock source input.
—
Oscillator crystal output. Connects to crystal or resonator in crystal
oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has
1/4 the frequency of OSC1, and denotes the instruction cycle rate.
ST
Master clear (reset) input or programming voltage input. This pin is
an active low reset to the device.
PORTA is a bi-directional I/O port.
ST
Analog comparator input.
ST
Analog comparator input.
ST
Analog comparator input or VREF output.
ST
Analog comparator input or comparator output.
ST
Can be selected to be the clock input to the Timer0 timer/counter
or a comparator output. Output is open drain type.
ST
PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
(1)
RB0 can also be selected as an external interrupt pin.
TTL/ST
TTL
TTL
TTL
TTL
TTL
PORTC is a bi-directional I/O port.
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
VSS
VDD
Legend:
11
I/O
ST
12
I/O
ST
13
I/O
ST
14
I/O
ST
15
I/O
ST
16
I/O
ST
17
I/O
ST
18
I/O
ST
8,19
P
—
Ground reference for logic and I/O pins.
20
P
—
Positive supply for logic and I/O pins.
O = output
I/O = input/output
P = power
I = input
— = not used
ST = Schmitt Trigger input
TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
DS30559A-page 12
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
TABLE 3-2:
PIC16C661/662 PINOUT DESCRIPTION
DIP
Pin #
QFP
Pin #
PLCC
Pin #
I/O/P
Type
OSC1/CLKIN
13
30
14
I
OSC2/CLKOUT
14
31
15
MCLR/VPP
1
18
2
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
2
3
4
5
6
19
20
21
22
23
3
4
5
6
7
RA5
7
24
8
RB0/INT
33
8
36
RB1
RB2
RB3
RB4
RB5
RB6
34
35
36
37
38
39
9
10
11
14
15
16
37
38
39
41
42
43
RB7
40
17
44
Name
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
Legend:
Buffer
Type
Description
ST/CMOS Oscillator crystal input or external clock source
input.
O
—
Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2
pin outputs CLKOUT which has 1/4 the frequency of
OSC1, and denotes the instruction cycle rate.
I/P
ST
Master clear (reset) input or programming voltage
input. This pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
I/O
ST
Analog comparator input.
I/O
ST
Analog comparator input.
I/O
ST
Analog comparator input or VREF output.
I/O
ST
Analog comparator input or comparator output.
I/O
ST
Can be selected to be the clock input to the
Timer0 timer/counter or a comparator output.
Output is open drain type.
I/O
ST
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-ups on
all inputs.
(1)
I/O
RB0 can also be selected as an external
TTL/ST
interrupt pin.
I/O
TTL
I/O
TTL
I/O
TTL
I/O
TTL
Interrupt on change pin.
I/O
TTL
Interrupt on change pin.
(2)
I/O
Interrupt on change pin. Serial programming
TTL/ST
clock.
(2)
I/O
Interrupt on change pin. Serial programming
TTL/ST
data.
PORTC is a bi-directional I/O port.
I/O
ST
I/O
ST
I/O
ST
I/O
ST
I/O
ST
I/O
ST
I/O
ST
I/O
ST
I/O = input/output
P = power
— = not used
ST = Schmitt Trigger input
15
32
16
16
35
18
17
36
19
18
37
20
23
42
25
24
43
26
25
44
27
26
1
29
O = output
I = input
TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as a general purpose I/O and a TTL input when used
in the Parallel Slave Port Mode (for interfacing to a microprocessor port).
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 13
PIC16C64X & PIC16C66X
DIP
Pin #
Name
QFP
Pin #
PLCC
Pin #
I/O/P
Type
Buffer
Type
Description
PORTD can be a bi-directional I/O port or parallel
slave port for interfacing to a microprocessor bus.
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
RE0/RD
RE1/WR
RE2/CS
VSS
VDD
NC
Legend:
Note 1:
2:
3:
19
20
21
22
27
28
29
30
38
39
40
41
2
3
4
5
21
22
23
24
30
31
32
33
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST/TTL(3)
ST/TTL(3)
ST/TTL(3)
ST/TTL(3)
ST/TTL(3)
ST/TTL(3)
ST/TTL(3)
ST/TTL(3)
PORTE is a bi-directional I/O port.
RE0/RD read control for parallel slave port.
ST/TTL(3)
RE1/WR write control for parallel slave port.
RE2/CS select control for parallel slave port.
ST/TTL(3)
—
Ground reference for logic and I/O pins.
—
Positive supply for logic and I/O pins.
—
Not Connected.
ST/TTL(3)
8
25
9
I/O
9
26
10
I/O
10
27
11
I/O
12,31 6,29 13,34
P
11,32 7,28 12,35
P
—
12,13, 1,17
—
33,34 28,40
O = output
I/O = input/output
P = power
I = input
— = not used
ST = Schmitt Trigger input
TTL = TTL input
This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when used in serial programming mode.
This buffer is a Schmitt Trigger input when configured as a general purpose I/O and a TTL input when used
in the Parallel Slave Port Mode (for interfacing to a microprocessor port).
DS30559A-page 14
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
Clocking Scheme/Instruction Cycle
3.1
3.2
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3, and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-3.
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3, and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-3:
CLOCK/INSTRUCTION CYCLE
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
EXAMPLE 3-1:
PC
Fetch INST (PC)
Execute INST (PC-1)
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
Tcy0
Tcy1
Fetch 1
Execute 1
2. MOVWF PORTB
3. CALL SUB_1
4. BSF
PC+1
Fetch 2
Tcy2
Tcy3
Tcy4
Tcy5
Execute 2
Fetch 3
Execute 3
Fetch 4
PORTA, BIT3 (Forced NOP)
Flush
Fetch SUB_1 Execute SUB_1
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 15
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 16
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
4.0
MEMORY ORGANIZATION
4.1
Program Memory Organization
FIGURE 4-2:
The PIC16C64X & PIC16C66X have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. For the PIC16C641 and PIC16C661
only the first 2K x 14 (0000h - 07FFh) is physically
implemented. For the PIC16C642 and PIC16C662 only
the first 4K x 14 (0000h - 0FFh) is physically implemented. Accessing a location above the 2K or 4K
boundary will cause a wrap-around. The reset vector is
at 0000h and the interrupt vector is at 0004h (Figure 41 and Figure 4-2). See Section 4.4 for Program Memory paging.
FIGURE 4-1:
PIC16C642/662 PROGRAM
MEMORY MAP AND STACK
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Stack Level 8
PIC16C641/661 PROGRAM
MEMORY MAP AND STACK
Reset Vector
0000h
Interrupt Vector
0004h
0005h
User Memory Space
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Stack Level 8
Page0
On-chip Program
Memory
Reset Vector
User Memory Space
On-chip Program
Memory
0000h
07FFh
0800h
Page1
0FFFh
1000h
Interrupt Vector
0004h
0005h
1FFFh
On-chip Program
Memory
TEST
2000h
Configuration Word
2007h
TEST
07FFh
3FFFh
0800h
1FFFh
TEST
2000h
Configuration Word
2007h
TEST
1996 Microchip Technology Inc.
3FFFh
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 17
PIC16C64X & PIC16C66X
4.2
Data Memory Organization
FIGURE 4-3:
The data memory (Figure 4-4) is partitioned into two
banks which contain the general purpose registers and
the special function registers. Bank 0 is selected when
bit RP0 (STATUS<5>) is cleared. Bank 1 is selected
when the RP0 bit is set. The Special Function Registers are located in the first 32 locations of each Bank.
Register locations A0h-EFh (Bank 1) are general purpose registers implemented as static RAM. Some special function registers are mapped in Bank 1.
4.2.1
PIC16C641/661 DATA
MEMORY MAP
File
Address
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
GENERAL PURPOSE REGISTER FILE
The register file is organized as 176 x 8 for the
PIC16C642/662, and 128 x8 for the PIC16C641/661.
Each is accessed either directly, or indirectly through
the File Select Register FSR (Section 4.5).
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(2)
PORTE(2)
PCLATH
INTCON
PIR1
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD(2)
TRISE(2)
PCLATH
INTCON
PIE1
PCON
CMCON
VRCON
General
Purpose
Register
General
Purpose
Register
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BFh
C0h
Mapped
in Page 0
7Fh
Bank 0
EFh
F0h
FFh
Bank 1
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
2: Not implemented on the PIC16C641.
DS30559A-page 18
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
FIGURE 4-4:
PIC16C642/662 DATA
MEMORY MAP
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
4.2.2
File
Address
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(2)
PORTE(2)
PCLATH
INTCON
PIR1
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD(2)
TRISE(2)
PCLATH
INTCON
PIE1
PCON
CMCON
VRCON
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
SPECIAL FUNCTION REGISTERS
The special function registers are registers used by the
CPU and Peripheral Modules for controlling the desired
operation of the device (Table 4-1). These registers are
static RAM.
The special function registers can be classified into two
sets (core and peripheral). The special function registers associated with the “core” functions are described
in this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.
A0h
General
Purpose
Register
General
Purpose
Register
EFh
Mapped
in Bank 0
7Fh
F0h
FFh
Bank 0
Bank 1
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
2: Not implemented on the PIC16C642.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 19
PIC16C64X & PIC16C66X
TABLE 4-1:
SPECIAL FUNCTION REGISTERS
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR,
PER
Value on
all other
resets(1)
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
01h
TMR0
Timer0 Module’s Register
xxxx xxxx uuuu uuuu
02h
PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
03h
STATUS
04h
FSR
05h
PORTA
IRP(2)
RP1(2)
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
—
—
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
PORTA Data Latch when written: PORTA pins when read
--xx 0000 --xu 0000
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
06h
PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx uuuu uuuu
06h
PORTD(3)
PORTD Data Latch when written: PORTD pins when read
06h
PORTE(3)
—
—
—
0Ah
PCLATH
—
—
—
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
PSPIF(4)
CMIF
—
—
—
—
—
—
00-- ---- 00-- ----
C2OUT
C1OUT
—
—
CIS
CM2
CM1
CM0
00-- 0000 00-- 0000
—
—
xxxx xxxx uuuu uuuu
RE2
RE1
RE0
Write buffer for upper 5 bits of program counter
---0 0000 ---0 0000
0Dh-1Eh Unimplemented
1Fh
CMCON
---- -xxx ---- -uuu
—
—
Bank 1
80h
INDF
81h
OPTION
82h
PCL
83h
STATUS
84h
FSR
85h
TRISA
86h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
86h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
86h
TRISD(3)
PORTD Data Direction Register
86h
TRISE(3)
IBF
OBF
IBOV
8Ah
PCLATH
—
—
—
8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
PSPIE(4)
CMIE
—
—
—
MPEEN
—
—
—
VREN
VROE
VRR
—
8Ch
PIE1
8Dh
Unimplemented
8Eh
PCON
8Fh-9Eh
Unimplemented
9Fh
VRCON
Note
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
IRP(2)
RP1(2)
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
—
—
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
PORTA Data Direction Register
--11 1111 --11 1111
1111 1111 1111 1111
PSPMODE
—
TRISE2
TRISE1
TRISE0
0000 -111 0000 -111
INTF
RBIF
0000 000x 0000 000x
—
—
—
00-- ---- 00-- ----
—
PER
POR
BOR
u--- -qqq u--- -uuu
VR3
VR2
VR1
VR0
000- 0000 000- 0000
Write buffer for upper 5 bits of program counter
---0 0000 ---0 0000
—
—
—
—
Legend: - = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
1: Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: The IRP and RP1 bits are reserved, always maintain these bits clear.
3: The PORTD, PORTE, TRISD, and TRISE registers are not implemented on the PIC16C641/642.
4: Bits PSPIE and PSPIF are reserved on the PIC16C641/642, always maintain these bits clear.
DS30559A-page 20
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
4.2.2.1
It is recommended, therefore, that only BCF, BSF,
SWAPF, and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect any status bit. For other instructions, not affecting
any status bits, see the “Instruction Set Summary.”
STATUS REGISTER
The STATUS register, shown in Figure 4-5, contains
the arithmetic status of the ALU, the RESET status, and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: The IRP and RP1 bits (STATUS<7:6>) are
reserved on the PIC16C64X &
PIC16C66X and should be maintained
clear. Use of these bits as general purpose R/W bits is NOT recommended,
since this may affect upward compatibility
with future products.
Note 2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000uu1uu (where u = unchanged).
FIGURE 4-5:
R/W-0
IRP
bit7
bit 7:
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
Bit IRP is reserved on the PIC16C64X & PIC16C66X, always maintain this bit clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes. Bit RP1 is reserved on the PIC16C64X & PIC16C66X, always maintain this bit
clear.
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0:
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 21
PIC16C64X & PIC16C66X
4.2.2.2
OPTION REGISTER
The OPTION register is a readable and writable
register which contains various control bits to configure
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0, and the weak pull-ups on PORTB.
FIGURE 4-6:
R/W-1
RBPU
bit7
Note:
To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT.
R/W-1
PS1
R/W-1
PS0
bit0
OPTION REGISTER (ADDRESS 81h)
R/W-1
INTEDG
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
bit 7:
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6:
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5:
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3:
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
R= Readable bit
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
DS30559A-page 22
TMR0 Rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
WDT Rate
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
4.2.2.3
INTCON REGISTER
The INTCON register is a readable and writable
register which contains the various enable and flag bits
for all non-peripheral interrupt sources.
FIGURE 4-7:
R/W-0
GIE
bit7
Note:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
bit0
R= Readable bit
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5:
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4:
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3:
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2:
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1:
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0:
RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (See Section 5.2 to clear interrupt)
0 = None of the RB7:RB4 pins have changed state
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 23
PIC16C64X & PIC16C66X
4.2.2.4
PIE1 REGISTER
This register contains the individual enable bits for the
comparator and Parallel Slave Port interrupts.
FIGURE 4-8:
R/W-0
PSPIE(1)
bit7
PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
CMIE
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7:
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6:
CMIE: Comparator Interrupt Enable bit
1 = Enables the Comparator interrupt
0 = Disables the Comparator interrupt
U-0
—
bit0
R= Readable bit
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 5-0: Unimplemented: Read as '0'
Note 1: Bit PSPIE is reserved on the PIC16C641/642, always maintain this bit clear.
DS30559A-page 24
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
4.2.2.5
PIR1 REGISTER
Note:
This register contains the individual flag bits for the
comparator and Parallel Slave Port interrupts.
FIGURE 4-9:
R/W-0
PSPIF(1)
bit7
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
PIR1 REGISTER (ADDRESS 0Ch)
R/W-0
CMIF
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit0
R= Readable bit
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 7:
PSPIF(1): Parallel Slave Port Interrupt Flag bit
1 = A read or write operation has taken place (must be cleared in software)
0 = No read or write operation has taken place
bit 6:
CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 5-0: Unimplemented: Read as '0'
Note 1: Bit PSPIF is reserved on the PIC16C641/642, always maintain this bit clear.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 25
PIC16C64X & PIC16C66X
4.2.2.6
PCON REGISTER
Note:
The PCON register contains flag bits to differentiate
between a Power-on Reset (POR), an external MCLR
reset, WDT reset, Brown-out Reset (BOR), and Parity
Error Reset (PER). The PCON register also contains a
status bit, MPEEN, which reflects the value of the
MPEEN bit in Configuration Word. See Table 9-4 for
status of these bits on various resets.
BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent resets to see if BOR is
cleared, indicating a brown-out has
occurred. The BOR status bit is a “don't
care” and is not necessarily predictable if
the brown-out circuit is disabled (by
programming the BODEN bit in the
Configuration word).
FIGURE 4-10: PCON REGISTER (ADDRESS 8Eh)
R-U
MPEEN
bit7
bit 7:
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
PER
R/W-0
POR
R/W-u
BOR
bit0
R= Readable bit
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
MPEEN: Memory Parity Error Circuitry Status bit
Reflects the value of Configuration Word bit, MPEEN
bit 6-3: Unimplemented: Read as '0'
bit 2:
PER: Memory Parity Error Reset Status bit
1 = No error occurred
0 = Program memory fetch parity error occurred
(must be set in software after a Parity Error Reset occurs)
bit 1:
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
DS30559A-page 26
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
4.3
PCL and PCLATH
4.3.2
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is readable and
writable. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any
reset, the PC is cleared. Figure 4-11 shows the two
situations for the loading of the PC. The upper example
in the figure shows how the PC is loaded on a write to
PCL (PCLATH<4:0> → PCH). The lower example in
the figure shows how the PC is loaded during a CALL
or GOTO instruction (PCLATH<4:3> → PCH).
FIGURE 4-11: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
5
8
PCLATH<4:0>
Instruction with
PCL as
Destination
ALU result
PCLATH
PCH
12
11 10
PIC16C64X & PIC16C66X devices have an 8 level
deep x 13-bit wide hardware stack (Figure 4-2). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
Note 2: There are no instructions mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt
address.
PCL
8
4.4
0
7
PC
Program Memory Paging
GOTO, CALL
2
PCLATH<4:3>
11
Opcode <10:0>
PCLATH
4.3.1
STACK
COMPUTED GOTO
A computed GOTO is accomplished by adding an
offset to the program counter (ADDWF PCL). When
doing a table read using a computed GOTO method,
care should be exercised if the table location crosses a
PCL memory boundary (each 256 byte block). Refer to
the application note “Implementing a Table Read”
(AN556).
PIC16C642 and PIC16C662 devices have 4K of program memory, but the CALL and GOTO instructions only
have an 11-bit address range. This 11-bit address
range allows a branch within a 2K program memory
page size. To allow CALL and GOTO instructions to
address the entire 4K program memory address range,
there must be another bit to specify the program memory page. This paging bit comes from the PCLATH<3>
bit (Figure 4-11). When doing a CALL or GOTO instruction, the user must ensure that this page select bit
(PCLATH<3>) is programmed so that the desired program memory page is addressed. If a return from a
CALL instruction (or interrupt) is executed, the entire
13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<3> bit is not required for the
return instructions (which POPs the address from the
stack).
Note:
1996 Microchip Technology Inc.
Preliminary
The PIC16C64X & PIC16C66X ignore the
PCLATH<4> bit, which is used for program
memory pages 2 and 3 (1000h - 1FFFh).
The use of PCLATH<4> as a general purpose read/write bit is not recommended
since this may affect upward compatibility
with future products.
DS30559A-page 27
PIC16C64X & PIC16C66X
4.5
Indirect Addressing, INDF, and FSR
Registers
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 4-1.
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
EXAMPLE 4-1:
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually
accesses data pointed to by the file select register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a nooperation (although status bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 4-12. However, bit IRP is not used in
the PIC16C64X & PIC16C66X.
movlw
movwf
clrf
incf
btfss
goto
NEXT
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no goto next
;yes continue
CONTINUE:
FIGURE 4-12: DIRECT/INDIRECT ADDRESSING
Direct Addressing
(1)RP1
RP0
bank select
6
from opcode
Indirect Addressing
IRP(1)
0
7
bank select
location select
00
01
10
FSR register
0
location select
11
00h
00h
not used
Data
Memory
7Fh
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
For memory map detail see Figure 4-3 and Figure 4-4.
Note 1: Bits RP1 and IRP are reserved, always maintain these bits clear.
DS30559A-page 28
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
5.0
I/O PORTS
FIGURE 5-1:
The PIC16C641 and PIC16C642 have three ports,
PORTA, PORTB, and PORTC. PIC16C661 and
PIC16C662 devices have five ports, PORTA through
PORTE. Some pins for these I/O ports are multiplexed
with alternate functions for the peripheral features on
the device. In general, when a peripheral is enabled,
that pin may not be used as a general purpose I/O pin.
Data
bus
D
Q
VDD
WR
Port
CK
Q
PORTA and TRISA Registers
PORTA is a 6-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. Pin RA4 is multiplexed
with the T0CKI clock input. All other RA port pins have
Schmitt Trigger input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers)
which can configure these pins as input or output.
P
Data Latch
D
5.1
BLOCK DIAGRAM OF
RA1:RA0 PINS
WR
TRIS
Q
N
CK
Q
VSS
TRIS Latch
Analog
Input Mode
RD TRIS
Setting a bit in the TRISA register puts the corresponding output driver in a hi-impedance mode. Clearing a bit
in the TRISA register puts the contents of the output
latch on the selected pin.
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified, and then written to the port
data latch.
The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(comparator control register) register and the VRCON
(voltage reference control) register. When selected as
comparator inputs, these pins will read as '0's.
I/O Pin
Schmitt Trigger
Input Buffer
Q
D
EN
RD PORT
To Comparator
Note: I/O pins have protection diodes to VDD and VSS.
Note:
On reset, the TRISA register is set to all
inputs. The digital inputs are disabled and
the comparator inputs are forced to ground
to reduce excess current consumption.
TRISA controls the direction of the RA pins, even when
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs.
The RA2 pin will also function as the output for the
voltage reference. When in this mode, the VREF pin is
a very hi-impedance output. The user must set the
TRISA<2> bit and use hi-impedance loads.
In one of the comparator modes defined by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA<4:3> bits must be
cleared to enable outputs to use this function.
EXAMPLE 5-1:
1996 Microchip Technology Inc.
INITIALIZING PORTA
CLRF
PORTA
MOVLW
MOVWF
BSF
MOVLW
0x07
CMCON
STATUS, RP0
0x1F
MOVWF
TRISA
Preliminary
This document was created with FrameMaker 4 0 4
;Initialize PORTA by
;clearing output latches
;Turn comparators off,
;enable pins for I/O
;Select bank1
;Value to initialize
;data direction
;Set RA<4:0> as inputs
;TRISA<7:5> are clear
DS30559A-page 29
PIC16C64X & PIC16C66X
FIGURE 5-2:
Data
bus
BLOCK DIAGRAM OF RA2 PIN
D
Q
VDD
WR
Port
CK
Q
P
Data Latch
D
WR
TRIS
Q
RA2 Pin
N
CK
Q
VSS
TRIS Latch
Analog
Input Mode
RD TRIS
Schmitt Trigger
Input Buffer
Q
D
EN
RD PORT
To Comparator
VROE
VREF
Note: I/O pin has protection diodes to VDD and VSS.
FIGURE 5-3:
Data
bus
BLOCK DIAGRAM OF RA3 PIN
Comparator Mode = 110
D
Q
Comparator Output
WR
Port
CK
VDD
Q
P
Data Latch
D
WR
TRIS
Q
N
CK
RA3 Pin
Q
VSS
TRIS Latch
Analog
Input Mode
Schmitt Trigger
Input Buffer
RD TRIS
Q
D
EN
RD PORT
To Comparator
DS30559A-page 30
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
FIGURE 5-4:
Data
bus
BLOCK DIAGRAM OF RA4 PIN
Comparator Mode = 110
D
Q
Comparator Output
WR
Port
CK
Q
Data Latch
D
Q
N
WR
TRIS
CK
RA4 Pin
Q
VSS
TRIS Latch
Schmitt Trigger
Input Buffer
RD TRIS
Q
D
EN
RD PORT
TMR0 Clock Input
TABLE 5-1:
PORTA FUNCTIONS
Name
Bit #
Buffer
Type
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
bit0
bit1
bit2
bit3
bit4
ST
ST
ST
ST
ST
Input/output or comparator input.
Input/output or comparator input.
Input/output or comparator input or VREF output.
Input/output or comparator input/output.
Input/output or external clock input for TMR0 or comparator output. Output is open drain type.
Input/output.
RA5
bit5
ST
Legend: ST = Schmitt Trigger input
TABLE 5-2:
Address Name
05h
85h
1Fh
9Fh
Legend:
Function
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
—
—
RA5
RA4
RA3
RA2
RA1
RA0
--xx 0000 --uu
PORTA
TRISA
—
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11
CMCON C2OUT C1OUT
—
—
CIS
CM2
CM1
CM0
00-- 0000 00-VRCON
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
000- 0000 000x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
1996 Microchip Technology Inc.
Preliminary
0000
1111
0000
0000
DS30559A-page 31
PIC16C64X & PIC16C66X
PORTB and TRISB Registers
5.2
PORTB is an 8-bit wide bi-directional port. The
corresponding data direction register is TRISB. Setting
a bit in the TRISB register puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the
TRISB register puts the contents of the output latch on
the selected pin(s).
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read,
this value is modified, and then written to the port data
latch.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
done by clearing the RBPU (OPTION<7>) bit. The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt
on change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RBIF interrupt (flag
latched in (INTCON<0>)).
FIGURE 5-5:
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
b)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a keypad and make it possible for
wake-up on key-depression. (See AN552 in the
Microchip Embedded Control Handbook.)
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 5-6:
VDD
RBPU(2)
Data bus
WR Port
BLOCK DIAGRAM OF
RB7:RB4 PINS
weak
P pull-up
Data Latch
D
Q
RBPU(2)
WR TRIS
I/O
pin(1)
CK
D
VDD
Data bus
BLOCK DIAGRAM OF
RB3:RB0 PINS
Q
TTL
Input
Buffer
CK
weak
P pull-up
Data Latch
D
Q
WR Port
RD TRIS
I/O
pin(1)
CK
Q
TRIS Latch
D
Q
WR TRIS
RD Port
TTL
Input
Buffer
CK
RD TRIS
D
EN
RB0/INT
ST
Buffer
ST
Buffer
RD Port
Latch
Q
RD Port
D
Note 1: I/O pins have diode protection to VDD and VSS.
EN
2: TRISB = '1' enables weak pull-up if RBPU = '0'
(OPTION<7>).
Set RBIF
From other
RB7:RB4 pins
Q
D
EN
RB7:RB6 in serial programming mode
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
2: TRISB = '1' enables weak pull-up if RBPU = '0'
(OPTION<7>).
DS30559A-page 32
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
EXAMPLE 5-2:
INITIALIZING PORTB
CLRF
PORTB
BSF
MOVLW
STATUS, RP0
0xCF
MOVWF
TRISB
TABLE 5-3:
Name
;
;
;
;
;
;
;
;
;
;
PORTB FUNCTIONS
Bit #
RB0/INT
Initialize PORTB by
clearing output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RB<3:0> as inputs
RB<5:4> as outputs
RB<7:6> as inputs
Buffer Type
bit0
Function
Input/output or external interrupt input. Internal software programmable
weak pull-up.
RB1
bit1
TTL
Input/output pin. Internal software programmable weak pull-up.
RB2
bit2
TTL
Input/output pin. Internal software programmable weak pull-up.
RB3
bit3
TTL
Input/output pin. Internal software programmable weak pull-up.
RB4
bit4
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB5
bit5
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB6
bit6
Input/output pin (with interrupt on change). Internal software programmable
TTL/ST(2)
weak pull-up. Serial programming clock pin.
(2)
RB7
bit7
Input/output
pin (with interrupt on change). Internal software programmable
TTL/ST
weak pull-up. Serial programming data pin.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 5-4:
TTL/ST
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Address Name
06h
86h
81h
(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PORTB
TRISB
OPTION
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111
RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
Legend: x = unknown, u = unchanged, shaded cells are not used by PORTB.
1996 Microchip Technology Inc.
Preliminary
Value on
all other
resets
uuuu uuuu
1111 1111
1111 1111
DS30559A-page 33
PIC16C64X & PIC16C66X
5.3
PORTC and TRISC Registers
FIGURE 5-7:
PORTC is an 8-bit bi-directional port. Each pin is individually configurable as an input or output through the
TRISC register. PORTC pins have Schmitt Trigger
input buffers.
EXAMPLE 5-3:
CLRF
BSF
MOVLW
MOVWF
Data
bus
PORTC BLOCK DIAGRAM (IN
I/O PORT MODE)
D
WR
PORT
I/O pin(1)
CK
INITIALIZING PORTC
PORTC
STATUS, RP0
0xCF
TRISC
;
;
;
;
;
;
;
;
;
;
Q
Data Latch
Initialize PORTC by
clearing output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RC<3:0> as inputs
RC<5:4> as outputs
RC<7:6> as inputs
D
WR
TRIS
Q
Schmitt
Trigger
input
buffer
CK
TRIS Latch
RD TRIS
Q
D
EN
EN
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 5-5:
PORTC FUNCTIONS
Name
Bit#
Buffer Type
Function
RC0
bit0
ST
Input/output
RC1
bit1
ST
Input/output
RC2
bit2
ST
Input/output
RC3
bit3
ST
Input/output
RC4
bit4
ST
Input/output
RC5
bit5
ST
Input/output
RC6
bit6
ST
Input/output
RC7
bit7
ST
Input/output
Legend: ST = Schmitt Trigger input
TABLE 5-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
07h
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
87h
TRISC
TRISC7
TRISC6
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111
1111 1111
Legend: x = unknown, u = unchanged.
DS30559A-page 34
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
5.4
PORTD and TRISD Registers
(PIC16C661 and PIC16C662 only)
FIGURE 5-8:
PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or
output.
Data
bus
D
WR
PORT
PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL.
PORTD BLOCK DIAGRAM (IN
I/O PORT MODE)
Q
I/O pin(1)
CK
Data Latch
D
WR
TRIS
Q
Schmitt
Trigger
input
buffer
CK
TRIS Latch
RD TRIS
Q
D
EN
EN
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 5-7:
PORTD FUNCTIONS
Name
Bit#
Buffer Type
RD0/PSP0
bit0
ST/TTL(1)
Input/output port pin or parallel slave port bit0
bit1
ST/TTL(1)
Input/output port pin or parallel slave port bit1
bit2
(1)
Input/output port pin or parallel slave port bit2
(1)
RD1/PSP1
RD2/PSP2
ST/TTL
Function
RD3/PSP3
bit3
ST/TTL
Input/output port pin or parallel slave port bit3
RD4/PSP4
bit4
ST/TTL(1)
Input/output port pin or parallel slave port bit4
bit5
(1)
Input/output port pin or parallel slave port bit5
(1)
Input/output port pin or parallel slave port bit6
RD5/PSP5
RD6/PSP6
ST/TTL
bit6
ST/TTL
ST/TTL(1)
RD7/PSP7
bit7
Input/output port pin or parallel slave port bit7
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.
TABLE 5-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
08h
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
uuuu uuuu
88h
TRISD
TRISD3 TRISD2 TRISD1 TRISD0 1111 1111
1111 1111
89h
TRISE
TRISD7 TRISD6 TRISD5
IBF
OBF
IBOV
TRISD4
PSPMODE
—
TRISE2 TRISE1 TRISE0 0000 -111
0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 35
PIC16C64X & PIC16C66X
5.5
PORTE and TRISE Register
(PIC16C661 and PIC16C662 only)
Figure 5-9 shows the TRISE register, which also controls the parallel slave port operation.
PORTE has three pins RE0/RD, RE1/WR, and RE2/
CS, which are individually configurable as inputs or
outputs. These pins have Schmitt Trigger input buffers.
I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In
this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs). In this mode the input buffers are TTL.
FIGURE 5-9:
R-0
IBF
bit7
TRISE REGISTER (ADDRESS 89h)
R-0
OBF
R/W-0
IBOV
R/W-0
PSPMODE
U-0
—
R/W-1
TRISE2
R/W-1
TRISE1
R/W-1
TRISE0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
IBF: Input Buffer Full Status bit
1 = A word has been received and waiting to be read by the CPU
0 = No word has been received
bit 6:
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5:
IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared in software)
0 = No overflow occurred
bit 4:
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel slave port mode
0 = General purpose I/O mode
bit 3:
Unimplemented: Read as '0'
bit 2:
TRISE2: Direction control bit for pin RE2/CS
1 = Input
0 = Output
bit 1:
TRISE1: Direction control bit for pin RE1/WR
1 = Input
0 = Output
bit 0:
TRISE0: Direction control bit for pin RE0/RD
1 = Input
0 = Output
DS30559A-page 36
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
FIGURE 5-10: PORTE BLOCK DIAGRAM (IN I/O PORT MODE)
Data Bus
D
Q
CK
Q
I/O pin
WR PORT
Data Latch
WR TRIS
D
Q
CK
Q
Schmitt
Trigger
input
buffer
TRIS Latch
RD TRIS
Q
D
EN
EN
RD PORT
Note: I/O pins have protection diodes to VDD and VSS.
TABLE 5-9:
PORTE FUNCTIONS
Name
Bit#
Buffer Type
RE0/RD
bit0
ST/TTL(1)
Function
Input/output port pin or read control input in parallel slave port mode:
RD
1 = Not a read operation
0 = Read operation. Reads PORTD register (if chip selected)
RE1/WR
bit1
ST/TTL(1)
Input/output port pin or write control input in parallel slave port mode:
WR
1 = Not a write operation
0 = Write operation. Writes PORTD register (if chip selected)
bit2
ST/TTL(1)
Input/output port pin or chip select control input in parallel slave port
mode:
CS
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.
RE2/CS
TABLE 5-10:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
PORTE
—
—
—
—
—
RE2
RE1
RE0
---- -xxx
---- -uuu
TRISE
IBF
OBF
IBOV
PSPMODE
—
TRISE2
TRISE1
TRISE0
0000 -111
0000 -111
Address
Name
09h
89h
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 37
PIC16C64X & PIC16C66X
5.6
I/O Programming Considerations
5.6.1
BI-DIRECTIONAL I/O PORTS
EXAMPLE 5-4:
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result
back to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(e.g., bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and rewritten to the data latch of this particular
pin, overwriting the previous content. As long as the pin
stays in the input mode, no problem occurs. However,
if bit0 is switched into output mode later on, the content
of the data latch may now be unknown.
Reading the port register reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(e.g., BCF, BSF, etc.) on a port, the value of the port
pins is read, the desired operation is done to this value,
and this value is then written to the port latch.
Example 5-4 shows the effect of two sequential
read-modify-write instructions on an I/O port.
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage
the chip.
READ-MODIFY-WRITE
INSTRUCTIONS ON AN I/O
PORT
;Initial PORT settings: PORTB<7:4> Inputs
;
PORTB<3:0> Outputs
;PORTB<7:6> have external pull-ups and are
;not connected to other circuitry
;
;
PORT latch PORT pins
;
---------- --------BCF PORTB, 7
; 01pp pppp
11pp pppp
BCF PORTB, 6
; 10pp pppp
11pp pppp
BCF STATUS, RP1 ;
BSF STATUS, RP0 ;
BCF TRISB, 7
; 10pp pppp
11pp pppp
BCF TRISB, 6
; 10pp pppp
10pp pppp
;
;Note that the user may have expected the
;pin values to be 00pp ppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(high).
5.6.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle
(Figure 5-11). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load
dependent) before the next instruction which causes
that file to be read into the CPU is executed. Otherwise,
the previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with an NOP or another
instruction not accessing this I/O port.
FIGURE 5-11: SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
fetched
PC
PC + 1
MOVWF PORTB MOVF PORTB,W
write to
PORTB
PC + 2
PC + 3
NOP
NOP
This example shows a write to PORTB
followed by a read from PORTB.
Note that:
data setup time = (0.25TCY - TPD)
RB7:RB0
where TCY = instruction cycle
TPD = propagation delay
Port pin
sampled here
TPD
Instruction
executed
NOP
MOVWF PORTB
write to
PORTB
DS30559A-page 38
Note:
MOVF PORTB,W
Preliminary
Therefore, at higher clock frequencies,
a write followed by a read may be
problematic.
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
5.7
Parallel Slave Port
(PIC16C661 and PIC16C662 only)
An interrupt is generated and latched into flag bit
PSPIF (PIR1<7>) when a read or a write operation is
completed. Flag bit PSPIF must be cleared by user
software. The interrupt can be disabled by clearing the
interrupt enable bit PSPIE (PIE1<7>).
PORTD operates as an 8-bit wide parallel slave port, or
as a microprocessor port when control bit PSPMODE
(TRISE<4>) is set. In slave mode it is asynchronously
readable and writable by the external world through
RD control input pin (RE0/RD) and WR control input pin
(RE1/WR).
FIGURE 5-12: PORTD AND PORTE AS A
PARALLEL SLAVE PORT
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set).
Data bus
D
WR
PORT
Q
RDx
pin
CK
TTL
Q
RD
PORT
There are actually two 8-bit latches, one for data-out
(from the PIC16/17) and one for data input. The user
writes 8-bit data to PORTD data latch and reads data
from the port pin latch (note that they have the same
address). In this mode, the TRISD register is ignored
since the microprocessor is controlling the direction of
data flow.
D
EN
EN
One bit of PORTD
Set interrupt flag
PSPIF (PIR1<7>)
Input Buffer Full Status Flag bit IBF (TRISE<7>) is set
if a received word is waiting to be read by the CPU.
Once the PORTD input latch is read, bit IBF is cleared.
IBF is a read only status bit. Output Buffer Full Status
Flag bit OBF (TRISE<6>) is set if a word written to
PORTD latch is waiting to be read by the external bus.
Once the PORTD output latch is read by the microprocessor, bit OBF is cleared. Input Buffer Overflow Status
flag bit IBOV (TRISE<5>) is set if a second write to the
microprocessor port is attempted when the previous
word has not been read by the CPU (the first word is
retained in the buffer).
Read
TTL
RD
Chip Select
TTL
CS
TTL
WR
Write
Note: I/O pins have protection diodes to VDD and VSS.
When not in Parallel Slave Port mode, bits IBF and
OBF are held clear. However, if flag bit IBOV was previously set, it must be cleared in software.
TABLE 5-11:
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
08h
PORTD
PSP7
PSP6
PSP5
PSP4
PSP3
PSP2
PSP1
PSP0
xxxx xxxx
uuuu uuuu
09h
PORTE
—
—
—
—
—
RE2
RE1
RE0
---- -xxx
---- -uuu
89h
TRISE
IBF
OBF
IBOV
PSPMODE
—
0000 -111
0000 -111
PIR1
PSPIF(1)
CMIF
—
—
—
—
—
—
00-- ----
00-- ----
PIE1
PSPIE(1)
CMIE
—
—
—
—
—
—
00-- ----
00-- ----
0Ch
8Ch
TRISE2 TRISE1 TRISE0
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by the PSP.
Note 1: These bits are reserved on the PIC16C641/642, always maintain these bits clear.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 39
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 40
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
6.0
TIMER0 MODULE
(OPTION<4>). Clearing bit T0SE selects the rising
edge. Restrictions on the external clock input are discussed in detail in Section 6.2.
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
- Read and write capability
- Interrupt on overflow from FFh to 00h
• 8-bit software programmable prescaler
• Internal or external clock select
- Edge select for external clock
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit
PSA (OPTION<3>). Clearing bit PSA will assign the
prescaler to the Timer0 module. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4, …,
1:256 are selectable. Section 6.3 details the operation
of the prescaler.
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing bit T0CS
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two instruction cycles (Figure 6-2 and
Figure 6-3). The user can work around this by writing
an adjusted value to the TMR0 register.
The TMR0 interrupt is generated when the register
(TMR0) overflows from FFh to 00h. This overflow sets
interrupt flag bit T0IF (INTCON<2>). The interrupt can
be masked by clearing enable bit T0IE (INTCON<5>).
Flag bit T0IF must be cleared in software by the Timer0
interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot wake the processor
from SLEEP since the timer is shut off during SLEEP.
Figure 6-4 displays the Timer0 interrupt timing.
Counter mode is selected by setting bit T0CS. In this
mode, Timer0 will increment either on every rising or
falling edge of pin RA4/T0CKI. The incrementing edge
is determined by the source edge select bit T0SE
FIGURE 6-1:
Timer0 Interrupt
6.1
TIMER0 BLOCK DIAGRAM
Data bus
RA4/T0CKI
pin
FOSC/4
0
PSout
1
Sync with
Internal
clocks
1
Programmable
Prescaler
8
0
TMR0 reg
PSout
(2 cycle delay)
T0SE
3
Set bit T0IF
on overflow
PSA
PS2, PS1, PS0
T0CS
Note 1: Bits, T0CS, T0SE, PSA, and PS2, PS1, PS0 are (OPTION<5:0).
2: The prescaler is shared with Watchdog Timer (refer to Figure 6-6 for detailed diagram).
FIGURE 6-2:
PC
(Program
Counter)
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
Instruction
Fetch
TMR0
PC
MOVWF TMR0
T0
T0+1
Instruction
Executed
1996 Microchip Technology Inc.
PC+1
PC+2
PC+3
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0+2
NT0
NT0
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
PC+4
MOVF TMR0,W
NT0
Read TMR0
reads NT0
Preliminary
This document was created with FrameMaker 4 0 4
PC+5
PC+6
MOVF TMR0,W
NT0+1
NT0+2
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0 + 2
DS30559A-page 41
PIC16C64X & PIC16C66X
FIGURE 6-3:
PC
(Program
Counter)
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
PC
MOVWF TMR0
Instruction
Fetch
PC+2
Instruction
Execute
PC+4
PC+5
MOVF TMR0,W
PC+6
MOVF TMR0,W
NT0+1
NT0
Read TMR0
reads NT0
Write TMR0
executed
FIGURE 6-4:
PC+3
T0+1
T0
TMR0
PC+1
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
T0
Read TMR0
reads NT0 + 1
TIMER0 INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT(3)
Timer0
FEh
T0IF bit
(INTCON<2>)
FFh
00h
01h
02h
1
1
GIE bit
(INTCON<7>)
INSTRUCTION
FLOW
PC
PC
Instruction
fetched
Inst (PC)
Instruction
executed
Inst (PC-1)
PC +1
PC +1
Inst (PC+1)
Inst (PC)
Dummy cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy cycle
Inst (0004h)
Note 1: Interrupt flag bit T0IF is sampled here (every Q1).
2: Interrupt latency = 4Tcy where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
DS30559A-page 42
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
6.2
Using Timer0 with External Clock
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. For
the external clock to meet the sampling requirement,
the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at
least 4Tosc (and a small RC delay of 40 ns) divided by
the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41, and 42 in the electrical specification of the
desired device.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
6.2.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 6-5).
Therefore, it is necessary for T0CKI to be high for at
least 2Tosc (and a small RC delay of 20 ns) and low for
at least 2Tosc (and a small RC delay of 20 ns). Refer to
the electrical specification of the desired device.
FIGURE 6-5:
6.2.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-5 shows the delay
from the external clock edge to the timer incrementing.
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
External Clock Input or
Prescaler output (2)
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(1)
(3)
External Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max.
2: External clock if no prescaler selected, prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 43
PIC16C64X & PIC16C66X
6.3
Prescaler
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer (WDT), respectively (Figure 6-6). For simplicity,
this counter is being referred to as “prescaler” throughout this data sheet. Note that the prescaler may be
used by either the Timer0 module or the Watchdog
Timer, but not both. Thus, a prescaler assignment for
the Timer0 module means that there is no prescaler for
the Watchdog Timer, and vice-versa.
FIGURE 6-6:
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1,x) will clear the prescaler count. When
assigned to Watchdog Timer, a CLRWDT instruction will
clear the prescaler count along with the Watchdog
Timer. The prescaler is not readable or writable.
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
CLKOUT (=Fosc/4)
0
RA4/T0CKI
pin
8
M
U
X
1
M
U
X
0
1
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
0
Watchdog
Timer
1
M
U
X
Set flag bit T0IF
on Overflow
PSA
8-bit Prescaler
8
8 - to - 1MUX
PS2:PS0
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).
DS30559A-page 44
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
6.3.1
SWITCHING PRESCALER ASSIGNMENT
To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 6-2.
The prescaler assignment is fully under software control, i.e., it can be changed “on the fly” during program
execution.
Note:
To avoid an unintended device RESET, the
following instruction sequence (shown in
Example 6-1) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This precaution must
be followed even if the WDT is disabled.
EXAMPLE 6-1:
BCF
CLRF
BSF
CLRWDT
MOVLW
MOVWF
BCF
EXAMPLE 6-2:
BSF
MOVLW
MOVWF
BCF
;Clear WDT and
;prescaler
STATUS, RP0 ;Bank 1
b'xxxx0xxx' ;Select TMR0, new
;prescale value and
OPTION_REG ;clock source
STATUS, RP0 ;Bank 0
CHANGING PRESCALER
(TIMER0→WDT)
STATUS, RP0
TMR0
STATUS, RP0
b'xxxx1xxx'
OPTION_REG
STATUS, RP0
TABLE 6-1:
CLRWDT
CHANGING PRESCALER
(WDT→TIMER0)
;Bank 0
;Clear TMR0 & Prescaler
;Bank 1
;Clears WDT
;Select new prescale
;value & WDT
;Bank 0
REGISTERS ASSOCIATED WITH TIMER0
Address Name
01h
TMR0
0Bh/8Bh
INTCON
81h
OPTION
85h
TRISA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 module’s register
GIE
PEIE
RBPU INTEDG
—
—
T0IE
T0CS
TRISA5
Value on:
POR,
BOR
Value on all
other resets
xxxx xxxx
uuuu uuuu
0000 000u
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111
--11 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 45
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 46
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
7.0
COMPARATOR MODULE
The comparator module contains two analog
comparators. The inputs to the comparators are
multiplexed with pins RA0 through RA4. The on-chip
Voltage Reference (Section 8.0) can also be an input to
the comparators.
FIGURE 7-1:
R-0
C2OUT
bit7
The CMCON register, shown in Figure 7-1, controls the
comparator input and output multiplexers. A block
diagram of the comparator is shown in Figure 7-2.
CMCON REGISTER (ADDRESS 1Fh)
R-0
C1OUT
U-0
—
U-0
—
bit 7:
C2OUT: Comparator 2 output
1 = C2 VIN+ > C2 VIN–
0 = C2 VIN+ < C2 VIN–
bit 6:
C1OUT: Comparator 1 output
1 = C1 VIN+ > C1 VIN–
0 = C1 VIN+ < C1 VIN–
R/W-0
CIS
R/W-0
CM2
R/W-0
CM1
R/W-0
CM0
bit0
R =Readable bit
W =Writable bit
U =Unimplemented bit, read
as ‘0’
- n =Value at POR reset
bit 5-4: Unimplemented: Read as '0'
bit 3:
CIS: Comparator Input Switch
When CM2:CM0: = 001:
Then:
1 = C1 VIN– connects to RA3
0 = C1 VIN– connects to RA0
When CM2:CM0 = 010:
Then:
1 = C1 VIN– connects to RA3
C2 VIN– connects to RA2
0 = C1 VIN– connects to RA0
C2 VIN– connects to RA1
bit 2-0: CM2:CM0: Comparator mode
Figure 7-2 shows the comparator modes and CM2:CM0 bit settings.
1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 47
PIC16C64X & PIC16C66X
7.1
Comparator Configuration
There are eight modes of operation for the
comparators. The CMCON register is used to select
the mode. Figure 7-2 shows the eight possible modes.
The TRISA register controls the data direction of the
comparator pins for each mode. If the comparator
FIGURE 7-2:
RA3/AN3
RA1/AN1
RA2/AN2
RA3/AN3
A
VIN-
A
VIN+
A
VIN-
A
VIN+
RA0/AN0
C1
Off (Read as '0')
A
VIN-
A
VIN+
A
VIN-
RA3/AN3
RA1/AN1
C2
Off (Read as '0')
RA2/AN2
RA0/AN0
C1
RA2/AN2
A
VIN+
C2
D
VIN-
D
VIN+
D
VIN-
D
VIN+
C1
Off (Read as '0')
C2
Off (Read as '0')
Four Inputs Multiplexed to Two Comparators
CM2:CM0 = 010
C1OUT
RA3/AN3
RA1/AN1
RA1/AN1
Comparator interrupts should be disabled
during a comparator mode change otherwise a false interrupt may occur.
Comparators Off
CM2:CM0 = 111
Two Independent Comparators
CM2:CM0 = 100
RA0/AN0
Note:
COMPARATOR I/O OPERATING MODES
Comparators Reset (POR Default Value)
CM2:CM0 = 000
RA0/AN0
mode is changed, the comparator output level may not
be valid for the specified mode change delay shown
in Table 12-2.
RA2/AN2
C2OUT
A
A
VIN-
CIS = 0
CIS = 1
VIN+
C1
C1OUT
C2
C2OUT
A
A
VIN-
CIS = 0
CIS = 1
VIN+
From VREF Module
Two Common Reference Comparators
CM2:CM0 = 011
RA0/AN0
RA3/AN3
RA1/AN1
RA2/AN2
A
VIN-
D
VIN+
A
VIN-
A
VIN+
Two Common Reference Comparators with Outputs
CM2:CM0 = 110
RA0/AN0
C1
C1OUT
RA3/AN3
RA1/AN1
C2
C2OUT
RA2/AN2
A
VIN-
D
VIN+
A
VIN-
A
VIN+
C1
C1OUT
C2
C2OUT
RA4 Open Drain
Three Inputs Multiplexed to Two Comparators
CM2:CM0 = 001
One Independent Comparator
CM2:CM0 = 101
RA0/AN0
RA3/AN3
RA1/AN1
RA2/AN2
D
VIN-
D
VIN+
A
VIN-
A
VIN+
RA0/AN0
C1
Off (Read as '0')
RA3/AN3
RA1/AN1
C2
C2OUT
RA2/AN2
A
A
CIS = 0
CIS = 1
VINVIN+
A
VIN-
A
VIN+
C1
C1OUT
C2
C2OUT
A = Analog Input, port reads zeros always.
D = Digital Input.
CIS (CMCON<3>) is the Comparator Input Switch.
DS30559A-page 48
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
The code example in Example 7-1 depicts the steps
required to configure the comparator module. RA3 and
RA4 are configured as digital outputs. RA0 and RA1
are configured as the V- inputs and RA2 as the V+ input
to both comparators.
EXAMPLE 7-1:
INITIALIZING THE
COMPARATOR MODULE
FLAG_REG
CLRF
CLRF
ANDLW
IORWF
MOVLW
MOVWF
BSF
MOVLW
MOVWF
EQU 0x20
FLAG_REG
PORTA
0xC0
FLAG_REG,F
0x03
CMCON
STATUS,RP0
0x07
TRISA
BCF
CALL
MOVF
STATUS,RP0
DELAY_10µs
CMCON,F
BCF
BSF
BSF
BCF
BSF
BSF
PIR1,CMIF
STATUS,RP0
PIE1,CMIE
STATUS,RP0
INTCON,PEIE
INTCON,GIE
7.2
Comparator Reference
An external or internal reference signal may be used
depending on the comparator operating mode. The
analog signal that is present at VIN– is compared to the
signal at VIN+, and the digital output of the comparator
is adjusted accordingly (Figure 7-3).
FIGURE 7-3:
;Init Flag Register
;Init PORTA
;Mask Comp bits
;Bits to Flag_Reg
;Init Comp Mode
;CM2:CM0 = 011
;Select Bank 1
;Init Data direction
;RA<2:0> to inputs
;RA<4:3> to outputs
;TRISA<7:5> read '0'
;Select Bank 0
;10 µs delay
;Read CMCON to end
;change condition
;Clear Pending Ints
;Select Bank 1
;Enable Comp Ints
;Select Bank 0
;Enable Periph Ints
;Global Int enable
Comparator Operation
A single comparator is shown in Figure 7-3 along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN–, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN–, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 7-3 represents
the uncertainty due to input offsets and response time.
1996 Microchip Technology Inc.
7.3
SINGLE COMPARATOR
VINVIN+
Output
VINVIN+
Output
7.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the comparators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD, and can be applied to either
pin of the comparator(s).
7.3.2
INTERNAL REFERENCE SIGNAL
The comparator module also allows the selection of an
internally generated voltage reference for the
comparators. Section 8.0, contains a detailed description of the Voltage Reference Module that provides this
signal. The internal reference signal is used when the
comparators
are
in
mode
CM2:CM0 = 010
(Figure 7-2). In this mode, the internal voltage reference is applied to the VIN+ pin of both comparators.
Preliminary
DS30559A-page 49
PIC16C64X & PIC16C66X
7.4
Comparator Response Time
7.5
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is guaranteed to have a valid level.
If the internal reference is changed, the maximum delay
of the internal voltage reference must be considered
when using the comparator outputs. Otherwise, the
maximum delay of the comparators should be used
(Table 12-2 and Table 12-3).
Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read only. The comparator
outputs may also be directly output to the RA3 and RA4
I/O pins. When CM2:CM0 = 110, multiplexors in the
output path of the RA3 and RA4 pins will switch and the
output of each pin will be the unsynchronized output of
the comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications.
Figure 7-4 shows the comparator output block diagram.
The TRISA bits will still function as an output enable/
disable for the RA3 and RA4 pins while in this mode.
Note 1: When reading the PORTA register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
Note 2: Analog levels on any pin that is defined as
a digital input may cause the input buffer
to consume more current than is specified.
FIGURE 7-4:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX
To RA3 or RA4 pin
To Data Bus
Q
D
EN
RD CMCON
Q
Set CMIF bit
D
RD CMCON
EN
CL
From other Comparator
DS30559A-page 50
NRESET
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
7.6
Comparator Interrupts
comparators, CM2:CM0 = 111, before entering sleep.
If the device wakes up from sleep, the contents of the
CMCON register are not affected.
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator. User
software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that has occurred. The
CMIF bit (PIR1<6>), is the comparator interrupt flag
and must be cleared in user software.
7.8
A device reset forces the CMCON register to its reset
state. This forces the comparator module to be in the
comparator reset mode, CM2:CM0 = 000. This
ensures that all potential inputs are analog inputs.
Device current is minimized when analog inputs are
present at reset time. The comparators will be powered
down during the reset interval.
To enable the Comparator interrupt the following bits
must be set:
• CMIE (PIE1<6>)
• PEIE (INTCON<6>)
• GIE (INTCON<7>)
7.9
The user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
b)
Comparator Operation During SLEEP
When a comparator is active and the device is placed
in SLEEP mode, the comparator remains active and
the interrupt is functional if enabled. This interrupt will
wake up the device from SLEEP mode when enabled.
While the comparator is powered up, higher sleep
currents than shown in the power-down current
specification will occur. Each comparator that is
operational will consume additional current as shown in
the comparator specifications. To minimize power
consumption while in SLEEP mode, turn off the
FIGURE 7-5:
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 7-5. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum
source
impedance
of
10 kΩ
is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
Any read or write of CMCON. This will end the
mismatch condition.
Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition, and
allow flag bit CMIF to be cleared.
7.7
Effects of a RESET
ANALOG INPUT MODEL
VDD
VT = 0.6V
RS
RC < 10k
AIN
VA
CPIN
5 pF
VT = 0.6V
ILEAKAGE
±500 nA
VSS
Legend CPIN
VT
ILEAKAGE
RIC
RS
VA
1996 Microchip Technology Inc.
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to various junctions
= Interconnect Resistance
= Source Impedance
= Analog Voltage
Preliminary
DS30559A-page 51
PIC16C64X & PIC16C66X
TABLE 7-1:
REGISTERS ASSOCIATED WITH THE COMPARATOR MODULE
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
resets
1Fh
CMCON
C2OUT
C1OUT
—
—
CIS
CM2
CM1
CM0
00-- 0000
00-- 0000
9Fh
VRCON
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
000- 0000
000- 0000
0Bh/8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
PSPIF(1)
CMIF
—
—
—
—
—
—
00-- ----
00-- ----
8Ch
PIE1
PSPIE(1)
CMIE
—
—
—
—
—
—
00-- ----
00-- ----
85h
TRISA
—
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111
--11 1111
Note 1: These bits are reserved on the PIC16C641/642, always maintain these bits clear.
DS30559A-page 52
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
8.0
VOLTAGE REFERENCE
MODULE
The VRCON register, shown in Figure 8-1, controls the
operation of the Voltage Reference Module. The block
diagram is given in Figure 8-2.
The Voltage Reference is a 16-tap resistor ladder
network that provides a selectable voltage reference.
The resistor ladder is segmented to provide two ranges
of VREF values and has a power-down function to
conserve power when the reference module is not
being used.
FIGURE 8-1:
R/W-0
VREN
bit7
VRCON REGISTER (ADDRESS 9Fh)
R/W-0
VROE
R/W-0
VRR
U-0
—
R/W-0
VR3
R/W-0
VR2
bit 7:
VREN: VREF Enable
1 = VREF circuit powered up
0 = VREF circuit powered down, no IDD drain
bit 6:
VROE: VREF Output Enable
1 = VREF is output on RA2 pin
0 = VREF is disconnected from RA2 pin
bit 5:
VRR: VREF Range selection
1 = Low Range
0 = High Range
bit 4:
Unimplemented: Read as '0'
R/W-0
VR1
R/W-0
VR0
bit0
R =Readable bit
W =Writable bit
U =Unimplemented bit, read
as ‘0’
- n =Value at POR reset
bit 3-0: VR3:VR0: VREF value selection 0 ≤ VR3:VR0 ≤ 15
When: VRR = 1
Then: VREF = (VR3:VR0/ 24) • VDD
When: VRR = 0
Then: VREF = 1/4 • VDD + (VR3:VR0/ 32) • VDD
FIGURE 8-2:
VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
VREN
8R
R
R
R
R
8R
VREF
Note:
16-1 Analog Mux
VRR
VR3
VR2 (From VRCON<3:0>)
VR1
VR0
R is defined in Table 12-3.
1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 53
PIC16C64X & PIC16C66X
Configuring the Voltage Reference
8.1
the VREF output changes with fluctuations in VDD. The
absolute accuracy of the Voltage Reference can be
found in Table 12-3.
The Voltage Reference Module can output 16 distinct
voltage levels for each range.
8.3
The equations used to calculate the output of the
Voltage Reference are as follows:
When the device wakes up from sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the VRCON register are not affected. To minimize
current consumption in SLEEP mode, the Voltage
Reference Module should be disabled.
If VRR = 1
Then VREF = (VR3:VR0/24) • VDD
If VRR = 0
Then VREF = (VDD • 1/4) + (VR3:VR0/32) • VDD
A device reset disables the Voltage Reference by clearing bit VREN (VRCON<7>). This reset also
disconnects the reference from the RA2 pin by clearing
bit VROE (VRCON<6>) and selects the high voltage
range by clearing bit VRR (VRCON<5>). The VREF
value select bits, VRCON<3:0>, are also cleared.
VOLTAGE REFERENCE
CONFIGURATION
MOVLW
MOVWF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
CALL
0x02
CMCON
STATUS,RP0
0x07
TRISA
0xA6
VRCON
STATUS,RP0
DELAY_10µs
;
;
;
;
;
;
;
;
8.2
Voltage Reference Accuracy/Error
8.5
4 inputs muxed
to 2 comparators
Select Bank 1
RA3:RA0 to outputs
Connection Considerations
The Voltage Reference Module operates independently
of the comparator module. The output of the reference
generator may be connected to the RA2 pin if the
TRISA<2> bit is set and bit VROE is set. Enabling the
Voltage Reference output onto the RA2 pin with an
input signal present will increase current consumption.
Connecting RA2 as a digital output with VREF enabled
will also increase current consumption.
enable Vref low
range, VR3:VR0 = 6
Select Bank 0
; 10 µs delay
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
Voltage Reference output for external connections to
VREF. Figure 8-3 shows an example buffering
technique.
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 8-2) keep VREF from approaching VSS or VDD.
The Voltage Reference is VDD derived and therefore,
FIGURE 8-3:
Effects of a Reset
8.4
The settling time of the Voltage Reference must be
considered when changing the VREF output
(Table 12-2). Example 8-1 shows an example of how to
configure the Voltage Reference for an output voltage
of 1.25V with VDD = 5.0V.
EXAMPLE 8-1:
Operation During Sleep
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC16C662
VREF
Module
R(1)
Pin RA2
VREF output
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.
TABLE 8-1:
REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value On
POR,
BOR
Value on
all other
resets
9Fh
VRCON
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
000- 0000
000- 0000
1Fh
CMCON
C2OUT
C1OUT
—
—
CIS
CM2
CM1
CM0
00-- 0000
00-- 0000
85h
TRISA
—
—
--11 1111
--11 1111
DS30559A-page 54
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
9.0
SPECIAL FEATURES OF THE
CPU
What sets apart a microcontroller from other
processors are special circuits to deal with the needs of
real-time applications. The PIC16C64X & PIC16C66X
families have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving
operating modes and offer code protection.
These are:
1.
2.
3.
4.
5.
6.
7.
8.
Oscillator selection
Resets
Power-on Reset (POR)
Power-up Timer (PWRT)
Oscillator Start-up Timer (OST)
Brown-out Reset (BOR)
Parity Error Reset (PER)
Interrupts
Watchdog Timer (WDT)
SLEEP
Code protection
ID Locations
In-circuit serial programming
1996 Microchip Technology Inc.
The PIC16C64X & PIC16C66X has a Watchdog Timer
which is enabled by a configuration bit (WDTE). It runs
off its own RC oscillator for added reliability. There are
two timers that offer necessary delays on power-up.
One is the Oscillator Start-up Timer (OST), intended to
keep the chip in reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which
provides a fixed delay of 72 ms (nominal) on power-up
only, designed to keep the part in reset while the power
supply stabilizes. Circuitry has been provided for
checking program memory parity with a reset when an
error is indicated. There is also circuitry to reset the
device if a brown-out occurs which provides at least a
72 ms reset. With these three functions on-chip, most
applications need no external reset circuitry.
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, Watchdog Timer wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 55
PIC16C64X & PIC16C66X
Configuration Bits
9.1
The user will note that address 2007h is beyond
the user program memory space. In fact, it belongs
to the special test/configuration memory space
(2000h–3FFFh), which can be accessed only during
programming.
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in
program memory location 2007h.
FIGURE 9-1:
CP1
CP0
CONFIGURATION WORD
CP1
CP0
CP1
CP0
MPEEN
BODEN CP1
CP0
PWRTE
bit13
bit 13-8
5-4:
FOSC1 FOSC0
bit0
CONFIG
REGISTER:
Address
2007h
CP1:CP0: Code protection bits(2)
11 = Code protection off
10 = Upper half of program memory code protected
01 = Upper 3/4th of program memory code protected
00 = All memory is code protected
bit 7:
MPEEN: Memory Parity Error Enable
1 = Memory Parity Checking is enabled
0 = Memory Parity Checking is disabled
bit 6:
BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3:
PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note
WDTE
1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the
Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
DS30559A-page 56
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
9.2
Oscillator Configurations
9.2.1
OSCILLATOR TYPES
TABLE 9-1:
The PIC16CXXX can be operated in four different
oscillator modes. The user can program two
configuration bits (FOSC1 and FOSC0) to select one of
these four modes:
•
•
•
•
LP
XT
HS
RC
9.2.2
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1 and OSC2 pins to establish
oscillation (Figure 9-2). The PIC16CXXX oscillator
design requires the use of a parallel cut crystal. Use of
a series cut crystal may give a frequency out of the
crystal manufacturers specifications. When in XT, LP or
HS modes, the device can have an external clock
source to drive the OSC1 pin (Figure 9-3).
FIGURE 9-2:
Ranges tested:
Mode
CRYSTAL OPERATION
(OR CERAMIC RESONATOR)
(HS, XT OR LP OSC
CONFIGURATION)
XT
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
Resonators used:
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
RF
TABLE 9-2:
RS
see Note
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
(PRELIMINARY)
Freq
OSC1
OSC2
LP
32 kHz
200 kHz
100 kHz
2 MHz
4 MHz
8 MHz
10 MHz
20 MHz
68 - 100 pF
15 - 30 pF
68 - 150 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
68 - 100 pF
15 - 30 pF
150 - 200 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
XT
PIC16CXXX
HS
A series resistor may be required for
AT strip cut crystals.
FIGURE 9-3:
Higher capacitance increases the stability of the
oscillator but also increases the start-up time.
These values are for design guidance only. Rs may
be required in HS mode as well as XT mode to
avoid overdriving crystals with low drive level specification. Since each crystal has its own
characteristics, the user should consult the crystal
manufacturer for appropriate values of external
components.
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
OSC1
Crystals used:
PIC16CXXX
Open
±0.3%
±0.5%
±0.5%
±0.5%
±0.5%
Mode
SLEEP
See Table 9-1 or Table 9-2 for recommended values of C1 and C2.
clock from
ext. system
Panasonic EFO-A455K04B
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
Murata Erie CSA16.00MX
All resonators used did not have built-in capacitors.
OSC2
Note:
22 - 100 pF
15 - 68 pF
15 - 68 pF
10 - 68 pF
10 - 22 pF
To internal logic
XTAL
C2
OSC1
Note: Recommended values of C1 and C2 are identical
to the ranges tested table.
Higher capacitance increases the stability of the
oscillator but also increases the start-up time.
These values are for design guidance only. Since
each resonator has its own characteristics, the
user should consult the resonator manufacturer for
appropriate values of external components.
OSC1
C1
Freq
HS
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
CAPACITOR SELECTION
FOR CERAMIC RESONATORS
(PRELIMINARY)
OSC2
1996 Microchip Technology Inc.
32.768 kHz
100 kHz
200 kHz
2.0 MHz
4.0 MHz
10.0 MHz
20.0 MHz
Preliminary
Epson C-001R32.768K-A
Epson C-2 100.00 KC-P
STD XTL 200.000 kHz
ECS ECS-20-S-2
ECS ECS-40-S-4
ECS ECS-100-S-4
ECS ECS-200-S-4
± 20 PPM
± 20 PPM
± 20 PPM
± 50 PPM
± 50 PPM
± 50 PPM
± 50 PPM
DS30559A-page 57
PIC16C64X & PIC16C66X
9.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
9.2.4
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and
better stability. A well-designed crystal oscillator will
provide good performance with TTL gates. Two types
of crystal oscillator circuits can be used: one with series
resonance, or one with parallel resonance.
Figure 9-4 shows implementation of a parallel resonant
oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter
performs the 180-degree phase shift that a parallel
oscillator requires. The 4.7 kΩ resistor provides the
negative feedback for stability. The 10 kΩ potentiometer biases the 74AS04 in the linear region. This could
be used for external oscillator designs.
FIGURE 9-4:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
4.7k
PIC16CXXX
CLKIN
74AS04
RC OSCILLATOR
For timing insensitive applications the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
Cext values. The user also needs to take into account
variation due to tolerance of external R and C components used. Figure 9-6 shows how the R/C combination is connected to the PIC16CXXX. For Rext values
below 2.2 kΩ, the oscillator operation may become
unstable, or stop completely. For very high Rext values
(e.g. 1 MΩ), the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend to keep
Rext between 3 kΩ and 100 kΩ.
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or package lead frame capacitance.
See characterization data for desired device for RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since
leakage current variation will affect RC frequency more
for large R) and for smaller C (since variation of input
capacitance will affect RC frequency more).
10k
XTAL
10k
20 pF
See characterization data for desired device for variation of oscillator frequency due to VDD for given Rext/
Cext values as well as frequency variation due to operating temperature for given R, C, and VDD values.
20 pF
Figure 9-5 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a
180-degree phase shift in a series resonant oscillator
circuit. The 330 kΩ resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 9-5:
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (see Figure 3-3 for
waveform).
FIGURE 9-6:
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
RC OSCILLATOR MODE
V DD
Rext
OSC1
330 kΩ
330 kΩ
74AS04
74AS04
To Other
Devices
74AS04
PIC16CXXX
CLKIN
Cext
Internal
clock
PIC16CXXX
VSS
0.1 µF
Fosc/4
OSC2/CLKOUT
XTAL
DS30559A-page 58
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
9.3
Reset
The PIC16CXXX differentiates between various kinds
of reset:
a)
b)
c)
d)
e)
f)
Power-on reset (POR)
MCLR reset during normal operation
MCLR reset during SLEEP
WDT reset (normal operation)
Brown-out Reset (BOR)
Parity Error Reset (PER)
A simplified block diagram of the on-chip reset circuit is
shown in Figure 9-7.
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
FIGURE 9-7:
state” on Power-on reset, MCLR, WDT reset,
Brown-out Reset, Parity Error Reset, and on MCLR
reset during SLEEP. They are not affected by a WDT
wake-up, since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different reset situations as indicated in
Table 9-4. These bits are used in software to determine
the nature of the reset. See Table 9-6 for a full description of reset states of all registers.
The MCLR reset path has a noise filter to detect and
ignore small pulses. See Table 12-6 for pulse width
specification.
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/
VPP Pin
MPEEN
Program
Memory
Parity
WDT SLEEP
Module
WDT Time-out
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset
S
BODEN
OST/PWRT
OST
Chip_Reset
10-bit Ripple-counter
OSC1/
CLKIN
Pin
On-chip(1)
RC OSC
R
Q
PWRT
10-bit Ripple-counter
Enable PWRT
See Table 9-3 for time-out situations.
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 59
PIC16C64X & PIC16C66X
9.4
9.4.1
Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST), Brown-out Reset (BOR),
and Parity Error Reset (PER)
The power-up time delay will vary from chip to chip due
to VDD, temperature, and process variations. See DC
parameters for details.
POWER-ON RESET (POR)
The Oscillator Start-Up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
9.4.3
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.6V to 1.8V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset. A maximum rise time for VDD
is required. See Electrical Specifications for details.
The OST time-out is invoked only for XT, LP, and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
9.4.4
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, etc.) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal)
delay on power-up only, from POR or BOR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in reset as long as PWRT is active. The
PWRT delay allows VDD to rise to an acceptable level.
A configuration bit, PWRTE can disable (if set) or
enable (if cleared or programmed) the Power-up Timer.
The Power-up Timer should always be enabled when
Brown-out Reset is enabled.
FIGURE 9-8:
BROWN-OUT RESET (BOR)
PIC16C64X & PIC16C66X devices have on-chip
Brown-out Reset circuitry. A configuration bit, BODEN,
can disable (if clear/programmed) or enable (if set) the
Brown-out Reset circuitry. If VDD falls below 4.0V
(Parameter D005 in ES section) for greater than
parameter 35 in Table 12-6, the brown-out situation will
reset the chip. A reset is not guaranteed to occur if VDD
falls below 4.0V for less than parameter 35. The chip
will remain in Brown-out Reset until VDD rises above
BVDD. The Power-up Timer will now be invoked and will
keep the chip in reset an additional 72 ms. If VDD drops
below BVDD while the Power-up Timer is running, the
chip will go back into a Brown-out Reset and the
Power-up Timer will be initialized. Once VDD rises
above BVDD, the Power-up Timer will execute a 72 ms
time delay. The Power-up Timer should always be
enabled when Brown-out Reset is enabled. Figure 9-8
shows typical Brown-out situations.
For additional information, refer to Application Note
AN607 “Power-up Trouble Shooting.”
9.4.2
OSCILLATOR START-UP TIMER (OST)
BROWN-OUT SITUATIONS
VDD
Internal
Reset
BVDD Max.
BVDD Min.
72 ms
VDD
Internal
Reset
BVDD Max.
BVDD Min.
<72 ms
72 ms
VDD
Internal
Reset
DS30559A-page 60
BVDD Max.
BVDD Min.
72 ms
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
9.4.5
9.4.7
PARITY ERROR RESET (PER)
PIC16C64X & PIC16C66X devices have on-chip parity
bits that can be used to verify the contents of program
memory. Parity bits may be useful in applications in
order to increase overall reliability of a system.
The power control/status register, PCON (address
8Eh) has four bits. See Figure 4-10 for register.
Bit0 is BOR (Brown-out Reset). BOR is unknown on a
Power-on-reset. It must initially be set by the user and
checked on subsequent resets to see if BOR = '0'
indicating that a Brown-out Reset has occurred. The
BOR status bit is a “don’t care” bit and is not necessarily predictable if the brown-out circuit is disabled (by
clearing the BODEN bit in the Configuration word).
There are two parity bits for each word of Program
Memory. The parity bits are computed on alternating
bits of the program word. One computation is performed using even parity, the other using odd parity. As
a program executes, the parity is verified. The even
parity bit is XOR’d with the even bits in the program
memory word. The odd parity bit is negated and XOR’d
with the odd bits in the program memory word. When
an error is detected, a reset is generated and the PER
flag bit in the PCON register is set. This indication can
allow software to act on a failure. However, there is no
indication of the program memory location of the failure
of the Program Memory. This flag can only be cleared
in software or by a POR.
Bit1 is POR (Power-on Reset). It is cleared on a
Power-on Reset and is unaffected otherwise. The user
set this bit following a Power-on Reset. On subsequent
resets if POR is ‘0’, it will indicate that a Power-on
Reset must have occurred.
Bit2 is PER (Parity Error Reset). It is cleared on a Parity
Error Reset and must be set by user software. It will
also be set on a Power-on Reset.
The parity array is user selectable during programming.
Bit7 of the configuration word located at address 2007h
can be programmed (read as '0') to disable parity
checking. If left unprogrammed (read as '1'), parity
checking is enabled.
9.4.6
POWER CONTROL/STATUS REGISTER
(PCON)
Bit7 is MPEEN (Memory Parity Error Enable). This bit
reflects the status of the MPEEN bit in configuration
word. It is unaffected by any reset or interrupt.
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows: First
PWRT time-out is invoked after POR has expired. Then
the OST is activated. The total time-out will vary based
on oscillator configuration and PWRTE bit status. For
example, in RC mode with the PWRTE bit set (PWRT
disabled), there will be no time-out at all. Figure 9-9,
Figure 9-10 and Figure 9-11 depict time-out
sequences.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 9-10). This is useful for testing purposes or to
synchronize more than one device operating in parallel.
Table 9-5 shows the reset conditions for some special
registers, while Table 9-6 shows the reset conditions
for all the registers.
TABLE 9-3:
TIME-OUT IN VARIOUS SITUATIONS
Power-up
Oscillator Configuration
Brown-out Reset
Wake-up
from SLEEP
PWRTE = 0
PWRTE = 1
XT, HS, LP
72 ms + 1024 TOSC
1024 TOSC
72 ms + 1024 TOSC
1024 TOSC
RC
72 ms
—
72 ms
—
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 61
PIC16C64X & PIC16C66X
TABLE 9-4:
STATUS BITS AND THEIR SIGNIFICANCE
PER
POR
BOR
TO
PD
1
0
x
1
1
Power-on Reset
x
0
x
0
x
Illegal, TO is set on POR
x
0
x
x
0
Illegal, PD is set on POR
1
1
0
1
1
Brown-out Reset
1
1
1
0
1
WDT Reset
1
1
1
0
0
WDT Wake-up
1
1
1
u
u
MCLR reset during normal operation
1
1
1
1
0
MCLR reset during SLEEP
0
1
1
1
1
Parity Error Reset
0
0
x
x
x
Illegal, PER is set on POR
0
x
0
x
x
Illegal, PER is set on BOR
TABLE 9-5:
INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program
Counter
Condition
STATUS
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
u--- -10x
MCLR reset during normal operation
000h
000u uuuu
u--- -uuu
MCLR reset during SLEEP
000h
0001 0uuu
u--- -uuu
WDT reset
000h
0000 1uuu
u--- -uuu
WDT Wake-up
PC + 1
uuu0 0uuu
u--- -uuu
Brown-out Reset
000h
0001 1uuu
u--- -uu0
Parity Error Reset
000h
0001 1uuu
1--- -0uu
Interrupt Wake-up from SLEEP
PC + 1(1)
uuu1 0uuu
u--- -uuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC+1.
DS30559A-page 62
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
TABLE 9-6:
INITIALIZATION CONDITION FOR REGISTERS
Register
Address
W
-
INDF
Power-on Reset
Brown-out Reset
Parity Error Reset
MCLR Reset during:
- normal operation
- SLEEP or
WDT Reset
Wake up from SLEEP
through:
- interrupt
- WDT time-out
xxxx xxxx
uuuu uuuu
uuuu uuuu
00h
-
-
-
TMR0
01h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
02h
0000 0000
0000 0000
PC + 1(2)
STATUS
03h
0001 1xxx
000q quuu(3)
uuuq quuu(3)
FSR
04h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
05h
--xx 0000
--xu 0000
--uu uuuu
PORTB
06h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
07h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTD(4)
08h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTE(4)
09h
---- -xxx
---- -uuu
---- -uuu
CMCON
1Fh
00-- 0000
00-- 0000
uu-- uuuu
PCLATH
0Ah
---0 0000
---0 0000
---u uuuu
INTCON
0Bh
0000 000x
0000 000u
uuuu uuuu(1)
PIR1
0Ch
00-- ----
00-- ----
uu-- ----(1)
OPTION
81h
1111 1111
1111 1111
uuuu uuuu
TRISA
85h
--11 1111
--11 1111
--uu uuuu
TRISB
86h
1111 1111
1111 1111
uuuu uuuu
TRISC
87h
1111 1111
1111 1111
uuuu uuuu
(4)
TRISD
88h
1111 1111
1111 1111
uuuu uuuu
TRISE(4)
89h
0000 -111
0000 -111
uuuu -uuu
PIE1
8Ch
00-- ----
00-- ----
uu-- ----
PCON
8Eh
u--- -qqq
u--- -uuu
u--- -uuu
VRCON
9Fh
000- 0000
000- 0000
uuu- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’,q = value depends on condition.
Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
3: See Table 9-5 for reset value for specific condition.
4: These registers are associated with the Parallel Slave Port and are not implemented on the PIC16C641/642.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 63
PIC16C64X & PIC16C66X
FIGURE 9-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 9-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 9-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30559A-page 64
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
FIGURE 9-12: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
FIGURE 9-14: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
VDD
VDD
VDD
VDD
R1
Q1
D
MCLR
R
R2
R1
40k
PIC16CXXX
MCLR
PIC16CXXX
C
Note 1: External power-on reset circuit is required
only if VDD power-up slope is too slow.
The diode D helps discharge the capacitor quickly when VDD powers down.
Note 1: This brown-out circuit is less expensive,
albeit less accurate. Transistor Q1 turns
off when VDD is below a certain level
such that:
2: R < 40 kΩ is recommended to make sure
that voltage drop across R does not violate the device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor C in the event of MCLR/VPP pin
breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress
(EOS).
R1
VDD •
= 0.7 V
R1 + R2
2: Internal Brown-out Reset circuitry
should be disabled when using this circuit.
3: Resistors should be adjusted for the
characteristics of the transistor.
FIGURE 9-13: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
VDD
33k
10k
MCLR
40k
PIC16CXXX
Note 1: This circuit will activate reset when VDD
goes below (Vz + 0.7V) where
Vz = Zener voltage.
2: Internal Brown-out Reset circuitry
should be disabled when using this circuit.
3: Resistors should be adjusted for the
characteristics of the transistor.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 65
PIC16C64X & PIC16C66X
9.5
Interrupts
The PIC16C641 and PIC16C642 have four sources of
interrupt, while the PIC16C661 and PIC16C662 have
five sources:
•
•
•
•
•
External interrupt RB0/INT
TMR0 overflow interrupt
PORTB change interrupts (pins RB7:RB4)
Comparator interrupt
Parallel Slave Port interrupt (PIC16C661/662)
The interrupt control register, (INTCON), records
individual core interrupt requests in flag bits. It also has
various individual enable bits and the global interrupt
enable bit.
The global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on reset.
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the interrupt service routine the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in
software before re-enabling interrupts to avoid recursive interrupts.
For external interrupt events, such as the RB0/INT or
Port RB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure 9-16).
The latency is the same for one or two cycle
instructions. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid multiple interrupt requests. Individual interrupt
flag bits are set regardless of the status of their
corresponding mask bit or the GIE bit.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
allows any pending interrupt to execute.
Note 1: Individual interrupt flag bits are set regardless of the status of their corresponding
mask bit or the GIE bit.
Those interrupts associated with the “core” have their
flag and enable bits in the INTCON register. The core
interrupts are: RB0/INT pin interrupt, the RB port
change interrupt, and the TMR0 overflow interrupt. The
INTCON register also contains the Peripheral Interrupt
Enable bit, PEIE. Bit PEIE will enable/mask the peripheral interrupts (CM and PSP) from vectoring when bit
PEIE is set/cleared.
Note 2: When an instruction that clears the GIE bit
is executed, any interrupts that were
pending for execution in the next cycle are
ignored. The CPU will execute a NOP in
the cycle immediately following the
instruction which clears the GIE bit. The
interrupts which were ignored are still
pending to be serviced when the GIE bit is
set again.
Flag bits PSPIF and CMIF are contained in special
function register PIR1. The corresponding interrupt
enable bits (PSPIE and CMIE) are contained in special
function register PIE1.
FIGURE 9-15: INTERRUPT LOGIC
Wake-up
(If in SLEEP mode)
T0IF
T0IE
INTF
INTE
Interrupt
to CPU
RBIF
RBIE
GIE
CMIF
CMIE
PEIE
PSPIF(1)
PSPIE(1)
Note 1: The Parallel Slave Port is implemented on the PIC16C661 and PIC16C662 only.
DS30559A-page 66
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
9.5.1
9.5.3
RB0/INT INTERRUPT
An input change on any bit of PORTB<7:4> sets flag bit
RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE
(INTCON<4>). For operation of PORTB (Section 5.2).
The external interrupt on the RB0/INT pin is edge triggered: either rising if bit INTEDG (OPTION<6>) is set,
or falling, if bit INTEDG is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be enabled/disabled by setting/clearing enable bit INTE
(INTCON<4>). The INTF bit must be cleared in software in the interrupt service routine before re-enabling
this interrupt. The RB0/INT interrupt can wake-up the
processor from SLEEP, if bit INTE was set prior to
going into SLEEP. The status of the GIE bit decides
whether or not the processor branches to the interrupt
vector following wake-up. See Section 9.8 for details
on SLEEP and Figure 9-19 for timing of wake-up from
SLEEP through RB0/INT interrupt.
9.5.2
PORTB INTERRUPT
9.5.4
COMPARATOR INTERRUPT
See Section 7.6 for complete description of the comparator interrupt.
TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be enabled/disabled by setting/clearing T0IE
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 6.0.
FIGURE 9-16: RB0/INT PIN INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT 3
4
INT pin
1
1
INTF flag
(INTCON<1>)
Interrupt Latency 2
5
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst (PC)
Instruction
executed
Inst (PC-1)
Inst (PC+1)
Inst (PC)
0004h
PC+1
PC+1
—
Dummy Cycle
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
Note 1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 67
PIC16C64X & PIC16C66X
9.6
Context Saving During Interrupts
Example 9-1:
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key registers during an interrupt e.g. W register and STATUS
register. This will have to be implemented in software.
Example 9-1 stores and restores the STATUS and W
registers. The user register, W_TEMP, must be defined
in both banks and must be defined at the same offset
from the bank base address (i.e., W_TEMP is defined
at 0x70 - 0x7F in Bank 0). The user register,
STATUS_TEMP, must be defined in Bank 0.
EXAMPLE 9-1:
Stores the W register regardless of current bank
Stores the STATUS register in Bank 0
Executes the ISR code
Restores the STATUS (and bank select bit
register)
• Restores the W register
SAVING THE STATUS AND W REGISTERS IN RAM
MOVWF
W_TEMP
;
SWAPF
STATUS,W
;
BCF
STATUS,RP0
;
MOVWF
STATUS_TEMP
;
:
: (Interrupt Service
:
SWAPF
STATUS_TEMP,W ;
MOVWF
STATUS
;
SWAPF
W_TEMP,F
;
SWAPF
W_TEMP,W
;
DS30559A-page 68
•
•
•
•
Copy W to a Temporary Register regardless of current bank
Swap STATUS nibbles and place into W register
Change to Bank 0 regardless of current bank
Save STATUS to a Temporary register in Bank 0
Routine)
Swap original STATUS register value into W (restores original bank)
Restore STATUS register from W register
Swap W_Temp nibbles and return value to W_Temp
Swap W_Temp to W to restore original W value without affecting STATUS
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
9.7
Watchdog Timer (WDT)
the WDT, under software control, by writing to the
OPTION register. Thus, time-out periods of up to 2.3
seconds can be realized.
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator which does not require any external components. The block diagram is shown in Figure 9-17.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. This means that the WDT will
run, even if the clock on the OSC1 and OSC2 pins has
been stopped, for example, by execution of a SLEEP
instruction. During normal operation, a WDT time-out
generates a device RESET. If the device is in SLEEP
mode, a WDT time-out causes the device to wake-up
and continue with normal operation, this is known as a
WDT wake-up. The WDT can be permanently disabled
by clearing configuration bit WDTE (Section 9.1).
9.7.1
The CLRWDT and SLEEP instructions clear the WDT and
the postscaler (if assigned to the WDT) and prevent it
from timing out and generating a device RESET.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out (WDT Reset and WDT
wake-up).
9.7.2
WDT PROGRAMMING CONSIDERATIONS
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., max.
WDT prescaler) it may take several seconds before a
WDT time-out occurs.
WDT PERIOD
Note:
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out period varies with temperature, VDD and process variations from part to part (see
DC specs). If longer time-outs are desired, a prescaler
with a division ratio of up to 1:128 can be assigned to
When the prescaler is assigned to the
WDT, always execute a CLRWDT instruction
before changing the prescale value, otherwise a WDT reset may occur.
FIGURE 9-17: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 7-6)
0
1
WDT Timer
Postscaler
M
U
X
8
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 7-6)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION register.
FIGURE 9-18: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
BODEN(1)
MPEEN
CP1
CP0
2007h
Config. bits
81h
OPTION
RBPU
INTEDG
T0CS T0SE
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 9-1 for details of the operation of these bits.
1996 Microchip Technology Inc.
Preliminary
Bit 3
Bit 2
Bit 1
Bit 0
PWRTE(1)
WDTE
PS2
FOSC1
PS1
FOSC0
PS0
PSA
DS30559A-page 69
PIC16C64X & PIC16C66X
9.8
Power-Down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the STATUS register is
cleared, the TO bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, all I/O
pins should be either at VDD, or VSS, with no external
circuitry drawing current from the I/O pin and the comparators and VREF module should be disabled. I/O pins
that are hi-impedance inputs should be pulled high or
low externally to avoid switching currents caused by
floating inputs. The T0CKI input should also be at VDD
or VSS for lowest current consumption. The contribution from on chip pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
9.8.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
Any device reset
Watchdog Timer Wake-up (if WDT was enabled)
Interrupt from RB0/INT pin, RB Port change, or
the Comparator.
The first event will reset the device upon wake-up.
However the latter two events will wake the device and
then resume program execution. The TO and PD bits in
the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up is cleared when SLEEP is invoked. The TO
bit is cleared if WDT wake-up occurred.
When the SLEEP instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have an NOP after the SLEEP instruction.
9.8.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag set, one of the following events will
occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will complete as an NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bit will not be cleared.
• If the interrupt occurs during or after the execution
of a SLEEP instruction, the device will immediately
wake-up from sleep. The SLEEP instruction will be
completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as an NOP.
To ensure that the WDT is clear, a CLRWDT instruction
should be executed before a SLEEP instruction.
FIGURE 9-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3
Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
Note
1:
2:
3:
4:
PC
Inst(PC) = SLEEP
Inst(PC - 1)
PC+1
Inst(PC + 1)
SLEEP
PC+2
PC+2
PC + 2
Inst(PC + 2)
Inst(PC + 1)
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
XT, HS or LP oscillator mode assumed.
TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
DS30559A-page 70
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
9.9
Code Protection
9.11
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
Note:
9.10
Microchip does not recommend code
protecting windowed devices.
ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are
readable and writable during program/verify. Only the
least significant 4 bits of the ID locations are used.
In-Circuit Serial Programming
The PIC16CXX microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
The device is placed into a program/verify mode by
holding the RB6 and RB7 pins low while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). RB6 becomes the programming clock
and RB7 becomes the programming data. Both RB6
and RB7 are Schmitt Trigger inputs in this mode.
After reset, to place the device into programming/verify
mode, the program counter (PC) is at location 00h. A
6-bit command is then supplied to the device.
Depending on the command, 14-bits of program data
are then supplied to or from the device, depending if
the command was a load or a read. For complete
details of serial programming, please refer to the
PIC16C6X/7X Programming Specifications (Literature
#DS30228).
A typical in-circuit serial programming connection is
shown in Figure 9-20.
FIGURE 9-20: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
CONNECTION
External
Connector
Signals
To Normal
Connections
PIC16CXX
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
RB6
Data I/O
RB7
VDD
To Normal
Connections
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 71
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 72
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
10.0
INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 10-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 10-1
shows the opcode field descriptions.
For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
TABLE 10-1:
OPCODE FIELD
DESCRIPTIONS
Field
Description
Register file address (0x00 to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
label Label name
f
W
b
k
x
Top of Stack
Program Counter
PCLATH Program Counter High Latch
GIE Global Interrupt Enable bit
WDT Watchdog Timer/Counter
TO Time-out bit
PD Power-down bit
dest Destination either the W register or the specified
register file location
[ ] Options
( ) Contents
TOS
PC
→
<>
∈
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruction, the instruction execution time is 2 µs.
Table 10-2 lists the instructions recognized by the
MPASM assembler.
Figure 10-1 shows the three general formats that the
instructions can have.
Note:
To maintain upward compatibility with
future PIC16CXX products, do not use the
OPTION and TRIS instructions.
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 10-1: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
0
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8 7
OPCODE
0
k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only
13
11
OPCODE
10
0
k (literal)
k = 11-bit immediate value
Assigned to
Register bit field
In the set of
italics User defined term (font is courier)
The instruction set is highly orthogonal and is grouped
into three basic categories:
1996 Microchip Technology Inc.
DS30559A-page 73
This document was created with FrameMaker 4 0 4
PIC16C64X & PIC16C66X
10.1
Special Function Registers as
Source/Destination
The PIC16C64X & PIC16C66X’s orthogonal instruction
set allows read and write of all file registers, including
special function registers. There are some special situations the user should be aware of:
10.1.1
STATUS AS DESTINATION
If an instruction writes to STATUS, the Z, C, and DC bits
may be set or cleared as a result of the instruction and
overwrite the original data bits written. For example,
executing CLRF STATUS will clear register STATUS,
and then set the Z bit leaving 0000 0100b in the register.
10.1.2
PCL AS SOURCE OR DESTINATION
Read, write or read-modify-write on PCL may have the
following results:
Read PC:
PCL → dest
Write PCL:
PCLATH → PCH;
8-bit destination value → PCL
Read-Modify-Write:
PCL→ ALU operand
PCLATH → PCH;
8-bit result → PCL
Where PCH = program counter high byte (not an
addressable register), PCLATH = Program counter
high holding latch, dest = destination, WREG or f.
10.1.3
BIT MANIPULATION
All bit manipulation instructions are done by first reading the entire register, operating on the selected bit and
writing the result back (read-modify-write). The user
should keep this in mind when operating on special
function registers, such as ports.
DS30559A-page 74
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
TABLE 10-2:
Mnemonic,
Operands
INSTRUCTION SET
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
0011
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
1996 Microchip Technology Inc.
DS30559A-page 75
PIC16C64X & PIC16C66X
10.2
Instruction Descriptions
ANDLW
And Literal with W
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
(W) + k → (W)
Operation:
(W) .AND. (k) → (W)
C, DC, Z
Status Affected:
Z
ADDLW
Add Literal and W
Syntax:
[ label ] ADDLW
Operands:
Operation:
Status Affected:
Encoding:
11
k
111x
kkkk
kkkk
Encoding:
11
Description:
The contents of the W register are
added to the eight bit literal 'k' and the
result is placed in the W register.
Description:
Words:
1
Words:
1
1
Cycles:
1
Cycles:
Example
ADDLW
=
=
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
Operands:
ANDLW
=
0xA3
After Instruction
W
0x25
=
0x03
ANDWF
AND W with f
Syntax:
[ label ] ANDWF
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) + (f) → (dest)
Operation:
(W) .AND. (f) → (dest)
Status Affected:
C, DC, Z
Status Affected:
Z
Encoding:
00
kkkk
0x5F
W
0x10
After Instruction
W
kkkk
Before Instruction
Before Instruction
W
1001
The contents of W register are
AND’ed with the eight bit literal 'k'. The
result is placed in the W register.
Example
0x15
k
f,d
0111
dfff
ffff
Encoding:
00
f,d
0101
dfff
ffff
Description:
Add the contents of the W register
with register 'f'. If 'd' is 0 the result is
stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
Description:
AND the W register with register 'f'. If
'd' is 0 the result is stored in the W
register. If 'd' is 1 the result is stored
back in register 'f'.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Example
ADDWF
FSR, 0
0x17
0xC2
After Instruction
W =
FSR =
DS30559A-page 76
ANDWF
FSR, 1
Before Instruction
Before Instruction
W =
FSR =
Example
W =
FSR =
0x17
0xC2
After Instruction
0xD9
0xC2
W =
FSR =
0x17
0x02
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
BCF
Bit Clear f
BTFSC
Bit Test, Skip if Clear
Syntax:
[ label ] BCF
Syntax:
[ label ] BTFSC f,b
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
0 → (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
None
Encoding:
01
f,b
00bb
bfff
ffff
Description:
Bit 'b' in register 'f' is cleared.
Words:
1
Cycles:
1
Example
BCF
Encoding:
FLAG_REG = 0x47
bfff
ffff
Words:
1
Cycles:
1(2)
Before Instruction
FLAG_REG = 0xC7
10bb
Description:
FLAG_REG, 7
After Instruction
01
If bit 'b' in register 'f' is '0' then the next
instruction is skipped.
If bit 'b' is '0' then the next instruction
fetched during the current instruction
execution is discarded, and a NOP is
executed instead, making this a 2 cycle
instruction.
Example
HERE
FALSE
TRUE
BTFSC
GOTO
•
•
•
FLAG,1
PROCESS_CODE
Before Instruction
PC =
address HERE
After Instruction
if FLAG<1> = 0,
PC =
address TRUE
if FLAG<1>=1,
PC =
address FALSE
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
1 → (f<b>)
Status Affected:
None
Encoding:
01
f,b
01bb
bfff
Description:
Bit 'b' in register 'f' is set.
Words:
1
Cycles:
1
Example
BSF
FLAG_REG,
ffff
7
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
1996 Microchip Technology Inc.
DS30559A-page 77
PIC16C64X & PIC16C66X
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CLRF
Operands:
0 ≤ f ≤ 127
0≤b<7
Operands:
0 ≤ f ≤ 127
Operation:
00h → (f)
1→Z
Status Affected:
Z
Operation:
skip if (f<b>) = 1
Status Affected:
None
Encoding:
Description:
01
11bb
bfff
ffff
If bit 'b' in register 'f' is '1' then the next
instruction is skipped.
If bit 'b' is '1', then the next instruction
fetched during the current instruction
execution, is discarded and a NOP is
executed instead, making this a 2 cycle
instruction.
Words:
1
Cycles:
1(2)
Example
HERE
FALSE
TRUE
Encoding:
00
f
0001
1fff
ffff
Description:
The contents of register 'f' are cleared
and the Z bit is set.
Words:
1
Cycles:
1
Example
CLRF
FLAG_REG
Before Instruction
FLAG_REG
BTFSC
GOTO
•
•
•
=
0x5A
=
=
0x00
1
After Instruction
FLAG,1
PROCESS_CODE
FLAG_REG
Z
Before Instruction
PC =
address HERE
After Instruction
if FLAG<1> = 0,
PC =
address FALSE
if FLAG<1> = 1,
PC =
address TRUE
CALL
Call Subroutine
CLRW
Clear W
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRW
Operands:
0 ≤ k ≤ 2047
Operands:
None
Operation:
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Operation:
00h → (W)
1→Z
Status Affected:
Z
Status Affected:
None
Encoding:
Encoding:
Description:
10
kkkk
kkkk
Call Subroutine. First, return address
(PC+1) is pushed onto the stack. The
eleven bit immediate address is loaded
into PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALL is a two cycle instruction.
Words:
1
Cycles:
2
Example
0kkk
Description:
00
0000
0011
W register is cleared. Zero bit (Z) is
set.
Words:
1
Cycles:
1
Example
0001
CLRW
Before Instruction
W
HERE
CALL
THERE
Before Instruction
=
0x5A
After Instruction
W
Z
=
=
0x00
1
PC = Address HERE
After Instruction
PC = Address THERE
TOS = Address HERE+1
DS30559A-page 78
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
CLRWDT
Clear Watchdog Timer
DECF
Decrement f
Syntax:
[ label ] CLRWDT
Syntax:
[ label ] DECF f,d
Operands:
None
Operands:
Operation:
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (dest)
Status Affected:
Z
Status Affected:
Encoding:
Description:
Encoding:
TO, PD
00
0000
0110
0100
CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD
are set.
Words:
1
Cycles:
1
Example
Description:
00
0011
dfff
Words:
1
Cycles:
1
Example
DECF
CNT, 1
Before Instruction
CLRWDT
CNT
Z
Before Instruction
WDT counter =
WDT counter =
WDT prescaler =
TO
=
PD
=
COMF
Complement f
Syntax:
[ label ] COMF
Operands:
=
=
0x01
0
=
=
0x00
1
After Instruction
?
CNT
Z
After Instruction
0x00
0
1
1
DECFSZ
Decrement f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) → (dest)
Operation:
(f) - 1 → (dest);
Status Affected:
Z
Status Affected:
None
Encoding:
00
1001
f,d
dfff
ffff
Description:
The contents of register 'f' are complemented. If 'd' is 0 the result is stored in
W. If 'd' is 1 the result is stored back in
register 'f'.
Words:
1
Cycles:
1
Example
ffff
Decrement register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd'
is 1 the result is stored back in register
'f'.
COMF
REG1,0
Before Instruction
REG1
=
0x13
=
=
0x13
0xEC
After Instruction
REG1
W
Encoding:
Description:
00
1011
dfff
ffff
The contents of register 'f' are decremented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
If the result is 0, the next instruction,
which is already fetched, is discarded. A
NOP is executed instead making it a two
cycle instruction.
Words:
1
Cycles:
1(2)
Example
skip if result = 0
HERE
DECFSZ
GOTO
CONTINUE •
•
•
CNT, 1
LOOP
Before Instruction
PC
=
address HERE
After Instruction
CNT
if CNT
PC
if CNT
PC
1996 Microchip Technology Inc.
=
=
=
≠
=
CNT - 1
0,
address CONTINUE
0,
address HERE+1
DS30559A-page 79
PIC16C64X & PIC16C66X
GOTO
Unconditional Branch
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 2047
Operands:
Operation:
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) + 1 → (dest), skip if result = 0
None
Status Affected:
None
Status Affected:
Encoding:
GOTO k
10
1kkk
kkkk
kkkk
Description:
GOTO is an unconditional branch. The
eleven bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTO is a two cycle instruction.
Words:
1
Cycles:
2
Example
GOTO THERE
After Instruction
PC =
Address THERE
Encoding:
Description:
00
INCFSZ f,d
1111
dfff
ffff
The contents of register 'f' are incremented. If 'd' is 0 the result is placed
in the W register. If 'd' is 1 the result is
placed back in register 'f'.
If the result is 0, the next instruction,
which is already fetched, is discarded.
A NOP is executed instead making it a
two cycle instruction.
Words:
1
Cycles:
1(2)
Example
HERE
INCFSZ
GOTO
CONTINUE •
•
•
CNT,
LOOP
1
Before Instruction
PC
=
address HERE
After Instruction
CNT =
if CNT=
PC
=
if CNT≠
PC
=
CNT + 1
0,
address CONTINUE
0,
address HERE +1
INCF
Increment f
IORLW
Inclusive OR Literal with W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ k ≤ 255
(f) + 1 → (dest)
Operation:
(W) .OR. k → (W)
Operation:
Status Affected:
Z
Status Affected:
Z
Encoding:
Description:
INCF f,d
Encoding:
00
1010
dfff
ffff
The contents of register 'f' are incremented. If 'd' is 0 the result is placed
in the W register. If 'd' is 1 the result is
placed back in register 'f'.
kkkk
Words:
1
1
Cycles:
Cycles:
1
Example
IORLW
0x35
Before Instruction
CNT, 1
W
Before Instruction
CNT
Z
kkkk
The contents of the W register is
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
1
INCF
1000
Description:
Words:
Example
11
IORLW k
=
0x9A
After Instruction
=
=
0xFF
0
=
=
0x00
1
W
Z
=
=
0xBF
1
After Instruction
CNT
Z
DS30559A-page 80
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
IORWF
Inclusive OR W with f
MOVF
Move f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) .OR. (f) → (dest)
Operation:
(f) → (dest)
Status Affected:
Z
Status Affected:
Z
Encoding:
00
IORWF
f,d
0100
dfff
ffff
Description:
Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Words:
1
Cycles:
1
Example
IORWF
RESULT, 0
Before Instruction
RESULT =
W
=
0x13
0x91
Encoding:
MOVF f,d
00
1000
Words:
1
Cycles:
1
Example
MOVF
FSR, 0
After Instruction
RESULT =
W
=
Z
=
0x13
0x93
1
W = value in FSR register
Z =1
MOVLW
Move Literal to W
MOVWF
Move W to f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
Operation:
k → (W)
Operation:
(W) → (f)
Status Affected:
None
Status Affected:
None
Encoding:
MOVLW k
00xx
kkkk
kkkk
Description:
The eight bit literal 'k' is loaded into W
register. The don’t cares will assemble
as 0’s.
Words:
1
Cycles:
1
Example
Encoding:
0x5A
=
0000
f
1fff
ffff
Description:
Words:
1
Cycles:
1
MOVWF
OPTION
Before Instruction
After Instruction
W
00
MOVWF
Move data from W register to register
'f'.
Example
MOVLW
ffff
Description:
After Instruction
11
dfff
The contents of register f is moved to
a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file
register f itself. d = 1 is useful to test a
file register since status flag Z is
affected.
0x5A
OPTION =
W
=
0xFF
0x4F
After Instruction
OPTION =
W
=
1996 Microchip Technology Inc.
0x4F
0x4F
DS30559A-page 81
PIC16C64X & PIC16C66X
NOP
No Operation
RETFIE
Return from Interrupt
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
None
Operation:
No operation
Operation:
Status Affected:
None
TOS → PC,
1 → GIE
Status Affected:
None
Encoding:
00
NOP
0000
0xx0
0000
No operation.
Encoding:
Words:
1
Description:
Cycles:
1
Description:
Example
RETFIE
00
0000
0000
1001
Return from Interrupt. Stack is POPed
and Top of Stack (TOS) is loaded in
the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE
(INTCON<7>). This is a two cycle
instruction.
NOP
Words:
1
Cycles:
2
Example
RETFIE
After Interrupt
PC =
GIE =
TOS
1
OPTION
Load Option Register
RETLW
Return with Literal in W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
0 ≤ k ≤ 255
Operation:
(W) → OPTION
Operation:
k → (W);
TOS → PC
Status Affected:
None
OPTION
Status Affected: None
Encoding:
Description:
Words:
Cycles:
00
0000
0110
0010
The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code compatibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly address
it.
Encoding:
Description:
RETLW k
11
01xx
Words:
1
1
Cycles:
2
Example
CALL TABLE
To maintain upward compatibility
with future PIC16CXX products, do
not use this instruction.
kkkk
The W register is loaded with the eight
bit literal 'k'. The program counter is
loaded from the top of the stack (the
return address). This is a two cycle
instruction.
1
Example
kkkk
•
•
•
TABLE ADDWF
RETLW
RETLW
•
•
•
RETLW
;W contains table
;offset value
;W now has table value
PC
k1
k2
;W = offset
;Begin table
;
kn
; End of table
Before Instruction
W
=
0x07
After Instruction
W
DS30559A-page 82
=
value of k8
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
RETURN
Return from Subroutine
RRF
Rotate Right f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
See description below
Status Affected:
C
RETURN
Operation:
TOS → PC
Status Affected:
None
Encoding:
Description:
00
0000
1000
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a two cycle instruction.
Words:
1
Cycles:
2
Example
0000
Encoding:
Description:
RRF f,d
00
1100
dfff
ffff
The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
C
Register f
RETURN
After Interrupt
PC =
TOS
Words:
1
Cycles:
1
Example
RRF
REG1,0
Before Instruction
REG1
C
=
=
1110 0110
0
=
=
=
1110 0110
0111 0011
0
After Instruction
REG1
W
C
RLF
Rotate Left f through Carry
SLEEP
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
None
Operation:
See description below
Operation:
Status Affected:
C
00h → WDT,
0 → WDT prescaler,
1 → TO,
0 → PD
Status Affected:
TO, PD
Encoding:
Description:
RLF
00
1101
dfff
ffff
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
stored back in register 'f'.
C
Words:
1
Cycles:
1
Example
f,d
Encoding:
REG1,0
Before Instruction
REG1
C
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
0000
0110
0011
Description:
The power-down status bit, PD is
cleared. Time-out status bit, TO is
set. Watchdog Timer and its prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
See Power-Down Mode (SLEEP) for
more details.
Words:
1
Cycles:
1
Example:
SLEEP
Register f
RLF
00
SLEEP
After Instruction
REG1
W
C
1996 Microchip Technology Inc.
DS30559A-page 83
PIC16C64X & PIC16C66X
SUBLW
Subtract W from Literal
SUBWF
Subtract W from f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
Operation:
k - (W) → (W)
0 ≤ f ≤ 127
d ∈ [0,1]
Status
Affected:
C, DC, Z
Encoding:
11
Description:
SUBLW k
110x
kkkk
kkkk
The W register is subtracted (2’s complement method) from the eight bit literal
'k'. The result is placed in the W register.
Words:
1
Cycles:
1
Example 1:
SUBLW
0x02
Before Instruction
W
C
=
=
Operation:
(f) - (W) → (dest)
Status
Affected:
C, DC, Z
Encoding:
Description:
Example 2:
=
=
1
Cycles:
1
Example 1:
SUBWF
1
?
=
=
W
C
Example 3:
=
=
=
=
REG1
W
C
2
?
Example 2:
0
1; result is zero
3
2
?
=
=
=
1
2
1; result is positive
=
=
=
2
2
?
After Instruction
3
?
0xFF
0; result is nega-
=
=
=
Before Instruction
REG1
W
C
REG1
W
C
After Instruction
W =
C
=
tive
ffff
After Instruction
Before Instruction
W
C
dfff
REG1,1
REG1
W
C
1
1; result is positive
After Instruction
0010
Before Instruction
Before Instruction
W
C
00
Subtract (2’s complement method) W register from register 'f'. If 'd' is 0 the result is
stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
Words:
After Instruction
W
C
SUBWF f,d
Example 3:
=
=
=
0
2
1; result is zero
Before Instruction
REG1
W
C
=
=
=
1
2
?
After Instruction
REG1
W
C
DS30559A-page 84
=
=
=
0xFF
2
0; result is negative
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
SWAPF
Swap Nibbles in f
XORLW
Exclusive OR Literal with W
Syntax:
[ label ] SWAPF f,d
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ k ≤ 255
Operation:
(f<3:0>) → (dest<7:4>),
(f<7:4>) → (dest<3:0>)
Operation:
(W) .XOR. k → (W)
Status Affected:
Z
Status Affected:
None
Encoding:
Description:
00
Encoding:
1110
dfff
ffff
The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the
result is placed in W register. If 'd' is 1
the result is placed in register 'f'.
Description:
1
1
XORLW
Words:
1
Cycles:
1
Example:
Example
SWAPF REG,
11
1010
0xAF
W
Before Instruction
=
W
=
=
=
0xB5
After Instruction
0xA5
After Instruction
REG1
W
=
0x1A
0xA5
0x5A
TRIS
Load TRIS Register
XORWF
Exclusive OR W with f
Syntax:
[ label ] TRIS
Syntax:
[ label ] XORWF
Operands:
5≤f≤7
Operands:
Operation:
(W) → TRIS register f;
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) .XOR. (f) → (dest)
Status Affected:
Z
f
Status Affected: None
Encoding:
Description:
00
0000
0110
0fff
The instruction is supported for code
compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly
address them.
Words:
1
Cycles:
1
kkkk
Before Instruction
0
REG1
kkkk
The contents of the W register are
XOR’ed with the eight bit literal 'k'.
The result is placed in the W register.
Words:
Cycles:
XORLW k
Example
To maintain upward compatibility
with future PIC16CXX products, do
not use this instruction.
Encoding:
Description:
00
0110
f,d
dfff
ffff
Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd'
is 1 the result is stored back in register
'f'.
Words:
1
Cycles:
1
Example
XORWF
REG
1
Before Instruction
REG
W
=
=
0xAF
0xB5
=
=
0x1A
0xB5
After Instruction
REG
W
1996 Microchip Technology Inc.
DS30559A-page 85
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 86
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
11.0
DEVELOPMENT SUPPORT
11.1
Development Tools
11.3
The PIC16/17 microcontrollers are supported with a full
range of hardware and software development tools:
• PICMASTER/PICMASTER CE Real-Time
In-Circuit Emulator
• ICEPIC Low-Cost PIC16C5X and PIC16CXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
• MPLAB-SIM Software Simulator
• MPLAB-C (C Compiler)
• Fuzzy logic development system (fuzzyTECH−MP)
11.2
PICMASTER: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
ICEPIC: Low-cost PIC16CXX In-Circuit
Emulator
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC16C5X and PIC16CXX families of 8-bit
OTP microcontrollers.
ICEPIC is designed to operate on PC-compatible
machines ranging from 286-AT through Pentium
based machines under Windows 3.x environment.
ICEPIC features real time, non-intrusive emulation.
11.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone
mode as well as PC-hosted mode.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC16C5X, PIC16CXX, PIC17CXX and
PIC14000 devices. It can also set configuration and
code-protect bits in this mode.
The PICMASTER Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXX and PIC17CXX families.
PICMASTER is supplied with the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is not
recommended for production programming.
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER
allows expansion to support all new Microchip microcontrollers.
PICSTART Plus supports all PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXX and PIC17CXX devices with up
to 40 pins. Larger pin count devices such as the
PIC16C923 and PIC16C924 may be supported with an
adapter socket.
11.5
PICSTART Plus Entry Level
Development System
The PICMASTER Emulator System has been designed
as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher)
machine platform and Microsoft Windows 3.x environment were chosen to best make these features available to you, the end user.
A CE compliant version of PICMASTER is available for
European Union (EU) countries.
1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 87
PIC16C64X & PIC16C66X
11.6
PICDEM-1 Low-Cost PIC16/17
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-16B programmer, and easily test firmware. The user can also connect the PICDEM-1
board to the PICMASTER emulator and download
the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
11.7
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-16C, and easily test firmware.
The PICMASTER emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding additional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
11.8
PICDEM-3 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the necessary hardware and software is included to run the
basic demonstration programs. The user can program the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and
easily test firmware. The PICMASTER emulator may
also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
DS30559A-page 88
an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A
simple serial interface allows the user to construct a
hardware demultiplexer for the LCD signals. PICDEM3 will be available in the 3rd quarter of 1996.
11.9
MPLAB Integrated Development
Environment Software
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PIC16/17 tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
• Transfer data dynamically via DDE (soon to be
replaced by OLE)
• Run up to four emulators on the same PC
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
11.10
Assembler (MPASM)
The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
MPASM allows full symbolic debugging from
the Microchip Universal Emulator System
(PICMASTER).
Both versions include Microchip’s fuzzyLAB demonstration board for hands-on experience with fuzzy logic
systems implementation.
MPASM has the following features to assist in developing software for specific use applications.
11.14
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol,
and special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal source
and listing formats.
MPASM provides a rich directive language to support
programming of the PIC16/17. Directives are helpful in
making the development of your assemble source code
shorter and more maintainable.
11.11
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C and MPASM. The Software Simulator offers
the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
C Compiler (MPLAB-C)
The MPLAB-C Code Development System is a complete ‘C’ compiler and integrated development environment
for
Microchip’s
PIC16/17
family
of
microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with
other compilers.
For easier source level debugging, the compiler provides symbol information that is compatible with the
MPLAB IDE memory display (PICMASTER emulator
software versions 1.13 and later).
11.13
MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can
visually configure all the peripherals in a PIC16/17
device and, with a click of the mouse, generate all the
initialization and many functional code modules in C
language. The output is fully compatible with Microchip’s MPLAB-C C compiler. The code produced is
highly modular and allows easy integration of your own
code. MP-DriveWay is intelligent enough to maintain
your code through subsequent code generation.
11.15
SEEVAL Evaluation and
Programming System
Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PIC16/17 series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The input/
output radix can be set by the user and the execution
can be performed in; single step, execute until break, or
in a trace mode.
11.12
MP-DriveWay – Application Code
Generator
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
11.16
TrueGauge Intelligent Battery
Management
The TrueGauge development tool supports system
development with the MTA11200B TrueGauge Intelligent Battery Management IC. System design verification can be accomplished before hardware prototypes
are built. User interface is graphically-oriented and
measured data can be saved in a file for exporting to
Microsoft Excel.
11.17
KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
Fuzzy Logic Development System
(fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, edition for implementing more complex systems.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 89
DS30559A-page 90
SW006005
SW006005
SW006005
SW007002
SW007002
SW007002
SW007002
PIC16C61
PIC16C62, 62A,
64, 64A
PIC16C620, 621, 622
SW006005
SW006005
SW007002
SW007002
SW007002
SW007002
SW007002
SW007002
SW007002
SW007002
PIC16C710, 711
PIC16C72
PIC16F83
Preliminary
PIC16C84
PIC16F84
PIC16C923, 924*
SW006006
SW006006
SW006006
SW006006
SW006006
SW006006
SW006006
—
SW006006
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
—
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
—
—
fuzzyTECH-MP
Explorer/Edition
Fuzzy Logic
Dev. Tool
—
Product
All 2 wire and 3 wire
Serial EEPROM's
MTA11200B
HCS200, 300, 301 *
SEEVAL Designers Kit
DV243001
N/A
N/A
TRUEGAUGE Development Kit
N/A
DV114001
N/A
PIC17C42,
SW007002
SW006005
SW006006
42A, 43, 44
*Contact Microchip Technology for availability date
**MPLAB Integrated Development Environment includes MPLAB-SIM Simulator and
MPASM Assembler
SW006005
SW006005
SW006005
SW006005
SW006005
SW006005
SW006005
SW007002
PIC16C63, 65, 65A,
73, 73A, 74, 74A
PIC16C641, 642, 661,
662*
PIC16C71
SW006006
SW006006
SW006006
—
SW006006
—
MP-DriveWay
Applications
Code
Generator
—
N/A
PG306001
Hopping Code Security Programmer Kit
N/A
N/A
DM303001
Hopping Code Security Eval/Demo Kit
N/A
****PRO MATE PICSTART Lite PICSTART Plus
*** PICMASTER/
ICEPIC
Low-Cost
PICMASTER-CE
Ultra Low-Cost
Low-Cost
II Universal
In-Circuit
In-Circuit
Dev. Kit
Universal
Microchip
Emulator
Emulator
Dev. Kit
Programmer
EM167015/
—
DV007003
—
DV003001
EM167101
EM147001/
—
DV007003
—
DV003001
EM147101
EM167015/
EM167201
DV007003
DV162003
DV003001
EM167101
EM167033/
—DV007003
—
DV003001
EM167113
EM167021/
EM167205
DV007003
DV162003
DV003001
N/A
EM167025/
EM167203
DV007003
DV162002
DV003001
EM167103
EM167023/
EM167202
DV007003
DV162003
DV003001
EM167109
EM167025/
EM167204
DV007003
DV162002
DV003001
EM167103
EM167035/
—DV007003
DV162002
DV003001
EM167105
EM167027/
EM167205
DV007003
DV162003
DV003001
EM167105
EM167027/
—
DV007003
DV162003
DV003001
EM167105
EM167025/
—
DV007003
DV162002
DV003001
EM167103
EM167029/
—
DV007003
DV162003
DV003001
EM167107
EM167029/
EM167206
DV007003
DV162003
DV003001
EM167107
EM167029/
—
DV007003
DV162003
DV003001
EM167107
EM167031/
—
DV007003
—
DV003001
EM167111
EM177007/
—
DV007003
—
DV003001
EM177107
***All PICMASTER and PICMASTER-CE ordering part numbers above include
PRO MATE II programmer
****PRO MATE socket modules are ordered separately. See development systems
ordering guide for specific ordering part numbers
TABLE 11-1:
SW006005
SW006005
SW007002
PIC16C52, 54, 54A,
55, 56, 57, 58A
PIC16C554, 556, 558
SW006005
SW006005
MPLAB C
Compiler
SW007002
** MPLAB
Integrated
Development
Environment
SW007002
PIC14000
PIC12C508, 509
Product
PIC16C64X & PIC16C66X
DEVELOPMENT TOOLS FROM MICROCHIP
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
12.0
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings †
Ambient Temperature under bias ............................................................................................................. –40° to +125°C
Storage Temperature ............................................................................................................................... –65° to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) .....................................................–0.3V to VDD + 0.3V
Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V
Voltage on MCLR with respect to VSS (Note 2) .................................................................................................0 to +14V
Total power Dissipation (Note 1) ...............................................................................................................................1.0W
Maximum Current out of VSS pin ..........................................................................................................................300 mA
Maximum Current into VDD pin .............................................................................................................................250 mA
Input Clamp Current, IIK (VI<0 or VI> VDD) .......................................................................................................................±20 mA
Output Clamp Current, IOK (Vo <0 or Vo>VDD) ................................................................................................................±20 mA
Maximum Output Current sunk by any I/O pin ........................................................................................................25 mA
Maximum Output Current sourced by any I/O pin...................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 2) ...................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 2) ..............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 2)..................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 2).............................................................200 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
Note 2: PORTD and PORTE are not implemented on the PIC16C641 and PIC16C642.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 12-1:
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16C641-04
PIC16C642-04
PIC16C661-04
PIC16C662-04
OSC
PIC16C641-10
PIC16C642-10
PIC16C661-10
PIC16C662-10
PIC16C641-20
PIC16C642-20
PIC16C661-20
PIC16C662-20
PIC16LC641-04
PIC16LC642-04
PIC16LC661-04
PIC16LC662-04
JW Devices
RC
VDD:
IDD:
IPD:
Freq:
4.0V to 6.0V
5 mA max. @ 5.5V
21 µA max. @ 4.0V
4.0 MHz max.
VDD:
IDD:
IPD:
Freq:
4.5V to 5.5V
2.7 mA typ. @ 5.5V
1.5 µA typ. @ 4.0V
4.0 MHz max.
VDD:
IDD:
IPD:
Freq:
4.5V to 5.5V
2.7 mA typ. @ 5.5V
1.5 µA typ. @ 4.0V
4.0 MHz max.
VDD:
IDD:
IPD:
Freq:
3.0V to 6.0V
2.0 mA typ. @ 3.0V
0.9 µA typ. @ 3.0V
4.0 MHz max.
VDD:
IDD:
IPD:
Freq:
4.0V to 6.0V
5 mA max. @ 5.5V
21 µA max. @ 4.0V
4.0 MHz Max.
XT
VDD:
IDD:
IPD:
Freq:
4.0V to 6.0V
5 mA max. @ 5.5V
21 µA max. @ 4.0V
4.0 MHz max.
VDD:
IDD:
IPD:
Freq:
4.5V to 5.5V
2.7 mA typ. @ 5.5V
1.5 µA typ. @ 4.0V
4.0 MHz max.
VDD:
IDD:
IPD:
Freq:
4.5V to 5.5V
2.7 mA typ. @ 5.5V
1.5 µA typ. @ 4.0V
4.0 MHz max.
VDD:
IDD:
IPD:
Freq:
3.0V to 6.0V
2.0 mA typ. @ 3.0V
0.9 µA typ. @ 3.0V
4.0 MHz max.
VDD:
IDD:
IPD:
Freq:
4.0V to 6.0V
5 mA max. @ 5.5V
21 µA max. @ 4.0V
4.0 MHz max.
HS
VDD:
IDD:
IPD:
Freq:
4.5V to 5.5V
13.5 mA typ. @ 5.5V
1.5 µA typ. @ 4.5V
4.0 MHz max.
VDD:
IDD:
IPD:
Freq:
4.5V to 5.5V
30 mA max. @ 5.5V
1.5 µA typ. @ 4.5V
10 MHz max.
VDD:
IDD:
IPD:
Freq:
Do not use in HS mode
4.5V to 5.5V
30 mA max. @ 5.5V
1.5 µA typ. @ 4.5V
20 MHz max.
VDD:
IDD:
IPD:
Freq:
4.5V to 5.5V
30 mA max. @ 5.5V
1.5 µA typ. @ 4.5V
10 MHz max.
LP
VDD: 4.0V to 6.0V
IDD: 52.5 µA typ. @
32 kHz, 4.0V
IPD: 0.9 µA typ. @ 4.0V
Freq: 200 kHz max.
Do not use in LP mode
Do not use in LP mode
VDD: 3.0V to 6.0V
IDD: 48 µA max. @
32 kHz, 3.0V
IPD: 5.0 µA max. @ 3.0V
Freq: 200 kHz max.
VDD: 3.0V to 6.0V
IDD: 48 µA max. @
32 kHz, 3.0V
IPD: 5.0 µA max. @ 3.0V
Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that
the user select the device type that ensures the specifications required.
1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 91
PIC16C64X & PIC16C66X
12.1
DC Characteristics:
Sym
Param
No.
D001
VDD
D001A
D002* VDR
D003
VPOR
PIC16C641/642/661/662-04 (Commercial, Industrial, Automotive)
PIC16C641/642/661/662-10 (Commercial, Industrial, Automotive)
PIC16C641/642/661/662-20 (Commercial, Industrial, Automotive)
Standard Operating Conditions (unless otherwise stated)
Operating temperature –40°C ≤ TA ≤ +85°C
for industrial,
0°C
≤ TA ≤ +70°C
commercial, and
–40°C ≤ TA ≤ +125°C automotive
Characteristic
Min Typ† Max Units
Supply Voltage
4.0
4.5
1.5
–
–
–
–
VSS
6.0
5.5
–
–
0.05
–
–
3.7
3.7
–
4.0
4.0
2.7
4.3
4.4
5
D010A
–
35
70
D013
–
13.5
30
–
–
350
–
425
100
D004*
SVDD
D005
VBOR
RAM Data Retention Voltage(1)
VDD start voltage to
ensure internal Power-on
Reset signal
VDD rise rate to ensure internal
Power-on Reset signal
Brown-out Reset Voltage
D010
IDD
Supply Current(2)
D015
D016
∆IBOR
∆ICOMP
Module Differential Current (5)
Brown-out Reset Current
Comparator Current for
each Comparator
VREF Current
WDT Current
V
V
V
V
Conditions
XT, RC and LP osc configuration
HS osc configuration
Device in SLEEP mode
See section on Power-on Reset for
details
V/ms See section on Power-on Reset for
details
V
BODEN configuration bit is clear
V
Automotive
mA XT and RC osc configuration
FOSC = 4 MHz, VDD = 5.5V,
WDT disabled (4)
µA LP osc configuration,
PIC16C64X & PIC16C66X-04 only
FOSC = 32 kHz, VDD = 4.0V,
WDT disabled
mA HS osc configuration
FOSC = 20 MHz, VDD = 5.5V,
WDT disabled
µA
µA
BODEN bit is clear, VDD = 5.0V
VDD = 4.0V
–
–
300 µA VDD = 4.0V
–
6.0
20
µA VDD = 4.0V
–
–
25
µA Automotive
(3)
D021
IPD
–
1.5
21
µA VDD = 4.0V, WDT disabled
Power-down Current
–
2.5
24
µA Automotive
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2Rext (mA) with Rext in kΩ.
5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
D017
D021
∆IVREF
∆IWDT
DS30559A-page 92
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
12.2
DC Characteristics:
Param
Sym
No.
D001
VDD
D002* VDR
D003
VPOR
D004*
SVDD
D005
D010
VBOR
IDD
PIC16LC641/642/661/662-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature –40°C ≤ TA ≤ +85°C
for industrial and
0°C
≤ TA ≤ +70°C
commercial
Characteristic
Min Typ† Max Units
Supply Voltage
3.0
RAM Data Retention
1.5
Voltage (1)
VDD start voltage to
–
ensure internal Power-on
Reset signal
VDD rise rate to ensure internal 0.05
Power-on Reset signal
Brown-out Reset Voltage
3.7
(2)
–
Supply Current
D010A
D015
D016
∆IBOR
∆ICOMP
D017
D021
D021
∆IVREF
∆IWDT
IPD
Module Differential Current (5)
Brown-out Reset Current
Comparator Current for
each Comparator
VREF Current
WDT Current
Conditions
–
–
6.0
–
V
V
XT, RC, and LP osc configuration
Device in SLEEP mode
VSS
–
V
See section on Power-on Reset for
details
–
–
4.0
2.0
4.3
3.8
–
22.5
48
µA
–
–
350
–
425
100
µA
µA
BODEN bit is clear, VDD = 5.0V
VDD = 3.0V
–
–
–
–
6.0
0.9
300
20
5
µA
µA
µA
VDD = 3.0V
VDD = 3.0V
VDD = 3.0V, WDT disabled
V/ms See section on Power-on Reset for
details
V
BODEN configuration bit is clear
mA XT and RC osc configuration
FOSC = 4.0 MHz, VDD = 3.0V,
WDT disabled (4)
LP osc configuration
FOSC = 32 kHz, VDD = 3.0V,
WDT disabled
Power-down Current (3)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2Rext (mA) with Rext in kΩ.
5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 93
PIC16C64X & PIC16C66X
12.3
Param
No.
DC Characteristics:
PIC16C641/661 (Commercial, Industrial, Automotive)
PIC16C642/662 (Commercial, Industrial, Automotive)
PIC16LC641/661 (Commercial, Industrial)
PIC16LC642/662 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature –40°C ≤ TA ≤ +85°C
for industrial,
0°C
≤ TA ≤ +70°C
commercial, and
–40°C ≤ TA ≤ +125°C automotive
Operating voltage VDD range as described in DC spec Section 12.1 and 12.2
Sym
Characteristic
Min
Typ
Max
Unit
†
VIL
D030
D031
D032
D033
VIH
D040
D041
D042
D043
D043A
D070 IPURB
IIL
Input Low Voltage
I/O ports
with TTL buffer
with Schmitt Trigger input
MCLR, RA4/T0CKI,OSC1 (in
RC mode)
OSC1 (XT and HS modes)
OSC1 (LP modes)
Input High Voltage
I/O ports
with TTL buffer
with Schmitt Trigger input
MCLR RA4/T0CKI
OSC1 (XT, HS, LP modes)
OSC1 (RC mode)
PORTB weak pull-up current
VSS
VSS
VSS
Vss
-
0.15VDD
0.8V
0.2VDD
0.2VDD
V
V
V
V
Vss
Vss
-
0.3VDD
0.6VDD-1.0
V
V
VDD
VDD
V
V
VDD
VDD
400
V
V
V
µA
2.0
0.25VDD
to 0.8V
0.8VDD
0.7VDD
0.9VDD
50
200
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
(1)
(1)
VDD = 5.0V, VPIN = VSS
Current(2,3)
Input Leakage
I/O ports (Except PORTA)
-
-
±1.0
µA
D060
PORTA
-
-
±0.5
µA
D061
D063
RA4/T0CKI
OSC1, MCLR
-
-
±1.0
±5.0
µA
µA
D080
Output Low Voltage
I/O ports
-
-
0.6
V
D083
OSC2/CLKOUT
-
-
0.6
0.6
V
V
VOL
Conditions
VSS ≤ VPIN ≤ VDD,
pin at hi-impedance
Vss ≤ VPIN ≤ VDD,
pin at hi-impedance
Vss ≤ VPIN ≤ VDD
Vss ≤ VPIN ≤ VDD, XT, HS and LP
osc configuration
IOL = 8.5 mA, VDD = 4.5V,
-40° to +85°C
IOL = 7.0 MA, VDD = 4.5V, +125°C
IOL = 1.6 mA, VDD = 4.5V,
-40° to +85°C
IOL = 1.2 mA, VDD = 4.5V, +125°C
(RC only)
0.6
V
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the
PIC16C64X & PIC16C66X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
DS30559A-page 94
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
Param
No.
Standard Operating Conditions (unless otherwise stated)
Operating temperature –40°C ≤ TA ≤ +85°C
for industrial,
0°C
≤ TA ≤ +70°C
commercial, and
–40°C ≤ TA ≤ +125°C automotive
Operating voltage VDD range as described in DC spec Section 12.1 and 12.2
Sym
Characteristic
Min
Typ
Max
Unit
†
VOH
D090
Output High Voltage (3)
I/O ports (Except RA4)
D092
OSC2/CLKOUT
D100
(RC only)
Capacitive Loading Specs
on Output Pins
OSC2 pin
COSC2
VDD-0.7
-
-
V
VDD-0.7
-
-
V
VDD-0.7
-
-
V
VDD-0.7
-
-
V
-
-
15
pF
Conditions
IOH = -3.0 mA, VDD = 4.5V,
-40° to +85°C
IOH = -2.5 mA,
VDD = 4.5V, +125°C
IOH = -1.3 mA, VDD=4.5V,
-40° to +85°C
IOH = -1.0 mA,
VDD = 4.5V, +125°C
In XT, HS and LP modes when
external clock used to drive OSC1.
D101 CIO
All I/O pins/OSC2 (in RC mode)
50
pF
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the
PIC16C64X & PIC16C66X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 95
PIC16C64X & PIC16C66X
TABLE 12-2:
COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 6.0V, -40˚C < TA < +125˚C, unless otherwise stated. Current consumption is specified in Table 12-1.
Characteristics
Sym
Input offset voltage
Min
Typ
Max
Units
-
± 5.0
± 10
mV
Input common mode voltage*
0
-
VDD - 1.5
V
CMRR*
35
-
-
db
Response Time(1)*
-
150
400
600
ns
ns
Comparator Mode Change to
Output Valid*
-
-
10
µs
Comments
PIC16C64X/66X
PIC16LC64X/66X
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from
VSS to VDD.
TABLE 12-3:
VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 6.0V, -40°C < TA < +125°C, unless otherwise stated. Current consumption is specified in Table 12-1.
Characteristics
Sym
Min
Typ
Max
Units
VDD/24
-
VDD/32
LSb
Absolute Accuracy
-
-
1/4
1/2
LSb
LSb
Unit Resistor Value (R)*
-
2k
-
Ω
-
-
10
µs
Resolution
(1)*
Settling Time
Comments
Low Range (VRR = 1)
High Range (VRR = 0)
Figure 8-2
* These parameters are characterized but not tested.
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.
DS30559A-page 96
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
12.4
Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency
Lowercase subscripts (pp) and their meanings:
pp
ck CLKOUT
io I/O port
mc MCLR
Uppercase letters and their meanings:
S
F Fall
H High
I
Invalid (Hi-impedance)
L Low
T
Time
osc OSC1
t0 T0CKI
P
R
V
Z
Period
Rise
Valid
Hi-Impedance
FIGURE 12-1: LOAD CONDITIONS
Load condition 2
Load condition 1
VDD/2
RL
CL
Pin
VSS
VSS
RL =
464Ω
CL =
50 pF
for all pins except OSC2
15 pF
for OSC2 output
1996 Microchip Technology Inc.
CL
Pin
Preliminary
DS30559A-page 97
PIC16C64X & PIC16C66X
12.5
Timing Diagrams and Specifications
FIGURE 12-2: EXTERNAL CLOCK TIMING
Q4
Q1
Q3
Q2
Q4
Q1
OSC1
1
3
3
4
4
2
CLKOUT
TABLE 12-4:
Param
No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Fosc
Characteristic
Min
Typ†
Max
External CLKIN Frequency(1)
DC
—
4
Units
MHz
Conditions
XT and RC osc mode,
VDD = 5.0V
HS osc mode
LP osc mode
RC osc mode, VDD = 5.0V
XT osc mode
HS osc mode
LP osc mode
XT and RC osc mode
HS osc mode
LP osc mode
RC osc mode
XT osc mode
HS osc mode
LP osc mode
TCY = FOSC/4
XT osc mode
LP osc mode
HS osc mode
XT osc mode
LP osc mode
HS osc mode
DC
—
20
MHz
DC
—
200 kHz
Oscillator Frequency (1)
DC
—
4
MHz
0.1
—
4
MHz
4
—
20
MHz
5
–
200 kHz
1
Tosc
External CLKIN Period(1)
250
—
—
ns
50
—
—
ns
5
—
—
µs
Oscillator Period(1)
250
—
—
ns
250
—
10,000 ns
50
—
250 ns
5
—
—
µs
2
TCY
Instruction Cycle Time(1)
200
—
DC
ns
3*
TosL, External Clock in (OSC1)
100
—
—
ns
TosH High or Low Time
2.5
—
—
µs
15
—
—
ns
4*
TosR, External Clock in (OSC1)
—
—
25
ns
TosF Rise or Fall Time
—
—
50
ns
—
—
15
ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an
external clock applied to the OSC1 pin.
When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices.
DS30559A-page 98
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
FIGURE 12-3: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
22
23
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: See Figure 12-1 for load conditions.
TABLE 12-5:
CLKOUT AND I/O TIMING REQUIREMENTS
Parameter Sym
No.
Characteristic
Min
Typ†
Max
Units Conditions
10*
TosH2ckL
OSC1↑ to CLKOUT↓
—
75
200
ns
Note 1
11*
TosH2ckH OSC1↑ to CLKOUT↑
—
75
200
ns
Note 1
12*
TckR
CLKOUT rise time
—
35
100
ns
Note 1
13*
TckF
CLKOUT fall time
—
35
100
ns
Note 1
14*
TckL2ioV
CLKOUT ↓ to Port out valid
—
—
0.5TCY + 20
ns
Note 1
15*
TioV2ckH
Port in valid before CLKOUT ↑
TOSC + 200
—
—
ns
Note 1
16*
TckH2ioI
Port in hold after CLKOUT ↑
0
—
—
ns
Note 1
17*
TosH2ioV
OSC1↑ (Q1 cycle) to
Port out valid
—
50
150
ns
18*
TosH2ioI
OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
PIC16C64X/66X
100
—
—
ns
PIC16LC64X/66X
200
—
—
ns
19*
TioV2osH
Port input valid to OSC1↑ (I/O in setup time)
0
—
—
ns
20*
TioR
Port output rise time
PIC16C64X/66X
—
10
40
ns
PIC16LC64X/66X
—
—
80
ns
PIC16C64X/66X
—
10
40
ns
PIC16LC64X/66X
—
—
80
ns
21*
TioF
Port output fall time
22††*
Tinp
INT pin high or low time
TCY
—
—
ns
23††*
Trbp
RB7:RB4 change INT high or low time
TCY
—
—
ns
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 99
PIC16C64X & PIC16C66X
FIGURE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Timeout
32
OSC
Timeout
Internal
RESET
Parity
Error
Reset
36
Watchdog
Timer
RESET
34
31
34
I/O Pins
FIGURE 12-5: BROWN-OUT RESET TIMING
BVDD
VDD
35
TABLE 12-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No.
Sym
30
TmcL
MCLR Pulse Width (low)
2
—
—
µs
VDD = 5V, -40˚C to +125˚C
31*
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7
18
33
ms
VDD = 5V, -40˚C to +125˚C
32
Tost
33*
Tpwrt
34
35
36
*
†
Characteristic
Min
Typ†
Max
Units
Conditions
Oscillation Start-up Timer Period
—
1024TOSC
—
—
TOSC = OSC1 period
Power up Timer Period
28
72
132
ms
VDD = 5V, -40˚C to +125˚C
TIOZ
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
—
—
2.1
µs
TBOR
Brown-out Reset pulse width
100
—
—
µs
TPER
Parity Error Reset
—
TBD
—
µs
VDD ≤ BVDD (D005)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30559A-page 100
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
FIGURE 12-6: TIMER0 CLOCK TIMING
RA4/T0CKI
41
40
42
TMR0
TABLE 12-7:
TIMER0 CLOCK REQUIREMENTS
Param
Sym
No.
Characteristic
40*
Tt0H T0CKI High Pulse Width
41*
Tt0L T0CKI Low Pulse Width
42*
Tt0P T0CKI Period
Min
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5TCY + 20
10
0.5TCY + 20
10
TCY + 40
N
Typ† Max Units
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
Conditions
N = prescale
value (1, 2, 4, …,
256)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 101
PIC16C64X & PIC16C66X
FIGURE 12-7: PARALLEL SLAVE PORT TIMING (PIC16C661 AND PIC16C662)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 12-1 for load conditions
TABLE 12-8:
Parameter
No.
PARALLEL SLAVE PORT REQUIREMENTS (PIC16C661 AND PIC16C662)
Sym
Characteristic
Min Typ† Max Units
62
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)
20
—
—
ns
63*
TwrH2dtI
20
—
—
ns
35
—
—
ns
WR↑ or CS↑ to data–in invalid (hold time) PIC16C66X
PIC16LC66X
†
64
TrdL2dtV
RD↓ and CS↓ to data–out valid
—
—
80
ns
65
TrdH2dtI
RD↑ or CS↓ to data–out invalid
10
—
30
ns
Conditions
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30559A-page 102
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
13.0
DEVICE CHARACTERIZATION
INFORMATION
NOT AVAILABLE AT THIS TIME.
1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 103
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 104
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
14.0
PACKAGING INFORMATION
Package Type: 28-Lead Skinny Plastic Dual In-Line (SP) - 300 mil
E1
E
C
eA
eB
Pin No. 1
Indicator
Area
B2
Base
Plane
Seating
Plane
S
B1
D
L
e1
Detail A
A1A2A
D1
B
B3
Detail A
Package Group: Plastic Dual In-Line (PLA)
Millimeters
Symbol
Min
Max
A
A1
A2
B
B1
B2
B3
C
D
D1
E
E1
e1
eA
eB
L
S
3.632
0.381
3.175
0.406
1.016
0.762
0.203
0.203
34.163
33.020
7.874
7.112
2.540
7.874
8.128
3.175
0.584
4.572
—
3.556
0.559
1.651
1.016
0.508
0.331
35.179
33.020
8.382
7.493
2.540
7.874
9.906
3.683
1.220
1996 Microchip Technology Inc.
Inches
Notes
Typical
4 places
4 places
Typical
BSC
Typical
BSC
Min
Max
0.143
0.015
0.125
0.016
0.040
0.030
0.008
0.008
1.385
1.300
0.310
0.280
0.100
0.310
0.320
0.125
0.023
0.180
—
0.140
0.022
0.065
0.040
0.020
0.013
1.395
1.300
0.330
0.295
0.100
0.310
0.390
0.145
0.048
Preliminary
This document was created with FrameMaker 4 0 4
Notes
Typical
4 places
4 places
Typical
BSC
Typical
BSC
DS30559A-page 105
PIC16C64X & PIC16C66X
Package Type: 28-Lead Plastic Small Outline (SO) - Wide, 300 mil Body
e
B
h x 45°
Pin No. 1
Indicator
Area
E
H
Chamfer
h x 45°
α
C
L
D
Seating
Plane
Base
Plane
CP
A1
A
Package Group: Plastic SOIC (SO)
Millimeters
Symbol
Min
Max
α
0°
A
A1
B
C
D
E
e
H
h
L
CP
2.362
0.101
0.355
0.241
17.703
7.416
1.270
10.007
0.381
0.406
—
DS30559A-page 106
Inches
Notes
Min
Max
8°
0°
8°
2.642
0.300
0.483
0.318
18.085
7.595
1.270
10.643
0.762
1.143
0.102
0.093
0.004
0.014
0.009
0.697
0.292
0.050
0.394
0.015
0.016
—
0.104
0.012
0.019
0.013
0.712
0.299
0.050
0.419
0.030
0.045
0.004
BSC
Preliminary
Notes
BSC
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
Package Type: 28-Lead Ceramic Side Brazed Dual In-Line with Window (JW) (300 mil)
α
E1 E
C
eA
eB
Pin No. 1
Indicator Area
D
S1
S
Base
Plane
Seating
Plane
L
B1
A3
A1
A2
A
e1
B
D1
Package Group: Ceramic Side Brazed Dual In-Line (CER)
Millimeters
Inches
Symbol
α
A
A1
A2
A3
B
B1
C
D
D1
E
E1
e1
eA
eB
L
S
S1
Min
Max
0°
3.937
1.016
2.921
1.930
0.406
1.219
0.228
35.204
32.893
7.620
7.366
2.413
7.366
7.594
3.302
1.143
0.533
10°
5.030
1.524
3.506
2.388
0.508
1.321
0.305
35.916
33.147
8.128
7.620
2.667
7.874
8.179
4.064
1.397
0.737
1996 Microchip Technology Inc.
Notes
Typical
Typical
BSC
Typical
BSC
Preliminary
Min
Max
0°
0.155
0.040
0.115
0.076
0.016
0.048
0.009
1.386
1.295
0.300
0.290
0.095
0.290
0.299
0.130
0.045
0.021
10°
0.198
0.060
0.138
0.094
0.020
0.052
0.012
1.414
1.305
0.320
0.300
0.105
0.310
0.322
0.160
0.055
0.029
Notes
DS30559A-page 107
PIC16C64X & PIC16C66X
Package Type: 40-Lead Ceramic Dual In-Line with Window (JW) - (600 mil)
E1
E
α
C
Pin No. 1
Indicator
Area
eA
eB
D
S
Base
Plane
S1
Seating
Plane
L
B1
B
e1
A1A3 A A2
D1
Package Group: Ceramic CERDIP Dual In-Line (CDP)
Millimeters
Symbol
Min
Max
Inches
Notes
Min
Max
α
0°
10°
0°
10°
A
A1
A2
A3
B
B1
C
D
D1
E
E1
e1
eA
eB
L
S
S1
4.318
0.381
3.810
3.810
0.355
1.270
0.203
51.435
48.260
15.240
12.954
2.540
14.986
15.240
3.175
1.016
0.381
5.715
1.778
4.699
4.445
0.585
1.651
0.381
52.705
48.260
15.875
15.240
2.540
16.002
18.034
3.810
2.286
1.778
0.170
0.015
0.150
0.150
0.014
0.050
0.008
2.025
1.900
0.600
0.510
0.100
0.590
0.600
0.125
0.040
0.015
0.225
0.070
0.185
0.175
0.023
0.065
0.015
2.075
1.900
0.625
0.600
0.100
0.630
0.710
0.150
0.090
0.070
DS30559A-page 108
Typical
Typical
BSC
BSC
Typical
Preliminary
Notes
Typical
Typical
BSC
BSC
Typical
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
Package Type: 40-Lead Plastic Dual In-Line (P) - 600 mil
E1
E
C
eA
eB
Pin No. 1
Indicator
Area
D
Base
Plane
S
Seating
Plane
B1
B
S1
L
e1
A1A2 A
D1
Package Group: Plastic Dual In-Line (PLA)
Millimeters
Symbol
Min
Max
A
A1
A2
B
B1
C
D
D1
E
E1
e1
eA
eB
L
S
S1
—
0.381
3.175
0.355
1.270
0.203
51.181
48.260
15.240
13.462
2.489
15.240
15.748
2.921
1.270
0.508
5.080
—
4.064
0.559
1.778
0.381
52.197
48.260
15.875
13.970
2.591
15.240
17.272
3.683
—
—
1996 Microchip Technology Inc.
Inches
Notes
Typical
Typical
BSC
Typical
BSC
Preliminary
Min
Max
—
0.015
0.125
0.014
0.050
0.008
2.015
1.900
0.600
0.530
0.098
0.600
0.620
0.115
0.050
0.020
0.200
—
0.160
0.022
0.070
0.015
2.055
1.900
0.625
0.550
0.102
0.600
0.680
0.145
—
—
Notes
Typical
Typical
BSC
Typical
BSC
DS30559A-page 109
PIC16C64X & PIC16C66X
Package Type: 44-Lead Plastic Leaded Chip Carrier (L) - Square
D/2
D
-A-
D1
-D-
3
-F-
0.812/0.661 N Pics
.032/.026
1.27
.050
2 Sides
0.177
.007 S B D-E S
-HA
A1
3
D3/E3
D2
3
-G-
8
0.38
.015
E/2
E1
F-G S
D
0.177
.007 S B A S
2 Sides
9
0.101 Seating
.004 Plane
-C-
4
E2
E
0.38
.015
F-G S
4
-B-
3
-E-
0.177
.007 S A F-G S
10
0.254
.010 Max
2
0.254
.010 Max
11
-H-
11
0.508
.020
0.508
.020
-H-
2
0.812/0.661
3
.032/.026
1.524
.060 Min
6
6
-C1.651
.065
1.651
.065
R 1.14/0.64
.045/.025
R 1.14/0.64
.045/.025
5
0.533/0.331
.021/.013
0.64 Min
.025
0.177
, D-E S
.007 M A F-G S
Package Group: Plastic Leaded Chip Carrier (PLCC)
Millimeters
Symbol
Min
Max
A
4.191
A1
D
D1
D2
D3
E
E1
E2
E3
CP
LT
2.413
17.399
16.510
15.494
12.700
17.399
16.510
15.494
12.700
—
0.203
DS30559A-page 110
Inches
Notes
Min
Max
4.572
0.165
0.180
2.921
17.653
16.663
16.002
12.700
17.653
16.663
16.002
12.700
0.102
0.381
0.095
0.685
0.650
0.610
0.500
0.685
0.650
0.610
0.500
—
0.008
0.115
0.695
0.656
0.630
0.500
0.695
0.656
0.630
0.500
0.004
0.015
BSC
BSC
Preliminary
Notes
BSC
BSC
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
Package Type: 44-Lead Thin Plastic Quad Flatpack (PT/TQ) - 10x10x1 mm Body 1.0/0.10 mm Lead Form
D1
D
D/2
PinNo. 1
Indicator
Area
E1
E
e
E/2
8 Places
11/13°
A
0° min.
Detail B
A2
Datum Plane
0.25
b
with Lead Finish
0.09/0.20
0.08
R min.
A1
0.20 min.
0.09/0.16
0-7°
Gauge Plane
L
1.00 ref.
b1
Base Metal
DETAIL B
Package Group: Plastic TQFP
Millimeters
Symbol
Min
Max
α
A
A1
A2
b
b1
D
D1
E
E1
e
L
0°
—
0.050
0.950
0.300
0.300
12.0
10.0
12.0
10.0
0.8
0.450
7°
1.200
0.150
1.050
0.450
0.400
12.0
10.0
12.0
10.0
0.8
0.750
1996 Microchip Technology Inc.
Inches
Notes
BSC
BSC
BSC
BSC
BSC
Preliminary
Min
Max
0°
—
0.002
0.037
0.012
0.012
0.472
0.394
0.472
0.394
0.031
0.018
7°
0.047
0.006
0.041
0.018
0.016
0.0472
0.394
0.472
0.394
0.031
0.030
Notes
BSC
BSC
BSC
BSC
BSC
DS30559A-page 111
PIC16C64X & PIC16C66X
14.1
Package Marking Information
28-Lead PDIP (Skinny DIP)
Example
MMMMMMMMMMMM
XXXXXXXXXXXXXXX
AABBCDE
28-Lead SOIC
PIC16C642-10/SP
AABBCDE
Example
MMMMMMMMMMMMMMMM
XXXXXXXXXXXXXXXXXXXX
AABBCDE
28-Lead Side Brazed Skinny Windowed
PIC16C642-10/SO
945/CAA
Example
XXXXXXXXXXX
XXXXXXXXXXX
AABBCDE
PIC16C642/JW
9517CAT
Legend: MM...MMicrochip part number information
XX...X Customer specific information*
AA
Year code (last 2 digits of calendar year)
BB
Week code (week of January 1 is week ‘01’)
C
Facility code of the plant at which wafer is manufactured
C = Chandler, Arizona, U.S.A.
D
Mask revision number
E
Assembly code of the plant or country of origin in which
part was assembled
Note:In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next
line thus limiting the number of available characters for customer specific information.
*Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and
assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in QTP price.
DS30559A-page 112
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
14.2
Package Marking Information
40-Lead PDIP
Example
MMMMMMMMMMMMMM
XXXXXXXXXXXXXXXXXX
AABBCDE
PIC16C662-04/P
9512CAA
40-Lead CERDIP Windowed
Example
MMMMMMMMM
XXXXXXXXXXX
XXXXXXXXXXX
AABBCDE
44-Lead PLCC
PIC16C662/JW
AABBCDE
Example
PIC16C662
-20/L
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
44-Lead TQFP
AABBCDE
Example
PIC16C662
-20/TQ
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
AABBCDE
Legend: MM...MMicrochip part number information
XX...X Customer specific information*
AA
Year code (last 2 digits of calendar year)
BB
Week code (week of January 1 is week ‘01’)
C
Facility code of the plant at which wafer is manufactured
C = Chandler, Arizona, U.S.A.
D
Mask revision number
E
Assembly code of the plant or country of origin in which
part was assembled
Note:In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next
line thus limiting the number of available characters for customer specific information.
*Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and
assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in QTP price.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 113
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 114
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
APPENDIX A: ENHANCEMENTS
APPENDIX B: COMPATIBILITY
The following are the list of enhancements over the
PIC16C5X microcontroller family:
To convert code written for PIC16C5X to PIC16CXX,
the user should take the following steps:
1.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
Instruction word length is increased to 14 bits.
This allows larger page sizes both in program
memory (4K now as opposed to 512 before) and
register file (up to 176 bytes now versus 32 bytes
before).
A PC high latch register (PCLATH) is added to
handle program memory paging. PA2, PA1, PA0
bits are removed from STATUS register.
Data memory paging is slightly redefined.
STATUS register is modified.
Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW.
Two instructions TRIS and OPTION are being
phased out although they are kept for
compatibility with PIC16C5X.
OPTION and TRIS registers are made
addressable.
Interrupt capability is added. Interrupt vector is
at 0004h.
Stack size is increased to 8 deep.
Reset vector is changed to 0000h.
Reset of all registers is revisited. Six different
reset (and wake-up) types are recognized.
Registers are reset differently.
Wake up from SLEEP through interrupt is
added.
Two separate timers, Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) are
included for more reliable power-up. These
timers can be invoked selectively to avoid
unnecessary delays on power-up and wake-up.
PORTB has weak pull-ups and interrupt on
change feature.
Timer0 clock input, T0CKI pin is also a port pin
(RA4/T0CKI) and has a TRIS bit.
FSR is made a full 8-bit register.
“In-circuit programming” is made possible. The
user can program PIC16CXX devices using only
five pins: VDD, VSS, VPP, RB6 (clock) and RB7
(data in/out).
PCON status register is added with a Power-on
Reset status bit (POR), a Brown-out Reset status bit (BOR), a Parity Error Reset (PER), and a
Memory Parity Enable (MPEEN) bit.
Code protection scheme is enhanced such that
portions of the program memory can be
protected, while the remainder is unprotected.
PORTA inputs are now Schmitt Trigger inputs.
Brown-out Reset circuitry has been added.
1996 Microchip Technology Inc.
2.
3.
4.
5.
Remove any program memory page select
operations (PA2, PA1, PA0 bits) for CALL, GOTO.
Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
Eliminate any data memory page switching.
Redefine data variables to reallocate them.
Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
Change reset vector to 0000h.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 115
PIC16C64X & PIC16C66X
APPENDIX C: WHAT’S NEW
APPENDIX D: WHAT’S CHANGED
New Data Sheet
New Data Sheet
DS30559A-page 116
Preliminary
1996 Microchip Technology Inc.
PIC14000
20
o
em
y
or
(x
)
r
wo
2
/I
I
SP
C
,U
T)
R
SA
Peripherals
g
in
m
am
4K
192
s
te
by
TMR0
I2C/
ADTMR SMBus
M
14
11
22
2.7-6.0
Internal Oscillator,
Bandgap Reference,
Temperature Sensor,
Calibration Factors,
Yes Low Voltage Detector,
SLEEP, HIBERNATE,
Comparators with
Programmable References
(2)
)
r
ts
gr
ol
rte nels
p
ro
V
s
e
(
)
P
m
hi
e
v
n
s
l
a
(
-c
rc
ia
ue
on ha
)(
e(
ge
y
gr
n
u
l
r
q
r
s
n
o
C
o
u
e
e
C
o
t(
a
S
lO
Pr
D )
Fr
R
od
or
tS
em
pt ins
na res
A/ -res
e
M
M
ui
u
lP
o
um
M
g
c
i
r
r
e
O
r
u
t
a
r
h
i
e
im
ri
R
ta
lta
di at
op ig
te /O P
m
-C
ax
Se
In
Sl (h
EP
I
Vo
Da
Ti
Ad Fe
M
In
y
nc
r
pe
fO
n
io
at
14
Memory
)
ds
Pa
a
ck
ge
s
28-pin DIP, SOIC, SSOP
(.300 mil)
Features
E.1
)
Hz
(M
Clock
PIC16C64X & PIC16C66X
APPENDIX E: PIC16/17 MICROCONTROLLERS
PIC14000 Devices
1996 Microchip Technology Inc.
DS30559A-page 117
This document was created with FrameMaker 4 0 4
20
20
20
20
20
20
20
20
PIC16C54A
PIC16CR54A
PIC16C55
PIC16C56
PIC16C57
PIC16CR57B
PIC16C58A
PIC16CR58A
im
um
en
qu
—
2K
—
2K
1K
512
—
512
—
RO
2K
—
2K
—
—
—
512
—
—
73
73
72
72
25
24
25
25
25
25
RA
D
M
M
at
a
Fr
e
384
yte
s)
or
TMR0
em
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
12
)
12
12
20
20
12
20
12
12
12
2.5-6.25
ns
2.5-6.25
2.0-6.25
2.5-6.25
2.5-6.25
2.5-6.25
2.5-6.25
2.0-6.25
2.0-6.25
2.5-6.25
e
33
33
33
33
33
33
33
33
33
33
ng
M
cy
of
O
p
er
at
ion
P
(
r
M
og
Hz
(x ram
)
12 M
wo em
rd or
s) y
OM
EP
R
512
y(
b
Ti
m
M
er
(s
le
od
u
Peripherals
es
s
In
ax
18-pin DIP, SOIC
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
28-pin DIP, SOIC, SSOP
28-pin DIP, SOIC, SSOP
18-pin DIP, SOIC; 20-pin SSOP
28-pin DIP, SOIC, SSOP
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
Features
All PIC16/17 Family devices have Power-On Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
4
20
PIC16C54
M
PIC16C52
Pi
I/O
on
cti
Memory
e
)
Nu
Ra
ag
Vo
lt
lts
(V
o
m
be
r
of
str
u
P
DS30559A-page 118
ag
E.2
ac
k
Clock
PIC16C64X & PIC16C66X
PIC16C5X Family of Devices
1996 Microchip Technology Inc.
20
20
20
20
20
20
20
20
PIC16C558
PIC16C620
PIC16C621
PIC16C622
PIC16C641
PIC16C642
PIC16C661
PIC16C662
Fr
e
im
um
en
cy
o
4K
2K
4K
2K
2K
1K
512
2K
p
fO
M
80
176
128
176
128
128
80
80
128
y(
b
s)
em
or
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
2
2
2
2
2
2
2
—
—
—
ra
t
qu
1K
yte
m
TMR0
pa
)
Co
m
)
or
te
(M
n
tio
Da
80
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
—
—
5
5
4
4
4
4
4
3
3
3
en
ce
M
er
a
O
EP
R
512
33
33
22
22
13
13
13
13
13
13
3.0-6.0
3.0-6.0
3.0-6.0
3.0-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
—
—
t
ge
o
Features
40-pin PDIP, Windowed CDIP;
44-pin PLCC, MQFP
40-pin PDIP, Windowed CDIP;
44-pin PLCC, MQFP
28-pin PDIP, SOIC
Windowed CDIP
28-pin PDIP, SOIC
Windowed CDIP
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O
current capability.
All PIC16C6XXX Family devices use serial programming with clock pin RB6 and data pin RB7.
20
PIC16C556
M
20
ax
PIC16C554
e
lR
fe
r
I
Hz
Pr
og
)
r
(x1 am
4 Me
w
or mor
ds y
)
ta
(s
du
le
M
er
Ti
e
ta
rc
So
u
pt
s)
ou
Vo
l
ru
nt
e
(s
rn
a
In
se
tR
e
Peripherals
ng
(V
B
e
ns
Pi
I/O
e
Ra
ag
Vo
lt
olt
nro
w
1996 Microchip Technology Inc.
P
Memory
ag
es
E.3
ac
k
Clock
PIC16C64X & PIC16C66X
PIC16CXXX Family of Devices
DS30559A-page 119
DS30559A-page 120
20
20
20
20
20
PIC16CR63(1)
PIC16C64
PIC16C64A(1)
PIC16CR64(1)
PIC16C65
Features
—
4K
4K
—
2K
2K
—
4K
—
2K
2K
4K
—
—
2K
—
—
4K
—
2K
—
—
192 TMR0,
TMR1, TMR2
192 TMR0,
TMR1, TMR2
192 TMR0,
TMR1, TMR2
128 TMR0,
TMR1, TMR2
128 TMR0,
TMR1, TMR2
128 TMR0,
TMR1, TMR2
192 TMR0,
TMR1, TMR2
192 TMR0,
TMR1, TMR2
128 TMR0,
TMR1, TMR2
128 TMR0,
TMR1, TMR2
128 TMR0,
TMR1, TMR2
H
2 SPI/I2C, Yes
USART
11
11
11
2 SPI/I2C, Yes
USART
2 SPI/I2C, Yes
USART
8
8
8
10
10
7
7
7
Yes
1 SPI/I2C
Yes
Yes
1 SPI/I2C
1 SPI/I2C
—
—
2 SPI/I2C,
USART
2 SPI/I2C,
USART
—
—
—
1 SPI/I2C
1 SPI/I2C
1 SPI/I2C
33
33
33
33
33
33
22
22
22
22
22
2.5-6.0
2.5-6.0
3.0-6.0
2.5-6.0
2.5-6.0
3.0-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
3.0-6.0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
28-pin SDIP, SOIC, SSOP
40-pin DIP;
44-pin PLCC, MQFP
40-pin DIP;
44-pin PLCC, MQFP
Yes 40-pin DIP;
44-pin PLCC, MQFP, TQFP
Yes 40-pin DIP;
44-pin PLCC, MQFP, TQFP
—
Yes 40-pin DIP;
44-pin PLCC, MQFP, TQFP
Yes 40-pin DIP;
44-pin PLCC, MQFP, TQFP
—
Yes 28-pin SDIP, SOIC
Yes 28-pin SDIP, SOIC
Yes 28-pin SDIP, SOIC, SSOP
Yes 28-pin SDIP, SOIC, SSOP
—
All PIC16/17 family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and high I/O current capability.
All PIC16C6X family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local sales office for availability of these devices.
20
20
PIC16C63
PIC16CR65(1)
20
PIC16CR62(1)
20
20
PIC16C62A(1)
PIC16C65A(1)
20
PIC16C62
(M
s)
Peripherals
y
(
or
le
T)
m )
g
du
e
s
o
in
i
AR
t
M
d
a
M
r
m
S
r
o
m
e
U
m
M
p
a w
,
)
a
O
)
2C
W
gr 4
ts
gr
of
ol
/I
/P
t
es
ro (x1
ro
I
t
r
y
e
V
P
y
s
P
r
o
P
)
(
et
e
l
nc
S
P
(b
(s
pa
rc
ge
e
ue
es
y
ria
)(
le
u
r
m
q
v
n
s
e
R
u
o
e
o
a
la
rt(
So
Fr
R
ut
tS
od
/C
es
em
lS
ui
pt ins
e
M
M
-o
Po
re
e
c
M
l
um
u
l
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C
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ax
Se
Da
In
In
Br
Pa
Ca
EP
RO
Ti
Pa
Vo
I/O
M
on
Memory
E.4
z)
Clock
PIC16C64X & PIC16C66X
PIC16C6X Family of Devices
1996 Microchip Technology Inc.
1996 Microchip Technology Inc.
4K
4K
4K
4K
20
20
20
20
20
PIC16C72
PIC16C73
PIC16C73A
PIC16C74
PIC16C74A
M
a
M
8
8
192 TMR0,
2 SPI/I2C, Yes
TMR1, TMR2
USART
5
192 TMR0,
2 SPI/I2C, Yes
TMR1, TMR2
USART
5
4
4
4
5
—
—
—
—
—
—
—
l
le
al
r
Pa
192 TMR0,
2 SPI/I2C,
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—
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8
4
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12
12
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33
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22
22
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13
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2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
18-pin DIP, SOIC
28-pin SDIP, SOIC
40-pin DIP;
44-pin PLCC, MQFP
Yes 40-pin DIP;
44-pin PLCC, MQFP, TQFP
—
Yes 28-pin SDIP, SOIC
—
Yes 28-pin SDIP, SOIC, SSOP
Yes 18-pin DIP, SOIC;
20-pin SSOP
—
Yes 18-pin DIP, SOIC;
20-pin SSOP
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36
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M
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gr
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Pr
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Memory
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current
capability.
All PIC16C7X Family devices use serial programming with clock pin RB6 and data pin RB7.
2K
1K
1K
20
20
PIC16C71
PIC16C711
512
20
um
im
PIC16C710
ax
M
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Fr
cy
r
pe
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)
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)
Hz
Clock
PIC16C64X & PIC16C66X
PIC16C7X Family of Devices
DS30559A-page 121
10
10
10
10
PIC16F84(1)
PIC16CR84(1)
PIC16F83(1)
PIC16CR83(1)
F
—
512
—
1K
—
—
—
—
—
1K
—
1K
—
—
512
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36
36
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68
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64
64
64
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TMR0
TMR0
TMR0
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4
4
4
4
Peripherals
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Features
13
13
13
13
13
2.0-6.0 18-pin DIP, SOIC
2.0-6.0 18-pin DIP, SOIC
2.0-6.0 18-pin DIP, SOIC
2.0-6.0 18-pin DIP, SOIC
2.0-6.0 18-pin DIP, SOIC
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ce
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M
am
r
og
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36
M
RO
M
ra
pe
O
O
PR
of
n
tio
)
Hz
All PIC16/17 family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and
high I/O current capability.
All PIC16C8X family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local sales office for availability of these devices.
10
PIC16C84
a
M
um
xim
cy
n
ue
q
re
h
DS30559A-page 122
as
E.6
Fl
Clock
PIC16C64X & PIC16C66X
PIC16C8X Family of Devices
1996 Microchip Technology Inc.
1996 Microchip Technology Inc.
y
or
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R
SA
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(s
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ne
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Features
4K
8
PIC16C924
176 TMR0,
1 SPI/I2C
TMR1, TMR2
176 TMR0,
1 SPI/I2C
TMR1, TMR2
am
—
—
5
—
4 Com
32 Seg
4 Com
32 Seg
,U
9
8
25
25
27
27
3.0-6.0
3.0-6.0
Yes
Yes
—
—
64-pin SDIP(1), TQFP,
68-pin PLCC, DIE
64-pin SDIP(1), TQFP,
68-pin PLCC, DIE
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
All PIC16CXX Family devices use serial programming with clock pin RB6 and data pin RB7.
1: Please contact your local Microchip representative for availability of this package.
4K
8
PIC16C923
Note
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In
Da
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M
In
Br
Ca
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i
at
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Memory
E.7
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Clock
PIC16C64X & PIC16C66X
PIC16C9XX Family Of Devices
DS30559A-page 123
25
25
25
25
25
PIC17C42A
PIC17CR42
PIC17C43
PIC17CR43
PIC17C44
im
8K
—
4K
—
2K
u
eq
4K
—
2K
—
—
RO
EP
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RO
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454
454
454
232
232
232
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TMR0,TMR1, 2 2
TMR2,TMR3
TMR0,TMR1, 2 2
TMR2,TMR3
TMR0,TMR1, 2 2
TMR2,TMR3
TMR0,TMR1, 2 2
TMR2,TMR3
TMR0,TMR1, 2 2
TMR2,TMR3
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Yes
Yes
Yes
Yes
—
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Yes
Yes
Yes
Yes
Yes
ly
11
11
11
11
11
11
33
33
33
33
33
33
Vo
es
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
4.5-5.5
58
58
58
58
58
55
Features
ns
)
U
ax
40-pin DIP;
44-pin PLCC, TQFP, MQFP
40-pin DIP;
44-pin PLCC, TQFP, MQFP
40-pin DIP;
44-pin PLCC, TQFP, MQFP
40-pin DIP;
44-pin PLCC, TQFP, MQFP
40-pin DIP;
44-pin PLCC, TQFP, MQFP
40-pin DIP;
44-pin PLCC, MQFP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
25
M
PIC17C42
o
rt(
s
lP
T)
M
re
s
pt
tip
In
al
In
)(
r
Ha
ru
te
r
ru
te
r
SA
R
dw
a
pt
So
u
Peripherals
lta
ge
Ra
N
ts
ol
r
ul
er
n
xt
E
ng
e
(V
um
tr
ns
of
I
be
rc
ns
Pi
I/O
io
uc
t
P
Memory
es
DS30559A-page 124
ag
E.8
ac
k
Clock
PIC16C64X & PIC16C66X
PIC17CXX Family of Devices
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
PIN COMPATIBILITY
Devices that have the same package type and VDD,
VSS and MCLR pin locations are said to be pin
compatible. This allows these different devices to
operate in the same socket. Compatible devices may
only requires minor software modification to allow
proper operation in the application socket
(ex., PIC16C56 and PIC16C61 devices). Not all
devices in the same package size are pin compatible;
for example, the PIC16C62 is compatible with the
PIC16C63, but not the PIC16C55.
Pin compatibility does not mean that the devices offer
the same features. As an example, the PIC16C54 is
pin compatible with the PIC16C71, but does not have
an A/D converter, weak pull-ups on PORTB, or
interrupts.
TABLE E-1:
PIN COMPATIBLE DEVICES
Pin Compatible Devices
Package
PIC12C508, PIC12C509
8-pin
PIC16C54, PIC16C54A,
PIC16CR54A,
PIC16C56,
PIC16C58A, PIC16CR58A,
PIC16C61,
PIC16C554, PIC16C556, PIC16C558
PIC16C620, PIC16C621, PIC16C622,
PIC16C710, PIC16C71, PIC16C711,
PIC16F83, PIC16CR83,
PIC16C84, PIC16F84A, PIC16CR84
18-pin
20-pin
PIC16C55,
PIC16C57, PIC16CR57B
28-pin
PIC16C62, PIC16CR62, PIC16C62A, PIC16C63,
PIC16C72, PIC16C73, PIC16C73A
28-pin
PIC16C64, PIC16CR64, PIC16C64A,
PIC16C65, PIC16C65A,
PIC16C74, PIC16C74A
40-pin
PIC17C42, PIC17CR42, PIC17C42A,
PIC17C43, PIC17CR43, PIC17C44
40-pin
PIC16C923, PIC16C924
64/68-pin
1996 Microchip Technology Inc.
DS30559A-page 125
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 126
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
INDEX
A
ADDLW Instruction ......................................................... 76
ADDWF Instruction ........................................................ 76
ANDLW Instruction ......................................................... 76
ANDWF Instruction ........................................................ 76
Architectural Overview ..................................................... 9
Assembler ........................................................................ 88
B
BCF Instruction ............................................................... 77
Bit Manipulation .............................................................. 74
Block Diagrams ............................................................... 30
Comparator Analog Input Mode .......................... 51
Comparator I/O Operating Modes ....................... 48
Comparator Output ................................................ 50
Crystal Operation ................................................... 57
External Brown-out Protection 1 .......................... 65
External Brown-out Protection 2 .......................... 65
External Clock Input Operation ............................ 57
External Parallel Cystal Oscillator ....................... 58
External Power-on Reset Circuit ......................... 65
External Series Crystal Oscillator ........................ 58
In-circuit Serial Programming ............................... 71
Interrupt Logic ......................................................... 66
On-chip Reset Circuit ............................................ 59
Parallel Slave Port, PORTD-PORTE .................. 39
PIC16C641 .............................................................. 10
PIC16C642 .............................................................. 10
PIC16C661 .............................................................. 11
PIC16C662 .............................................................. 11
PORTC (In I/O Port Mode) ................................... 34
PORTD (In I/O Port Mode) ................................... 35
PORTE (In I/O Port Mode) ................................... 37
RA1:RA0 pins .......................................................... 29
RA3 pin ..................................................................... 30
RA4 pin ..................................................................... 31
RB3:RB0 pins .......................................................... 32
RB7:RB4 pins .......................................................... 32
RC Oscillator ........................................................... 58
Single Comparator ................................................. 49
Timer0 ...................................................................... 41
Timer0/WDT Prescaler .......................................... 44
Voltage Reference ................................................. 53
Voltage Reference Output Buffer ........................ 54
Watchdog Timer ..................................................... 69
Brown-out Reset (BOR) ................................................ 60
BSF Instruction ............................................................... 77
BTFSC Instruction .......................................................... 77
BTFSS Instruction .......................................................... 78
C
C Compiler (MPLAB-C) ................................................. 89
CALL Instruction ............................................................. 78
Clocking Scheme/Instruction Cycle ............................. 15
CLRF Instruction ............................................................. 78
CLRW Instruction ........................................................... 78
CLRWDT Instruction ...................................................... 79
CMCON Register ............................................................ 47
1996 Microchip Technology Inc.
Code Examples
Changing Prescaler (T0 to WDT) ........................ 45
Changing Prescaler (WDT to T0) ........................ 45
Indirect Addressing ................................................ 28
Initializing Comparator Module ............................ 49
Initializing PORTA .................................................. 29
Initializing PORTC .................................................. 34
Read-Modify-Write Instructions on an I/O Port . 38
Saving the STATUS and W Registers in RAM . 68
Voltage Reference Configuration ........................ 54
Code Protection .............................................................. 71
COMF Instruction ........................................................... 79
Comparator Configuration ............................................ 48
Comparator Interrupt ..................................................... 51
Comparator Module ....................................................... 47
Comparator Operation .................................................. 49
Comparator Reference .................................................. 49
Configuration Bits ........................................................... 56
Configuring the Voltage Reference ............................. 54
D
Data Memory Organization .......................................... 18
DECF Instruction ............................................................ 79
DECFSZ Instruction ....................................................... 79
Development Support .................................................... 87
Development Tools ........................................................ 87
Device Drawings
28-Lead Ceramic CERDIP Dual In-line with Window (300 mil)) ....................................... 107
28-Lead Ceramic Dual In-Line with Window (JW) (300 mil) ................................................. 107
28-Lead Plastic Small Outline (SO) - Wide, 300 mil
Body ....................................................... 106
28-Lead Skinny Plastic Dual In-Line (SP) 300 mil ................................................... 105
40-Lead Ceramic Dual In-Line with Window
(JW) - (600 mil) ..................................... 108
40-Lead Plastic Dual In-Line (P) - 600 mil ....... 109
44-Lead Plastic Leaded Chip Carrier (L) Square ................................................... 110
44-Lead Plastic Quad Flatpack (PQ) - 10x10x2
mm Body 1.6/0.15 mm Lead Form ... 111
F
Family of Devices
PIC14XXX ............................................................. 117
PIC16C5X ............................................................. 118
PIC16C64X ................................................................6
PIC16C66X ................................................................6
PIC16C6X ............................................................. 120
PIC16C7X ............................................................. 121
PIC16C8X ............................................................. 122
PIC16C9XX ........................................................... 123
PIC16CXXX .......................................................... 119
PIC17CXX ............................................................. 124
Fuzzy Logic Dev. System (fuzzyTECH-MP) .... 87, 89
G
General Purpose Register File .................................... 18
GOTO Instruction ........................................................... 80
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 127
PIC16C64X & PIC16C66X
I
I/O Ports ........................................................................... 29
PORTA ..................................................................... 29
PORTB ..................................................................... 32
PORTC ..................................................................... 34
PORTD ..................................................................... 35
PORTE ..................................................................... 36
I/O Programming Considerations ................................ 38
ICEPIC In-Circuit Emulator ........................................... 87
ID Locations ..................................................................... 71
INCF Instruction .............................................................. 80
INCFSZ Instruction ......................................................... 80
In-Circuit Serial Programming ...................................... 71
Indirect Addressing, INDF and FSR Registers ......... 28
Instruction Flow/Pipelining ............................................ 15
Instruction Format ........................................................... 73
Instruction Set
ADDLW .................................................................... 76
ADDWF .................................................................... 76
ANDLW .................................................................... 76
ANDWF .................................................................... 76
BCF ........................................................................... 77
BSF ........................................................................... 77
BTFSC ...................................................................... 77
BTFSS ...................................................................... 78
CALL ......................................................................... 78
CLRF ........................................................................ 78
CLRW ....................................................................... 78
CLRWDT .................................................................. 79
COMF ....................................................................... 79
DECF ........................................................................ 79
DECFSZ ................................................................... 79
GOTO ....................................................................... 80
INCF .......................................................................... 80
INCFSZ .................................................................... 80
IORLW ...................................................................... 80
IORWF ...................................................................... 81
MOVF ....................................................................... 81
MOVLW .................................................................... 81
MOVWF .................................................................... 81
NOP .......................................................................... 82
OPTION .................................................................... 82
RETFIE ..................................................................... 82
RETLW ..................................................................... 82
RETURN .................................................................. 83
RLF ........................................................................... 83
RRF ........................................................................... 83
SLEEP ...................................................................... 83
SUBLW ..................................................................... 84
SUBWF .................................................................... 84
SWAPF ..................................................................... 85
TRIS .......................................................................... 85
XORLW .................................................................... 85
XORWF .................................................................... 85
Section ...................................................................... 73
Summary Table ...................................................... 75
INT Interrupt .................................................................... 67
INTCON Register ........................................................... 23
Interrupts .......................................................................... 66
Comparator .............................................................. 51
DS30559A-page 128
PORTB Change ..................................................... 32
PSP Read-Write ..................................................... 39
RB0/INT ................................................................... 66
Section ..................................................................... 66
Timer0 ...................................................................... 41
Timer0, Timing ........................................................ 42
IORLW Instruction .......................................................... 80
IORWF Instruction ......................................................... 81
M
MOVF Instruction ........................................................... 81
MOVLW Instruction ........................................................ 81
MOVWF Instruction ....................................................... 81
MPASM Assembler .................................................. 87, 88
MPLAB-C C Compiler ................................................... 89
MPLAB-SIM Software Simulator ........................... 87, 89
N
NOP Instruction .............................................................. 82
O
One-Time-Programmable (OTP) Devices ................... 7
Opcode ............................................................................. 73
OPTION Instruction ....................................................... 82
OPTION Register ........................................................... 22
Oscillator Configurations ............................................... 57
Oscillator Start-up Timer (OST) ................................... 60
P
Package Marking Information ............................ 112, 113
Packaging Information ................................................. 105
Parallel Slave Port ......................................................... 35
Section ..................................................................... 39
Parity Error Reset (PER) ........................................ 60, 61
PCL ................................................................................... 74
PCL and PCLATH .......................................................... 27
PCON Register ......................................................... 26, 61
PICDEM-1 Low-Cost PIC16/17 Demo Board ..... 87, 88
PICDEM-2 Low-Cost PIC16CXX Demo Board ... 87, 88
PICDEM-3 Low-Cost PIC16C9XX Demo Board ...... 88
PICDEM-3 PIC16C9XX Low-Cost Demonstration
Board ................................................................ 87
PICMASTER High Performance
In-Circuit Emulator ......................................... 87
PICSTART Plus Entry Level Development
System ............................................................. 87
PICSTART Plus Entrvel Prototype
Programmer .................................................... 87
PIE1 Register .................................................................. 24
Pin Compatible Devices .............................................. 125
Pin Functions
RD7/PSP7:RD0/PSP0 .......................................... 14
RE0/RD ....................................................... 14, 39
RE1/WR ...................................................... 14, 39
RE2/CS ....................................................... 14, 39
PIR1 Register .................................................................. 25
Port RB Interrupt ............................................................ 67
PORTA ............................................................................. 29
PORTB ............................................................................. 32
PORTC Register ............................................................ 34
PORTD Register ............................................................ 35
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
PORTE Register ............................................................. 36
Ports
Parallel Slave Port .................................................. 39
PORTA ..................................................................... 29
PORTB ..................................................................... 32
PORTC ..................................................................... 34
PORTD ..................................................................... 14
PORTE ..................................................................... 14
Power Control/Status Register (PCON) ..................... 61
Power-down Mode (SLEEP) ........................................ 70
Power-on Reset (POR) ................................................. 60
Power-up Timer (PWRT) ............................................... 60
Prescaler .......................................................................... 44
PRO MATE Universal Programmer .......................... 87
Program Memory Organization .................................... 17
PSPMODE bit ........................................................... 35, 36
TRISA ............................................................................... 29
TRISB ............................................................................... 32
TRISC Register .............................................................. 34
TRISD Register .............................................................. 35
TRISE Register ............................................................... 36
Q
LIST OF EXAMPLES
Quick-Turnaround-Production (QTP) Devices ............ 7
Example 3-1:Instruction Pipeline Flow ............................... 15
Example 4-1:Indirect Addressing........................................ 28
Example 5-1:Initializing PORTA ......................................... 29
Example 5-2:Initializing PORTC ......................................... 34
Example 5-3:Read-Modify-Write Instructions on an
I/O Port .......................................................... 38
Example 6-1:Changing Prescaler (Timer0→WDT)............. 45
Example 6-2:Changing Prescaler (WDT→Timer0)............. 45
Example 7-1:Initializing Comparator Module ...................... 49
Example 8-1:Voltage Reference Configuration .................. 54
Example 9-1:Saving the STATUS and W Registers in
RAM............................................................... 68
R
RA2 pin ............................................................................. 30
RC Oscillator ................................................................... 58
Reset ................................................................................ 59
RETFIE Instruction ......................................................... 82
RETLW Instruction ......................................................... 82
RETURN Instruction ...................................................... 83
RLF Instruction ................................................................ 83
RRF Instruction ............................................................... 83
S
Serialized Quick-Turnaround-Production (SQTP)
Devices .............................................................. 7
SFR ................................................................................... 74
SFR As Source/Destination .......................................... 74
SLEEP Instruction .......................................................... 83
Software Simulator (MPLAB-SIM) ............................... 89
Special Features of the CPU ........................................ 55
Special Function Registers ..................................... 19, 74
Stack ................................................................................. 27
STATUS Register ........................................................... 21
SUBLW Instruction ......................................................... 84
SUBWF Instruction ......................................................... 84
SWAPF Instruction ......................................................... 85
Switching Prescalers ..................................................... 45
T
Timer Modules
Timer0
Block Diagram ................................................. 41
Counter Mode ................................................. 41
External Clock ................................................. 43
Interrupt ............................................................ 41
Prescaler .......................................................... 44
Section ............................................................. 41
Timer Mode ..................................................... 41
Timing Diagram .............................................. 41
TMR0 register ................................................. 41
Timing Diagrams and Specifications .......................... 98
TMR0 Interrupt ................................................................ 67
TRIS Instruction .............................................................. 85
1996 Microchip Technology Inc.
V
Voltage Reference Module ........................................... 53
VRCON Register ............................................................ 53
W
Watchdog Timer (WDT) ................................................ 69
X
XORLW Instruction ........................................................ 85
XORWF Instruction ........................................................ 85
LIST OF FIGURES
Figure 3-1:
Figure 3-2:
Figure 3-3:
Figure 4-1:
Figure 4-2:
Figure 4-3:
Figure 4-4:
Figure 4-5:
Figure 4-6:
Figure 4-7:
Figure 4-8:
Figure 4-9:
Figure 4-10:
Figure 4-11:
Figure 4-12:
Figure 5-1:
Figure 5-2:
Figure 5-3:
Figure 5-4:
Figure 5-5:
Figure 5-6:
Figure 5-7:
Figure 5-8:
Figure 5-9:
Figure 5-10:
Figure 5-11:
Figure 5-12:
Figure 6-1:
Figure 6-2:
Figure 6-3:
Preliminary
PIC16C641/642 Block Diagram..................... 10
PIC16C661/662 Block Diagram..................... 11
Clock/Instruction Cycle .................................. 15
PIC16C641/661 Program Memory Map and
Stack.............................................................. 17
PIC16C642/662 Program Memory Map and
Stack.............................................................. 17
PIC16C641/661 Data Memory Map .............. 18
PIC16C642/662 Data Memory Map .............. 19
STATUS Register (Address 03h, 83h) .......... 21
OPTION Register (address 81h) ................... 22
INTCON Register (address 0Bh, 8Bh) .......... 23
PIE1 Register (address 8Ch)......................... 24
PIR1 Register (address 0Ch) ........................ 25
PCON Register (Address 8Eh)...................... 26
Loading Of PC In Different Situations............ 27
Direct/indirect Addressing.............................. 28
Block Diagram of RA1:RA0 Pins ................... 29
Block Diagram of RA2 Pin ............................. 30
Block Diagram of RA3 Pin ............................. 30
Block Diagram of RA4 Pin ............................. 31
Block Diagram of RB7:RB4 Pins ................... 32
Block Diagram of RB3:RB0 Pins ................... 32
PORTC Block Diagram (in I/O port Mode) .... 34
PORTD Block Diagram (in I/O Port Mode) .... 35
TRISE Register (Address 89h) ...................... 36
PORTE Block Diagram (in I/O Port Mode) .... 37
Successive I/O Operation.............................. 38
PORTD and PORTE as a Parallel Slave Port 39
Timer0 Block Diagram ................................... 41
Timer0 Timing: Internal Clock/No Prescaler.. 41
Timer0 Timing: Internal Clock/Prescale 1:2... 42
DS30559A-page 129
PIC16C64X & PIC16C66X
Figure 6-4:
Figure 6-5:
Figure 6-6:
Figure 7-1:
Figure 7-2:
Figure 7-3:
Figure 7-4:
Figure 7-5:
Figure 8-1:
Figure 8-2:
Figure 8-3:
Figure 9-1:
Figure 9-2:
Figure 9-3:
Figure 9-4:
Figure 9-5:
Figure 9-6:
Figure 9-7:
Figure 9-8:
Figure 9-9:
Figure 9-10:
Figure 9-11:
Figure 9-12:
Figure 9-13:
Figure 9-14:
Figure 9-15:
Figure 9-16:
Figure 9-17:
Figure 9-18:
Figure 9-19:
Figure 9-20:
Figure 10-1:
Figure 12-1:
Figure 12-2:
Figure 12-3:
Figure 12-4:
Figure 12-5:
Figure 12-6:
Figure 12-7:
Timer0 Interrupt Timing.................................. 42
Timer0 Timing With External Clock................ 43
Block Diagram of the Timer0/WDT Prescaler 44
CMCON Register (Address 1Fh) ................... 47
Comparator I/O Operating Modes.................. 48
Single Comparator ......................................... 49
Comparator Output Block Diagram ................ 50
Analog Input Model ........................................ 51
VRCON Register(Address 9Fh) ..................... 53
Voltage Reference Block Diagram ................. 53
Voltage Reference Output Buffer Example .... 54
Configuration Word ........................................ 56
Crystal Operation
(or Ceramic Resonator)
(HS, XT or LP Osc Configuration).................. 57
External Clock Input Operation
(HS, XT or LP Osc Configuration).................. 57
External Parallel Resonant Crystal Oscillator
Circuit ............................................................. 58
External Series Resonant Crystal Oscillator
Circuit ............................................................. 58
RC Oscillator Mode ........................................ 58
Simplified Block Diagram of On-chip Reset
Circuit ............................................................. 59
Brown-out Situations ...................................... 60
Time-out Sequence on Power-up (MCLR not
tied to VDD): Case 1 ....................................... 64
Time-out Sequence on Power-up (MCLR not
tied to VDD): Case 2 ....................................... 64
Time-out Sequence on Power-up (MCLR tied to
VDD) ............................................................... 64
External Power-on Reset Circuit (For Slow VDD
Power-up) ...................................................... 65
External Brown-out Protection Circuit 1 ......... 65
External Brown-out Protection Circuit 2 ......... 65
Interrupt Logic ................................................ 66
RB0/INT Pin Interrupt Timing ......................... 67
Watchdog Timer Block Diagram .................... 69
Summary of Watchdog Timer Registers ........ 69
Wake-up from Sleep Through Interrupt ......... 70
Typical In-Circuit Serial Programming
Connection ..................................................... 71
General Format for Instructions ..................... 73
Load Conditions ............................................. 97
External Clock Timing .................................... 98
CLKOUT and I/O Timing ................................ 99
Reset, Watchdog Timer, Oscillator Start-Up Timer, and Power-Up Timer Timing ................... 100
Brown-out Reset Timing .............................. 100
Timer0 Clock Timing .................................... 101
Parallel Slave Port Timing (PIC16C661 and
PIC16C662) ................................................. 102
Table 5-6:
Table 5-7:
Table 5-8:
Table 5-9:
Table 5-10:
Table 5-11:
Table 6-1:
Table 7-1:
Table 8-1:
Table 9-1:
Table 9-2:
Table 9-3:
Table 9-4:
Table 9-5:
Table 9-6:
Table 10-1:
Table 10-2:
Table 11-1:
Table 12-1:
Table 12-2:
Table 12-3:
Table 12-4:
Table 12-5:
Table 12-6:
Table 12-7:
Table 12-8:
Table E-1:
Summary of Registers Associated with
PORTC .......................................................... 34
PORTD Functions.......................................... 35
Summary of Registers Associated with
PORTD .......................................................... 35
PORTE Functions.......................................... 37
Summary of Registers Associated with
PORTE .......................................................... 37
Registers Associated with Parallel Slave Port39
Registers Associated with Timer0 ................. 45
Registers Associated with
Comparator Module ....................................... 52
Registers Associated with Voltage Reference54
Capacitor Selection for Ceramic Resonators
(Preliminary) .................................................. 57
Capacitor Selection for Crystal Oscillator
(Preliminary) .................................................. 57
Time-out in Various Situations....................... 61
Status Bits and Their Significance ................. 62
Initialization Condition for Special Registers.. 62
Initialization Condition for Registers .............. 63
Opcode Field Descriptions............................. 73
Instruction Set................................................ 75
Development Tools From Microchip .............. 90
Cross Reference of Device Specs for Oscillator
Configurations and Frequencies of Operation
(Commercial Devices) ................................... 91
Comparator Specifications............................. 96
Voltage Reference Specifications.................. 96
External Clock Timing Requirements ............ 98
CLKOUT and I/O Timing Requirements ........ 99
Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and Brown-out Reset Requirements ................................................... 100
Timer0 Clock Requirements ........................ 101
Parallel Slave Port Requirements (PIC16C661
and PIC16C662) .......................................... 102
Pin Compatible Devices............................... 125
LIST OF TABLES
Table 1-1:
Table 3-1:
Table 3-2:
Table 4-1:
Table 5-1:
Table 5-2:
Table 5-3:
Table 5-4:
Table 5-5:
PIC16C64X & PIC16C66X Device Features ... 6
PIC16C641/642 Pinout Description ............... 12
PIC16C661/662 Pinout Description ............... 13
Special Function Registers ............................ 20
PORTA Functions .......................................... 31
Summary of Registers Associated With
PORTA........................................................... 31
PORTB Functions .......................................... 33
Summary of Registers Associated with
PORTB........................................................... 33
PORTC Functions .......................................... 34
DS30559A-page 130
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
ON-LINE SUPPORT
Microchip provides two methods of on-line support.
These are the Microchip BBS and the Microchip World
Wide Web (WWW) site.
Use Microchip's Bulletin Board Service (BBS) to get
current information and help about Microchip products.
Microchip provides the BBS communication channel for
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To provide you with the most responsive service possible,
the Microchip systems team monitors the BBS, posts
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The web site, like the BBS, is used by Microchip as a
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Connecting to the Microchip Internet Web Site
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The file transfer site is available by using an FTP service to connect to:
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Connect worldwide to the Microchip BBS using either
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2. Dial your local CompuServe access number.
3. Depress the <Enter> key and a garbage string will
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All other trademarks mentioned herein are the property of
their respective companies.
1996 Microchip Technology Inc.
DS30559A-page 131
This document was created with FrameMaker 4 0 4
PIC16C64X & PIC16C66X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product.
If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can
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Questions:
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Y
N
Literature Number: DS30559A
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
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DS30559A-page 132
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
NOTES:
1996 Microchip Technology Inc.
DS30559A-page 133
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 134
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
PIC16C64X & PIC16C66X PRODUCT IDENTIFICATION SYSTEM
Examples
PART NO. -XX X /XX XXX
Pattern:
Special Requirements
Package:
SO
L
P
TQ
SP
JW
I
E
04
10
20
Temperature
Range:
Frequency
Range:
=
=
=
=
=
=
=
=
=
=
=
=
SOIC
PLCC
PDIP
TQFP
Skinny DIP
Windowed DIP
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
4 MHz
10MHz
20 MHz
a)
PIC16C662-04/P
Commercial Temp.,
PDIP Package, 4 MHz,
normal VDD limits
b)
PIC16C662-04I/SO
Industrial Temp., SOIC
package, 4 MHz, normal
VDD limits
c)
PIC16C662-04E/P
Automotive Temp.,
PDIP package, 4 MHz,
normal VDD limits
Device
Please contact your local sales office for exact ordering procedures.
JW devices are UV erasable and can be programmed to any device configuration. JW devices meet the electrical
requirements of each oscillator type (including LC devices).
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office (see below)
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
1996 Microchip Technology Inc.
DS30559A-page 135
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
Corporate Office
Toronto
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Microchip Technology Inc.
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Technical Support: 480-786-7627
Web Address: http://www.microchip.com
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Tel: 905-405-6279 Fax: 905-405-6253
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ASIA/PACIFIC
Hong Kong
ASIA/PACIFIC (continued)
Taiwan, R.O.C
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Italy
11/15/99
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
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logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.