LTC1408-12 6 Channel, 12-Bit, 600ksps Simultaneous Sampling ADC with Shutdown DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®1408-12 is a 12-bit, 600ksps ADC with six simultaneously sampled differential inputs. The device draws only 5mA from a single 3V supply, and comes in a tiny 32 pin (5mm × 5mm) QFN package. A SLEEP shutdown feature further reduces power consumption to 6µW. The combination of low power and tiny package makes the LTC1408-12 suitable for portable applications. 600ksps ADC with 6 Simultaneously Sampled Differential Inputs 100ksps Throughput per Channel 72dB SINAD Low Power Dissipation: 15mW 3V Single Supply Operation 2.5V Internal Bandgap Reference, Can be Overdriven with External Reference 3-Wire SPI-Compatible Serial Interface 0V to 2.5V Unipolar, or ±1.25V Bipolar Differential Input Range SLEEP (6µW) Shutdown Mode NAP (3.3mW) Shutdown Mode Internal Conversion Triggered by CONV 83dB Common Mode Rejection Tiny 32-Pin (5mm × 5mm) QFN Package The LTC1408-12 contains six separate differential inputs that are sampled simultaneously on the rising edge of the CONV signal. These six sampled inputs are then converted at a rate of 100ksps per channel. The 83dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The device converts 0V to 2.5V unipolar inputs differentially, or ±1.25V bipolar inputs also differentially, depending on the state of the BIP pin. Any analog input may swing rail-to-rail as long as the differential input range is maintained. U APPLICATIO S ■ ■ ■ ■ Multiphase Power Measurement Multiphase Motor Control Data Acquisition Systems Uninterruptable Power Supplies The conversion sequence can be abbreviated to convert fewer than six channels, depending on the logic state of the SEL2, SEL1 and SEL0 inputs. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6084440, 6522187. The serial interface sends out the six conversion results in 96 clocks for compatibility with standard serial interfaces. W BLOCK DIAGRA CH5– CH5+ CH4– CH4+ CH3– CH3+ CH2– CH2+ CH1– CH1+ CH0– 10µF CH0+ 3V VCC 21 18 15 12 13 11 – S AND H 10 S AND H 9 8 – 7 S AND H 6 5 – 24 4 + – 14 + S AND H 16 + – 17 + S AND H 19 + + – 20 S AND H 600ksps 12-BIT ADC VDD 25 12-BIT LATCH 0 12-BIT LATCH 1 12-BIT LATCH 2 12-BIT LATCH 3 12-BIT LATCH 4 12-BIT LATCH 5 THREESTATE SERIAL OUTPUT PORT OVDD 3V 3 1 SD0 0.1µF 2 OGND MUX TIMING LOGIC 2.5V REFERENCE 33 GND 22 30 VREF 10µF 23 29 BIP 26 27 CONV 32 SCK 31 DGND 28 SEL2 SEL1 SEL0 235114 TA01 140812f 1 LTC1408-12 U U RATI GS W W W W AXI U U ABSOLUTE PACKAGE/ORDER I FOR ATIO (Notes 1, 2) ORDER PART NUMBER VDD SEL2 SEL1 SEL0 BIP CONV SCK DGND TOP VIEW Supply Voltage (VDD, VCC, OVDD) .............................. 4V Analog and VREF Input Voltages (Note 3) ................................... – 0.3V to (VDD + 0.3V) Digital Input Voltages .................. – 0.3V to (VDD + 0.3V) Digital Output Voltage .................. – 0.3V to (VDD + 0.3V) Power Dissipation .............................................. 100mW Operation Temperature Range LTC1408C-12 .......................................... 0°C to 70°C LTC1408I-12 ...................................... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 125°C 32 31 30 29 28 27 26 25 SDO 1 24 VCC OGND 2 23 VREF OVDD 3 22 GND CH0+ 4 21 CH5– CH0– 5 GND 6 19 GND CH1+ 7 18 CH4– CH1– 8 33 LTC1408CUH-12 LTC1408IUH-12 20 CH5+ 17 CH4+ QFN PART MARKING 1408-12 GND CH3– CH3+ GND GND CH2– GND CH2+ 9 10 11 12 13 14 15 16 QFN PACKAGE 32-PIN (5mm × 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/ W EXPOSED PIN IS GND (PAD 33) MUST BE SOLDERED TO PCB Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. U CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With internal reference, VDD = VCC = 3V. PARAMETER CONDITIONS MIN ● Resolution (No Missing Codes) TYP MAX 12 UNITS Bits Integral Linearity Error (Note 5) ● –1 ±0.25 1 LSB Offset Error (Note 4) ● –4.5 ±1 4.5 mV –3 ±0.5 3 mV –12 ±2 12 mV –5 ±1 5 mV Offset Match from CH0 to CH5 Range Error (Note 4) ● Range Match from CH0 to CH5 Range Tempco ±15 ±1 Internal Reference (Note 4) External Reference ppm/°C ppm/°C U U A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With internal reference, VDD = VCC = 3V. SYMBOL PARAMETER CONDITIONS VIN Analog Differential Input Range (Notes 3, 8, 9) 2.7V ≤ VDD ≤ 3.3V VCM Analog Common Mode + Differential Input Range (Note 8) IIN Analog Input Leakage Current CIN Analog Input Capacitance tACQ Sample-and-Hold Acquisition Time tAP Sample-and-Hold Aperture Delay Time tJITTER Sample-and-Hold Aperture Delay Time Jitter tSK Channel to Channel Aperture Skew CMRR Analog Input Common Mode Rejection Ratio MIN TYP MAX V 0 to VDD V ● 1 13 (Note 6) fIN = 100kHz, VIN = 0V to 3V fIN = 10MHz, VIN = 0V to 3V UNITS 0 to 2.5 ● µA pF 39 ns 1 ns 0.3 ps 200 ps –83 –67 dB dB 140812f 2 LTC1408-12 W U DY A IC ACCURACY The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With internal reference, VDD = VCC = 3V. SYMBOL PARAMETER CONDITIONS MIN TYP SINAD Signal-to-Noise Plus Distortion Ratio 100kHz Input Signal 300kHz Input Signal THD Total Harmonic Distortion 100kHz First 5 Harmonics 300kHz First 5 Harmonics SFDR Spurious Free Dynamic Range IMD ● 70 72 72 dB dB ● –80 –90 –86 dB dB 100kHz Input Signal 300kHz Input Signal 90 86 dB dB Intermodulation Distortion 0.625VP-P, 833kHz into CH0+, 0.625VP-P, 841kHz into CH0–. Bipolar Mode. Also Applicable to Other Channels –80 dB Code-to-Code Transition Noise VREF = 2.5V (Note 17) 0.2 LSBRMS Full Power Bandwidth VIN = 2.5VP-P, SDO = 11585LSBP-P (–3dBFS) (Note 15) 50 MHz Full Linear Bandwidth S/(N + D) ≥ 68dB, Bipolar Differential Input 5 MHz U U U I TER AL REFERE CE CHARACTERISTICS PARAMETER CONDITIONS VREF Output Voltage IOUT = 0 MAX UNITS TA = 25°C. VDD = VCC = 3V. MIN VREF Output Tempco TYP MAX UNITS 2.5 V 15 ppm/°C µV/V VREF Line Regulation VDD = 2.7V to 3.6V, VREF = 2.5V 600 VREF Output Resistance Load Current = 0.5mA 0.2 Ω VREF Settling Time CREF = 10µF 2 ms External VREF Input Range 2.55 VDD V U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = VCC = 3V. SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage VDD = 3.3V ● VIL Low Level Input Voltage VDD = 2.7V ● 0.6 V IIN Digital Input Current VIN = 0V to VDD ● ±10 µA CIN Digital Input Capacitance VOH High Level Output Voltage VDD = 3V, IOUT = – 200µA ● VOL Low Level Output Voltage VDD = 2.7V, IOUT = 160µA VDD = 2.7V, IOUT = 1.6mA ● 0.4 V V VOUT = 0V and VDD ● ±10 µA IOZ Hi-Z Output Leakage DOUT COZ Hi-Z Output Capacitance DOUT ISOURCE Output Short-Circuit Source Current ISINK Output Short-Circuit Sink Current MIN TYP MAX 2.4 2.5 UNITS V 5 pF 2.9 V 0.05 1 pF VOUT = 0V, VDD = 3V 20 mA VOUT = VDD = 3V 15 mA 140812f 3 LTC1408-12 U W POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With internal reference, VDD = VCC= 3V. SYMBOL PARAMETER CONDITIONS VDD, VCC Supply Voltage IDD + ICC Supply Current Active Mode, fSAMPLE = 600ksps Nap Mode Sleep Mode PD Power Dissipation Active Mode with SCK, fSAMPLE = 600ksps MIN TYP MAX UNITS 2.7 3.0 3.6 V 5 1.1 2.0 7 1.9 15 mA mA µA ● ● 15 mW WU TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V. SYMBOL PARAMETER fSAMPLE(MAX) Maximum Sampling Rate per Channel (Conversion Rate) ● tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisiton Period) ● tSCK Clock Period (Note 16) tCONV Conversion Time (Notes 6, 17) 96 SCLK cycles t1 Minimum High or Low SCLK Pulse Width (Note 6) 2 ns t2 CONV to SCK Setup Time (Notes 6, 10) 3 t3 SCK Before CONV (Note 6) 0 ns t4 Minimum High or Low CONV Pulse Width (Note 6) 4 ns t5 SCK↑ to Sample Mode (Note 6) 4 ns t6 CONV↑ to Hold Mode (Notes 6, 11) 1.2 ns t7 96th SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13) 45 ns t8 Delay from SCK to Valid Bits 0 Through 11 (Notes 6, 12) t9 SCK↑ to Hi-Z at SDO (Notes 6, 12) t10 Previous SDO Bit Remains Valid After SCK (Notes 6, 12) t11 VREF Settling Time After Sleep-to-Wake Transition (Notes 6, 14) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliabilty and lifetime. Note 2: All voltage values are with respect to ground GND. Note 3: When these pins are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below GND or greater than VDD without latchup. Note 4: Offset and range specifications apply for a single-ended CH0+ – CH5+ input with CH0 – – CH5– grounded and using the internal 2.5V reference. Note 5: Integral linearity is tested with an external 2.55V reference and is defined as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. The deviation is measured from the center of quantization band. Linearity is tested for CH0 only. Note 6: Guaranteed by design, not subject to test. Note 7: Recommended operating conditions. Note 8: The analog input range is defined for the voltage difference between CHx+ and CHx–, x = 0–5. CONDITIONS MIN ● TYP MAX 100 UNITS kHz 100 10 µs 10000 ns 10000 2 ns 8 ns 6 ns ns 2 ms Note 9: The absolute voltage at CHx+ and CHx– must be within this range. Note 10: If less than 3ns is allowed, the output data will appear one clock cycle later. It is best for CONV to rise half a clock before SCK, when running the clock at rated speed. Note 11: Not the same as aperture delay. Aperture delay (1ns) is the difference between the 2.2ns delay through the sample-and-hold and the 1.2ns CONV to Hold mode delay. Note 12: The rising edge of SCK is guaranteed to catch the data coming out into a storage latch. Note 13: The time period for acquiring the input signal is started by the 96th rising clock and it is ended by the rising edge of CONV. Note 14: The internal reference settles in 2ms after it wakes up from Sleep mode with one or more cycles at SCK and a 10µF capacitive load. Note 15: The full power bandwidth is the frequency where the output code swing drops by 3dB with a 2.5VP-P input sine wave. Note 16: Maximum clock period guarantees analog performance during conversion. Output data can be read with an arbitrarily long clock period. Note 17: The conversion process takes 16 clocks for each channel that is enabled, up to 96 clocks for all 6 channels. 140812f 4 LTC1408-12 U W TYPICAL PERFOR A CE CHARACTERISTICS VDD = 3V, TA = 25°C THD, 2nd and 3rd vs Input Frequency THD, 2nd and 3rd vs Input Frequency SINAD vs Input Frequency –50 74 –50 UNIPOLAR SINGLE-ENDED 71 62 –74 2nd –80 –86 –92 59 3rd –98 56 53 0.1 10 1 FREQUENCY (MHz) THD –74 2nd –80 –86 –92 3rd –98 –104 –104 –110 0.1 1 FREQUENCY (MHz) 10 1 FREQUENCY (MHz) 10 140812 G03 140812 G02 100kHz Unipolar Sine Wave 8192 Point FFT Plot SNR vs Input Frequency SFDR vs Input Frequency 0 –10 77 92 74 86 –20 74 68 71 –30 68 –40 MAGNITUDE (dB) SNR (dB) 80 65 62 59 62 –50 –60 –70 –80 –90 56 –100 56 53 50 0.1 50 0.1 10 1 FREQUENCY (MHz) –110 –120 1 FREQUENCY (MHz) 10 0 140812 G05 140814 G04 1 1 0.8 0.8 0.6 0.6 DIFFERENTIAL LINEARITY (LSB) –40 –50 –60 –70 –80 –90 –100 INTEGRAL LINEARITY (LSB) 0 –30 0.4 0.2 0 –0.2 –0.4 –0.6 –120 10 30 20 FREQUENCY (KHZ) 40 50 140812 G07 50 0.4 0.2 0 –0.2 –0.4 –0.6 0 –1 0 40 –0.8 –0.8 –110 30 20 FREQUENCY (kHz) Integral Linearity vs Output Code, CH0, Unipolar Mode –10 –20 10 140812 G06 Differential Linearity vs Output Code, CH0, Unipolar Mode 100kHz Bipolar Sine Wave 8192 Point FFT Plot MAGNITUDE (dB) –68 –110 0.1 140814 G01 SFDR (dB) THD, 2nd, 3rd (dB) 65 THD –68 THD, 2nd, 3rd (dB) SINAD (dB) –62 –62 68 BIPOLAR SINGLE-ENDED –56 –56 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE 140812 G08 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE 140812 G09 140812f 5 LTC1408-12 U W TYPICAL PERFOR A CE CHARACTERISTICS VDD = 3V, TA = 25°C Full Scale Signal Response CMRR vs Frequency 3 0 0 –20 –3 MAGNITUDE (dB) –6 –40 CMRR (dB) –9 –12 –15 –18 –60 –80 –21 –24 –100 –27 –30 100 FREQUENCY (MHz) 10 1000 –120 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 1408 G11 1408 G10 PSRR vs Frequency 0 –20 –20 –40 –40 PSRR (dB) CROSSTALK (dB) Crosstalk vs Frequency 0 –60 –60 –80 –80 –100 –100 –120 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 1408 G12 –120 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 1408 G13 140812f 6 LTC1408-12 U U U PI FU CTIO S SDO (Pin 1): Three-State Serial Data Output. Each set of six output data words represent the six analog input channels at the start of the previous conversion. Data for CH0 comes out first and data for CH5 comes out last. Each data word comes out MSB first. OGND (Pin 2): Ground Return for SDO Currents. Connect to the solid ground plane. OVDD (Pin 3): Power Supply for the SDO Pin. OVDD must be no more than 300mV higher than VDD and can be brought to a lower voltage to interface to low voltage logic families. The unloaded high state at SDO is at the potential of OVDD. CH3+ (Pin 14): Non-Inverting Channel 3. CH3+ operates fully differentially with respect to CH3– with a 0V to 2.5V, or ±1.25V differential swing and a 0V to VDD absolute input range. CH3– (Pin 15): Inverting Channel 3. CH3– operates fully differentially with respect to CH3+ with a –2.5V to 0V, or ±1.25V differential swing and a 0V to VDD absolute input range. CH4+ (Pin 17): Non-Inverting Channel 4. CH4+ operates fully differentially with respect to CH4– with a 0V to 2.5V, or ±1.25V differential swing and a 0V to VDD absolute input range. CH0+ (Pin 4): Non-Inverting Channel 0. CH0+ operates fully differentially with respect to CH0– with a 0V to 2.5V, or ±1.25V differential swing and a 0V to VDD absolute input range. CH4– (Pin 18): Inverting Channel 4. CH4– operates fully differentially with respect to CH4+ with a –2.5V to 0V, or ±1.25V differential swing and a 0V to VDD absolute input range. CH0– (Pin 5): Inverting Channel 0. CH0– operates fully differentially with respect to CH0+ with a –2.5V to 0V, or ±1.25V differential swing and a 0V to VDD absolute input range. CH5+ (Pin 20): Non-Inverting Channel 5. CH5+ operates fully differentially with respect to CH5– with a 0V to 2.5V, or ±1.25V differential swing and a 0V to VDD absolute input range. GND (Pins 6, 9, 12, 13, 16, 19): Analog Grounds. These ground pins must be tied directly to the solid ground plane under the part. Analog signal currents flow through these connections. CH5– (Pin 21): Inverting Channel 5. CH5– operates fully differentially with respect to CH5+ with a –2.5V to 0V, or ±1.25V differential swing and a 0V to VDD absolute input range. CH1+ (Pin 7): Non-Inverting Channel 1. CH1+ operates fully differentially with respect to CH1– with a 0V to 2.5V, or ±1.25V differential swing and a 0V to VDD absolute input range. GND (PIN 22): Analog Ground for Reference. Analog ground must be tied directly to the solid ground plane under the part. Analog signal currents flow through this connection. The 10µF reference bypass capacitor should be returned to this pad. CH1– (Pin 8): Inverting Channel 1. CH1– operates fully differentially with respect to CH1+ with a –2.5V to 0V, or ±1.25V differential swing and a 0V to VDD absolute input range. CH2+ (Pin 10): Non-Inverting Channel 2. CH2+ operates fully differentially with respect to CH2– with a 0V to 2.5V, or ±1.25V differential swing and a 0V to VDD absolute input range. CH2– (Pin 11): Inverting Channel 2. CH2– operates fully differentially with respect to CH2+ with a –2.5V to 0V, or ±1.25V differential swing and a 0V to VDD absolute input range. VREF (Pin 23): 2.5V Internal Reference. Bypass to GND and a solid analog ground plane with a 10µF ceramic capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). Can be overdriven by an external reference voltage between 2.55V and VDD, VCC. VCC (Pin 24): 3V Positive Analog Supply. This pin supplies 3V to the analog section. Bypass to the solid analog ground plane with a 10µF ceramic capacitor (or 10µF tantalum) in parallel with 0.1µF ceramic. Care should be taken to place the 0.1µF bypass capacitor as close to Pin 24 as possible. Pin 24 must be tied to Pin 25. 140812f 7 LTC1408-12 U U U PI FU CTIO S VDD (Pin 25): 3V Positive Digital Supply. This pin supplies 3V to the logic section. Bypass to DGND pin and solid analog ground plane with a 10µF ceramic capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). Keep in mind that internal digital output signal currents flow through this pin. Care should be taken to place the 0.1µF bypass capacitor as close to Pin 25 as possible. Pin 25 must be tied to Pin 24. SEL2 (Pin 26): Most significant bit controlling the number of channels being converted. In combination with SEL1 and SEL0, 000 selects just the first channel (CH0) for conversion. Incrementing SELx selects additional channels(CH0–CH5) for conversion. 101, 110 or 111 select all 6 channels for conversion. Must be kept in a fixed state during conversion and during the subsequent conversion to read data. SEL1 (Pin 27): Middle significance bit controlling the number of channels being converted. In combination with SEL0 and SEL2, 000 selects just the first channel (CH0) for conversion. Incrementing SELx selects additional channels for conversion. 101, 110 or 111 select all 6 channels (CH0–CH5) for conversion. Must be kept in a fixed state during conversion and during the subsequent conversion to read data. SEL0 (Pin 28): Least significant bit controlling the number of channels being converted. In combination with SEL1 and SEL2, 000 selects just the first channel (CH0) for conversion. Incrementing SELx selects additional channels for conversion. 101, 110 or 111 select all 6 channels (CH0–CH5) for conversion. Must be kept in a fixed state during conversion and during the subsequent conversion to read data. BIP (Pin 29): Bipolar/Unipolar Mode. The input differential range is 0V – 2.5V when BIP is LOW, and it is ±1.25V when BIP is HIGH. Must be kept in fixed state during conversion and during subsequent conversion to read data. When changing BIP between conversions the full acquisition time must be allowed before starting the next conversion. The output data is in 2’s complement format for bipolar mode and straight binary format for unipolar mode. CONV (Pin 30): Convert Start. Holds the six analog input signals and starts the conversion on CONV’s rising edge. Two CONV pulses with SCK in fixed high or fixed low state starts Nap mode. Four or more CONV pulses with SCK in fixed high or fixed low state starts Sleep mode. DGND (Pin 31): Digital Ground. This ground pin must be tied directly to the solid ground plane. Digital input signal currents flow through this pin. SCK (Pin 32): External Clock Input. Advances the conversion process and sequences the output data at SD0 (Pin1) on the rising edge. One or more SCK pulses wake from sleep or nap power saving modes. 16 clock cycles are needed for each of the channels that are activated by SELx (Pins 26, 27, 28), up to a total of 96 clock cycles needed to convert and read out all 6 channels. EXPOSED PAD (Pin 33): GND. Must be tied directly to the solid ground plane. 140812f 8 LTC1408-12 W BLOCK DIAGRA 0.1µF 10µF 3V VCC 24 CH0+ 4 VDD 25 + S&H CH0– 5 – 6 CH1+ 7 + CH1– 8 – S&H 9 + CH2 10 + S&H CH2– 11 – CH3+ 14 CH3– 15 600ksps 12-BIT ADC MUX 12 13 + OVDD 3V 12-BIT LATCH 0 12-BIT LATCH 1 12-BIT LATCH 2 12-BIT LATCH 3 12-BIT LATCH 4 12-BIT LATCH 5 THREESTATE SERIAL OUTPUT PORT 3 SD0 0.1µF 1 OGND 2 S&H – 16 CH4+ 17 TIMING LOGIC + S&H CH4– 18 30 CONV 32 SCK – 19 + CH5 20 + CH5– 21 – S&H 2.5V REFERENCE VREF EXPOSED PAD 33 GND 22 23 29 26 27 28 10µF 31 DGND BIP SEL2 SEL1 SEL0 1408 BD 140812f 9 94 CONV 96 66 98 68 35 Hi-Z 36 t8 2 D11 37 3 D11 69 70 D11 D10 71 38 4 6 HOLD 7 8 t1 9 t10 10 D10 39 D9 40 D8 41 D7 42 D5 D4 43 44 D9 D8 45 12-BIT DATA WORD D6 72 D9 73 D8 74 D7 75 D5 D4 76 77 D3 78 12-BIT DATA WORD D6 79 D2 D7 D5 D4 12-BIT DATA WORD D6 D3 D2 D1 D0 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH4 D10 11 12 13 14 15 D3 46 D2 47 X 80 81 D0 82 49 X X X 84 D11 tTHROUGHPUT tCONV 18 50 t9 X 19 20 51 52 53 85 87 22 23 24 25 26 D10 D9 D8 27 28 29 55 D9 56 D8 57 D7 58 D5 D4 59 60 61 12-BIT DATA WORD D6 D3 62 D2 63 D10 88 D9 89 D8 90 D7 91 D5 D4 92 93 D3 94 12-BIT DATA WORD D6 t6 95 D2 D7 D6 D4 12-BIT DATA WORD D5 D3 D2 D1 D0 X t8 96 D1 X t6 t4 98 SAMPLE 97 D0 X D1 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH3 54 D10 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH5 86 tTHROUGHPUT tCONV D11 t8 21 30 X 2 65 31 1408 TD01 Hi-Z 1 64 D0 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH1 D11 tTHROUGHPUT tCONV Hi-Z Back to SAMPLE mode if SELx = 010 83 48 D0 17 Back to SAMPLE mode if SELx = 000 16 Back to SAMPLE mode if SELx = 100 D1 X D1 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH0 5 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH2 to SAMPLE mode if SELx = 001 34 1 Back to SAMPLE mode if SELx = 011 67 SDO t6 t4 SCK SAMPLE 97 t2 t8 X 3 32 D11 X 4 Back to 33 D10 5 D9 6 TI I G DIAGRA S UW D8 W 10 INTERNAL S/H STATUS 95 t3 LTC1408-12 Timing Diagram LTC1408-12 140812f LTC1408-12 W UW TI I G DIAGRA S Nap Mode and Sleep Mode Waveforms SCK t1 t1 CONV NAP SLEEP t11 VREF 1408 TD02 NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS SCK to SDO Delay SCK VIH SCK VIH t8 t10 SDO t9 VOH SDO Hi-Z VOL 1408 TD03 140812f 11 LTC1408-12 U W U U APPLICATIO S I FOR ATIO SELECTING THE NUMBER OF CONVERTED CHANNELS (SEL2, SEL1, SEL0) These three control pins select the number of channels being converted (see Table 1). 000 selects only the first channel (CH0) for conversion. Incrementing SELx selects additional channels for conversion, up to 6 channels. 101, 110 or 111 select all 6 channels for conversion. These pins must be kept in a fixed state during conversion and during the subsequent conversion to read data. When changing modes between conversions, keep in mind that the output data of a particular channel will remain unchanged until after that channel is converted again. For example: convert a sequence of 4 channels (CH0, CH1, CH2, CH3) with SELx = 011, then, after these channels are converted change SELx to 001 to convert just CH0 and CH1. During the conversion of the first set of two channels you will be able to read the data from the same two channels converted as part of the previous group of 4 channels. Later, you could convert 4 or more channels to read back the unread CH2 and CH3 data that was converted in the first set of 4 channels. These pins are often hardwired to enable the right number of channels for a particular application. Choosing to convert fewer channels per conversion results in faster throughput of those channels. For example, 6 channels can be converted at 100ksps/ch, while 3 channels can be converted at 200ksps/ch. BIPOLAR/UNIPOLAR MODE The input voltage range for each of the CHx input differential pairs is UNIPOLAR 0V – 2.5V when BIP is LOW, and BIPOLAR ±1.25V when BIP is HIGH. This pin must be kept in fixed state during conversion and during subsequent conversion to read data. When changing BIP between conversions the full acquisition time must be allowed before starting the next conversion. After changing modes from BIPOLAR to UNIPOLAR, or from UNIPOLAR to BIPOLAR, you can still read the first set of channels in the new mode, by inverting the MSB to read these channels in the mode that they were converted in. DRIVING THE ANALOG INPUT The differential analog inputs of the LTC1408-12 may be driven differentially or as a single-ended input (i.e., the CHx– input is grounded). All twelve analog inputs of all six differential analog input pairs, CH0+ and CH0–, CH1+ and CH1–, CH2+ and CH2–, CH3+ and CH3–, CH4+ and CH4– and CH5+ and CH5–, are sampled at the same instant. Any unwanted signal that is common to both inputs of each input pair will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the Table 1. Conversion Sequence Control (“acquire” represents simultaneous sampling of all channels; CHx represents conversion of channels) SEL2 SEL1 SEL0 CHANNEL ACQUISITION AND CONVERSION SEQUENCE 0 0 0 acquire, CH0, acquire, CH0... 0 0 1 acquire, CH0, CH1, acquire, CH0, CH1... 0 1 0 acquire, CH0, CH1, CH2, acquire, CH0, CH1, CH2... 0 1 1 acquire, CH0, CH1, CH2, CH3, acquire, CH0, CH1, CH2, CH3... 1 0 0 acquire, CH0, CH1, CH2, CH3, CH4, acquire, CH0,CH1,CH2, CH3, CH4... 1 0 1 acquire, CH0, CH1, CH2, CH3, CH4, CH5, acquire, CH0, CH1, CH2, CH3, CH4, CH5... 1 1 0 acquire, CH0, CH1, CH2, CH3, CH4, CH5, acquire, CH0, CH1, CH2, CH3, CH4, CH5... 1 1 1 acquire, CH0, CH1, CH2, CH3, CH4, CH5, acquire, CH0, CH1, CH2, CH3, CH4, CH5... 140812f 12 LTC1408-12 U W U U APPLICATIO S I FOR ATIO LTC1408-12 inputs can be driven directly. As source impedance increases, so will acquisition time. For minimum acquisition time with high source impedance, a buffer amplifier must be used. The main requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (the time allowed for settling must be at least 39ns for full throughput rate). Also keep in mind while choosing an input amplifier the amount of noise and harmonic distortion added by the amplifier. CHOOSING AN INPUT AMPLIFIER Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (< 100Ω) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 50MHz, then the output impedance at 50MHz must be less than 100Ω. The second requirement is that the closed-loop bandwidth must be greater than 40MHz to ensure adequate smallsignal settling for full throughput rate. If slower op amps are used, more time for settling can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC1408-12 depends on the application. Generally, applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC1408-12. (More detailed information is available in the Linear Technology Databooks and on the website at www.linear.com.) LinearView is a trademark of Linear Technology Corporation. LTC1566-1: Low Noise 2.3MHz Continuous Time Lowpass Filter. LT®1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier. 2.7V to ±15V supplies. Very high AVOL, 500µV offset and 520ns settling to 0.5LSB for a 4V swing. THD and noise are – 93dB to 40kHz and below 1LSB to 320kHz (AV = 1, 2VP-P into 1kΩ, VS = 5V), making the part excellent for AC applications (to 1/3 Nyquist) where rail-to-rail performance is desired. Quad version is available as LT1631. LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier. 2.7V to ±15V supplies. Very high AVOL, 1.5mV offset and 400ns settling to 0.5LSB for a 4V swing. It is suitable for applications with a single 5V supply. THD and noise are – 93dB to 40kHz and below 1LSB to 800kHz (AV = 1, 2VP-P into 1kΩ, VS = 5V), making the part excellent for AC applications where rail-to-rail performance is desired. Quad version is available as LT1633. LT1801: 80MHz GBWP, –75dBc at 500kHz, 2mA/amplifier, 8.5nV/√Hz. LT1806/LT1807: 325MHz GBWP, –80dBc distortion at 5MHz, unity gain stable, rail-to-rail in and out, 10mA/amplifier, 3.5nV/√Hz. LT1810: 180MHz GBWP, –90dBc distortion at 5MHz, unity gain stable, rail-to-rail in and out, 15mA/amplifier, 16nV/√Hz. LT1818/LT1819: 400MHz, 2500V/µs, 9mA, Single/Dual Voltage Mode Operational Amplifier. LT6200: 165MHz GBWP, –85dBc distortion at 1MHz, unity gain stable, rail-to-rail in and out, 15mA/amplifier, 0.95nV/√Hz. LT6203: 100MHz GBWP, –80dBc distortion at 1MHz, unity gain stable, rail-to-rail in and out, 3mA/amplifier, 1.9nV/√Hz. LT6600: Amplifier/Filter Differential In/Out with 10MHz Cutoff frequency. 140812f 13 LTC1408-12 U W U U APPLICATIO S I FOR ATIO INPUT FILTERING AND SOURCE IMPEDANCE INPUT RANGE The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1408-12 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 50MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 1 shows a 47pF capacitor from CHO+ to ground and a 51Ω source resistor to limit the net input bandwidth to 30MHz. The 47pF capacitor also acts as a charge reservoir for the input sampleand-hold and isolates the ADC input from sampling-glitch sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silvermica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. When high amplitude unwanted signals are close in frequency to the desired signal frequency a multiple pole filter is required. The analog inputs of the LTC1408-12 may be driven fully differentially with a single supply. Either input may swing up to VCC, provided the differential swing is no greater than 2.5V with BIP (Pin 29) Low, or ±1.25V with (BIP Pin 29) High. The 0V to 2.5V range is also ideally suited for singleended input use with single supply applications. The common mode range of the inputs extend from ground to the supply voltage VCC. If the difference between the CH+ and CH– at any input pair exceeds 2.5V (unipolar) or 1.25V (bipolar), the output code will stay fixed at positive fullscale, and if this difference goes below 0V (unipolar) or – 1.25V (bipolar), the output code will stay fixed at negative full-scale. High external source resistance, combined with 13pF of input capacitance, will reduce the rated 50MHz input bandwidth and increase acquisition time beyond 39ns. ANALOG INPUT 51Ω* 1 47pF* 2 CH0+ CH0– INTERNAL REFERENCE The LTC1408-12 has an on-chip, temperature compensated, bandgap reference that is factory trimmed to 2.5V to obtain a precise 2.5V input span. The reference amplifier output VREF, (Pin 23) must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 1µF or greater. For the best noise performance, a 10µF ceramic or a 10µF tantalum in parallel with a 0.1µF ceramic is recommended. The VREF pin can be overdriven with an external reference as shown in Figure 2. The voltage of the external reference must be higher than the 2.5V of the open-drain P-channel output of the internal reference. The recommended range for an external reference is 2.55V to VDD. An external reference at 2.55V will see a DC quiescent load of 0.75mA and as much as 3mA during conversion. LTC1408-12 3 10µF 11 ANALOG INPUT 51Ω* 4 47pF* 5 VREF 3.5V to 18V GND CH1+ LT1790-3 CH1– 3V 23 10µF 1408 F01 *TIGHT TOLERANCE REQUIRED TO AVOID APERTURE SKEW DEGRADATION Figure 1. RC Input Filter VREF LTC2351-12 22 GND 1408 F02 Figure 2. Overdriving VREF Pin with an External Reference 140812f 14 LTC1408-12 U W U U APPLICATIO S I FOR ATIO INPUT SPAN VERSUS REFERENCE VOLTAGE The differential input range has a unipolar voltage span that equals the difference between the voltage at the reference buffer output VREF (Pin 23) and the voltage at ground. The differential input range of the ADC is 0V to 2.5V when using the internal reference. The internal ADC is referenced to these two nodes. This relationship also holds true with an external reference. Figure 4 shows the ideal input/output characteristics for the LTC1408-12 in unipolar mode (BIP = Low). The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, FS – 1.5LSB). The output code is straight binary with 1LSB = 2.5V/4096 = 610µV for the LTC1408-12. The LTC1408-12 has 0.2 LSB RMS of Gaussian white noise. DIFFERENTIAL INPUTS The ADC will always convert the difference of CH+ minus CH–, independent of the common mode voltage at any pair of inputs. The common mode rejection holds up at high frequencies (see Figure 3.) The only requirement is that both inputs not go below ground or exceed VDD. STRAIGHT BINARY OUTPUT CODE 111...111 111...110 111...101 000...010 000...001 000...000 0 0 FS – 1LSB INPUT VOLTAGE (V) 1408 F04 –20 Figure 4. LTC1408-12 Transfer Characteristic in Unipolar Mode (BIP = Low) CMRR (dB) –40 –60 –80 –100 –120 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) Figure 5 shows the ideal input/output characteristics for the LTC1408-12 in bipolar mode (BIP = High). The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, FS – 1.5LSB). The output code is 2’s complement with 1LSB = 2.5V/4096 = 610µV for the LTC1408-12. The LTC1408-12 has 0.2 LSB RMS of Gaussian white noise. 1408 G11 Figure 3. CMRR vs Frequency 2'S COMPLEMENT OUTPUT CODE Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are largely independent of the common mode voltage. However, the offset error will vary. DC CMRR is typically better than –90dB. 011...111 011...110 011...101 100...010 100...001 100...000 –FS FS – 1LSB INPUT VOLTAGE (V) 1408 F05 Figure 5. LTC1408-12 Transfer Characteristic in Bipolar Mode (BIP = High) 140812f 15 LTC1408-12 U W U U APPLICATIO S I FOR ATIO POWER-DOWN MODES Conversion Start Input (CONV) Upon power-up, the LTC1408-12 is initialized to the active state and is ready for conversion. The Nap and Sleep mode waveforms show the power down modes for the LTC1408-12. The SCK and CONV inputs control the power down modes (see Timing Diagrams). Two rising edges at CONV, without any intervening rising edges at SCK, put the LTC1408-12 in Nap mode and the power consumption drops from 15mW to 3.3mW. The internal reference remains powered in Nap mode. One or more rising edges at SCK wake up the LTC1408-12 very quickly and CONV can start an accurate conversion within a clock cycle. Four rising edges at CONV, without any intervening rising edges at SCK, put the LTC1408-12 in Sleep mode and the power consumption drops from 15mW to 6µW. One or more rising edges at SCK wake up the LTC1408-12 for operation. The internal reference (VREF ) takes 2ms to slew and settle with a 10µF load. Using sleep mode more frequently compromises the accuracy of the output data. Note that for slower conversion rates, the Nap and Sleep modes can be used for substantial reductions in power consumption. The rising edge of CONV starts a conversion, but subsequent rising edges at CONV are ignored by the LTC1408-12 until the following 96 SCK rising edges have occurred. The duty cycle of CONV can be arbitrarily chosen to be used as a frame sync signal for the processor serial port. A simple approach to generate CONV is to create a pulse that is one SCK wide to drive the LTC1408-12 and then buffer this signal to drive the frame sync input of the processor serial port. It is good practice to drive the LTC1408-12 CONV input first to avoid digital noise interference during the sample-to-hold transition triggered by CONV at the start of conversion. It is also good practice to keep the width of the low portion of the CONV signal greater than 15ns to avoid introducing glitches in the front end of the ADC just before the sample-and-hold goes into Hold mode at the rising edge of CONV. DIGITAL INTERFACE The LTC1408-12 has a 3-wire SPI (Serial Peripheral Interface) interface. The SCK and CONV inputs and SDO output implement this interface. The SCK and CONV inputs accept swings from 3V logic and are TTL compatible, if the logic swing does not exceed VDD. A detailed description of the three serial port signals follows: Minimizing Jitter on the CONV Input In high speed applications where high amplitude sine waves above 100kHz are sampled, the CONV signal must have as little jitter as possible (10ps or less). The square wave output of a common crystal clock module usually meets this requirement. The challenge is to generate a CONV signal from this crystal clock without jitter corruption from other digital circuits in the system. A clock divider and any gates in the signal path from the crystal clock to the CONV input should not share the same integrated circuit with other parts of the system. The SCK and CONV inputs should be driven first, with digital buffers 140812f 16 LTC1408-12 U W U U APPLICATIO S I FOR ATIO used to drive the serial port interface. Also note that the master clock in the DSP may already be corrupted with jitter, even if it comes directly from the DSP crystal. Another problem with high speed processor clocks is that they often use a low cost, low speed crystal (i.e., 10MHz) to generate a fast, but jittery, phase-locked-loop system clock (i.e., 40MHz). The jitter in these PLL-generated high speed clocks can be several nanoseconds. Note that if you choose to use the frame sync signal generated by the DSP port, this signal will have the same jitter of the DSP’s master clock. The Typical Application Figure on page 20 shows a circuit for level-shifting and squaring the output from an RF signal generator or other low-jitter source. A single D-type flip flop is used to generate the CONV signal to the LTC1408-12. Re-timing the master clock signal eliminates clock jitter introduced by the controlling device (DSP, FPGA, etc.) Both the inverter and flip flop must be treated as analog components and should be powered from a clean analog supply. after the next convert pulse. It is good practice to drive the LTC1408-12 SCK input first to avoid digital noise interference during the internal bit comparison decision by the internal high speed comparator. Unlike the CONV input, the SCK input is not sensitive to jitter because the input signal is already sampled and held constant. Serial Data Output (SDO) Upon power-up, the SDO output is automatically reset to the high impedance state. The SDO output remains in high impedance until a new conversion is started. SDO sends out up to six sets of 12 bits in the output data stream after the third rising edge of SCK after the start of conversion with the rising edge of CONV. The six or fewer 12-bit words are separated by two don’t care bits and two clock cycles in high impedance mode. Please note the delay specification from SCK to a valid SDO. SDO is always guaranteed to be valid by the next rising edge of SCK. The 16 – 96-bit output data stream is compatible with the 16-bit or 32-bit serial port of most processors. Serial Clock Input (SCK) The rising edge of SCK advances the conversion process and also udpates each bit in the SDO data stream. After CONV rises, the third rising edge of SCK sends out up to six sets of 12 data bits, with the MSB sent first. A simple approach is to generate SCK to drive the LTC1408-12 first and then buffer this signal with the appropriate number of inverters to drive the serial clock input of the processor serial port. Use the falling edge of the clock to latch data from the Serial Data Output (SDO) into your processor serial port. The 12-bit Serial Data will be received in six 16-bit words with 96 or more clocks per frame sync. If fewer than 6 channels are selected by SEL0–SEL2 for conversion, then 16 clocks are needed per channel to convert the analog inputs and read out the resulting data BOARD LAYOUT AND BYPASSING Wire wrap boards are not recommended for high resolution and/or high speed A/D converters. To obtain the best performance from the LTC1408-12, a printed circuit board with ground plane is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track. If optimum phase match between the inputs is desired, the length of the twelve input wires of the six input channels should be kept matched. But each pair of input wires to the six input channels should be kept separated by a ground trace to avoid high frequency crosstalk between channels. 140812f 17 LTC1408-12 U W U U APPLICATIO S I FOR ATIO High quality tantalum and ceramic bypass capacitors should be used at the VCC, VDD and VREF pins as shown in the Block Diagram on the first page of this data sheet. For optimum performance, a 10µF surface mount tantalum capacitor with a 0.1µF ceramic is recommended for the VCC, VDD and VREF pins. Alternatively, 10µF ceramic chip capacitors such as X5R or X7R may be used. The capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. The VCC and VDD bypass capacitor returns to the ground plane and the VREF bypass capacitor returns to the Pin 22. Care should be taken to place the 0.1µF VCC and VDD bypass capacitor as close to Pins 24 and 25 as possible. Figure 6 shows the recommended system ground connections. All analog circuitry grounds should be terminated at the LTC1408-12 Exposed Pad. The ground return from the LTC1408-12 to the power supply should be low impedance for noise-free operation. The Exposed Pad of the 32pin QFN package is also internally tied to the ground pads. The Exposed Pad should be soldered on the PC board to reduce ground connection inductance. All ground pins (GND, DGND, OGND) must be connected directly to the same ground plane under the LTC1408-12. HARDWARE INTERFACE TO TMS320C54x The LTC1408-12 is a serial output ADC whose interface has been designed for high speed buffered serial ports in fast digital signal processors (DSPs). Figure 7 shows an example of this interface using a TMS320C54X. The buffered serial port in the TMS320C54x has direct access to a 2kB segment of memory. The ADC’s serial data can be collected in two alternating 1kB segments, in real time, at the full 600ksps conversion rate of the LTC1408-12. The DSP assembly code sets frame sync mode at the BFSR pin to accept an external positive going pulse and the serial clock at the BCLKR pin to accept an external positive edge clock. Buffers near the LTC1408-12 may be added to drive long tracks to the DSP to prevent corruption of the signal to LTC1408-12. This configuration is adequate to traverse a typical system board, but source resistors at the buffer outputs and termination resistors at the DSP, may be needed to match the characteristic impedance of very long transmission lines. If you need to terminate the SDO transmission line, buffer it first with one or two 74ACxx gates. The TTL threshold inputs of the DSP port respond properly to the 3V swing used with the LTC1408-12. OVDD BYPASS, 0.1µF, 0402 LTC1408-12 OVDD CONV SCK VDD BYPASS, 0.1µF, 0402 SDO OGND VCC BYPASS, 0.1µF, 0402 AND 10µF, 0805 DGND 3V TMS320C54x 5V 3 VCC 30 BFSR 32 BCLKR B11 1 B10 BDR 2 31 CONV CLK 3-WIRE SERIAL INTERFACE LINK 1408 F06 0V TO 3V LOGIC SWING Figure 7. DSP Serial Interface to TMS320C54x VREF BYPASS, 10µF, 0805 Figure 6. Recommended Layout 140812f 18 LTC1408-12 U PACKAGE DESCRIPTIO UH Package 32-Lead Plastic QFN (5mm x 5mm) (Reference LTC DWG # 05-08-1693) 0.70 ±0.05 5.50 ±0.05 4.10 ±0.05 3.50 REF (4 SIDES) 3.45 ± 0.05 3.45 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD 0.75 ± 0.05 R = 0.05 TYP 0.00 – 0.05 PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER R = 0.115 TYP 31 32 0.40 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 3.50 REF (4-SIDES) 3.45 ± 0.10 3.45 ± 0.10 (UH32) QFN 0406 REV D 0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 ± 0.05 0.50 BSC 140812f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC1408-12 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS ADCs LTC1402 12-Bit, 2.2Msps Serial ADC 5V or ±5V Supply, 4.096V or ±2.5V Span LTC1403/LTC1403A 12-/14-Bit, 2.8Msps Serial ADC 3V, 15mW, Unipolar Inputs, MSOP Package LTC1403-1/LTC1403A-1 12-/14-Bit, 2.8Msps Serial ADC 3V, 15mW, Bipolar Inputs, MSOP Package LTC1405 12-Bit, 5Msps Parallel ADC 5V, Selectable Spans, 115mW LTC1407/LTC1407A 12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 14mW, 2-Channel Unipolar Input Range LTC1407-1/LTC1407A-1 12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 14mW, 2-Channel Bipolar Input Range LTC1408 14-Bit, 600ksps Simultaneous Sampling ADC 3V, 15mW, Selectable Bipolar (Unipolar Input, Six Differential Inputs) LTC1411 14-Bit, 2.5Msps Parallel ADC 5V, Selectable Spans, 80dB SINAD LTC1412 12-Bit, 3Msps Parallel ADC ±5V Supply, ±2.5V Span, 72dB SINAD LTC1420 12-Bit, 10Msps Parallel ADC 5V, Selectable Spans, 72dB SINAD LTC1608 16-Bit, 500ksps Parallel ADC ±5V Supply, ±2.5V Span, 90dB SINAD LTC1609 16-Bit, 250ksps Serial ADC 5V Configurable Bipolar/Unipolar Inputs LTC1864/LTC1865 LTC1864L/LTC1865L 16-Bit, 250ksps 1-/2-Channel Serial ADCs 5V or 3V (L-Version), Micropower, MSOP Package LTC1592 16-Bit, Serial SoftSpanTM IOUT DAC ±1LSB INL/DNL, Software Selectable Spans LTC1666/LTC1667 LTC1668 12-/14-/16-Bit, 50Msps DAC 87dB SFDR, 20ns Settling Time DACs References LT1460-2.5 Micropower Series Voltage Reference 0.10% Initial Accuracy, 10ppm Drift LT1461-2.5 Precision Voltage Reference 0.04% Initial Accuracy, 3ppm Drift LT1790-2.5 Micropower Series Reference in SOT-23 0.05% Initial Accuracy, 10ppm Drift SoftSpan is a trademark of Linear Technology Corporation. U TYPICAL APPLICATIO Low-Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level Shifting Circuit and Re-Timing Flip-Flop VCC 0.1µF 1k NC7SVU04P5X MASTER CLOCK 50Ω VCC 1k CONTROL LOGIC (FPGA, CPLD, DSP, ETC.) PRE D Q CONV LTC 1408-12 Q CLR NL17SZ74 CONVERT ENABLE 1408 TA02 140812f 20 Linear Technology Corporation LT/LWI 1006 • PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006