LTC1415 12-Bit, 1.25Msps, 55mW Sampling A/D Converter U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC ®1415 is a 700ns, 1.25Msps, 12-bit sampling A/D converter that draws only 55mW from a single 5V supply. This easy-to-use device includes a high dynamic range sample-and-hold, precision reference and a trimmed internal clock. Two power shutdown modes provide flexibility for low power systems. 1.25Msps Sample Rate Single 5V Supply Power Dissipation: 55mW Nap and Sleep Power Shutdown Modes ± 0.35LSB INL and ± 0.25LSB DNL 72dB S/(N + D) and 80dB THD at 100kHz External or Internal Reference Operation True Differential Inputs Reject Common Mode Noise Input Range: 4.096V (1mV/LSB) 28-Pin SSOP and SO Packages The LTC1415’s full-scale input range is 4.096V. Low linearity errors ±0.35LSB INL, ±0.25LSB DNL make it ideal for imaging systems. Outstanding AC performance includes 72dB S/(N + D) and 80dB THD with an input frequency of 100kHz. UO APPLICATI ■ ■ ■ ■ ■ S The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 18MHz bandwidth. The 60dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. High Speed Data Acquisition Imaging Systems Digital Signal Processing Multiplexed Data Acquisition Systems Telecommunications The ADC has a µP compatible, 12-bit parallel output port. There is no pipeline delay in the conversion results. A separate convert start input and data ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors. A separate output logic supply pin allows direct connection to 3V components. , LTC and LT are registered trademarks of Linear Technology Corporation. UO TYPICAL APPLICATI 1.25MHz, 12-Bit Sampling A/D Converter LTC1415 DVDD OVDD BUSY CS CONVST RD SHDN NAP/SLP OGND D0 D1 D2 D3 28 26 25 OUTPUT LOGIC SUPPLY 3V OR 5V 22 68 11 10µF NYQUIST FREQUENCY 10 9 24 23 74 12 27 µP CONTROL LINES 21 20 19 EFFECTIVE BITS AVDD 62 56 8 7 6 5 4 3 18 2 17 1 16 SIGNAL/(NOISE + DISTORTION) (dB) DIFFERENTIAL 1 +AIN ANALOG INPUT (0V TO 4.096V) 2 –AIN 2.50V 3 V VREF OUTPUT 4 REF REFCOMP 5 AGND 10µF 6 D11(MSB) 7 D10 8 D9 9 D8 10 D7 11 12-BIT D6 PARALLEL 12 D5 BUS 13 D4 14 DGND Effective Bits and Signal-to-(Noise + Distortion) vs Input Frequency 5V fSAMPLE = 1.25Msps 0 15 1k 10k 100k INPUT FREQUENCY (Hz) 1M 2M LTC1415 • TA02 1415 TA01 1 LTC1415 W U U W W W AXI U U ABSOLUTE PACKAGE/ORDER I FOR ATIO RATI GS AVDD = DVDD =OVDD = VDD (Notes 1, 2) ORDER PART NUMBER TOP VIEW Supply Voltage (VDD) ................................................ 6V Analog Input Voltage (Note 3) ...... – 0.3V to VDD + 0.3V Digital Input Voltage (Note 4) .................. – 0.3V to 12V Digital Output Voltage .................... – 0.3V to VDD + 0.3V Power Dissipation............................................. 500mW Operating Temperature Range LTC1415C............................................... 0°C to 70°C LTC1415I........................................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C +AIN 1 28 AVDD –AIN 2 27 DVDD VREF 3 26 OVDD REFCOMP 4 25 BUSY AGND 5 24 CS D11 (MSB) 6 23 CONVST D10 7 22 RD D9 8 21 SHDN D8 9 20 NAP/SLP D7 10 19 OGND D6 11 18 D0 D5 12 17 D1 D4 13 16 D2 DGND 14 15 D3 G PACKAGE 28-LEAD PLASTIC SSOP LTC1415CG LTC1415CSW LTC1415IG LTC1415ISW SW PACKAGE 28-LEAD PLASTIC SO WIDE TJMAX = 110°C, θJA = 95°C/W (G) TJMAX = 110°C, θJA = 130°C/W (SW) Consult factory for Military grade parts. U CO VERTER CHARACTERISTICS PARAMETER With Internal Reference (Notes 5, 6) CONDITIONS Resolution (No Missing Codes) MIN TYP MAX ● 0.35 ±1 LSB ● 0.25 ±1 LSB ±1 ±6 ±8 LSB LSB ±20 LSB ● Integral Linearity Error (Note 7) Differential Linearity Error Offset Error 12 (Note 8) Bits ● Full-Scale Error Full-Scale Tempco ±15 IOUT(REF) = 0 U U A ALOG I PUT ppm/°C (Note 5) SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (Note 9) 4.75V ≤ VDD ≤ 5.25V ● IIN Analog Input Leakage Current CS = High ● CIN Analog Input Capacitance Between Conversions During Conversions t ACQ Sample-and-Hold Acquisition Time t AP Sample-and-Hold Aperture Delay Time tjitter Sample-and-Hold Aperture Delay Time Jitter CMRR Analog Input Common Mode Rejection Ratio 2 UNITS MIN TYP 4.096 50 –1.5 UNITS V ±1 19 5 ● 0V < VCM < VDD, DC to MHz MAX µA pF pF 150 ns ns 2 psRMS 60 dB LTC1415 W U DY A IC ACCURACY (Note 5) SYMBOL PARAMETER CONDITIONS S/(N + D) Signal-to-(Noise + Distortion) Ratio 100kHz Input Signal 600kHz Input Signal THD Total Harmonic Distortion SFDR IMD MIN TYP MAX UNITS 72 69 dB dB 100kHz Input Signal, First 5 Harmonics 600kHz Input Signal, First 5 Harmonics – 80 – 72 dB dB Spurious Free Dynamic Range 600kHz Input Signal – 75 dB Intermodulation Distortion fIN1 = 29.37kHz, fIN2 = 32.446kHz – 84 dB Full-Power Bandwidth Full-Linear Bandwidth S/(N + D) ≥ 68dB U U U I TER AL REFERE CE CHARACTERISTICS PARAMETER 18 MHz 1 MHz (Note 5) CONDITIONS MIN TYP MAX VREF Output Voltage IOUT = 0 2.480 2.500 2.520 VREF Output Tempco IOUT = 0 ±15 ppm/°C VREF Line Regulation 4.75V ≤ VDD ≤ 5.25V 0.01 LSB/V VREF Output Resistance IOUT ≤ 0.1mA REFCOMP Output Voltage IOUT = 0 U U DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL PARAMETER 2 V (Note 5) CONDITIONS MIN High Level Input Voltage VDD = 5.25V ● VIL Low Level Input Voltage VDD = 4.75V ● IIN Digital Input Current VIN = 0V to VDD ● CIN Digital Input Capacitance VOH High Level Output Voltage Low Level Output Voltage V kΩ 4.096 VIH VOL UNITS VDD = 4.75V IO = – 10µA IO = – 200µA ● VDD = 4.75V IO = 160µA IO = 1.6mA ● TYP MAX 2.4 UNITS V 0.8 V ±10 µA 5 pF 4.5 V V 4.0 0.05 0.10 0.4 V V ±10 µA IOZ Hi-Z Output Leakage D11 to D0 VOUT = 0V to VDD, CS High ● COZ Hi-Z Output Capacitance D11 to D0 CS High (Note 9 ) ● ISOURCE Output Source Current VOUT = 0V – 10 mA ISINK Output Sink Current VOUT = VDD 10 mA W U POWER REQUIRE E TS SYMBOL PARAMETER 15 pF (Note 5) CONDITIONS VDD Supply Voltage (Notes 10, 11) IDD Supply Current Nap Mode Sleep Mode CS High SHDN = 0V, NAP/SLP = 5V (Note 12) SHDN = 0V, NAP/SLP = 0V (Note 12) PD Power Dissipation Nap Mode Sleep Mode CS High SHDN = 0V, NAP/SLP = 5V SHDN = 0V, NAP/SLP = 0V MIN TYP 4.75 ● ● MAX UNITS 5.25 V 11 1.5 1.0 20 2.3 mA mA µA 55 7.5 0.01 100 12 mW mW mW 3 LTC1415 WU TI I G CHARACTERISTICS (Note 5) SYMBOL PARAMETER fSAMPLE(MAX) Maximum Sampling Frequency Conversion and Acquisition Time CONDITIONS ● ● MIN tCONV Conversion Time tACQ Acquisition Time t1 CS to RD Setup Time t2 t3 t4 SHDN↑ to CONVST↓ Wake-Up Time Nap Mode (Note 10) Sleep Mode, CREFCOMP = 10µF (Note 10) t5 CONVST Low Time (Notes 10, 11) MAX UNITS 800 MHz ns ● 700 ns ● 150 ns t6 CONVST to BUSY Delay CL = 25pF (Notes 9, 10) ● 0 CS↓ to CONVST↓ Setup Time (Notes 9, 10) ● 10 NAP/SLP↑ to SHDN↓ Setup Time (Notes 9, 10) ● TYP 1.25 ns ns 200 ns 200 10 ns ms 50 ns 10 60 ● t7 Data Ready Before BUSY↑ t8 Delay Between Conversions t9 Wait Time RD↓ After BUSY↑ t10 Data Access Time After RD↓ (Note 10) ● 20 15 ● 50 ● –5 CL = 25pF 35 ns 20 35 45 ns ns 25 45 60 ns ns 10 30 35 40 ns ns ns ● t11 Bus Relinquish Time 0°C = TA = 70°C – 40°C = TA = 85°C ns ns ns ● CL = 100pF ns ns ● ● t12 RD Low Time ● t 10 ns t13 CONVST High Time ● 50 ns t14 Aperture Delay of Sample-and-Hold The ● denotes specifications which apply over the full operating temperature range; all other limits and typicals TA = 25°C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND and AGND wired together unless otherwise noted. Note 3: When these pin voltages are taken below ground or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below ground or above VDD without latchup. Note 4: When these pin voltages are taken below ground, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below ground without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, fSAMPLE = 1.25MHz, tr = tf = 5ns unless otherwise specified. 4 – 1.5 ns Note 6: Linearity, offset and full-scale specifications apply for a singleended +AIN input with – AIN grounded. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The falling edge of CONVST starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For best performance ensure that CONVST returns high either within 425ns after the start of the conversion or after BUSY rises. Note 12: CS = RD = CONVST = 0V. LTC1415 U W TYPICAL PERFORMANCE CHARACTERISTICS S/(N + D) vs Input Frequency and Amplitude Signal-to-Noise Ratio vs Input Frequency 80 AMPLITUDE (dB BELOW THE FUNDAMENTAL) 70 70 60 SIGNAL-TO -NOISE RATIO (dB) SIGNAL/(NOISE + DISTORTION) (dB) VIN = 0dB VIN = –20dB 50 40 30 VIN = –60dB 20 60 50 40 30 20 10 10 0 0 10k 100k INPUT FREQUENCY (Hz) 1k 1M 2M 1k 10k 100k INPUT FREQUENCY (Hz) LTC1415 • TPC01 0 –10 –20 –30 –40 –50 –60 –70 THD 2ND –80 –90 3RD –100 1k 1M 2M 10k 100k INPUT FREQUENCY (Hz) 1M 2M LTC1415 • TPC03 LTC1415 • TPC02 Spurious-Free Dynamic Range vs Input Frequency Intermodulation Distortion Plot 0 0 fSAMPLE = 1.25MHz fIN1 = 86.97509766kHz fIN2 = 113.2202148kHz –10 –20 AMPLITUDE (dB) –20 –30 –40 –50 –60 –70 –40 fb – fa 2fb – fa 2fa + fb fa + fb –60 2fa 2fa – fb 2fb fa + 2fb 3fb 3fa –80 –100 –80 –120 –90 10k 100k INPUT FREQUENCY (Hz) 1M 0 2M 100k 200k 300k FREQUENCY (Hz) 400k 600k 500k LTC1415 • TPC04 LTC1415 • TPC05 Integral Nonlinearity vs Output Code Differential Nonlinearity vs Output Code 1.00 1.00 0.50 0.50 DNL ERROR (LSBs) INL ERROR (LSBs) SPURIOUS-FREE DYNAMIC RANGE (dB) Distortion vs Input Frequency 80 0.00 –0.50 0.00 –0.50 –1.00 –1.00 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE LTC1415 • TPC07 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE LTC1415 • TPC06 5 LTC1415 U W Power Supply Feedthrough vs Ripple Frequency Input Common Mode Rejection vs Input Frequency 0 80 –10 70 COMMON MODE REJECTION (dB) AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB) TYPICAL PERFORMANCE CHARACTERISTICS –20 –30 –40 –50 –60 –70 VDD –80 DGND –90 OVDD –100 1k 100k 10k RIPPLE FREQUENCY (Hz) 60 50 40 30 20 10 0 1M 2M LTC1415 • TPC08 1k 10k 100k INPUT FREQUENCY (Hz) 1M 2M LTC1415 • TPC09 U U U PI FU CTIO S + AIN (Pin 1): Positive Analog Input, 0V to 4.096V. – AIN (Pin 2): Negative Analog Input, 0V to 4.096V. VREF (Pin 3): 2.50V Reference Output. REFCOMP (Pin 4): Bypass to AGND with 10µF tantalum in parallel with 0.1µF or 10µF ceramic. AGND (Pin 5): Analog Ground. D11 to D4 (Pins 6 to 13): Three-State Data Outputs. DGND (Pin 14): Digital Ground. D3 to D0 (Pins 15 to 18): Three-State Data Outputs. OGND (Pin 19): Digital Output Buffer Ground. NAP/SLP (Pin 20): Power Shutdown Mode. High for quick wake-up Nap mode. SHDN (Pin 21): Power Shutdown Input. A low logic level will invoke the Shutdown mode selected by the NAP/SLP pin. Tie high if unused. 6 RD (Pin 22): Read Input. This enables the output drivers when CS is low. CONVST (Pin 23): Conversion Start Signal. This active low signal starts a conversion on its falling edge. CS (Pin 24): The Chip Select input must be low for the ADC to recognize CONVST and RD inputs. BUSY (Pin 25): The BUSY output shows the converter status. It is low when a conversion is in progress. Its rising edge may be used to latch the output data. 0VDD (Pin 26): Digital output buffer supply. Short to Pin 28 for 5V output. Tie to 3V for driving 3V logic. DVDD (Pin 27): 5V Positive Supply. Short to Pin 28. AVDD (Pin 28): 5V Positive Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF or 10µF ceramic. LTC1415 U U W FU CTIO AL BLOCK DIAGRA CSAMPLE +AIN AVDD CSAMPLE – AIN 2k VREF DVDD ZEROING SWITCHES 2.5V REF + REF AMP COMP 12-BIT CAPACITIVE DAC – REFCOMP (4.096V) OVDD AGND 12 SUCCESSIVE APPROXIMATION REGISTER • • • OUTPUT LATCHES DGND D11 D0 OGND INTERNAL CLOCK CONTROL LOGIC NAP/SLP SHDN CONVST RD CS BUSY 1415 BD TEST CIRCUITS Load Circuits for Bus Relinquish Time Load Circuits for Access Timing 5V 5V 1k DBN 1k DBN DBN 1k CL (A) Hi-Z TO VOH AND VOL TO VOH CL DBN 1k (B) Hi-Z TO VOL AND VOH TO VOL 1415 TC01 (A) VOH TO Hi-Z 100pF 100pF (B) VOL TO Hi-Z 1415 TC02 7 LTC1415 U U W U APPLICATIONS INFORMATION The LTC1415 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs (please refer to Digital Interface section for the data format). Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. During the conversion, the internal differential 12-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the +AIN and –AIN inputs are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum delay of 150ns will provide enough time for the sampleand-hold capacitors to acquire the analog signal. During the convert phase the comparator zeroing switches open, putting the comparator into compare mode. The input switches the connect CSAMPLE capacitors to ground, transferring the differential analog input charge onto the summing junction. This input charge is successively compared with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the differential DAC output balances the + AIN and – AIN input charges. The SAR contents (a 12-bit data word) which represents the difference of + AIN and – AIN are loaded into the 12-bit output latches. DYNAMIC PERFORMANCE The LTC1415 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using a FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 2 shows a typical LTC1415 FFT plot. 0 fSAMPLE = 1.25MHz fIN = 99.792kHz SFDR - 87.5 SINAD = 72.1 –20 AMPLITUDE (dB) CONVERSION DETAILS –40 –60 –80 –100 –120 0 +CSAMPLE +AIN SAMPLE ZEROING SWITCHES –CSAMPLE SAMPLE HOLD 600 Signal-to-Noise Ratio +CDAC + –CDAC COMP – –VDAC 12 SAR • D11 • • D0 OUTPUT LATCHES LTC1415 • F01 Figure 1. Simplified Block Diagram 8 500 Figure 2. LTC1415 Nonaveraged, 4096 Point FFT HOLD HOLD +VDAC 200 300 400 FREQUENCY (kHz) LTC1415 • F02 HOLD –AIN 100 The signal-to-noise plus distortion ratio [S/(N + D)] or SINAD is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 2 shows a typical spectral content with a 1.25MHz sampling rate and a 100kHz input. The dynamic performance is excellent for input frequencies up to the Nyquist limit of 625kHz. LTC1415 U U W U APPLICATIONS INFORMATION Effective Number of Bits The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: N = [S/(N + D) – 1.76]/6.02 where N is the effective number of bits of resolution and S/(N + D) is expressed in dB. At the maximum sampling rate of 1.25MHz the LTC1415 maintains very good ENOBs up to the Nyquist input frequency of 625kHz (refer to Figure 3). Total Harmonic Distortion 74 11 68 10 62 9 56 8 7 6 5 4 3 2 Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by AMPLITUDE (dB BELOW THE FUNDAMENTAL) 12 V22 + V32 + V42 + …Vn2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. THD vs input frequency is shown in Figure 4. The LTC1415 has good distortion performance up to the Nyquist frequency and beyond. THD = 20Log SIGNAL/(NOISE + DISTORTION) (dB) EFFECTIVE BITS Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: 1 0 1k 100k 10k INPUT FREQUENCY (Hz) 0 –10 –20 –30 –40 –50 –60 THD –70 –80 2ND –90 3RD –100 1M 2M 1k 100k 10k INPUT FREQUENCY (Hz) LT1415 • F03 1M 2M LTC1415 • F04 Figure 3. Effective Bits and Signal/(Noise + Distortion) vs Input Frequency Figure 4. Distortion vs Input Frequency 0 fSAMPLE = 1.25MHz fIN1 = 86.97509766kHz fIN2 = 113.2202148kHz AMPLITUDE (dB) –20 –40 fb – fa 2fb – fa 2fa + fb fa + fb –60 2fa 2fa – fb 2fb 3fa –80 fa + 2fb 3fb –100 –120 0 100k 200k 300k FREQUENCY (Hz) 400k 500k 600k LTC1415 • F05 Figure 5. Intermodulation Distortion Plot 9 LTC1415 U W U U APPLICATIONS INFORMATION If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa + – nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: IMD( fa + fb) = 20Log Amplitude at (fa + fb) Amplitude at fa Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. The full-linear bandwidth is the input frequency at which the S/(N + D) has dropped to 68dB (11 effective bits). The LTC1415 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist Frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. Driving the Analog Input The differential analog inputs of the LTC1415 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the –AIN input is grounded). The +AIN and –AIN inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion the analog inputs draw 10 only a small leakage current. If the source impedance of the driving circuit is low, then the LTC1415 inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 6). For minimum acquisition time with high source impedance, a buffer amplifier should be used. The only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 150ns for full throughput rate). 10 ACQUISITION TIME (µs) the presence of another sinusoidal input at a different frequency. 1 0.1 0.01 0.01 1 10 0.1 SOURCE RESISTANCE (kΩ) 100 1415 F06 Figure 6. Acquisition Time vs Source Resistance Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (< 100Ω) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of +1 and has a unity-gain bandwidth of 50MHz, then the output impedance at 50MHz should be less than 100Ω. The second requirement is that the closed-loop bandwidth must be greater than 20MHz to ensure adequate small-signal settling for full throughput rate. If slower op amps are used, more settling time can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC1415 will depend on the application. Generally applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. LTC1415 U W U U APPLICATIONS INFORMATION The following list is a summary of the op amps that are suitable for driving the LTC1415, more detailed information is available in the Linear Technology databooks and the LinearViewTM CD-ROM. LT ® 1215/LT1216: Dual and quad 23MHz, 50V/µs single supply op amps. Single 5V to ±15V supplies, 6.6mA specifications, 90ns settling to 0.5LSB. LT1223: 100MHz video current feedback amplifier. ±5V to ±15V supplies, 6mA supply current. Low distortion up to and above 400kHz. Low noise. Good for AC applications. capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. 100Ω ANALOG INPUT 2 4 The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1415 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 20MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example Figure 7 shows a 1000pF capacitor from +AIN to ground and a 100Ω source resistor to limit the input bandwidth to 1.6MHz. The 1000pF LinearView is a trademark of Linear Technology Corporation. VREF REFCOMP 10µF 5 LT1360: 37MHz voltage feedback amplifier. ±5V to ±15V supplies. 3.8mA supply current. Good AC and DC specs. 70ns settling to 0.5LSB. Input Filtering –AIN LTC1415 3 LT1229/LT1230: Dual and quad 100MHz current feedback amplifiers. ±2V to ±15V supplies, 6mA supply current each amplifier. Low noise. Good AC specs. LT1364/LT1365: Dual and quad 50MHz, 450V/µs op amps. ±5V to ±15V supplies, 6.3mA supply current per amplifier. 60ns settling to 0.5LSB. +AIN 1000pF LT1227: 140MHz video current feedback amplifier. ±5V to ±15V supplies, 10mA supply current. Lowest distortion at frequencies above 400kHz. Low noise. Best for AC applications. LT1363: 50MHz, 450V/µs op amps. ±5V to ±15V supplies. 6.3mA supply current. Good AC and DC specs. 60ns settling to 0.5LSB. 1 AGND LTC1415 • F07 Figure 7. RC Input Filter Input Range The 4.096V input range of the LTC1415 is optimized for low noise. Most single supply op amps also perform well over this same range, allowing direct coupling to the analog inputs and eliminating the need for special translation circuitry. Some applications may require other input ranges. The LTC1415 differential inputs and reference circuitry can accommodate other input ranges often with little or no additional circuitry. The following sections describe the reference and input circuitry and how they affect the input range. Internal Reference The LTC1415 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500V. It is connected internally to a reference amplifier and is available at VREF (Pin 3) see Figure 8a. A 2k resistor is in series with the output so that it can be easily overdriven by an external reference or other 11 LTC1415 U U W U APPLICATIONS INFORMATION circuitry. The reference amplifier gains the voltage at the VREF pin by 1.638 to create the required internal reference voltage of 4.096V. This provides buffering between the VREF pin and the high speed capacitive DAC. The reference amplifier compensation pin (REFCOMP, Pin 4) must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 1µF or greater. For the best noise performance a 10µF ceramic or tantalum in parallel with a 0.1µF ceramic is recommended. 1 DIFFERENTIAL ANALOG INPUT RANGE = (VREF)(1.638) LTC1450 12-BIT RAIL-TO-RAIL DAC 2 +AIN –AIN LTC1415 1.25V TO 3V 3 4 VREF REFCOMP 10µF 5 AGND LTC1415 • F09 R1 2k V 2.500V 3 REF 4 REFCOMP 4.096V BANDGAP REFERENCE bandwidth and settling time of this circuit. A settling time of 5ms should be allowed for after a reference adjustment. REFERENCE AMP Differential Inputs R2 40k 10µF 5 AGND Figure 9. Driving VREF with a DAC to Adjust Full Scale R3 64k LTC1415 LTC1415 • F08a Figure 8a. LTC1415 Reference Circuit 5V VIN 1 ANALOG INPUT 2 LT1019A-2.5 VOUT 3 4 +AIN –AIN VREF LTC1415 REFCOMP 10µF 5 AGND 1415 F08b Figure 8b. Using the LT1019-2.5 as an External Reference The VREF pin can be driven with a DAC or other means shown in Figure 9. This is useful in applications where the peak input signal amplitude may vary. The input span of the ADC can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. The filtering of the internal LTC1415 reference amplifier will limit the 12 The LTC1415 has a unique differential sample-and-hold circuit that allows rail-to-rail inputs. The ADC will always convert the difference of +AIN – (–AIN) independent of the common mode voltage. The common mode rejection is constant from DC to 1MHz, see Figure 10a. The only requirement is that both inputs can not exceed the AVDD or AGND power supply voltages. Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are independent of the common mode voltage, however, the bipolar zero error (BZE) will vary. The change in BZE is typically less than 0.1% of the common mode voltage. Differential inputs allow greater flexibility for accepting different input ranges. Figure 10b shows a circuit that shifts the input range up in voltage by 200mV. This can be useful in applications where the amplifier driving the ADC input is not able to swing all the way to ground, because of output loading or settling time issues. Some AC applications may have their performance limited by distortion. Most circuits exhibit higher distortion when signals approach the supply or ground. Distortion can be reduced by reducing the signal amplitude and keeping the common mode voltage at approximately midsupply. The circuit of Figure 10c reduces the ADC full scale from LTC1415 U U W U APPLICATIONS INFORMATION 4.096V to 2.048V and shifts the common mode voltage from half of full scale to 2.274V. AC Coupled Inputs The analog inputs can be AC coupled for applications where the input has no DC information. The input of the ADC does need to be DC biased at midscale. Figures 10d and 10e demonstrate AC coupling and the required biasing. Figure 10d shows the ADC with a full scale of 4.096V, a common mode voltage of 2.048V and an input that swings from 0V to 4.096V. This circuit has the lowest noise (SINAD = 72dB to 100kHz) but will have distortion SIGNAL/(NOISE + DISTORTION) (dB) 80 ANALOG INPUT 1 0.2V TO 4.296V 70 R1 200Ω 60 2 50 R2 3.9k 40 3 +AIN –AIN LTC1415 VREF 30 4 20 REFCOMP 10µF 10 5 AGND 0 1k 10k 100k INPUT FREQUENCY (Hz) 1M 2M LTC1415 • F10b LTC1415 • F10a Figure 10a. CMRR vs Input Frequency Figure 10b. Shifting the Input Range Up from Ground by 200mV ANALOG INPUT 1 +AIN 1.25V TO 3.298V 2 –AIN 24Ω 3 VOUT = 1.2V VREF LT1004-1.2 1 ANALOG INPUT 4.096VP-P 2 3 1µF LTC1415 –AIN VREF LTC1415 4 4 +AIN REFCOMP 2k REFCOMP 10µF 10µF 5 2k AGND 5 AGND LTC1415 • F10c LTC1415 • F10d Figure 10c. 2.048V Input Range with a Common Mode Voltage of 2.274V. For Low Distortion AC Applications Figure 10d. 4.096VP-P Input Range with AC Coupling. For Low Noise AC Applications 1 ANALOG INPUT 2.048VP-P 2 25Ω 1k 3 +AIN –AIN VREF 1µF LT1004-1.2 LTC1415 1k + 4 – 10µF 9k 5 REFCOMP AGND LTC1415 • F10e Figure 10e. 2.048VP-P Input Range with AC Coupling. For Low Distortion AC Applications 13 LTC1415 U W U U APPLICATIONS INFORMATION limitations at high input frequencies (THD = 75dB at 600kHz). The ADC in Figure 10e has a full scale of 2.048V and a common mode of 2.27V. The reduced signal swing of this circuit results in improved distortion at higher input frequencies (THD = 82dB at 600kHz) but with worse SINAD at low frequencies (SINAD = 70dB at 100kHz). ANALOG INPUT R1 100Ω R2 47k R8 50k R5 47k 1 R4 100Ω R7 50k Full-Scale and Offset Adjustment Figure 11a shows the ideal input/output characteristics for the LTC1415. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB,... FS – 1.5LSB, FS – 0.5LSB). The output is straight binary with 1LSB = FS/4096 = 4.096V/4096 = 1mV. 3 R6 24k 10µF 2 4 0.1µF +AIN –AIN VREF LTC1415 REFCOMP 5 AGND LTC1415 • F11b Figure 11b. Offset and Full-Scale Adjust Circuit the output code flickers between 1111 1111 1110 and 1111 1111 1111. 111...111 111...110 BOARD LAYOUT AND GROUNDING OUTPUT CODE 111...101 000...010 000...001 000...000 1LSB INPUT VOLTAGE (V) FS – 1LSB LTC1415 • F11a Figure 11a. LTC1415 Transfer Characteristics In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before full-scale error. Figure 11b shows the extra components required for full-scale error adjustment. Zero offset is achieved by adjusting the offset applied to the – AIN input. For zero offset error apply 0.5mV (i.e., 0.5LSB) at +AIN and adjust the offset at the – AIN input (R8) until the output code flickers between 0000 0000 0000 and 0000 0000 0001. For full-scale adjustment, an input voltage of 4.0945V (FS – 1.5LSBs) is applied to the analog input and R7 is adjusted until 14 R3 24k 5V Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1415, a printed circuit board with ground plane is required. The ground plane under the ADC area should be as free of breaks and holes as possible, such that a low impedance path between all ADC grounds and all ADC decoupling capacitors is provided. It is critical to prevent digital noise from being coupled to the analog input, reference or analog power supply lines. Layout should ensure that digital and analog signal lines are separated as much as possible. Particular care should be taken not to run any digital track alongside an analog signal track. An analog ground plane separate from the logic system ground should be established under and around the ADC. Pin 5 (AGND), Pin 14 and Pin 19 (ADC’s DGND) and all other analog grounds should be connected to this single analog ground point. The REFCOMP bypass capacitor and the DVDD bypass capacitor should also be connected to this analog ground plane. No other digital grounds should be connected to this analog ground plane. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the foil LTC1415 U U W U APPLICATIONS INFORMATION width for these tracks should be as wide as possible. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a WAIT state during conversion or by using three-state buffers to isolate the ADC data bus. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. SUPPLY BYPASSING High quality, low series resistance ceramic, 10µF bypass capacitors should be used at the VDD and REFCOMP pins as shown in the Typical Application on the fist page of this data sheet. Surface mount ceramic capacitors such as Murata GRM235Y5V106Z016 provide excellent bypassing in a small board space. Alternatively 10µF tantalum capacitors in parallel with 0.1µF ceramic capacitors can be used. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. The LTC1415 has differential inputs to minimize noise coupling. Common mode noise on the + AIN and – AIN leads will be rejected by the input CMRR. The – AIN input can be used as a ground sense for the + AIN input; the LTC1415 will hold and convert the difference voltage between + AIN and – AIN. The leads to + AIN (Pin 1) and – AIN (Pin 2) should be kept as short as possible. In applications where this is not possible, the + AIN and – AIN traces should be run side by side to equalize coupling. 1 ANALOG INPUT CIRCUITRY Figures 13a, 13b, 13c and 13d show the schematic and layout of a suggested evaluation board. The layout demonstrates the proper use of decoupling capacitors and ground plane with a two layer printed circuit board. DIGITAL SYSTEM LTC1415 +AIN –AIN REFCOMP AGND + Example Layout 2 4 – + OVDD DGND OGND AVDD DVDD 28 27 5 26 14 19 LTC1415 • F12 + 10µF 0.1µF 10µF 0.1µF ANALOG GROUND PLANE Figure 12. Power Supply Grounding Practice 15 TAB 4 GND 2 VCC RD SHDN NAP/SLP JP4B JP4A 4 JP4C U5B HC14 CS 23 JP3 3 JP4D R13 51Ω 1 U5A HC14 C5 1µF 16V R20 10k R19 10k C10 10µF 16V VOUT VIN AGND DGND 1 R16 51Ω C8 1000pF R15 51Ω R17 1M + VCC C1 22µF 10V R18 1M C4 1000pF C3 1000pF C6 10µF 16V D15 SS12 VCC 3.3V 4 3 2 1 14 5 26 27 28 21 22 23 24 JP2B JP2A D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 13 U5F HC14 12 NAP/SLP 20 19 18 17 16 15 13 12 11 10 9 8 7 6 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C9 0.1µF + C12 0.1µF 14 OVDD 7 B10 B9 B8 B7 B6 B5 B4 B0 B1 B2 B3 B11 C7 10µF 10V VCC U5G HC14 GND B0 TO B11 C11 0.1µF OVDD 5 1 11 2 3 4 5 6 7 8 9 1 11 2 3 4 5 6 7 8 9 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 U5C HC14 OE CLK D0 D1 D2 D3 D4 D5 D6 D7 6 19 18 17 16 15 14 13 12 19 18 17 16 15 14 13 12 R14 1k Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 U4 74HC574 OE CLK D0 D1 D2 D3 D4 D5 D6 D7 U3 74HC574 Figure 13a. Suggested Evaluation Circuit Schematic DGND AGND OVDD DVDD AVDD SHDN RD CONVST CS BUSY COMP VREF – AIN D11 OGND U2 LTC1415 +AIN R12 20Ω 25 VCC C2 10µF 16V OVDD NOTES: UNLESS OTHERWISE SPECIFIED 1. ALL RESISTOR VALUE IN OHMS, 1/10W, 5% 2. ALL CAPACITOR VALUES IN µF, 25V, 20% AND IN pF, 50V, 10% J7 CLK J5 – AIN J3 + AIN J1 GND J2 7V TO 15V U1 LT1121-5 D10 D9 D8 D7 D6 D5 D4 D0 D1 D2 D3 D11 C13 15pF 9 11 U5D HC14 U5E HC14 8 10 D11 D0 TO D11 D11 RDY DGND DGND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 LTC1415 • F13a 11 12 9 10 7 8 5 6 3 4 1 2 13 14 15 16 J6 HEADER R0 TO R11 1.2k D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 JP1 LED U U 16 W 3.3V APPLICATIONS INFORMATION U J4 OPTIONAL LTC1415 LTC1415 U W U U APPLICATIONS INFORMATION Figure 13b. Suggested Evaluation Circuit Board Component Side Silkscreen Figure 13c. Suggested Evaluation Circuit Board Component Side Layout 17 LTC1415 U W U U APPLICATIONS INFORMATION Figure 13d. Suggested Evaluation Circuit Board Solder Side Layout DIGITAL INTERFACE The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. A separate CONVST is used to initiate a conversion. Internal Clock The A/D converter has an internal clock that eliminates the need of synchronization between the external clock and the CS and RD signals found in other ADCs. The internal clock is factory trimmed to achieve a typical conversion time of 0.70µs and a maximum conversion time over the full operating temperature range of 0.75µs. No external adjustments are required. The guaranteed maximum acquisition time is 150ns. In addition, a throughput time of 800ns and a minimum sampling rate of 1.25Msps are guaranteed. Power Shutdown The LTC1415 provides two power shutdown modes, Nap and Sleep, to save power during inactive periods. The 18 Nap mode reduces the power by 87% and leaves only the digital logic and reference powered up. The wake-up time from Nap to active is 200ns. Follow the setup time shown in Figure 14a to avoid inadvertently invoking Sleep mode. In Sleep mode all bias currents are shut down and only leakage current remains, about 1µA. Wake-up time from Sleep mode is much slower since the reference circuit must power up and settle to 0.01% for full 12-bit accuracy. Sleep mode wake-up time is dependent on the value of the capacitor connected to the REFCOMP (Pin 4). The wake-up time is 10ms with the recommended 10µF capacitor. Shutdown is controlled by Pin 21 (SHDN); the ADC is in shutdown when it is low. The shutdown mode is selected with Pin 20 (NAP/SLP); high selects Nap. NAP/SLP t3 SHDN 1415 F14a Figure 14a. NAP/SLP to SHDN Timing LTC1415 W U U UO APPLICATI S I FOR ATIO In slow memory and ROM modes (Figures 19 and 20) CS is tied low and CONVST and RD are tied together. The MPU starts the conversion and reads the output with the RD signal. Conversions are started by the MPU or DSP (no external sample clock). SHDN t4 CONVST 1415 F14b Figure 14b. SHDN to CONVST Wake-Up Timing Timing and Control Conversion start and data read operations are controlled by three digital inputs: CONVST, CS and RD. A logic “0” applied to the CONVST pin will start a conversion after the ADC has been selected (i.e., CS is low). Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY is low during a conversion. Figures 16 through 20 show several different modes of operation. In modes 1a and 1b (Figures 16 and 18) CS and RD are both tied low. The falling edge of CONVST starts the conversion. The data outputs are always enabled and data can be latched with the BUSY rising edge. Mode 1a shows operation with a narrow logic low CONVST pulse. Mode 1b shows a narrow logic high CONVST pulse. In slow memory mode the processor applies a logic low to RD (= CONVST), starting the conversion. BUSY goes low, forcing the processor into a WAIT state. The previous conversion result appears on the data outputs. When the conversion is complete, the new conversion results appear on the data outputs; BUSY goes high, releasing the processor and the processor takes RD (= CONVST) back high and reads the new conversion data. In ROM mode, the processor takes RD (= CONVST) low, starting a conversion and reading the previous conversion result. After the conversion is complete, the processor can read the new result and initiate another conversion. CS t2 CONVST In mode 2 (Figure 18) CS is tied low. The falling edge of the CONVST signal again starts the conversion. Data outputs are in three-state until read by the MPU with the RD signal. Mode 2 can be used for operation with a shared MPU databus. t1 RD 1415 • F15 Figure 15. CS to CONVST Setup Timing t CONV t5 CONVST t6 t8 BUSY t7 DATA DATA (N – 1) DB11 TO DB0 DATA N DB11 TO DB0 DATA (N + 1) DB11 TO DB0 1415 • F16 Figure 16. Mode 1a CONVST Starts a Conversion. Data Outputs Always Enabled 19 LTC1415 U W U UO APPLICATI S I FOR ATIO tCONV t8 t5 t13 CONVST t6 t6 t6 BUSY t7 DATA (N – 1) DB11 TO DB0 DATA DATA N DB11 TO DB0 DATA (N + 1) DB11 TO DB0 1415 • F17 Figure 17. Mode 1b CONVST Starts a Conversion. Data is Read by RD t13 tCONV t5 t8 CONVST t6 BUSY t 11 t9 t 12 RD t 10 DATA DATA N DB11 TO DB0 1415 F18 Figure 18. Mode 2 CONVST Starts a Conversion. Data is Read by RD 20 LTC1415 W U U UO APPLICATI S I FOR ATIO t8 t CONV RD = CONVST t 11 t6 BUSY t 10 t7 DATA (N – 1) DB11 TO DB0 DATA DATA N DB11 TO DB0 DATA N DB11 TO DB0 DATA (N + 1) DB11-DB0 1415 • F19 Figure 19. Slow Memory Mode Timing CS = 0 t CONV t8 RD = CONVST t6 t 11 BUSY t 10 DATA DATA N DB11 TO DB0 DATA (N – 1) DB11 TO DB0 1415 • F20 Figure 20. ROM Mode Timing 21 LTC1415 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. G Package 28-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 0.397 – 0.407* (10.07 – 10.33) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.301 – 0.311 (7.65 – 7.90) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0.205 – 0.212** (5.20 – 5.38) 0.068 – 0.078 (1.73 – 1.99) 0° – 8° 0.005 – 0.009 (0.13 – 0.22) 0.022 – 0.037 (0.55 – 0.95) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 22 0.0256 (0.65) BSC 0.010 – 0.015 (0.25 – 0.38) 0.002 – 0.008 (0.05 – 0.21) G28 SSOP 0694 LTC1415 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. SW Package 28-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620) 0.697 – 0.712* (17.70 – 18.08) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.394 – 0.419 (10.007 – 10.643) NOTE 1 0.291 – 0.299** (7.391 – 7.595) 1 2 3 4 5 6 7 8 9 10 0.093 – 0.104 (2.362 – 2.642) 0.010 – 0.029 × 45° (0.254 – 0.737) 11 12 13 14 0.037 – 0.045 (0.940 – 1.143) 0° – 8° TYP 0.009 – 0.013 (0.229 – 0.330) 0.050 (1.270) TYP NOTE 1 0.016 – 0.050 (0.406 – 1.270) 0.014 – 0.019 (0.356 – 0.482) TYP NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS 0.004 – 0.012 (0.102 – 0.305) S28 (WIDE) 0996 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC1415 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1273/75/76 Complete 5V Sampling 12-Bit ADCs with 70dB SINAD at Nyquist Lower Power 75mW and Cost Effective for fSAMPLE ≤ 300ksps LTC1274/77 Low Power 12-Bit ADCs with Nap and Sleep Mode Shutdown Lowest Power (10mW) for fSAMPLE ≤ 100ksps LTC1278/79 High Speed Sampling 12-Bit ADCs with Shutdown Cost Effective 12-Bit ADCs with Convert Start Input Best for 300ksps < fSAMPLE ≤ 600ksps LTC1282 Complete 3V 12-Bit ADC with 12mW Power Dissipation Fully Specified for 3V-Powered Applications, fSAMPLE ≤ 140ksps LTC1409 Low Power 12-Bit, 800ksps Sampling ADC Best Dynamic Performance, fSAMPLE ≤ 800ksps, 80mW Dissipation LTC1410 12-Bit, 1.25Msps Sampling ADC with Shutdown Best Dynamic Performance, THD = 84 and SINAD = 71 at Nyquist LTC1419 14-Bit, 800ksps Sampling ADC 81.5dB SINAD, 150mW from ± 5V Supplies LTC1605 16-Bit, 100ksps Sampling ADC Single Supply, ±10V Input Range, Low Power 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 ● (408) 432-1900 FAX: (408) 434-0507● TELEX: 499-3977 ● www.linear-tech.com 1415f LT/TP 0497 7K • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 1996