LTC1664 Micropower Quad 10-Bit DAC U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Tiny: 4 DACs in the Board Space of an SO-8 Micropower: 59µA per DAC Plus 1µA Sleep Mode for Extended Battery Life Wide 2.7V to 5.5V Supply Range Rail-to-Rail Voltage Outputs Drive 1000pF Reference Range Includes Supply for Ratiometric 0V-to-VCC Output Reference Input Impedance is Code-Independent —Eliminates External Reference Buffer Individually Addressable DACs Differential Nonlinearity: ≤ ±0.75LSB Max Pin-Compatible Octal Version Available (LTC1660) ■ ■ ■ Mobile Communications Remote Industrial Devices Automatic Calibration for Manufacturing Portable Battery-Powered Instruments Trim/Adjust Applications , LTC and LT are registered trademarks of Linear Technology Corporation. W ■ Linear Technology’s proprietary, inherently monotonic voltage interpolation architecture provides excellent linearity while allowing for an exceptionally small external form factor. Ultralow supply current, power-saving Sleep mode and extremely compact size make the LTC1664 ideal for battery-powered applications, while its ease of use, high performance and wide supply range make it an excellent choice as a general-purpose converter. U APPLICATIO S ■ The LTC®1664 integrates four accurate, serially addressable 10-bit digital-to-analog converters (DACs) in a tiny 16-pin Narrow SSOP package. Each buffered DAC draws just 59µA total supply current, yet is capable of supplying DC output currents in excess of 5mA and reliably driving capacitive loads of up to 1000pF. Sleep mode further reduces total supply current to 1µA. BLOCK DIAGRA GND 1 VOUT A 2 16 VCC 10-BIT DAC A 10-BIT DAC D 5 Differential Nonlinearity (DNL) VOUT D 1.0 VCC = 5V VREF = 4.096V 0.8 0.6 3 10-BIT DAC B 10-BIT DAC C 4 0.4 VOUT C 0.2 LSB VOUT B 0 –0.2 CONTROL LOGIC –0.4 ADDRESS DECODER REF 6 11 CLR CS/LD 7 10 DOUT –0.6 –0.8 SCK 8 SHIFT REGISTER 9 DIN –1.0 0 256 512 CODE 768 1023 1664 G08 1664 BD 1 LTC1664 U U RATI GS W W W W AXI U U ABSOLUTE PACKAGE/ORDER I FOR ATIO (Note 1) VCC to GND .............................................. – 0.3V to 7.5V Logic Inputs to GND ................................ – 0.3V to 7.5V VOUT A, VOUT B…VOUT D, REF to GND ................................. – 0.3V to (VCC + 0.3V) Maximum Junction Temperature ......................... 125°C Operating Temperature Range LTC1664C ............................................. 0°C to 70°C LTC1664I ........................................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................ 300°C ORDER PART NUMBER TOP VIEW GND 1 16 VCC VOUT A 2 15 NC VOUT B 3 14 NC VOUT C 4 13 NC VOUT D 5 12 NC REF 6 11 CLR CS/LD 7 10 DOUT SCK 8 9 GN PACKAGE 16-LEAD PLASTIC SSOP LTC1664CGN LTC1664CN LTC1664IGN LTC1664IN DIN GN PART MARKING N PACKAGE 16-LEAD PDIP 1664 1664I TJMAX = 125°C, θJA = 150°C/W (GN) TJMAX = 125°C, θJA = 100°C/W (N) Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER CONDITONS MIN TYP MAX UNITS Accuracy Resolution ● 10 Bits Monotonicity (Notes 2, 4) ● 10 Bits DNL Differential Nonlinearity (Notes 2, 4) ● ±0.2 ±0.75 LSB INL Integral Nonlinearity (Notes 2, 4) ● ±0.6 ±2.5 LSB VOS Offset Error (Note 7) ● ±10 ±30 mV ● ±15 ● ±3 VOS Temperature Coefficient FSE Full-Scale Error PSR Power Supply Rejection VCC = 5V, VREF = 4.096V (Note 4) Full-Scale Error Temperature Coefficient ● VREF = 2.5V µV/°C ±15 LSB ±30 µV/°C 0.18 LSB/V Reference Input Input Voltage Range Resistance Not in Sleep Mode ● 0 ● 70 Capacitance IREF Reference Current Sleep Mode ● VCC V 130 kΩ 12 pF µA 0.001 1 5.5 V 236 186 1 380 290 3 µA µA µA Power Supply VCC Positive Supply Voltage ICC Supply Current 2 ● VCC = 5V (Note 3) VCC = 3V (Note 3) Sleep Mode (Note 3) ● ● ● 2.7 LTC1664 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Performance Short-Circuit Current Low VOUT = 0V, VCC = 5.5V, VREF = 5.1V, Code = 1023 (Note 9) ● 10 30 100 mA Short-Circuit Current High VOUT = VCC = 5.5V, VREF = 5.1V, Code = 0 (Note 9) ● 10 27 120 mA AC Performance Voltage Output Slew Rate Rising (Notes 4, 5) Falling (Notes 4, 5) Voltage Output Settling Time Rising 0.1VFS to 0.9VFS ±0.5LSB (Notes 4, 5) Falling 0.9VFS to 0.1VFS ± 0.5LSB (Notes 4, 5) 0.60 0.25 Capacitive Load Driving V/µs V/µs 6 19 µs µs 1000 pF Digital I/O VIH Digital Input High Voltage VCC = 2.7V to 5.5V VCC = 2.7V to 3.6V ● ● VIL Digital Input Low Voltage VCC = 4.5V to 5.5V VCC = 2.7V to 5.5V ● ● VOH Digital Output High Voltage IOUT = – 1mA, DOUT Only ● VOL Digital Output Low Voltage IOUT = 1mA, DOUT Only ● ILK Digital Input Leakage VIN = GND to VCC ● CIN Digital Input Capacitance 2.4 2.0 V V 0.8 0.6 V V 0.4 V ±10 µA VCC – 1 V 0.05 2 pF WU TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (See Figure 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 40 15 ns VCC = 4.5V to 5.5V t1 DIN Valid to SCK Setup t2 DIN Valid to SCK Hold ● 0 –11 ns t3 SCK High Time (Note 6) ● 30 5 ns t4 SCK Low Time (Note 6) ● 30 7 ns t5 CS/LD Pulse Width (Note 6) ● 80 30 ns t6 LSB SCK High to CS/LD High (Note 6) ● 30 4 ns t7 CS/LD Low to SCK High (Note 6) ● 80 26 t8 DOUT Propagation Delay CLOAD = 15pF (Note 6) ● 5 26 t9 SCK Low to CS/LD Low (Note 6) ● 20 0 ns t10 CLR Pulse Width (Note 6) ● 100 37 ns t11 CS/LD High to SCK Positive Edge (Note 6) ● 30 0 ns SCK Frequency (Notes 6 and 8) ● ● ns 80 16.7 ns MHz VCC = 2.7V to 5.5V t1 DIN Valid to SCK Setup (Note 6) ● 60 20 ns t2 DIN Valid to SCK Hold (Note 6) ● 0 –14 ns t3 SCK High Time (Note 6) ● 50 8 ns t4 SCK Low Time (Note 6) ● 50 12 ns 3 LTC1664 WU TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (See Figure 1) SYMBOL PARAMETER CONDITIONS t5 CS/LD Pulse Width (Note 6) ● t6 LSB SCK High to CS/LD High (Note 6) ● 50 5 ns t7 CS/LD Low to SCK High (Note 6) ● 100 27 ns t8 DOUT Propagation Delay CLOAD = 15pF (Note 6) ● 5 47 t9 SCK Low to CS/LD Low (Note 6) ● 30 0 ns t10 CLR Pulse Width (Note 6) ● 120 41 ns t11 CS/LD High to SCK Positive Edge (Note 6) ● 30 0 SCK Frequency (Notes 6 and 8) ● Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: Nonlinearity and monotonicity are defined and tested at VCC = 5V, VREF = 4.096V, from code 20 to code 1023. See Rail-to-Rail output considerations. Note 3: Digital inputs at 0V or VCC. Note 4: Load is 10kΩ in parallel with 100pF. MIN TYP 100 30 MAX UNITS ns 150 ns ns 10 MHz Note 5: VCC = VREF = 5V. Note 6: Guaranteed by design and not subject to test. Note 7: Measured at code 20. Note 8: If a continuous clock is used, CS/LD timing (t7 and t9) will limit the maximum clock frequency to 5MHz at 4.5V to 5.5V(3.85MHz at 2.7V to 5.5V). Note 9: Any output shorted. U W TYPICAL PERFOR A CE CHARACTERISTICS Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 1.0 2.5 VCC = 5V VREF = 4.096V 300 VCC = 5V VREF = 4.096V 1.5 0.6 1.0 0.4 0.5 0.2 0 0 – 0.5 –0.2 –1.0 –0.4 –1.5 –0.6 – 2.0 280 SUPPLY CURENT (µA) 0.8 LSB LSB 2.0 0 256 512 CODE 768 1023 1664 G07 VREF = VCC CODE = 1023 260 VCC = 5.5V 240 VCC = 4.5V 220 VCC = 3.6V 200 VCC = 2.7V 180 –0.8 – 2.5 4 Supply Current vs Temperature –1.0 0 256 512 CODE 768 1023 1664 G08 160 –55 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 1664 G11 LTC1664 U W TYPICAL PERFOR A CE CHARACTERISTICS VCC = VREF = 5V CODE = 512 1.5 1.5 1 1 0 –0.5 0.5 0 –0.5 –1 –1 –1.5 –1.5 SOURCE –2 –2 –1 SINK 0 IOUT (mA) SOURCE 0 IOUT (µA) 2 2.3 1.6 VCC = 3V 1.5 1.4 VCC = 2.7V 1.3 VCC = 4.5V SUPPLY CURRENT (mA) VOUT (V) 2.4 1.2 2.2 SOURCE –20 –10 SINK SOURCE 1 0 10 IOUT (mA) 20 30 –15 –12 –8 –4 0 4 IOUT (mA) 8 0 0 1 2 3 4 LOGIC INPUT VOLTAGE (V) 1664 G02 5 1664 G12 Minimum Supply Headroom vs Load Current (Output Sourcing) Minimum VOUT vs Load Current (Output Sinking) 1400 VCC = 5V CODE = 0 1200 0.4 12 15 1664 G01 1400 0.6 SINK VREF = 4.096V ∆VOUT < 1LSB CODE = 1023 1200 125°C 1000 1000 VCC – VOUT (mV) 2 0.8 0.2 1.1 2.1 VOUT (mV) VOUT (V) VCC = 5V 100 ALL DIGITAL INPUTS SHORTED TOGETHER 1.0 VCC = 3.6V 1.7 VCC = 5.5V 2.5 80 1.2 1.8 2.8 2.6 40 60 TIME (µs) Supply Current vs Logic Input Voltage VREF = VCC CODE = 512 1.9 2.7 20 1664 G05 Midscale Output Voltage vs Load Current VREF = VCC CODE = 512 –30 0 500 1664 G10 Midscale Output Voltage vs Load Current 2.9 2 SINK 1664 G09 3 3 0 –500 2 10% TO 90% STEP 1 –2 1 VCC = VREF = 5V 4 VOUT (V) 0.5 5 VCC = VREF = 3V CODE = 512 2 ∆VOUT (LSB) ∆VOUT (LSB) 2 Large-Signal Step Response Load Regulation vs Output Current Load Regulation vs Output Current 800 25°C 600 –55°C 800 25°C 600 –55°C 400 400 200 200 0 125°C 0 0 2 4 6 IOUT (mA) (Sinking) | | 8 10 1664 G04 0 2 4 6 |IOUT| (mA) (Sourcing) 8 10 1664 G03 5 LTC1664 U U U PIN FUNCTIONS GND (Pin 1): System Ground. VOUT A to VOUT D (Pins 2–5): DAC Analog Voltage Outputs. The output range is 1023 0 to V 1024 REF REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC. DIN (Pin 9): Serial Interface Data Input. Data on the DIN pin is shifted into the 16-bit register on the rising edge of SCK. CMOS and TTL compatible. DOUT (Pin 10): Serial Interface Data Output. Data appears on DOUT 16 positive SCK edges after being applied to DIN. May be tied to DIN of another serial device for daisy-chain operaton. CMOS and TTL compatible. CS/LD (Pin 7): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on DIN into the register. When CS/LD is pulled high, SCK is disabled and data is loaded from the shift register into the specified DAC register(s), updating the analog output(s). CMOS and TTL compatible. CLR (Pin 11): Asynchronous Clear Input. All internal shift and DAC registers are cleared to zero at the falling edge of the CLR signal, forcing the analog outputs to zero scale. CMOS and TTL compatible. SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL compatible. VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V. 6 NC (Pins 12–15): Make no electrical connection to these pins. LTC1664 W BLOCK DIAGRA 16 VCC GND 1 VOUT A 2 10-BIT DAC A 10-BIT DAC D 5 VOUT D VOUT B 3 10-BIT DAC B 10-BIT DAC C 4 VOUT C 11 CLR 10 DOUT CONTROL LOGIC REF 6 CS/LD 7 SCK 8 ADDRESS DECODER SHIFT REGISTER 9 DIN 1664 BD WU W TI I G DIAGRA t1 t2 t3 t6 t4 SCK t9 t11 DIN A3 t5 A1 A2 X1 X0 t7 CS/LD t8 DOUT A3 A2 A1 X1 X0 A3 1664 F01 Figure 1 7 LTC1664 U OPERATIO Transfer Function The buffered serial output of the shift register is available on the DOUT pin, which swings from GND to VCC. Data appears on DOUT 16 positive SCK edges after being applied to DIN. The transfer function is k VOUT(IDEAL) = V 1024 REF The LTC1664 clears the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. Multiple LTC1664’s can be controlled from a single 3-wire serial port (i.e., SCK, DIN and CS/LD) by using the included “daisy-chain” facility. A series of m chips is configured by connecting each DOUT (except the last) to DIN of the next chip, forming a single 16m-bit shift register. The SCK and CS/LD signals are common to all chips in the chain. In use, CS/LD is held low while m 16-bit words are clocked to DIN of the first chip; CS/LD is then pulled high, updating all of them simultaneously. Power Supply Sequencing Sleep Mode The voltage at REF (Pin 6) should be kept within the range – 0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 16) is in transition. If it is not possible to sequence the supplies, connect a Schottky diode from REF (anode) to VCC (cathode). DAC address 1110b is reserved for the special Sleep instruction (see Table 2). In this mode, the digital interface stays active while the analog circuits are disabled; static power consumption is thus virtually eliminated. The reference input and analog outputs are set in a high impedance state and all DAC settings are retained in memory so that when Sleep mode is exited, the outputs of DACs not updated by the Wake command are restored to their last active state. where k is the decimal equivalent of the binary DAC input code and VREF is the voltage at REF (Pin 6). Power-On Reset Serial Interface Referring to Figure 2: With CS/LD held low, data on the D IN input is shifted into the 16-bit shift register on the positive edge of SCK. The 4-bit DAC address, A3-A0, is loaded first (see Table 2), then the 10-bit input code, D9-D0, ordered MSB-to-LSB in each case. Two don’t-care bits, X1-X0, are loaded last. When the full 16-bit input word has been shifted in, CS/LD is pulled high, loading the DAC register with the word and causing the addressed DAC output(s) to update. The clock is disabled internally when CS/LD is high. Note: SCK must be low before CS/LD is pulled low. Sleep mode is initiated by performing a load sequence to address 1110b (the DAC input word D9-D0 is ignored). Once in Sleep mode, a load sequence to any other address (including “No Change” address 0000b) causes the LTC1664 to Wake. It is possible to keep one or more chips of a daisy chain in continuous Sleep mode by giving the Sleep instruction to these chips each time the active chips in the chain are updated. Table 1. LTC1664 Input Word A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0 Address/Control 8 Input Code Don’t Care LTC1664 U OPERATIO SCK 1 A3 DIN 2 A2 3 A1 4 5 A0 D9 6 D8 7 8 D7 9 D6 10 D5 ADDRESS/CONTROL 11 D4 D3 12 D2 13 14 D1 D0 INPUT CODE 15 X1 16 X0 DON’T CARE INPUT WORD W0 CS/LD DOUT (ENABLE SCK) (UPDATE OUTPUT) A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 INPUT WORD W–1 X1 X0 A3 INPUT WORD W0 1664 F02 Figure 2. LTC1664 Register Loading Sequence Table 2. DAC Address/Control Functions ADDRESS/CONTROL A3 A2 A1 A0 DAC STATUS SLEEP STATUS 0 0 0 0 No Change Wake 0 0 0 1 Load DAC A Wake 0 0 1 0 Load DAC B Wake 0 0 1 1 Load DAC C Wake 0 1 0 0 Load DAC D Wake 0 1 0 1 Reserved 0 1 1 0 Reserved 0 1 1 1 Reserved 1 0 0 0 Reserved 1 0 0 1 Reserved 1 0 1 0 Reserved 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 1 1 1 0 No Change Sleep 1 1 1 1 Load ALL DACs with Same 10-Bit Code Wake Reserved 9 LTC1664 U OPERATIO Voltage Outputs Rail-to-Rail Output Considerations Each of the four rail-to-rail output amplifiers contained in the LTC1664 can source or sink up to 5mA. The outputs swing to within a few millivolts of either supply rail when unloaded and have an equivalent output resistance of 85Ω when driving a load to the rails. The output amplifiers are stable driving capacitive loads of up to 1000pF. In any rail-to-rail voltage output DAC, the output is limited to voltages within the supply range. A small resistor placed in series with the output can be used to achieve stability for any load capacitance. A 1µF load can be successfully driven by inserting a 20Ω resistor; a 2.2µF load needs only a 10Ω resistor. In either case, larger values of resistance, capacitance or both may be safely substituted for the values given. 10 If the DAC offset is negative, the output for the lowest codes limits at 0V as shown in Figure 3b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 3c. No full-scale limiting can occur if VREF is less than VCC – FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. LTC1664 U OPERATIO VREF = VCC POSITIVE FSE OUTPUT VOLTAGE INPUT CODE (c) VREF = VCC OUTPUT VOLTAGE 0 512 INPUT CODE (a) 1023 OUTPUT VOLTAGE 0V NEGATIVE OFFSET INPUT CODE (b) 1665/60 F03 Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC 11 LTC1664 U TYPICAL APPLICATIONS A Low Power Dual Trim Circuit with Coarse/Fine Adjustment R1 3.3V 110Ω 3.3V R2 11k 0.1µF 0.1µF 8 – 1 U2A LT®1490 VOUT1 GND 2 R1 110Ω COARSE VOUT A 3 U1 LTC1664 1 2 DAC A 16 DAC D 5 R2 11k VCC VOUT D R1 110Ω COARSE VOUT C R2 11k FINE R1 110Ω 6 – 5 +LT1490 U2B + 4 0.1µF 3.3V 0.1µF R2 11k FINE VOUT B 3 DAC B DAC C 4 2 LTC1258-2.5 1 REF 6 4 CS/LD 3-WIRE SERIAL INTERFACE SCK 7 8 11 CONTROL LOGIC ADDRESS DECODER 10 SHIFT REGISTER 9 CLR DOUT DIN 1664 TA01 ) ) ) ) VOUT 1 = VREF CODE A + R1 CODE B 1024 R2 1024 ) ) ) ) = 2.5V CODE A + 1 CODE B 1024 100 1024 VOUT 2 = VREF CODE D + R1 CODE C 1024 R2 1024 = 2.5V CODE D + 1 CODE C 1024 100 1024 12 TO OTHER LTC1664s 0.1µF 7 VOUT2 LTC1664 U TYPICAL APPLICATIONS A 4-Channel Bipolar Output Voltage Circuit Configuration 5V R R R R 0.1µF 0.1µF VS+ 4 – 1 U2A LT1491 ± 5V + VOUT A ′ 0.1µF 11 16 VCC 2 DAC A DAC D 5 VOUT D U2B LT1491 13 – 12 +LT1491 R R – + ± 5V 7 U1 LTC1664 1 14 U2D VOUT A 3 VS– R VOUT B ′ GND 2 6 9 VOUT B REF CS/LD 3-WIRE SERIAL INTERFACE CLK 3 DAC B DAC C 6 7 8 4 11 CONTROL LOGIC ADDRESS DECODER SHIFT REGISTER 10 9 VOUT C ± 5V R – U2C 5 VOUT D′ 10 +LT1491 8 VOUT C′ ± 5V CLR DOUT DIN CODE VOUT X – 5V 0 0V 512 1023 +4.99V 1664 TA02 13 LTC1664 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. GN Package 16-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641) 0.189 – 0.196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157** (3.810 – 3.988) 1 0.015 ± 0.004 × 45° (0.38 ± 0.10) 0.007 – 0.0098 (0.178 – 0.249) 0.053 – 0.068 (1.351 – 1.727) 2 3 4 5 6 7 8 0.004 – 0.0098 (0.102 – 0.249) 0° – 8° TYP 0.016 – 0.050 (0.406 – 1.270) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 14 0.009 (0.229) REF 0.008 – 0.012 (0.203 – 0.305) 0.0250 (0.635) BSC GN16 (SSOP) 1098 LTC1664 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N Package 16-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.770* (19.558) MAX 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 0.255 ± 0.015* (6.477 ± 0.381) 0.130 ± 0.005 (3.302 ± 0.127) 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) ( +0.035 0.325 –0.015 8.255 +0.889 –0.381 ) 0.045 – 0.065 (1.143 – 1.651) 0.020 (0.508) MIN 0.065 (1.651) TYP 0.125 (3.175) MIN 0.100 (2.54) BSC *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 0.018 ± 0.003 (0.457 ± 0.076) N16 1098 15 LTC1664 U TYPICAL APPLICATION An 11-Bit Pin Driver VH and VL Adjustment Circuit for ATE Applications 5V 11 16 6 CLR VCC REF 0.1µF VH (FROM MAIN DAC) U1 LTC1664 DAC A 2 RG VA 50k 10V RF 5k 3 2 DAC B 3 + 4 4 – 5V CS/LD 7 DIN 9 SCK 8 GND 1 5 0.1µF RF 5k VH VL RF 5k 5 6 DAC D VL′ 0.1µF – VL (FROM MAIN DAC) DAC C VH′ VH′ = VH + ∆VH 1 U2A LT1368 RG VB 50k RG VC 50k 0.1µF 8 + 7 U2B LT1368 VL′ = VL + ∆VL 0.1µF – RG VD 50k VOUT PIN DRIVER LOGIC DRIVE RF 5k CODE A CODE B 1023 1023 1023 512 1023 0 512 1023 512 512 512 0 0 1023 0 512 0 0 1664 TA03 ∆VH, ∆VL 0 + 250mV +500mV – 250mV 0 + 250mV –500mV –250mV 0 VA = VC = 2.5V VH′ = VH + RF (V – V ) B RG A VL′ = VL + RF (V – V ) D RG C For Resistor Values Shown: Adjustment Range = ±500mV Adjustment Step Size = 500µV RELATED PARTS PART NUMBER LTC1665/LTC1660 LTC1661 LTC1662 LTC1663 LTC1446/LTC1446L DESCRIPTION Octal 8/10-Bit VOUT DAC in 16-Pin Narrow SSOP Dual 10-Bit VOUT DAC in 8-Pin MSOP Package Ultra Low Power Dual 10-Bit VOUT DAC in 8-Pin MSOP Package Single 10-Bit VOUT DAC with 2-Wire Interface in SOT-23 Package Dual 12-Bit VOUT DACs in SO-8 Package with Internal Reference LTC1448 LTC1454/LTC1454L Dual 12-Bit VOUT DAC in SO-8 Package Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LT1460 LTC1590 LTC1654 LTC1659 Micropower Precision Series Reference, 2.5V, 5V, 10V Versions Dual 12-Bit IOUT DAC in SO-16 Package Dual 14-Bit DAC in SO-8 Footprint Single Rail-to-Rail 12-Bit VOUT DAC in 8-Lead MSOP Package VCC: 2.7V to 5.5V 16 Linear Technology Corporation COMMENTS VCC = 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output VCC = 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output VCC = 2.7V to 5.5V, 1.5µA per DAC, Rail-to-Rail Output VCC = 2.7V to 5.5V, Internal Reference, 60µA LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V VCC = 2.7V to 5.5V, External Reference Can Be Tied to VCC LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V 0.075% Max, 10ppm/°C Max, Only 130µA Supply Current VCC = 4.5V to 5.5V, 4-Quadrant Multiplication 1LBS DNL, Selectable Speed/Power Low Power Multiplying VOUT DAC. Output Swings from GND to REF. REF Input Can Be Tied to VCC 1664f LT/TP 0700 4K • PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 2000