application INFO available Current Mode PWM Controller FEATURES • UC1846/7 UC2846/7 UC3846/7 DESCRIPTION Automatic Feed Forward Compensation • The UC1846/7 family of control ICs provides all of the necessary features to implement fixed frequency, current mode control Programmable Pulse-by-Pulse Current schemes while maintaining a minimum external parts count. The Limiting superior performance of this technique can be measured in imAutomatic Symmetry Correction in Push-pull proved line regulation, enhanced load response characteristics, and Configuration a simpler, easier-to-design control loop. Topological advantages include inherent pulse-by-pulse current limiting capability, automatic Enhanced Load Response Characteristics symmetry correction for push-pull converters, and the ability to parParallel Operation Capability for Modular allel “power modules" while maintaining equal current sharing. Power Systems Protection circuitry includes built-in under-voltage lockout and proDifferential Current Sense Amplifier with grammable current limit in addition to soft start capability. A shutWide Common Mode Range down function is also available which can initiate either a complete shutdown with automatic restart or latch the supply off. Double Pulse Suppression • 500mA (Peak) Totem-pole Outputs • ±1% Bandgap Reference • Under-voltage Lockout • Soft Start Capability • Shutdown Terminal • 500kHZ Operation • • • • • Other features include fully latched operation, double pulse suppression, deadline adjust capability, and a ±1% trimmed bandgap reference. The UC1846 features low outputs in the OFF state, while the UC1847 features high outputs in the OFF state. BLOCK DIAGRAM 5.1 V REFERENCE REGULATOR VIN 15 2 VREF 13 VC SYNC 10 RT UVLO LOCKOUT Q CT 8 C/S- 3 11 A OUT T OSC Q UC1846 Output Stage COMP X3 C/S+ F/F 9 UC1847 Output Inverted S R Q 4 S 14 B OUT 0.5 V + 0.5 mA NI 5 INV 6 COMP 7 12 GND E/A 1 CURRENT LIMIT ADJUST 16 SHUTDOWN 350 mV 6k UDG-02057 SLUS352A - JANUARY 1997 - REVISED MARCH 2002 UC1846/7 UC2846/7 UC3846/7 ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage (Pin 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +40V Collector Supply Voltage (Pin 13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +40V Output Current, Source or Sink (Pins 11, 14) . . . . . . . . . . . . . . . . . . . . . . . 500mA Analog Inputs (Pins 3, 4, 5, 6, 16). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +VIN Reference Output Current (Pin 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -30mA Sync Output Current (Pin 10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA Error Amplifier Output Current (Pin 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA Soft Start Sink Current (Pin 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Oscillator Charging Current (Pin 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Power Dissipation at TA=25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000mW Power Dissipation at TC=25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000mW Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . +300°C Note 1. All voltages are with respect to Ground, Pin 13. Currents are positive into, negative out of the speficied terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. Pin numbers refer to DIL and SOIC packages only. CONNECTION DIAGRAMS DIL-16, SOIC-16 (TOP VIEW) J or N Package, DW Package PLCC-20, LCC-20 (TOP VIEW) Q, L Packages PACKAGE PIN FUNCTION FUNCTION PIN 1 N/C C/L SS 2 VREF 3 C/S4 C/S+ 5 N/C 6 E/A+ 7 E/A8 Comp 9 CT 10 N/C 11 RT 12 Sync 13 A Out 14 Gnd 15 N/C 16 VC 17 B Out 18 VIN 19 Shutdown 20 ELECTRICAL CHARACTERISTICS (Unless otherwise stated, these specifications apply for TA=-55°C to +125°C for UC1846/7; -40°C to +85°C for the UC2846/7; and 0°C to +70°C for the UC3846/7; VIN=15V, RT=10k, CT=4.7nF, TA=TJ.) UC1846/UC1847 PARAMETER TEST CONDITIONS UC2846/UC2847 UC3846/UC3847 MIN. TYP. MAX. MIN. TYP. MAX. UNITS 5.05 5.10 5.15 5.00 5.10 5.20 V Reference Section Output Voltage TJ=25°C, IO=1mA Line Regulation VIN=8V to 40V 5 20 5 20 mV Load Regulation IL=1mA to 10mA 3 15 3 15 mV Temperature Stability Over Operating Range, (Note 2) Total Output Variation Line, Load, and Temperature (Note 2) Output Noise Voltage 10Hz ≤ f ≤10kHz, TJ=25°C (Note 2) Long Term Stability TJ=125°C, 1000 Hrs. (Note 2) Short Circuit Output Current VREF=0V 0.4 5.00 -10 2 0.4 5.20 4.95 mV/°C 5.25 V 100 100 µV 5 5 mV -45 mA -45 -10 UC1846/7 UC2846/7 UC3846/7 (Unless otherwise stated, these specifications apply for TA=-55°C to +125°C for UC1846/7; ELECTRICAL CHARACTERISTICS (cont.) -40°C to +85°C for the UC2846/7; and 0°C to +70°C for the UC3846/7; VIN=15V, RT=10k, CT=4.7nF, TA=TJ.) UC1846/UC1847 PARAMETER TEST CONDITIONS UC2846/UC2847 UC3846/UC3847 MIN. TYP. MAX. MIN. TYP. MAX. UNITS 39 43 47 39 43 47 kHz 2 -1 2 % Oscillator Section Initial Accuracy TJ=25°C Voltage Stability VIN=8V to 40V -1 Temperature Stability Over Operating Range (Note 2) -1 Sync Output High Level 3.9 Sync Output Low Level 4.35 2.3 Sync Input High Level Pin 8=0V Sync Input Low Level Pin 8=0V Sync Input Current Sync Voltage=3.9V, Pin 8=0V -1 3.9 2.5 3.9 % 4.35 2.3 V 2.5 3.9 V 2.5 1.3 1.5 V 2.5 V 1.3 1.5 mA Error Amp Section Input Offset Voltage 0.5 5 0.5 10 mV Input Bias Current -0.6 -1 -0.6 -2 µA 250 nA VIN-2V V Input Offset Current 40 0 250 VIN-2V 40 Common Mode Range VIN=8V to 40V 0 Open Loop Voltage Gain ∆VO=1.2 to 3V, VCM=2V 80 105 80 105 dB Unity Gain Bandwidth TJ=25°C (Note 2) 0.7 1.0 0.7 1.0 MHz CMRR VCM=0V to 38V, VIN=40V 75 100 75 100 dB PSRR VIN=8V to 40V 80 105 80 105 dB Output Sink Current VID=-15mV to -5V, VPIN 7=1.2V 2 6 2 6 mA Output Source Current VID=15mV to 5V, VPIN 7=2.5V -0.4 -0.5 -0.4 -0.5 mA High Level Output Voltage RL=(Pin 4.3 4.6 4.3 4.6 V 7) 15kΩ Low Level Output Voltage 0.7 1 2.5 2.75 3.0 1.1 1.2 0.7 1 V 2.5 2.75 3.0 V 1.1 1.2 25 mV Current Sense Amplifier Section Amplifier Gain VPIN 3=0V, Pin 1 Open (Notes 3 & 4) Maximum Differential Input Pin 1 Open (Note 3) Signal (VPIN 4-VPIN 3) RL (Pin 7)=15kW VPIN 1=0.5V, Pin 7 Open (Note 3) CMRR VCM=1V to 12V 60 83 60 83 dB PSRR VIN=8V to 40V 60 84 60 84 dB Input Bias Current VPIN 1=0.5V, Pin 7 Open (Note 3) -2.5 -10 -2.5 -10 µA Input Offset Current VPIN 1=0.5V, Pin 7 Open (Note 3) 0.08 1 0.08 1 µA Input Common Mode Range Delay to Outputs 5 VIN-3 0 TJ=25°C, (Note 2) 25 200 500 5 V Input Offset Voltage 0 VIN-3 V 200 500 ns Current Limit Adjust Section Current Limit Offset VPIN 3=0V, VPIN 4=0V, Pin 7 Open (Note 3) Input Bias Current 0.45 VPIN 5=VREF, VPIN 6=0V 0.5 0.55 -10 -30 0.45 350 400 250 VIN 0 0.5 0.55 V -10 -30 µA 350 400 mV VIN V Shutdown Terminal Section Threshold Voltage 250 Input Voltage Range Minimum Latching Current 0 (Note 6) (IPIN 1) 3.0 3 1.5 3.0 1.5 mA UC1846/7 UC2846/7 UC3846/7 (Unless otherwise stated, these specifications apply for TA=-55°C to +125°C for UC1846/7; ELECTRICAL -40°C to +85°C for the UC2846/7; and 0°C to +70°C for the UC3846/7; VIN=15V, RT=10k, CHARACTERISTICS (cont.) CT=4.7nF, TA=TJ.) UC1846/UC1847 PARAMETER TEST CONDITIONS UC2846/UC2847 MIN. UC3846/UC3847 TYP. MAX. MIN. TYP. MAX. UNITS 1.5 0.8 1.5 0.8 mA 300 600 300 600 ns 200 µA Shutdown Terminal Section (cont.) Maximum Non-Latching (Note 7) Current (IPIN 1) Delay to Outputs TJ=25°C (Note 2) Output Section Collector-Emitter Voltage Collector Leakage Current Output Low Level Output High Level 40 40 VC=40V (Note 5) V 200 ISINK=20mA 0.1 0.4 0.1 0.4 V ISINK=100mA 0.4 2.1 0.4 2.1 V ISOURCE=20mA 13 13.5 13 13.5 V ISOURCE=100mA 12 13.5 12 13.5 V Rise Time CL=1nF, TJ=25°C (Note 2) 50 300 50 300 ns Fall Time CL=1nF, TJ=25°C (Note 2) 50 300 50 300 ns Start-Up Threshold 7.7 8.0 7.7 8.0 V Threshold Hysteresis 0.75 Under-Voltage Lockout Section 0.75 V Total Standby Current Supply Current 17 21 17 21 mA Note 2. These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production. Note 3. Parameter measured at trip point of latch with VPIN 5 = VREF, VPIN 6 = 0V. ∆V PIN 7 Note 4. Amplifier gain defined as: G = ; VPIN4 = 0 to 1.0V ∆V PIN 4 Note 5. Applies to UC1846/UC2846/UC3846 only due to polarity of outputs. Note 6. Current into Pin 1 guaranteed to latch circuit in shutdown state. Note 7. Current into Pin 1 guaranteed not to latch circuit in shutdown state. APPLICATIONS DATA Oscillator Circuit ID . Output deadtime is determined by the external capacitor, CT, according to the formula: τd (µs ) = 145CT (µf ) 3.6 ID ID = Oscillator discharge current at 25°C is typically 7.5. RT (kΩ ) For large values of RT: τd (µs ) ≈ 145CT (µf ). 2.2 Oscillator frequency is approximated by the formula: fT (kHz ) ≈ . RT (kΩ ) • CT (µf ) 4 UC1846/7 UC2846/7 UC3846/7 APPLICATIONS DATA (cont.) Error Amp Gain and Phase vs Frequency Error Amp Output Configuration Error Amp Open-Logic D.C. Gain vs Load Resistance Parallel Operation 5 UC1846/7 UC2846/7 UC3846/7 APPLICATIONS DATA (cont.) Pulse by Pulse Current Limiting R 2 VREF − 0.5 R1 + R 2 Peak Current (IS) is determined by the formula: IS = 3RS Soft Start and Shutdown /Restart Functions 6 UC1846/7 UC2846/7 UC3846/7 APPLICATIONS DATA (cont.) Current Sense Amp Connection A small RC filter may be required in some applications to reduce switch transients. Differential input allows remote, noise free sensing. UC1846 Open Loop Test Circuit 7 PACKAGE OPTION ADDENDUM www.ti.com 2-May-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 5962-86806012A ACTIVE LCCC FK 20 1 TBD 5962-8680601EA ACTIVE CDIP J 16 1 TBD POST-PLATE Level-NC-NC-NC A42 SNPB Level-NC-NC-NC 5962-8680601V2A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC 5962-8680601VEA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC UC1846J ACTIVE CDIP J 16 1 TBD A42 SNPB Level-NC-NC-NC UC1846J/80257 OBSOLETE CDIP J 16 TBD Call TI Call TI UC1846J/80364 OBSOLETE CDIP J 16 TBD Call TI Call TI UC1846J/80619 OBSOLETE CDIP J 16 TBD Call TI Call TI TBD A42 SNPB TBD Call TI UC1846J883B ACTIVE CDIP J 16 UC1846JQMLV ACTIVE CDIP J 16 1 UC1846L883B ACTIVE LCCC FK 20 UC1846LQMLV ACTIVE LCCC FK 20 TBD Call TI Call TI UC1847J OBSOLETE CDIP J 16 TBD Call TI Call TI UC1847J883B OBSOLETE CDIP J 16 TBD Call TI Call TI 1 TBD Level-NC-NC-NC Call TI POST-PLATE Level-NC-NC-NC UC1847L OBSOLETE LCCC FK 20 TBD Call TI Call TI UC1847L883B OBSOLETE LCCC FK 20 TBD Call TI Call TI UC2846DW ACTIVE SOIC DW 16 40 TBD CU NIPDAU Level-2-220C-1 YEAR UC2846DWTR ACTIVE SOIC DW 16 2000 TBD CU NIPDAU Level-2-220C-1 YEAR UC2846J ACTIVE CDIP J 16 1 TBD A42 SNPB Level-NC-NC-NC UC2846N ACTIVE PDIP N 16 25 TBD CU NIPDAU Level-NA-NA-NA UC2846Q ACTIVE PLCC FN 20 46 TBD Call TI Level-2-220C-1 YEAR UC2846QTR ACTIVE PLCC FN 20 1000 TBD Call TI Level-2-220C-1 YEAR UC2847DW ACTIVE SOIC DW 16 40 TBD CU NIPDAU Level-2-220C-1 YEAR UC2847DWTR ACTIVE SOIC DW 16 2000 TBD CU NIPDAU Level-2-220C-1 YEAR UC2847N ACTIVE PDIP N 16 25 TBD CU NIPDAU Level-NA-NA-NA UC3846DW ACTIVE SOIC DW 16 40 TBD CU NIPDAU Level-2-220C-1 YEAR UC3846DWTR ACTIVE SOIC DW 16 2000 TBD CU NIPDAU Level-2-220C-1 YEAR UC3846J ACTIVE CDIP J 16 1 TBD A42 SNPB Level-NC-NC-NC UC3846N ACTIVE PDIP N 16 25 TBD CU NIPDAU Level-NA-NA-NA UC3846Q ACTIVE PLCC FN 20 46 TBD Call TI Level-2-220C-1 YEAR UC3846QTR ACTIVE PLCC FN 20 1000 TBD Call TI Level-2-220C-1 YEAR UC3847DW ACTIVE SOIC DW 16 40 TBD CU NIPDAU Level-2-220C-1 YEAR UC3847DWTR ACTIVE SOIC DW 16 2000 TBD CU NIPDAU Level-2-220C-1 YEAR UC3847J OBSOLETE CDIP J 16 UC3847N ACTIVE PDIP N 16 25 (1) TBD Call TI TBD CU NIPDAU Call TI Level-NA-NA-NA The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 2-May-2005 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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