SN54LVC32A, SN74LVC32A QUADRUPLE 2-INPUT POSITIVE-OR GATES www.ti.com SCAS286P – JANUARY 1993 – REVISED APRIL 2005 FEATURES • • • • Operate From 1.65 V to 3.6 V Specified From –40°C to 85°C, –40°C to 125°C, and –55°C to 125°C Inputs Accept Voltages to 5.5 V Max tpd of 3.8 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y 14 1B 1A NC VCC 4B 1 SN54LVC32A . . . FK PACKAGE (TOP VIEW) 1Y NC 2A NC 2B 13 4B 2 3 4 12 4A 5 6 10 3B 9 3A 11 4Y 7 8 4 3 2 1 20 19 18 5 6 17 16 7 8 15 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A 14 2 VCC 1 3Y 1A 1B 1Y 2A 2B 2Y GND SN74LVC32A . . . RGY PACKAGE (TOP VIEW) 1A SN54LVC32A . . . J OR W PACKAGE SN74LVC32A . . . D, DB, NS, OR PW PACKAGE (TOP VIEW) • GND • • • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) NC - No internal connection DESCRIPTION/ORDERING INFORMATION The SN54LVC32A quadruple 2-input positive-OR gate is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC32A quadruple 2-input positive-OR gate is designed for 1.65-V to 3.6-V VCC operation. The 'LVC32A devices perform the Boolean function Y A B or Y A • B in positive logic. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C QFN – RGY SN74LVC32ARGYR Tube of 50 SN74LVC32AD Reel of 2500 SN74LVC32ADR Reel of 250 SN74LVC32ADT SOP – NS Reel of 2000 SN74LVC32ANSR LVC32A SSOP – DB Reel of 2000 SN74LVC32ADBR LC32A Tube of 90 SN74LVC32APW Reel of 2000 SN74LVC32APWR Reel of 250 SN74LVC32APWT CDIP – J Tube of 25 SNJ54LVC32AJ SNJ54LVC32AJ CFP – W Tube of 150 SNJ54LVC32AW SNJ54LVC32AW LCCC – FK Tube of 55 SNJ54LVC32AFK SNJ54LVC32AFK TSSOP – PW –55°C to 125°C (1) TOP-SIDE MARKING Reel of 1000 SOIC – D –40°C to 125°C ORDERABLE PART NUMBER LC32A LVC32A LC32A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1993–2005, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. SN54LVC32A, SN74LVC32A QUADRUPLE 2-INPUT POSITIVE-OR GATES www.ti.com SCAS286P – JANUARY 1993 – REVISED APRIL 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. FUNCTION TABLE (EACH GATE) INPUTS A B OUTPUT Y H X H X H H L L L LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC) A Y B Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply voltage range –0.5 6.5 UNIT V range (2) –0.5 6.5 V –0.5 VCC + 0.5 VI Input voltage VO Output voltage range (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND D package (4) 86 DB package (4) θJA Package thermal impedance 96 NS package (4) 76 PW package (4) 113 RGY package (5) Tstg Storage temperature range Ptot Power dissipation (1) (2) (3) (4) (5) (6) (7) 2 °C/W 47 –65 TA = –40°C to 125°C (6) (7) V 150 °C 500 mW Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. The package thermal impedance is calculated in accordance with JESD 51-5. For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K. For the DB, DGV, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K. SN54LVC32A, SN74LVC32A QUADRUPLE 2-INPUT POSITIVE-OR GATES www.ti.com SCAS286P – JANUARY 1993 – REVISED APRIL 2005 Recommended Operating Conditions (1) SN54LVC32A –55 TO 125°C Operating VCC Supply voltage VIH High-level input voltage VCC = 2.7 V to 3.6 V VIL Low-level input voltage VCC = 2.7 V to 3.6 V VI Input voltage VO Output voltage Data retention only IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate (1) MIN MAX 2 3.6 1.5 2 UNIT V V 0.8 V 0 5.5 V 0 VCC V VCC = 2.7 V –12 VCC = 3 V –24 VCC = 2.7 V 12 VCC = 3 V 24 7 mA mA ns/V All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Recommended Operating Conditions (1) SN74LVC32A TA = 25°C VCC Supply voltage VIH High-level input voltage Low-level input voltage VIL Operating Data retention only VCC = 1.65 V to 1.95 V –40 TO 85°C –40 TO 125°C UNIT MIN MAX MIN MAX MIN MAX 1.65 3.6 1.65 3.6 1.65 3.6 1.5 1.5 1.5 0.65 × VCC 0.65 × VCC 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 1.7 1.7 VCC = 2.7 V to 3.6 V 2 VCC = 1.65 V to 1.95 V 2 V V 2 0.35 × VCC 0.35 × VCC 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 0.7 0.7 VCC = 2.7 V to 3.6 V 0.8 0.8 0.8 V VI Input voltage 0 5.5 0 5.5 0 5.5 V VO Output voltage 0 VCC 0 VCC 0 VCC V VCC = 1.65 V ∆t/∆v (1) –4 –8 –8 –8 VCC = 2.7 V –12 –12 –12 VCC = 3 V –24 –24 –24 VCC = 1.65 V 4 4 4 VCC = 2.3 V 8 8 8 VCC = 2.7 V 12 12 12 VCC = 3 V 24 24 24 Input transition rise or fall rate 7 7 7 Low-level output current IOL –4 VCC = 2.3 V High-level output current IOH –4 mA mA ns/V All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 SN54LVC32A, SN74LVC32A QUADRUPLE 2-INPUT POSITIVE-OR GATES www.ti.com SCAS286P – JANUARY 1993 – REVISED APRIL 2005 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) SN54LVC32A PARAMETER TEST CONDITIONS VCC –55 TO 125°C UNIT MIN MAX IOH = –100 µA VOH VOL 2.7 V to 3.6 V 2.2 3V 2.4 IOH = –24 mA 3V 2.2 IOL = 100 µA 2.7 V to 3.6 V 0.2 IOL = 12 mA 2.7 V 0.4 3V 0.55 IOH = –12 mA IOL = 24 mA II ICC ∆ICC VCC – 0.2 2.7 V V V VI = 5.5 V or GND 3.6 V ±5 µA VI = VCC or GND, IO = 0 3.6 V 10 µA 2.7 V to 3.6 V 500 µA One input at VCC – 0.6 V, Other inputs at VCC or GND Electrical Characteristics over operating free-air temperature range (unless otherwise noted) SN74LVC32A PARAMETER TEST CONDITIONS VCC TA = 25°C MIN IOH = –100 µA VOH 1.65 V to 3.6 V II ICC ∆ICC Ci –40 TO 85°C MAX MIN –40 TO 125°C MAX MIN VCC – 0.2 VCC – 0.2 VCC – 0.3 1.65 V 1.29 1.2 1.05 IOH = –8 mA 2.3 V 1.9 1.7 1.55 2.7 V 2.2 2.2 2.05 3V 2.4 2.4 2.25 IOH = –24 mA 3V 2.3 IOL = 100 µA 1.65 V to 3.6 V 0.1 0.2 0.3 IOL = 4 mA 1.65 V 0.24 0.45 0.6 IOL = 8 mA 2.3 V 0.3 0.7 0.85 IOL = 12 mA 2.7 V 0.4 0.4 0.6 IOL = 24 mA 3V 0.55 0.55 0.8 2.2 UNIT MAX IOH = –4 mA IOH = –12 mA VOL TYP V 2 V VI = 5.5 V or GND 3.6 V ±1 ±5 ±20 µA VI = VCC or GND, IO = 0 3.6 V 1 10 40 µA 500 500 5000 µA One input at VCC – 0.6 V, Other inputs at VCC or GND VI = VCC or GND 2.7 V to 3.6 V 3.3 V 5 pF Switching Characteristics over operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVC32A PARAMETER FROM (INPUT) TO (OUTPUT) VCC –55 TO 125°C MIN tpd 4 A or B Y 2.7 V 3.3 V ± 0.3 V 4.4 1 UNIT MAX 3.8 ns SN54LVC32A, SN74LVC32A QUADRUPLE 2-INPUT POSITIVE-OR GATES www.ti.com SCAS286P – JANUARY 1993 – REVISED APRIL 2005 Switching Characteristics over operating free-air temperature range (unless otherwise noted) (see Figure 1) SN74LVC32A PARAMETER tpd FROM (INPUT) A or B TO (OUTPUT) Y tsk(o) VCC TA = 25°C –40 TO 85°C –40 TO 125°C MIN TYP MAX MIN MAX MIN MAX 1.8 V ± 0.15 V 1 4.2 8.2 1 8.7 1 10.2 2.5 V ± 0.2 V 1 2.6 4.9 1 5.4 1 6.9 2.7 V 1 3 4.2 1 4.4 1 5.5 3.3 V ± 0.3 V 1 2.5 3.6 1 3.8 1 3.3 V ± 0.3 V 1 UNIT ns 5 1.5 ns Operating Characteristics TA = 25°C PARAMETER Cpd Power dissipation capacitance per gate TEST CONDITIONS f = 10 MHz VCC TYP 1.8 V 7.5 2.5 V 10.6 3.3 V 12.5 UNIT pF 5 SN54LVC32A, SN74LVC32A QUADRUPLE 2-INPUT POSITIVE-OR GATES www.ti.com SCAS286P – JANUARY 1993 – REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH - V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 PACKAGE OPTION ADDENDUM www.ti.com 25-Jan-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 5962-9761801Q2A ACTIVE LCCC FK 20 1 TBD 5962-9761801QCA ACTIVE CDIP J 14 1 TBD 5962-9761801QDA ACTIVE CFP W 14 1 SN74LVC32AD ACTIVE SOIC D 14 50 SN74LVC32ADBLE OBSOLETE SSOP DB 14 SN74LVC32ADBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32ADE4 ACTIVE SOIC D 14 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32ADT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32ADTE4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32ANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32ANSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32APW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32APWLE OBSOLETE TSSOP PW 14 TBD Call TI SN74LVC32APWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32APWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32APWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32APWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC32ARGYR ACTIVE QFN RGY 14 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SN74LVC32ARGYRG4 ACTIVE QFN RGY 14 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR A42 SNPB N / A for Pkg Type TBD A42 N / A for Pkg Type Green (RoHS & no Sb/Br) CU NIPDAU TBD 50 Addendum-Page 1 POST-PLATE N / A for Pkg Type Call TI Level-1-260C-UNLIM Call TI Call TI PACKAGE OPTION ADDENDUM www.ti.com 25-Jan-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SNJ54LVC32AFK ACTIVE LCCC FK 20 1 TBD SNJ54LVC32AJ ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type SNJ54LVC32AW ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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