Revised April 2001 74LCX16841 Low Voltage 20-Bit Transparent Latch with 5V Tolerant Inputs and Outputs General Description Features The LCX16841 contains twenty non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. ■ 5V tolerant inputs and outputs The LCX16841 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX16841 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. ■ 2.3V–3.6V VCC specifications provided ■ 5.5 ns tPD max (VCC = 3.3V), 20 µA ICC max ■ Power down high impedance inputs and outputs ■ Supports live insertion/withdrawal (Note 1) ■ ±24 mA output drive (VCC = 3.0V) ■ Implements patented noise/EMI reduction circuitry ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human body model > 2000V Machine model > 200V Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number 74LCX16841MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Description 74LCX16841MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names Description OEn Output Enable Input (Active LOW) LEn Latch Enable Input D0–D19 Inputs O0–O19 Outputs © 2001 Fairchild Semiconductor Corporation DS012578 www.fairchildsemi.com 74LCX16841 Low Voltage 20-Bit Transparent Latch with 5V Tolerant Inputs and Outputs October 1995 74LCX16841 Connection Diagram Truth Tables Inputs Outputs LE1 OE1 D0–D9 O0–O9 X H X Z H L L L H L H H L L X O0 Inputs Outputs LE2 OE2 D10–D19 O10–O19 X H X Z H L L L H L H H L L X O0 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Functional Description its D input changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3-STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. The LCX16841 contains twenty D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 20-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the latches. In this condition the latches are transparent, i.e. a latch output will change states each time Logic Diagrams Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Symbol Parameter Value VCC Supply Voltage −0.5 to +7.0 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Conditions Units V V Output in 3-STATE −0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 3) IIK DC Input Diode Current −50 VI < GND IOK DC Output Diode Current −50 VO < GND +50 VO > VCC V mA mA IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current per Supply Pin ±100 mA IGND DC Ground Current per Ground Pin ±100 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions (Note 4) Symbol VCC Parameter VI Input Voltage VO Output Voltage IOH/IOL Min Max Operating 2.0 3.6 Data Retention 1.5 3.6 Supply Voltage Output Current TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V − 2.0V, VCC = 3.0V 0 5.5 HIGH or LOW State 0 VCC 3-STATE 0 5.5 VCC = 3.0V − 3.6V ±24 VCC = 2.7V − 3.0V ±12 VCC = 2.3V − 2.7V ±8 Units V V V mA −40 85 °C 0 10 ns/V Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 3: IO Absolute Maximum Rating must be observed. Note 4: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH VOL Parameter Conditions HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage IOH = −100 µA VCC TA = −40°C to +85°C (V) Min 2.3 − 2.7 1.7 2.7 − 3.6 2.0 Max Units V 2.3 − 2.7 0.7 2.7 − 3.6 0.8 2.3 − 3.6 VCC − 0.2 IOH = −8 mA 2.3 1.8 IOH = −12 mA 2.7 2.2 IOH = −18 mA 3.0 2.4 IOH = −24 mA 3.0 2.2 IOL = 100 µA 2.3 − 3.6 0.2 IOL = 8 mA 2.3 0.6 IOL = 12 mA 2.7 0.4 IOL = 16 mA 3.0 0.4 V V V IOL = 24 mA 3.0 0.55 II Input Leakage Current 0 ≤ VI ≤ 5.5V 2.3 − 3.6 ±5.0 µA IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 5.5V 2.3 − 3.6 ±5.0 µA 0 10 µA VI = VIH or VIL IOFF Power-Off Leakage Current VI or VO = 5.5V 3 www.fairchildsemi.com 74LCX16841 Absolute Maximum Ratings(Note 2) 74LCX16841 DC Electrical Characteristics Symbol Parameter (Continued) TA = −40°C to +85°C VCC Conditions (V) ICC ∆ICC Quiescent Supply Current Increase in ICC per Input Min Units Max VI = VCC or GND 2.3 − 3.6 20 3.6V ≤ VI, VO ≤ 5.5V (Note 5) 2.3 − 3.6 ±20 VIH = VCC −0.6V 2.3 − 3.6 500 µA µA Note 5: Outputs disabled or 3-STATE only. AC Electrical Characteristics TA = −40°C to +85°C, RL = 500Ω Symbol Parameter VCC = 3.3V ± 0.3V V CC = 2.7V VCC = 2.5V ± 0.2V CL = 50 pF CL = 50 pF CL = 30 pF Min Max Min Max Min Max tPHL Propagation Delay 1.5 5.5 1.5 6.0 1.5 6.6 tPLH Dn to On 1.5 5.5 1.5 6.0 1.5 6.6 tPHL Propagation Delay 1.5 5.5 1.5 6.5 1.5 6.6 tPLH LE to On 1.5 5.5 1.5 6.5 1.5 6.6 tPZL Output Enable Time 1.5 6.5 1.5 7.0 1.5 8.5 1.5 6.5 1.5 7.0 1.5 8.5 1.5 6.5 1.5 7.0 1.5 7.8 1.5 6.5 1.5 7.0 1.5 7.8 tPZH tPLZ Output Disable Time tPHZ tOSHL Output to Output Skew (Note 6) 1.0 tOSLH Units ns ns ns ns ns 1.0 tS Setup Time, Dn to LE 2.5 2.5 3.0 ns tH Hold Time, Dn to LE 1.5 1.5 2.0 ns tW LE Pulse Width 3.3 3.3 3.8 ns Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions VCC TA = 25°C (V) Typical CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.8 CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 0.6 CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 −0.8 CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 −0.6 Units V V Capacitance Typical Units CIN Symbol Input Capacitance Parameter VCC = Open, V I = 0V or VCC 7 pF CO Output Capacitance VCC = 3.3V, V I = 0V or VCC 8 pF CPD Power Dissipation Capacitance VCC = 3.3V, V I = 0V or VCC, f = 10 MHz 20 pF www.fairchildsemi.com Conditions 4 74LCX16841 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V VCC x 2 at VCC = 2.5 ± 0.2V tPZH,tPHZ GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic trise and tfall 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Symbol VCC 3.3V ± 0.3V 2.7V 2.5V ± 0.2V Vmi 1.5V 1.5V VCC/2 Vmo 1.5V 1.5V VCC/2 Vx VOL + 0.3V VOL + 0.3V VOL + 0.15V Vy VOH − 0.3V VOH − 0.3V VOH − 0.15V 5 www.fairchildsemi.com 74LCX16841 Schematic Diagram Generic for LCX Family www.fairchildsemi.com 6 74LCX16841 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A 7 www.fairchildsemi.com 74LCX16841 Low Voltage 20-Bit Transparent Latch with 5V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8