Revised March 2001 74LCX16501 Low Voltage 18-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs General Description Features The LCX16501 is an 18-bit universal bus transceiver combining D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. ■ 5V tolerant inputs and outputs Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The LCX16501 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX16501 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power. ■ 2.3V–3.6V VCC specifications provided ■ 6.0 ns tPD max (VCC = 3.3V), 20 µA ICC max ■ Power down high impedance inputs and outputs ■ Supports live insertion/withdrawal (Note 1) ■ ±24 mA Output Drive (VCC = 3.0V) ■ Implements patented noise/EMI reduction circuitry ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human body model > 2000V Machine model < 200V Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC and OE tied to GND through a resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number 74LCX16501MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Description 74LCX16501MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2001 Fairchild Semiconductor Corporation DS012550 www.fairchildsemi.com 74LCX16501 Low Voltage 18-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs October 1995 74LCX16501 Connection Diagram Truth Table (Note 2) Inputs Output OEAB LEAB CLKAB An Bn L X X X Z H H X L L H H X H H H L ↑ L L H L ↑ H H H L H X B0 (Note 3) H L L X B0 (Note 4) Note 2: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. Note 3: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. Note 4: Output level before the indicated steady-state input conditions were established. Functional Description OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high impedance state. For A-to-B data flow, the LCX16501 operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is LOW, the A bus data is stored in the latch/ flip-flop on the LOW-to-HIGH transition of CLKAB. When Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active HIGH and OEBA is active LOW). Logic Diagram www.fairchildsemi.com 2 Symbol Parameter Value VCC Supply Voltage −0.5 to +7.0 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Conditions Units V V Output in 3-STATE −0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 6) IIK DC Input Diode Current −50 VI < GND IOK DC Output Diode Current −50 VO < GND +50 VO > VCC V mA mA IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current per Supply Pin ±100 mA IGND DC Ground Current per Ground Pin ±100 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions (Note 7) Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage IOH/IOL Output Current TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Min Max Operating 2.0 3.6 Data Retention 1.5 3.6 0 5.5 HIGH or LOW State 0 VCC 3-STATE 0 5.5 VCC = 3.0V − 3.6V ±24 VCC = 2.7V − 3.0V ±12 VCC = 2.3V − 2.7V ±8 Units V V V mA −40 85 °C 0 10 ns/V Note 5: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 6: IO Absolute Maximum Rating must be observed. Note 7: Unused (inputs or I/Os) must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH VOL Parameter Conditions HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage IOH = −100 µA VCC TA = −40°C to +85°C (V) Min 2.3 − 2.7 1.7 2.7 − 3.6 2.0 Max V 2.3 − 2.7 0.7 2.7 − 3.6 0.8 2.3 − 3.6 VCC − 0.2 IOH = −8 mA 2.3 1.8 IOH = −12 mA 2.7 2.2 IOH = −18 mA 3.0 2.4 IOH = −24 mA 3.0 2.2 IOL = 100 µA 2.3 − 3.6 0.2 IOL = 8 mA 2.3 0.6 IOL = 12 mA 2.7 0.4 IOL = 16 mA 3.0 0.4 IOL = 24 mA 3.0 0.55 Input Leakage Current 0 ≤ VI ≤ 5.5V 2.3 − 3.6 ±5.0 IOZ 3-STATE I/O Leakage 0 ≤ VO ≤ 5.5V 2.3 − 3.6 ±5.0 0 10 VI = V IH or VIL Power-Off Leakage Current VI or VO = 5.5V 3 V V II IOFF Units V µA µA µA www.fairchildsemi.com 74LCX16501 Absolute Maximum Ratings(Note 5) 74LCX16501 DC Electrical Characteristics Symbol Parameter (Continued) TA = −40°C to +85°C VCC Conditions (V) ICC ∆ICC Quiescent Supply Current Increase in ICC per Input Min Units Max VI = VCC or GND 2.3 − 3.6 20 3.6V ≤ VI, VO ≤ 5.5V (Note 8) 2.3 − 3.6 ±20 VIH = VCC −0.6V 2.3− 3.6 500 µA µA Note 8: Outputs disabled or 3-STATE only. AC Electrical Characteristics TA = −40°C to +85°C, RL = 500Ω Symbol Parameter VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V CL = 50 pF CL = 50 pF CL = 30 pF Min Max Min Max Min Max 1.5 6.0 1.5 7.0 1.5 7.2 1.5 6.0 1.5 7.0 1.5 7.2 fMAX Maximum Clock Frequency 170 tPHL Propagation Delay tPLH Bus to Bus MHz tPHL Propagation Delay 1.5 6.7 1.5 8.0 1.5 8.4 tPLH Clock to Bus 1.5 6.7 1.5 8.0 1.5 8.4 tPHL Propagation Delay 1.5 7.0 1.5 8.0 1.5 8.4 tPLH LE to Bus 1.5 7.0 1.5 8.0 1.5 8.4 tPZL Output Enable Time 1.5 7.2 1.5 8.2 1.5 9.4 1.5 7.2 1.5 8.2 1.5 9.4 tPZH tPLZ Output Disable Time tPHZ Units 1.5 7.0 1.5 8.0 1.5 8.4 1.5 7.0 1.5 8.0 1.5 8.4 ns ns ns ns ns tS Setup Time 2.5 2.5 3.0 ns tH Hold Time 1.5 1.5 2.0 ns tW Pulse Width 3.0 3.0 3.5 ns tOSHL Output to Output Skew 1.0 tOSLH (Note 9) 1.0 ns Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH). Dynamic Switching Characteristics Symbol VOLP VOLV VCC TA = 25°C (V) Typical CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.8 CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 0.6 CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 −0.8 CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 −0.6 Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions Units V V Capacitance Typical Units CIN Symbol Input Capacitance Parameter VCC = Open, VI = 0V or VCC 7 pF CI/O Input/Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 20 pF www.fairchildsemi.com Conditions 4 74LCX16501 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V VCC x 2 at VCC = 2.5 ± 0.2V tPZH,tPHZ GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic trise and tfall 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Symbol VCC 3.3V ± 0.3V 2.7V 2.5V ± 0.2V Vmi 1.5V 1.5V VCC/2 Vmo 1.5V 1.5V VCC/2 Vx VOL + 0.3V VOL + 0.3V VOL + 0.15V Vy VOH − 0.3V VOH − 0.3V VOH − 0.15V 5 www.fairchildsemi.com 74LCX16501 Schematic Diagram Generic for LCX Family www.fairchildsemi.com 6 74LCX16501 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A 7 www.fairchildsemi.com 74LCX16501 Low Voltage 18-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8