TC7135 4-1/2 Digit A/D Converter Features General Description • • • • • • • • The TC7135 4-1/2 digit A/D Converter (ADC) offers 50 ppm (1 part in 20,000) resolution with a maximum nonlinearity error of 1 count. An auto-zero cycle reduces zero error to below 10 µV and zero drift to 0.5 µV/°C. Source impedance errors are minimized by a 10 pA maximum input current. Rollover error is limited to ±1 count. • • • • • Low Rollover Error: ±1 Count Max Nonlinearity Error: ±1 Count Max Reading for 0V Input True Polarity Indication at Zero for Null Detection Multiplexed BCD Data Output TTL-Compatible Outputs Differential Input Control Signals Permit Interface to UARTs and Microprocessors Blinking Display Visually Indicates Overrange Condition Low Input Current: 1 pA Low Zero Reading Drift: 2 µV/°C Auto-Ranging Supported with Overrange and Underrange Signals Available in PDIP and Surface-Mount Packages Microprocessor-based measurement systems are supported by the BUSY, STROBE and RUN/HOLD control signals. Remote data acquisition systems with data transfer via UARTs are also possible. The additional control pins and multiplexed BCD outputs make the TC7135 the ideal converter for display or microprocessor-based measurement systems. Applications • Precision Analog Signal Processor • Precision Sensor Interface • High Accuracy DC Measurements Functional Block Diagram Set VREF = 1V VREF IN 100 kΩ 5V TC7135 1 2 V– UNDERRANGE REF IN OVERRANGE 3 ANALOG STROBE COMMON Analog GND 4 RUN/HOLD INT OUT 1 µF 0.47 µF 5 DIGTAL GND AZ IN 6 BUFF OUT POLARITY 100 kΩ 7 CLOCK IN C – Signal 1 µF 8 REF 100 kΩ BUSY Input CREF+ 9 (LSD) D1 –INPUT 0.1 µF 10 D2 +INPUT 11 D3 +5V V+ 12 D4 D5 (MSD) 13 (MSB) B8 B1 (LSB) 14 B4 B2 2004 Microchip Technology Inc. 28 27 26 25 24 23 22 21 Clock Input 120 kHz 20 19 18 17 16 15 DS21460C-page 1 TC7135 Package Types AZ IN 5 25 RUN/HOLD BUFF OUT 6 TC7135 REF CAP+ 8 NC 35 22 CLOCK IN STROBE 36 –INPUT 9 21 BUSY 20 D1 (LSD) V+ 11 NC NC D2 D1 BUSY CLOCK IN POLARITY 20 D3 19 D4 18 B8 V– 39 TC7135 REF IN 40 D3 D4 (MSB) B8 B4 B2 21 NC UNDERRANGE 38 12 13 14 15 16 17 18 (LSB) B1 22 NC OVERRANGE 37 19 D2 (MSD) D5 DIGITAL GND NC 34 23 POLARITY +INPUT 10 RUN/HOLD 33 32 31 30 29 28 27 26 25 24 23 24 DIGTAL GND REF CAP– 7 NC NC 2 44-Pin MQFP STROBE 1 28 27 26 3 OR V– 4 UR INT OUT ANALOG COM REF IN 28-Pin PLCC 17 B4 16 B2 COMMON ANALOG 41 15 B1 NC 42 14 D5 NC 43 13 NC NC 44 BUFF OUT CREF– 5 6 7 CREF+ 8 –INPUT 9 TC7135 NC NC V+ +INPUT –INPUT CREF+ CREF– INT OUT 9 10 11 NC NC NC D2 D1 BUSY 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 24 DIGiTAL GND 23 POLARITY NC 2 47 NC NC 3 46 NC NC 4 45 D3 NC 5 44 D4 NC 6 43 B8 22 CLOCK IN 21 BUSY 20 D1 (LSD) 19 D2 V+ 11 18 D3 (MSD) D5 12 17 D4 B2 14 8 NC 1 +INPUT 10 (LSB) B1 13 CLOCK IN 25 RUN/HOLD AZ IN 7 6 5 NC 4 POL 26 STROBE DGND 27 OVERRANGE 3 RUN/HOLD 2 STROBE REF IN NC 28 UNDERRANGE NC 1 NC V– ANALOG COM INT OUT 4 64-Pin MQFP NC 28-Pin PDIP 3 BUFF OUT 2 AZ IN 1 NC 12 NC 16 B8 (MSB) 15 B4 48 NC l 42 B4 OVERRANGE 7 TC7135 UNDERRANGE 8 41 B2 NC 9 40 NC V– 10 39 B1 REF IN 11 38 D5 ANALOG COM 12 37 NC NC 13 36 NC NC 14 35 NC NC 15 34 NC NC 16 33 NC DS21460C-page 2 V+ NC +INPUT NC –INPUT NC NC CREF+ NC CREF– BUFF OUT NC AZ IN NC NC NOTE: NC = No internal connection. INT OUT 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2004 Microchip Technology Inc. TC7135 1.0 ELECTRICAL SPECIFICATIONS † Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings† Positive Supply Voltage.....................................................+6V Negative Supply Voltage ...................................................- 9V Analog Input Voltage (Pin 9 or 10) ...............V+ to V- (Note 2) Reference Input Voltage (Pin 2) ................................. V+ to VClock Input Voltage ................................................... 0V to V+ Operating Temperature Range .......................... 0°C to +70°C Storage Temperature Range ........................ –65°C to +150°C Package Power Dissipation; (TA ≤ 70°C) 28-Pin PDIP .......................................................... 1.14Ω 28-Pin PLCC ......................................................... 1.00Ω 44-Pin MQFP.......................................................................... 64-Pin MQFP ........................................................ 1.14Ω DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, TA = +25°C, FCLOCK = 120 kHz, V+ = +5V, V- = -5V. (see Functional Block Diagram). Parameters Sym Min. Typ. Max. Units -0.0000 ±0.0000 +0.0000 Display Reading Conditions Analog Display Reading with Zero Volt Input Note 2, Note 3 Zero Reading Temperature Coefficient TCZ — 0.5 2 µV/°C Full Scale Temperature Coefficient TCFS — — 5 ppm/°C NL — 0.5 1 Count Note 6 DNL — 0.01 — LSB Note 6 Nonlinearity Error Differential Linearity Error Display Reading in Ratiometric Operation ± Full Scale Symmetry Error (Rollover Error) +0.9996 ±FSE — Input Leakage Current IIN Noise eN +0.9999 +1.0000 VIN = 0V, (Note 4) VIN = 2V, (Note 4, Note 5) Display Reading VIN = VREF, (Note 2) Count -VIN = +VIN, (Note 7) 0.5 1 — 1 10 pA — 15 — µVP-P IIL — 10 100 µA VIN = 0V Input High Current IIH — 0.08 10 µA VIN = +5V Output Low Voltage VOL — 0.2 0.4 V IOL = 1.6 mA Output High Voltage; VOH 2.4 4.4 5 V IOH = 1 mA 4.9 4.99 5 V IOH = 10 µA 0 200 1200 kHz Note 3 Peak-to-Peak Value not Exceeded 95% of Time Digital Input Low Current B1, B2, B4, B8, D1 –D5 Busy, Polarity, Overrange, Underrange, Strobe Clock Frequency Note 1: 2: 3: 4: 5: 6: 7: 8: FCLK Note 8 Limit input current to under 100 µA if input voltages exceed supply voltage. Full-scale voltage = 2V VIN = 0V 30°C ≤ TA ≤ +70°C External reference temperature coefficient less than 0.01 ppm/°C. -2V ≤ VIN ≤ +2V. Error of reading from best fit straight line. IVIN| = 1.9959 Specification related to clock frequency range over which the TC7135 correctly performs its various functions. Increased errors result at higher operating frequencies. 2004 Microchip Technology Inc. DS21460C-page 3 TC7135 DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, TA = +25°C, FCLOCK = 120 kHz, V+ = +5V, V- = -5V. (see Functional Block Diagram). Parameters Sym Min. Typ. Max. Units Conditions Positive Supply Voltage V+ 4 5 6 V Negative Supply Voltage V- -3 -5 -8 V Positive Supply Current I+ — 1 3 mA FCLK = 0 Hz Negative Supply Current I- — 0.7 3 mA FCLK = 0 Hz PD — 8.5 30 mW FCLK = 0 Hz Power Supply Power Dissipation Note 1: 2: 3: 4: 5: 6: 7: 8: Limit input current to under 100 µA if input voltages exceed supply voltage. Full-scale voltage = 2V VIN = 0V 30°C ≤ TA ≤ +70°C External reference temperature coefficient less than 0.01 ppm/°C. -2V ≤ VIN ≤ +2V. Error of reading from best fit straight line. IVIN| = 1.9959 Specification related to clock frequency range over which the TC7135 correctly performs its various functions. Increased errors result at higher operating frequencies. DS21460C-page 4 2004 Microchip Technology Inc. TC7135 2.0 PIN DESCRIPTIONS The description of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Number 28-Pin PDIP, 28-Pin PLCC Pin Number 44-Pin MQFP* Pin Number 64-Pin MQFP* 1 39 10 V– 2 40 11 REF IN 3 41 12 ANALOG COMMON 4 2 18 INT OUT 5 3 20 AZ IN 6 4 22 BUFF OUT 7 5 23 CREF– Reference capacitor input. Reference capacitor negative connection. 8 6 26 CREF+ Reference capacitor input. Reference capacitor positive connection. 9 7 28 –INPUT Analog input. Analog input negative connection. 10 8 30 +INPUT Analog input. Analog input positive connection. 11 9 32 V+ Positive power supply input. 12 14 38 D5 Digit drive output. Most Significant Digit (MSD) 13 15 39 B1 Binary Coded Decimal (BCD) output. Least Significant bit (LSb). 14 16 41 B2 BCD output. 15 17 42 B4 BCD output. 16 18 43 B8 BCD output. Most Significant bit (MSb). 17 19 44 D4 Digit drive output. 18 20 45 D3 Digit drive output. 19 25 52 D2 Digit drive output. 20 26 53 D1 Digit drive output. Least Significant Digit (LSD). 21 27 54 BUSY 22 28 55 CLOCK IN Clock input. Conversion clock connection. 23 29 57 POLARITY Polarity output. A positive input is indicated by a logic high output. The polarity output is valid at the beginning of the reference integrate phase and remains valid until determined during the next conversion. 24 30 58 DGND 25 31 59 RUN/HOLD Run/Hold input. When at a logic high, conversions are performed continuously. A logic low holds the current data as long as the low condition exists. 26 36 60 STROBE Strobe output. The STROBE output pulses low in the center of the digit drive outputs. 27 37 7 OVERRANGE Overrange output. A logic high indicates that the analog input exceeds the full-scale input range. 28 38 8 UNDERRANGE Underrange output. A logic high indicates that the analog input is less than 9% of the full-scale input range. Symbol Description Negative power supply input. External reference input. Reference point for REF IN. Integrator output. Integrator capacitor connection. Auto-zero inpt. Auto-zero capacitor connection. Analog input buffer output. Integrator resistor connection. Busy output. At the beginning of the signal-integration phase, BUSY goes high and remains high until the first clock pulse after the integrator zero crossing. Digital logic reference input. * Pins not identified or documented are NC (no connects). 2004 Microchip Technology Inc. DS21460C-page 5 TC7135 3.0 DETAILED DESCRIPTION All pin designations refer to the 28-pin PDIP package. 3.1 Dual-Slope Conversion Principles The TC7135 is a dual-slope, integrating A/D converter. An understanding of the dual-slope conversion technique will aid in following the detailed TC7135 operational theory. The conventional dual-slope converter measurement cycle has two distinct phases: 1. 2. Input signal integration. Reference voltage integration (de-integration). The dual-slope converter accuracy is unrelated to the integrating resistor and capacitor values, as long as they are stable during a measurement cycle. An inherent benefit is noise immunity. Noise spikes are integrated, or averaged, to zero during the integration periods. Integrated ADCs are immune to the large conversion errors that plague successive approximation converters in high-noise environments (see Figure 3-1). Analog Input Signal + REF Voltage Integrator Output 3.2 Reference voltage Signal integration time (fixed) TDEINT = Reference voltage integration time (variable) Clock Control Logic Counter ≈ VREF ≈ 1/2 VREF Variable Reference Integrate Time FIGURE 3-1: Where: = Polarity Control VIN VIN Fixed Signal Integrate Time EQUATION 3-1: = Phase Control Display A simple mathematical equation relates the input signal, reference voltage and integration time: VREF T DEINT 1 - T INT ----------------------V IN ( T )DT = -------------------------------∫ RINT C INT 0 RINT C INT + Switch Drive In a simple dual-slope converter, a complete conversion requires the integrator output to “ramp-up” and “ramp-down”. TINT Comparator - The input signal being converted is integrated for a fixed time period. Time is measured by counting clock pulses. An opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The reference integration time is directly proportional to the input signal. VREF Integrator Basic Dual-Slope Converter. TC7135 Operational Theory The TC7135 incorporates a system zero phase and integrator output voltage zero phase to the normal twophase dual-slope measurement cycle. Reduced system errors, fewer calibration steps and a shorter overrange recovery time result. For a constant VIN: The TC7135 measurement cycle contains four phases: 1. 2. 3. 4. EQUATION 3-2: V REF T DEINT V IN = -------------------------------T INT System zero. Analog input signal integration. Reference voltage integration. Integrator output zero. Internal analog gate status for each phase is shown in Figure 3-1. TABLE 3-1: INTERNAL ANALOG GATE STATUS Conversion Cycle Phase System Zero SWI SWRI+ SWRI- SWZ SWR SW1 SWIZ Reference Figures — — — Closed Closed Closed — Figure 3-2 Closed — — — — — — Figure 3-3 Reference Voltage Integration — Closed* — — — Closed — Figure 3-4 Integrator Output Zero — — — — — Closed Closed Figure 3-5 Input Signal Integration * Assumes a positive polarity input signal. SWRI would be closed for a negative input signal. DS21460C-page 6 2004 Microchip Technology Inc. TC7135 3.2.3 Analog Input Buffer RINT + – SWI Analog Common SWI IN – + SWZ SW1 FIGURE 3-2: 3.2.2 [ Differential Input ] Reading = 10, 000 ----------------------------------------------VREF +IN REF IN Integrator – To Digital Section Switch Open Switch Closed System Zero Phase. ANALOG INPUT SIGNAL INTEGRATION The TC7135 integrates the differential voltage between the +INPUT and -INPUT pins. The differential voltage must be within the device Common mode range; -1V from either supply rail, typically. The input signal polarity is determined at the end of this phase. Analog Common SWI IN SWZ SW1 FIGURE 3-4: Integration Cycle. 3.2.4 Analog Common SWI IN FIGURE 3-3: Phase. SWRI- SWIZ SWZ Comparator + + – To Integrator Digital Section – SWZ SW1 Switch Open Switch Closed CREF SWR SWZ SWRI+ SWRIREF IN Analog Common SWI IN FIGURE 3-5: Phase. CINT CSZ SWRI- SWRI+ SWRISWZ SWRI+ REF IN CREF SWR Reference Voltage Analog Input Buffer RINT + – SWI CINT CSZ Switch Open Switch Closed This phase ensures the integrator output is at 0V when the system zero phase is entered. It also ensures that the true system offset voltages are compensated for. This phase normally lasts 100 to 200 clock cycles. If an overrange condition exists, the phase is extended to 6200 clock cycles (see Figure 3-5). SWRI+ SWI +IN Comparator – + + To Integrator – Digital Section INTEGRATOR OUTPUT ZERO +IN Analog Input Buffer RINT + – CINT CSZ SWIZ SWZ CREF SWR SWZ Comparator + Analog Input Buffer RINT + – SWI CSZ SWRI- SWZ CINT SWIZ SWZ CREF SWR SWRI+ REF IN SWRI+ SWRI- +IN EQUATION 3-3: SWRI+ The external input signal is disconnected from the internal circuitry by opening the two SWI switches. The internal input points connect to the ANALOG COMMON pin. The reference capacitor charges to the reference voltage potential through SWR. A feedback loop, closed around the integrator and comparator, charges the CAZ capacitor with a voltage to compensate for buffer amplifier, integrator and comparator offset voltages (see Figure 3-2). The previously charged reference capacitor is connected with the proper polarity to ramp the integrator output back to zero (see Figure 3-4). The digital reading displayed is: SWRI- During this phase, errors due to buffer, integrator and comparator offset voltages are compensated for by charging CAZ (auto-zero capacitor) with a compensating error voltage. With a zero input voltage, the integrator output will remain at zero. REFERENCE VOLTAGE INTEGRATION SWRI- SYSTEM ZERO SWRI+ 3.2.1 SWIZ SWZ SWZ SW1 Comparator + + – To Integrator Digital Section – Switch Open Switch Closed Integrator Output Zero Input Signal Integration 2004 Microchip Technology Inc. DS21460C-page 7 TC7135 4.0 4.1 ANALOG SECTION FUNCTIONAL DESCRIPTION Differential Inputs The TC7135 operates with differential voltages (+INPUT, pin 10 and -INPUT, pin 9) within the input amplifier Common mode range, which extends from 1V below the positive supply to 1V above the negative supply. Within this Common mode voltage range, an 86 dB Common mode rejection ratio is typical. The integrator output also follows the Common mode voltage and must not be allowed to saturate. A worstcase condition exists, for example, when a large positive Common mode voltage with a near full scale negative differential input voltage is applied. The negative input signal drives the integrator positive when most of its swing has been used up by the positive Common mode voltage. For these critical applications, the integrator swing can be reduced to less than the recommended 4V full scale swing, resulting in some loss of accuracy. The integrator output can swing within 0.3V of either supply without loss of linearity. 4.2 4.3 Reference Voltage Input The reference voltage input (REF IN) must be a positive voltage with respect to ANALOG COMMON. A reference voltage circuit is shown in Figure 4-1. V+ V+ TC7135 REF IN 10 kΩ MCP1525 2.5 VREF 10 kΩ 1 µF ANALOG COMMON Analog Ground FIGURE 4-1: Reference. Using An External Analog Common Input The ANALOG COMMON pin is used as the -INPUT return during auto-zero and de-integrate. If -INPUT is different from ANALOG COMMON, a Common mode voltage exists in the system. However, this signal is rejected by the excellent CMRR of the converter. In most applications, –INPUT will be set at a fixed, known voltage (power supply common, for instance). In this application, ANALOG COMMON should be tied to the same point, thus removing the Common mode voltage from the converter. The reference voltage is referenced to ANALOG COMMON. DS21460C-page 8 2004 Microchip Technology Inc. TC7135 5.0 DIGITAL SECTION FUNCTIONAL DESCRIPTION The major digital subsystems within the TC7135 are illustrated in Figure 5-1, with timing relationships shown in Figure 5-2. The multiplexed BCD output data can be displayed on LCD or LED displays. The digital section is best described through a discussion of the control signals and data outputs. Polarity D5 MSB D4 D3 Digit Drive D2 Signal D1 13 B1 14 B2 15 B4 16 B8 LSB Data Output Multiplexer From Analog Section Latch Polarity FF Latch Latch Zero Cross Detect Latch Latch Counters Control Logic 24 DGND FIGURE 5-1: 22 Clock In 25 RUN/ HOLD 27 Overrange 28 Underrange 26 STROBE 21 Busy Digital Section Functional Diagram. 2004 Microchip Technology Inc. DS21460C-page 9 TC7135 5.2 Integrator Output During the measurement cycle, the STROBE control line is pulsed low five times. The five low pulses occur in the center of the digit drive signals (D1, D2, D3, D5) (see Figure 5-3). Signal System Integrate Reference Integrate Zero 10,000 20,001 10,001 Counts Counts (Fixed) Counts (Max) Full Measurement Cycle 40,002 Counts D5 (MSD) goes high for 201 counts when the measurement cycles end. In the center of the D5 pulse, 101 clock pulses after the end of the measurement cycle, the first STROBE occurs for one half clock pulse. After the D5 digit strobe, D4 goes high for 200 clock pulses. The STROBE then goes low 100 clock pulses after D4 goes high. This continues through the D1 digit drive pulse. Busy Overrange when Applicable Underrange when Applicable Expanded Scale Below Digit Scan D5 D4 D3 D2 D1 * First D5 of System Zero and Reference Integrate One Count Longer 100 Counts STROBE Auto-Zero Digit Scan * D5 for Overrange D4 STROBE Output Signal Integrate Reference Integrate The digit drive signals will continue to permit display scanning. STROBE pulses are not repeated until a new measurement is completed. The digit drive signals will not continue if the previous signal resulted in an overrange condition. The active-low STROBE pulses aid BCD data transfer to UARTs, processors and external latches. For more information, please refer to Application Note 784 (DS00784). * D3 TC835 Outputs Busy D2 * D1 FIGURE 5-2: Outputs. 5.1 Timing Diagrams For RUN/HOLD Input B1 B8 D5 (MSD) Data D4 Data D3 Data D2 Data STROBE D5 D4 When RUN/HOLD changes to a logic ‘0’, the measurement cycle in progress will be completed, with the data held and displayed as long as the logic ‘0’ condition exists. D2 D3 D1 D1 (LSD) Data D5 Data Note Absence of STROBE 200 Counts When left open, this pin assumes a logic ‘1’ level. With a RUN/HOLD = 1, the TC7135 performs conversions continuously, with a new measurement cycle beginning every 40,002 clock pulses. A positive pulse (>300 nsec) at RUN/HOLD initiates a new measurement cycle. The measurement cycle in progress when RUN/HOLD initially assumed the logic ‘0’ state must be completed before the positive pulse can be recognized as a single conversion run command. End of Conversion 201 Counts 200 Counts 200 Counts 200 Counts 200 Counts 200 Counts *Delay between Busy going Low and First STROBE pulse is dependent on Analog Input. FIGURE 5-3: Strobe Signal Low Five Times Per Conversion. The new measurement cycle begins with a 10,001 count auto-zero phase. At the end of this phase, the busy signal goes high. DS21460C-page 10 2004 Microchip Technology Inc. TC7135 5.3 BUSY Output At the beginning of the signal integration phase, BUSY goes high and remains high until the first clock pulse after the integrator zero crossing. BUSY returns to the logic ‘0’ state once the measurement cycle ends in an overrange condition. The internal display latches are loaded during the first clock pulse after BUSY and are latched at the clock pulse end. The BUSY signal does not go high at the beginning of the measurement cycle, which starts with the auto-zero cycle. 5.4 OVERRANGE Output If the input signal causes the reference voltage integration time to exceed 20,000 clock pulses, the OVERRANGE output is set to a logic ‘1’. The OVERRANGE output register is set when BUSY goes low and is reset at the beginning of the next reference integration phase. 5.5 UNDERRANGE Output If the output count is 9% of full scale or less (-1800 counts), the UNDERRANGE register bit is set at the end of BUSY. The bit is set low at the next signal integration phase. 2004 Microchip Technology Inc. 5.6 POLARITY Output A positive input is registered by a logic ‘1’ polarity signal. The polarity bit is valid at the beginning of reference integrate and remains valid until determined during the next conversion. The polarity bit is valid even for a zero reading. Signals less than the converter's LSB will have the signal polarity determined correctly. This is useful in null applications. 5.7 Digit Drive Outputs Digit drive signals are positive-going signals. The scan sequence is D5 to D1. All positive pulses are 200 clock pulses wide, with the exception D5, which is 201 clock pulses wide. All five digits are scanned continuously, unless an overrange condition occurs. In an overrange condition, all digit drives are held low from the final STROBE pulse until the beginning of the next reference integrate phase. The scanning sequence is then repeated. This provides a blinking visual display indication. 5.8 BCD Data Outputs The binary coded decimal (BCD) bits B8, B4, B2 and B1 are positive-true logic signals. The data bits become active at the same time as the digit drive signals. In an overrange condition, all data bits are at a logic ‘0’ state. DS21460C-page 11 TC7135 6.0 TYPICAL APPLICATIONS 6.1.3 6.1 Component Value Selection The size of the auto-zero capacitor has some influence on the noise of the system, with a larger capacitor reducing the noise. The reference capacitor should be large enough such that stray capacitance to ground from its nodes is negligible. 6.1.1 INTEGRATING RESISTOR The integrating resistor RINT is determined by the fullscale input voltage and the output current of the buffer used to charge the integrator capacitor (CINT). Both the buffer amplifier and the integrator have a class A output stage, with 100 µA of quiescent current. A 20 µA drive current gives negligible linearity errors. Values of 5 µA to 40 µA give good results. The exact value of an integrating resistor for a 20 µA current is easily calculated. EQUATION 6-1: Full Scale Voltage RINT = -------------------------------------------20µA 6.1.2 INTEGRATING CAPACITOR (CINT) The product of integrating resistor and capacitor should be selected to give the maximum voltage swing that ensures the tolerance build-up will not saturate the integrator swing (approximately 0.3V from either supply). For ±5V supplies and ANALOG COMMON tied to supply ground, a ±3.5V to ±4V full scale integrator swing is adequate. A 0.10 µF to 0.47 µF is recommended. In general, the value of CINT is given by: AUTO-ZERO AND REFERENCE CAPACITORS The dielectric absorption of the reference and autozero capacitors are only important at power-on or when the circuit is recovering from an overload. Smaller or cheaper capacitors can be used if accurate readings are not required for the first few seconds of recovery. 6.1.4 REFERENCE VOLTAGE The analog input required to generate a full-scale output is VIN = 2 VREF. The stability of the reference voltage is a major factor in the overall absolute accuracy of the converter. For this reason, it is recommended that a high-quality reference be used where high-accuracy absolute measurements are being made. 6.2 6.2.1 Conversion Timing LINE FREQUENCY REJECTION A signal integration period at a multiple of the 60 Hz line frequency will maximize 60 Hz “line noise” rejection. A 100 kHz clock frequency will reject 50 Hz, 60 Hz and 400 Hz noise. This corresponds to five readings per second (see Table 6-1 and Table 6-2). EQUATION 6-2: C INT [ 10, 000 × clock period ] × I INT = --------------------------------------------------------------------------integrator output voltage swing ( 10, 000 ) ( clock period ) × 20µA = -----------------------------------------------------------------------------integrator output voltage swing A very important characteristic of the integrating capacitor CINT is that it has low dielectric absorption to prevent rollover or ratiometric errors. A good test for dielectric absorption is to use the capacitor with the input tied to the reference. This ratiometric condition should read half scale 0.9999, with any deviation probably due to dielectric absorption. Polypropylene capacitors give undetectable errors at reasonable cost. Polystyrene and polycarbonate capacitors may also be used in less critical applications. DS21460C-page 12 TABLE 6-1: CONVERSION RATE VS. CLOCK FREQUENCY Oscillator Frequency (kHz) Conversion Rate (Conv./Sec.) 100 2.5 120 3 200 5 300 7.5 400 10 800 20 1200 30 2004 Microchip Technology Inc. TC7135 TABLE 6-2: LINE FREQUENCY REJECTION VS. CLOCK FREQUENCY Oscillator Frequency (kHz) Line Frequency Rejection (Hz) 300 60 200 150 120 100 40 33-1/3 250 50 166-2/3 125 50, 60,400 The conversion rate is easily calculated: EQUATION 6-3: Clock Frequency (Hz) Reading 1/sec = ----------------------------------------------------4000 6.3 High Speed Operation The maximum conversion rate of most dual-slope A/D converters is limited by the frequency response of the comparator. The comparator in this circuit follows the integrator ramp with a 3 µsec delay, at a clock frequency of 160 kHz (6 µsec period). Half of the first reference integrate clock period is lost in delay. This means that the meter reading will change from 0 to 1 with a 50 µV input, 1 to 2 with 150 µV, 2 to 3 at 250 µV, etc. This transition at midpoint is considered desirable by most users. However, if the clock frequency is increased appreciably above 200 kHz, the instrument will flash "1" on noise peaks, even when the input is shorted. For many dedicated applications where the input signal is always of one polarity, the delay of the comparator need not be a limitation. Since the nonlinearity and noise do not increase substantially with frequency, clock rates of up to ~1 MHz may be used. For a fixed clock frequency, the extra count (or counts) caused by comparator delay will be a constant and can be subtracted out digitally. The clock frequency may be extended above 160 kHz without this error, however, by using a low value resistor in series with the integrating capacitor. The effect of the resistor is to introduce a small pedestal voltage on to the integrator output at the beginning of the reference integrate phase. By careful selection of 2004 Microchip Technology Inc. The minimum clock frequency is established by leakage on the auto-zero and reference capacitors. With most devices, measurement cycles as long as 10 seconds give no measurable leakage error. The clock used should be free from significant phase or frequency jitter. Several suitable low-cost oscillators are shown in Section 6.0 “Typical Applications”. The multiplexed output means that if the display takes significant current from the logic supply, the clock should have good PSRR. 6.4 100 100 the ratio between this resistor and the integrating resistor (a few tens of ohms in the recommended circuit), the comparator delay can be compensated and the maximum clock frequency extended by approximately a factor of 3. At higher frequencies, ringing and second-order breaks will cause significant nonlinearities in the first few counts of the instrument. Zero Crossing Flip Flop The flip flop interrogates the data once every clock pulse after the transients of the previous clock pulse and half clock pulse have died down. False zero crossings caused by clock pulses are not recognized. Of course, the flip flop delays the true zero crossing by up to one count in every instance. If a correction were not made, the display would always be one count too high. Therefore, the counter is disabled for one clock pulse at the beginning of the reference integrate (de-integrate) phase. This one-count delay compensates for the delay of the zero crossing flip flop and allows the correct number to be latched into the display. Similarly, a onecount delay at the beginning of auto-zero gives an overload display of 0000 instead of 0001. No delay occurs during signal integrate so that true ratiometric readings result. 6.5 Generating a Negative Supply A negative voltage can be generated from the positive supply by using a TC7135 (see Figure 6-1). +5V V+ 11 TC7135 1 V– 8 (-5V) 5 TC7660 10 µF + 4 24 FIGURE 6-1: Generator. + 2 3 10 µF Negative Supply Voltage DS21460C-page 13 TC7135 +5V 20 19 18 17 12 D1 D2 D3 D4 D5 4 INT OUT 0.33 µF 1 µF 5 AZ IN 4.7 kΩ 23 POL 6 BUFF OUT CREF – 7 100 kΩ 22 F TC7135 1 µF 200 kHz IN CREF+ 8 100 kΩ 10 + +INPUT Analog 16 1 µF B8 9 Input 15 –INPUT – B4 14 B2 3 ANALOG B1 13 COMMON REF V– IN V+ 1 2 11 V+ 5V c 7 7 X7 Blank MSD On Zero 5 6 D 2 C 1 B 7 A 9 15 RBI +5V +5V R1 16 kΩ FO 56 kΩ 2 Gates are 74C04 R 1 R2 1 F O = -------------------------------------------------- , R P = -----------------R1 + R 2 2C ( 0.41RP + 0.7R 1 ) 0.22 µF 2. Examples: a. F = 120 kHz, C = 420 pF R1 = R2 ≈ 10.9 kΩ b. F = 120 kHz, C = 420pF, R2 = 50 kΩ R1 = 8.93 kΩ c. F = 120 kHz, C = 220 pF, R2 = 5 kΩ R1 = 27.3 kΩ RC Oscillator Circuit. 8 + 1 kΩ VOUT 7 LM311 3 – 1 4 30 kΩ 16 kΩ a. If R1 = R2 = R1, F≅ 0.55/RC b. If R2 >> R1, F ≅ 0.45/R1C c. If R2 << R1, F ≅ 0.72/R1C 390 pF R2 100 kΩ +5V R4 2 kΩ C2 10 pF 2 R2 100 kΩ C1 0.1 µF FIGURE 6-4: DS21460C-page 14 16 DM7447A 1 µF C FIGURE 6-3: 7 4-1/2 Digit ADC With Multiplexed Common Anode Led Display. R2 1. 7 MCP1525 100 kΩ FIGURE 6-2: b 6 + LM311 3 4 – 1 7 VOUT R3 50 kΩ Comparator Clock Circuits. 2004 Microchip Technology Inc. TC7135 +5V +5V SET VREF = 1V 5V 1 MCP1525 1 µF Analog GND 0.33 µF 100 kΩ + SIG IN V– 2 TC7135 UR 28 27 OR REF IN 26 3 ANALOG STROBE GND 100 kΩ 4 INT OUT 1 µF 5 AZ IN 6 BUFF OUT 100 kΩ 7 CREF+ 1 µF 8 C – RUN/HOLD DGND POLARITY REF 9 0.1 µF +5V –INPUT 10 +INPUT 11 V+ 12 D5 (MSD) CLK IN BUSY (LSD) D1 D2 D3 D4 150Ω 47 kΩ 10 9 25 150Ω 11 8 24 12 7 23 13 MC14513 6 22 14 5 21 15 4 20 16 3 19 17 2 18 18 1 +5V 17 13 16 B1 (LSB) (MSB) B8 14 B4 15 B2 FOSC = 200 kHz FIGURE 6-5: 4-1/2 Digit ADC With Multiplexed Common Cathode LED Display. 2004 Microchip Technology Inc. DS21460C-page 15 TC7135 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 28-Pin PLCC Example: 1 1 M M XXXXXXXXXX XXXXXXXXXX YYWWNNN TC7135CLI 0444256 28-Pin PDIP (Wide) Example: XXXXXXXXXXXXXXX XXXXXXXXXXXXXXX XXXXXXXXXXXXXXX YYWWNNN TC7135CPI 0444256 *h *h 44-Pin MQFP Example: M XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 64-Pin MQFP Example: M XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: Note: DS21460C-page 16 M TC7135CKW 0444256 XX...X YY WW NNN M TC7135CBU 0444256 Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. 2004 Microchip Technology Inc. TC7135 28-Lead Plastic Leaded Chip Carrier (LI) – Square (PLCC) E E1 #leads=n1 D1 D n 1 2 CH2 x 45 ° CH1 x 45 ° α A3 A2 32° A B1 c B β A1 p E2 Units Dimension Limits n p D2 INCHES* NOM 28 .050 7 .165 .173 .145 .153 .020 .028 .021 .026 .035 .045 .000 .005 .485 .490 .485 .490 .450 .453 .450 .453 .410 .420 .410 .420 .008 .011 .026 .029 .013 .020 0 5 0 5 MIN MAX MILLIMETERS NOM 28 1.27 7 4.19 4.39 3.68 3.87 0.51 0.71 0.53 0.66 0.89 1.14 0.00 0.13 12.32 12.45 12.32 12.45 11.43 11.51 11.43 11.51 10.41 10.67 10.41 10.67 0.20 0.27 0.66 0.74 0.33 0.51 0 5 0 5 MIN Number of Pins Pitch Pins per Side n1 Overall Height A .180 Molded Package Thickness .160 A2 Standoff § A1 .035 A3 Side 1 Chamfer Height .031 Corner Chamfer 1 CH1 .055 Corner Chamfer (others) CH2 .010 Overall Width E .495 Overall Length D .495 Molded Package Width E1 .456 Molded Package Length D1 .456 Footprint Width E2 .430 Footprint Length D2 .430 c Lead Thickness .013 Upper Lead Width B1 .032 Lower Lead Width B .021 α Mold Draft Angle Top 10 β Mold Draft Angle Bottom 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-047 Drawing No. C04-026 2004 Microchip Technology Inc. MAX 4.57 4.06 0.89 0.79 1.40 0.25 12.57 12.57 11.58 11.58 10.92 10.92 0.33 0.81 0.53 10 10 DS21460C-page 17 TC7135 28-Lead Plastic Dual In-line (PI) – 600 mil (PDIP) E1 D 2 1 n α E A2 A L c β B1 A1 p B eB Units Dimension Limits n p MIN INCHES* NOM 28 .100 .175 .150 MAX MILLIMETERS NOM 28 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 12.83 13.84 35.43 36.32 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.51 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .160 .190 Molded Package Thickness .140 .160 A2 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .595 .600 .625 Molded Package Width E1 .505 .545 .560 Overall Length D 1.395 1.430 1.465 Tip to Seating Plane L .120 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .030 .050 .070 Lower Lead Width B .014 .018 .022 eB Overall Row Spacing § .620 .650 .680 α Mold Draft Angle Top 5 10 15 β Mold Draft Angle Bottom 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-079 DS21460C-page 18 MAX 4.83 4.06 15.88 14.22 37.21 3.43 0.38 1.78 0.56 17.27 15 15 2004 Microchip Technology Inc. TC7135 44-Lead Plastic Metric Quad Flatpack (KW) 10x10x2 mm Body, Lead Form (MQFP) E E1 #leads=n1 p D1 D 2 1 B n CH x 45° c A β φ L Units Dimension Limits n p Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff § Foot Length Footprint (Reference) Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic n1 A A2 A1 L (F) φ E D E1 D1 c B CH α β MIN .079 .077 .002 .029 0 .510 .510 .390 .390 .005 .012 .025 5 5 α A1 (F) INCHES NOM 44 .031 11 .086 .080 .006 .035 .063 3.5 .520 .520 .394 .394 .007 .015 .035 10 10 MAX .093 .083 .010 .041 7 .530 .530 .398 .398 .009 .018 .045 15 15 A2 MILLIMETERS* NOM 44 0.80 11 2.00 2.18 1.95 2.03 0.05 0.15 0.73 0.88 1.60 0 3.5 12.95 13.20 12.95 13.20 9.90 10.00 9.90 10.00 0.13 0.18 0.30 0.38 0.64 0.89 5 10 5 10 MIN MAX 2.35 2.10 0.25 1.03 7 13.45 13.45 10.10 10.10 0.23 0.45 1.14 15 15 Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-022 Drawing No. C04-071 2004 Microchip Technology Inc. DS21460C-page 19 TC7135 64 Lead Metric Plastic Quad Flat (BU) (MQFP) E E1 e D1 D B 2 1 n a A c A2 b f L Units Dimension Limits n e Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Molded Package Length Foot Length Footprint (Reference) Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D D1 L (F) f c B a b MIN .098 .098 .000 .029 0° .004 .011 5° 5° A1 INCHES NOM 64 .031 BSC -.106 -.677 BSC .551 BSC .677 BSC .551 BSC .035 .063 REF ------ (F) MAX MIN .124 .114 .010 2.50 2.50 0.00 .041 0.73 6° .009 .018 16° 16° 0° 0.11 0.29 5° 5° MILLIMETERS* NOM 64 0.80 BSC -2.70 -17.20 BSC 14.00 BSC 17.20 BSC 14.00 BSC 0.88 1.60 REF ------ MAX 3.15 2.90 0.25 1.03 7° 0.23 0.45 16° 16° *Controlling Parameter § Significant Characteristic Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC equivalent: MS-022 BE. Formerly TelCom PQFP package. Drawing No. C04-022 DS21460C-page 20 2004 Microchip Technology Inc. TC7135 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Range Package Examples: a) b) Device TC7135: 4-1/2 Digit A/D, BCD Output Temperature Range C Package LI = Plastic Leaded Chip Carrier (PLCC), 28-lead LI713 = Plastic Leaded Chip Carrier (PLCC), 28-lead, Tape and Reel PI = Plastic DIP, (600 mil Body), 28-lead KW = Plastic Metric Quad Flatpack, (MQFP), 44-lead BU = Plastic Metric Quad Flatpack, (MQFP), 64-lead = 0°C to +70°C c) d) TC7135CLI: 4-1/2 Digit A/D, BCD Output, PLCC package. TC7135CPI: 4-1/2 Digit A/D, BCD Output, PDIP package. TC7135CLI713: 4-1/2 Digit A/D, BCD Output, PLCC package, Tape and Reel. TC7135CBU: 4-1/2 Digit A/D, BCD Output, MQFP package. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2004 Microchip Technology Inc. DS21460C-page 21 TC7135 NOTES: DS21460C-page 22 2004 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2004 Microchip Technology Inc. DS21460C-page 23 WORLDWIDE SALES AND SERVICE AMERICAS China - Beijing Korea Corporate Office Unit 706B Wan Tai Bei Hai Bldg. No. 6 Chaoyangmen Bei Str. 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