TC7129 4-1/2 Digit Analog-to-Digital Converters with On-Chip LCD Drivers Features General Description • • • • • The TC7129 is a 4-1/2 digit analog-to-digital converter (ADC) that directly drives a multiplexed liquid crystal display (LCD). Fabricated in high performance, low power CMOS, the TC7129 ADC is designed specifically for high resolution, battery powered digital multimeter applications. The traditional dual slope method of A/D conversion has been enhanced with a successive integration technique to produce readings accurate to better than 0.005% of full scale, and resolution down to 10µV per count. • • • • Count Resolution: ±19,999 Resolution on 200mV Scale: 10µV True Differential Input and Reference Low Power Consumption: 500µA at 9V Direct LCD Driver for 4-1/2 Digits, Decimal Points, Low Battery Indicator, and Continuity Indicator Over Range and Under Range Outputs Range Select Input: 10:1 High Common Mode Rejection Ratio: 110dB External Phase Compensation Not Required The TC7129 includes features important to multimeter applications. It detects and indicates low battery condition. A continuity output drives an annunciator on the display, and can be used with an external driver to sound an audible alarm. Over range and under range outputs and a range change input provide the ability to create auto-ranging instruments. For snapshot readings, the TC7129 includes a latch-and-hold input to freeze the present reading. This combination of features makes the TC7129 the ideal choice for full featured multimeter and digital measurement applications. Applications • Full Featured Multimeters • Digital Measurement Devices Device Selection Table Package Code Pin Layout Temperature Range Package TC7129CPL Normal 40-Pin PDIP 0°C to +70°C TC7129CKW Formed 44-Pin PQFP 0°C to +70°C TC7129CLW – 44-Pin PLCC 0°C to +70°C Typical Application Low Battery Continuity V+ 5pF 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TC7129 120kHz 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 330kΩ * 0.1µF 1µF + 10pF 0.1 µF 20 kΩ 150kΩ 0.1µF V+ 10kΩ + 100kΩ 9V + *Note: RC network between Pins 26 and 28 is not required. – VIN 2002 Microchip Technology Inc. DS21459B-page 1 TC7129 Package Type 40-Pin PDIP OSC1 1 40 OSC2 OSC3 2 39 DP1 ANNUNICATOR 3 38 DP2 B1, C1, CONT 4 37 RANGE A1, G1, D1 5 36 DGND F1, E1, DP1 6 35 REF LO B2, C2, LO BATT 7 34 REF HI A2, G2, D2 8 33 IN HI F2, E2, DP2 9 32 IN LO TC7129CPL A3, G3, D3 11 30 CREF- F3, E3, DP3 12 29 CREF+ B4, C4, BC5 13 28 COMMON A4, G4, D4 14 27 CONTINUITY F4, E4, DP4 15 26 INT OUT BP3 16 25 INT IN BP2 17 24 V+ BP1 18 23 V22 LATCH/HOLD VDISP 19 A1, G1, D1 B1, C1, CONT ANNUNCIATOR OSC3 OSC1 NC OSC2 21 DP3/UR 6 5 4 3 2 1 44 43 42 41 40 44 43 42 41 40 39 38 37 36 35 34 F1, E1, DP1 1 DGND RANGE F1, E1, DP1 7 33 REF LO 32 REF HI B2, C2, BATT 2 44-Pin PLCC DP2 DGND RANGE DP1 DP2 OSC2 NC OSC1 44-Pin QFP OSC3 ANNUNCIATOR B1, C1, CONT DP4/OR 20 A1, G1, D1 31 BUFF DP1 B3, C3, MINUS 10 Display Output Lines 39 REF LO B2, C2, BATT 8 38 REF HI A2, G2, D2 9 37 IN HI A2, G2, D2 3 31 IN HI F2, E2, DP2 4 30 IN LO F2, E2, DP2 10 36 IN LO B3, C3, MINUS 5 29 BUFF B3, C3, MINUS 11 35 BUFF NC 6 28 NC TC7129CKW NC 12 34 NC TC7129CLW A3, G3, D3 7 27 CREF- A3, G3, D3 13 33 CREF- F3, E3, DP3 8 26 CREF+ F3, E3, DP3 14 32 CREF+ B4, C4, BC5 9 25 COMMON B4, C4, BC5 15 31 COMMON DS21459B-page 2 29 INT OUT INT IN V+ V- LATCH/HOLD NC DP3/UR DP4/OR 18 19 20 21 22 23 24 25 26 27 28 VDISP V+ INT IN V- LATCH/HOLD DP3/UR NC DP4/OR VDISP BP1 BP2 BP3 12 13 14 15 16 17 18 19 20 21 22 30 CONTINUITY F4, E4, DP4 17 BP1 23 INT OUT F4, E4, DP4 11 A4, G4, D4 16 BP3 24 CONTINUITY BP2 A4, G4, D4 10 2002 Microchip Technology Inc. TC7129 1.0 ELECTRICAL CHARACTERISTICS *Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings* Supply Voltage (V+ to V-)....................................... 15V Reference Voltage (REF HI or REF LO) ......... V+ to VInput Voltage (IN HI or IN LO) (Note 1)........... V+ to VVDISP .......................................... V+ to (DGND – 0.3V) Digital Input (Pins 1, 2, 19, 20, 21, 22, 27, 37, 39, 40) .......................... DGND to V+ Analog Input (Pins 25, 29, 30) ........................ V+ to VPackage Power Dissipation (TA ≤ 70°C) Plastic DIP ..................................................... 1.23W PLCC ............................................................. 1.23W Plastic QFP .................................................... 1.00W Operating Temperature Range ............... 0°C to +70°C Storage Temperature Range .............. -65°C to +150°C TC7129 ELECTRICAL SPECIFICATIONS Electrical Characteristics: V+ to V- = 9V, VREF = 1V, TA = +25°C, fCLK = 120kHz, unless otherwise indicated. Pin numbers refer to 40-pin DIP. Symbol Parameter Min Typ Max Unit Test Conditions Zero Input Reading -0000 0000 +0000 Counts VIN = 0V, 200mV Scale Zero Reading Drift — ±0.5 — µV/°C VIN = 0V, 0°C < TA < +70°C VIN = VREF = 1000mV, Range = 2V Input Ratiometric Reading Range Change Accuracy 9997 9999 10000 Counts 0.9999 1.0000 1.0001 Ratio VIN = 1V on High Range, VIN = 0.1V on Low Range RE Rollover Error — 1 2 Counts VIN- = VIN+ = 199mV NL Linearity Error — 1 — Counts 200mV Scale VCM = 1V, VIN = 0V, 200mV Scale CMRR Common Mode Rejection Ratio — 110 — dB CMVR Common Mode Voltage Range — (V-) + 1.5 — V VIN = 0V — (V+) – 1 — V 200mV Scale Noise (Peak-to-Peak Value not Exceeded 95% of Time) — 14 — µVP-P VIN = 0V 200mV Scale eN IIN Input Leakage Current — 1 10 pA Scale Factor Temperature Coefficient — 2 7 ppm/°C VIN = 0V, Pins 32, 33 Common Voltage 2.8 3.2 3.5 V Common Sink Current — 0.6 — mA ∆Common = +0.1V Common Source Current — 10 — µA ∆Common = -0.1V Digital Ground Voltage 4.5 5.3 5.8 V Sink Current — 1.2 — mA VIN = 199mV, 0°C < TA < +70°C External VREF = 0ppm/°C Power VCOM DGND IS Supply Voltage Range 6 9 12 V Supply Current Excluding Common Current — 0.8 1.3 mA V+ to Pin 28 V+ to Pin 36, V+ to V- = 9V ∆DGND = +0.5V V+ to VV+ to V- = 9V Note 1: Input voltages may exceed supply voltages, provided input current is limited to ±400µA. Currents above this value may result in invalid display readings, but will not destroy the device if limited to ±1mA. Dissipation ratings assume device is mounted with all leads soldered to printed circuit board. 2002 Microchip Technology Inc. DS21459B-page 3 TC7129 TC7129 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: V+ to V- = 9V, VREF = 1V, TA = +25°C, fCLK = 120kHz, unless otherwise indicated. Pin numbers refer to 40-pin DIP. Symbol fCLK Parameter Min Typ Max Unit Test Conditions Clock Frequency — 120 360 kHz VDISP Resistance — 50 — kΩ Low Battery Flag Activation Voltage 6.3 7.2 7.7 V Continuity Comparator Threshold Voltages 100 200 — mV — 200 400 mV VOUT Pin 27 = Low Pull-down Current — 2 10 µA Pins 37, 38, 39 "Weak Output" Current Sink/Source — 3/3 — µA Pins 20, 21 Sink/Source — 3/9 — µA Pin 27 Sink/Source Pin 22 Source Current — 40 — µA Pin 22 Sink Current — 3 — µA VDISP to V+ V+ to V- Digital VOUT Pin 27 = High Note 1: Input voltages may exceed supply voltages, provided input current is limited to ±400µA. Currents above this value may result in invalid display readings, but will not destroy the device if limited to ±1mA. Dissipation ratings assume device is mounted with all leads soldered to printed circuit board. DS21459B-page 4 2002 Microchip Technology Inc. TC7129 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin No. Pin No. Pin No. 40-Pin PDIP 44-Pin PQFP 44-Pin PLCC 1 40 2 2 41 3 3 42 4 Symbol Function OSC1 Input to first clock inverter. OSC3 Output of second clock inverter. ANNUNCIATOR Backplane square wave output for driving annunciators. 4 43 5 B1, C 1, CONT Output to display segments. 5 44 6 A1, G1, D1 Output to display segments. 6 1 7 F1, E1, DP1 Output to display segments. 7 2 8 8 3 9 A2, G2, D2 Output to display segments. 9 4 10 F2, E2, DP2 Output to display segments. B2, C 2, LO BATT Output to display segments. 10 5 11 B3, C3, MINUS Output to display segments. 11 7 13 A3, G3, D3 Output to display segments. 12 8 14 F3, E3, DP3 Output to display segments. 13 9 15 B4, C4, BC5 Output to display segments. 14 10 16 A4, D 4, G4 Output to display segments. 15 11 17 F4, E4, DP4 Output to display segments. 16 12 18 BP3 Backplane #3 output to display. 17 13 19 BP2 Backplane #2 output to display. 18 14 20 BP1 Backplane #1 output to display. 19 15 21 VDISP 20 16 22 DP4/OR Input: When HI, turns on most significant decimal point. Output: Pulled HI when result count exceeds ±19,999. 21 18 24 DP3/UR Input: Second most significant decimal point on when HI. Output: Pulled HI when result count is less than ±1000. 22 19 25 LATCH/HOLD 23 20 26 V- Negative power supply terminal. 24 21 27 V+ Positive power supply terminal and positive rail for display drivers. 25 22 28 INT IN 26 23 29 INT OUT 27 24 30 CONTINUITY 28 25 31 COMMON Negative rail for display drivers. Input: When floating, ADC operates in the Free Run mode. When pulled HI, the last displayed reading is held. When pulled LO, the result counter contents are shown incrementing during the de-integrate phase of cycle. Output: Negative going edge occurs when the data latches are updated. Can be used for converter status signal. Input to integrator amplifier. Output of integrator amplifier. Input: When LO, continuity flag on the display is OFF. When HI, continuity flag is ON. Output: HI when voltage between inputs is less than +200mV. LO when voltage between inputs is more than +200mV. Sets Common mode voltage of 3.2V below V+ for DE, 10X, etc. Can be used as pre-regulator for external reference. 29 26 32 CREF + Positive side of external reference capacitor. 30 27 33 CREF- Negative side of external reference capacitor. 31 29 35 BUFFER 32 30 36 IN LO 33 31 37 IN HI 34 32 38 REF HI Positive reference voltage. 35 33 39 REF LO Negative reference voltage 2002 Microchip Technology Inc. Output of buffer amplifier. Negative input voltage terminal. Positive input voltage terminal. DS21459B-page 5 TC7129 TABLE 2-1: PIN FUNCTION TABLE (CONTINUED) Pin No. Pin No. Pin No. 40-Pin PDIP 44-Pin PQFP 44-Pin PLCC Symbol 36 34 40 DGND 37 35 41 RANGE Function Internal ground reference for digital section. See Section 4.3, ±5V Power Supply. 3µA pull-down for 200mV scale. Pulled HI externally for 2V scale. 38 36 42 DP2 39 37 43 DP1 Internal 3µA pull-down. When HI, decimal point 1 will be on. 40 38 44 OSC2 Output of first clock inverter. Input of second clock inverter. — 6,17, 28, 39 12, 23, 34, 1 NC DS21459B-page 6 Internal 3µA pull-down. When HI, decimal point 2 will be on. No connection. 2002 Microchip Technology Inc. TC7129 3.0 DETAILED DESCRIPTION (All Pin Designations Refer to 40-Pin PDIP.) The TC7129 is designed to be the heart of a high resolution analog measurement instrument. The only additional components required are a few passive elements: a voltage reference, an LCD, and a power source. Most component values are not critical; substitutes can be chosen based on the information given below. The basic circuit for a digital multimeter application is shown in Figure 3-1. See Section 4.0, Typical Applications for variations. Typical values for each component are shown. The sections below give component selection criteria. 3.1 Oscillator (XOSC, CO1, CO2, R O) The primary criterion for selecting the crystal oscillator is to choose a frequency that achieves maximum rejection of line frequency noise. To do this, the integration phase should last an integral number of line cycles. The integration phase of the TC7129 is 10,000 clock cycles on the 200mV range and 1000 clock cycles on the 2V range. One clock cycle is equal to two oscillator cycles. For 60Hz rejection, the oscillator frequency should be chosen so that the period of one line cycle equals the integration time for the 2V range: The resistor and capacitor values are not critical; those shown work for most applications. In some situations, the capacitor values may have to be adjusted to compensate for parasitic capacitance in the circuit. The capacitors can be low cost ceramic devices. Some applications can use a simple RC network instead of a crystal oscillator. The RC oscillator has more potential for jitter, especially in the least significant digit. See Section 4.8, RC Oscillator. 3.2 Integrating Resistor (RINT) The integrating resistor sets the charging current for the integrating capacitor. Choose a value that provides a current between 5µA and 20µA at 2V, the maximum full scale input. The typical value chosen gives a charging current of 13.3µA: EQUATION 3-2: ICHARGE = 2V 13.3µA 150kΩ Too high a value for RINT increases the sensitivity to noise pickup and increases errors due to leakage current. Too low a value degrades the linearity of the integration, leading to inaccurate readings. EQUATION 3-1: 1/60 second = 16.7msec = 1000 clock cycles *2 OSC cycles/clock cycle OSC Frequency This equation gives an oscillator frequency of 120kHz. A similar calculation gives an optimum frequency of 100kHz for 50Hz rejection. 2002 Microchip Technology Inc. DS21459B-page 7 TC7129 FIGURE 3-1: STANDARD CIRCUIT Low Battery Continuity V+ 14 13 12 11 9 10 7 8 6 5 4 ANNUNC OSC3 DP2 DP1 OSC2 30 31 32 33 34 35 1 DGND 29 2 RANGE 28 REF LO 27 IN HI IN LO 26 REF HI BUFF 25 36 37 38 39 40 TC7129 CREF- 24 INT IN V+ 23 3 OSC1 15 Display Drive Outputs VLATCH/ HOLD DP3 /UR 22 16 CREF+ VDISP 21 17 COMMON DP4 /OR 18 INT OUT 19 CONTINUITY 20 5pF CO1 120 kHz Crystal 330kΩ RO 10pF CINT 0.1µF CREF+ 1µF 150kΩ RINT + 9V RREF 20 kΩ 0.1 µF DREF CRF 0.1µF CO2 V+ CIF 10kΩ RBIAS RIF 100kΩ – + VIN 3.3 Integrating Capacitor (C INT) The charge stored in the integrating capacitor during the integrate phase is directly proportional to the input voltage. The primary selection criterion for C INT is to choose a value that gives the highest voltage swing while remaining within the high linearity portion of the integrator output range. An integrator swing of 2V is the recommended value. The capacitor value can be calculated using the following equation: EQUATION 3-3: CINT = tINT x IINT VSWING Where t INT is the integration time. Using the values derived above (assuming 60Hz operation), the equation becomes: EQUATION 3-4: The capacitor should have low dielectric absorption to ensure good integration linearity. Polypropylene and Teflon capacitors are usually suitable. A good measurement of the dielectric absorption is to connect the reference capacitor across the inputs by connecting: Pin to Pin: 20 → 33 (CREF+ to IN HI) 30 → 32 (CREF- to IN LO) A reading between 10,000 and 9998 is acceptable; anything lower indicates unacceptably high dielectric absorption. 3.4 Reference Capacitor (CREF) The reference capacitor stores the reference voltage during several phases of the measurement cycle. Low leakage is the primary selection criterion for this component. The value must be high enough to offset the effect of stray capacitance at the capacitor terminals. A value of at least 1µF is recommended. CINT = 16.7msec x 13.3µA = 0.1µA 2V DS21459B-page 8 2002 Microchip Technology Inc. TC7129 3.5 Voltage Reference (DREF, RREF, RBIAS, CRF) FIGURE 4-1: The reference potentiometer (R REF) provides an adjustment for adjusting the reference voltage; any value above 20kΩ is adequate. The bias resistor (RBIAS) limits the current through D REF to less than 150µA. The reference filter capacitor (CRF) forms an RC filter with RBIAS to help eliminate noise. 3.6 POWERING THE TC7129 FROM A ±5V POWER SUPPLY +5V TC7129 24 V+ Input Filter (RIF, CIF) 35 REF LO 36 DGND 28 COMMON 0.1µF 33 IN HI For added stability, an RC input noise filter is usually included in the circuit. The input filter resistor value should not exceed 100kΩ. A typical RC time constant value is 16.7msec to help reject line frequency noise. The input filter capacitor should have low leakage for a high-impedance input. 0.1µF 3.7 IN LO V23 Battery The typical circuit uses a 9V battery as a power source. Any value between 6V and 12V can be used. For operation from batteries with voltages lower than 6V and for operation from power supplies, see Section 4.2, Powering the TC7129. 4.0 TYPICAL APPLICATIONS 4.1 TC7129 as a Replacement Part The TC7129 is a direct pin-for-pin replacement part for the ICL7129. Note, however, that part requires a capacitor and resistor between Pins 26 and 28 for phase compensation. Since the TC7129 uses internal phase compensation, these parts are not required and, in fact, must be removed from the circuit for stable operation. 34 REF HI 0.1µF + VIN 32 – -5V 4.4 Low Voltage Battery Source A battery with voltage between 3.8V and 6V can be used to power the TC7129, when used with a voltage doubler circuit, as shown in Figure 4-2. The voltage doubler uses the TC7660 DC-to-DC voltage converter and two external capacitors. FIGURE 4-2: POWERING THE TC7129 FROM A LOW VOLTAGE BATTERY 24 4.2 Powering the TC7129 While the most common power source for the TC7129 is a 9V battery, there are other possibilities. Some of the more common ones are explained below. 4.3 V+ REF HI 36 + 3.8V to 6V Measurements are made with respect to power supply ground. DGND (Pin 36) is set internally to about 5V less than V+ (Pin 24); it is not intended as a power supply input and must not be tied directly to power supply ground. It can be used as a reference for external logic, as explained in Section 4.6, Connecting to External Logic (see Figure 4-1). DGND REF LO COMMON ±5V Power Supply TC7129 IN HI 8 IN LO V- 2 + TC7660 34 10µF 35 28 33 32 + VIN – 23 4 5 3 10µF + 2002 Microchip Technology Inc. DS21459B-page 9 TC7129 4.5 FIGURE 4-4: +5V Power Supply EXTERNAL LOGIC REFERENCED DIRECTLY TO DGND Measurements are made with respect to power supply ground. COMMON (Pin 28) is connected to REF LO (Pin 35). A voltage doubler is needed, since the supply voltage is less than the 6V minimum needed by the TC7129. DGND (Pin 36) must be isolated from power supply ground (see Figure 4-3). V + 24 FIGURE 4-3: POWERING THE TC7129 FROM A +5V POWER SUPPLY External Logic TC7129 36 +5V DGND ILOGIC 24 V+ 23 34 0.1µF V- TC7129 35 36 DGND 33 8 V+ 2 TC7660 4 32 V- + FIGURE 4-5: 28 0.1µF + EXTERNAL LOGIC REFERENCED TO DGND WITH BUFFER VIN V+ – 23 10µF 24 5 GND 3 External Logic 10µF TC7129 + – 4.6 Connecting to External Logic + ILOGIC External logic can be directly referenced to DGND (Pin 36), provided that the supply current of the external logic does not exceed the sink current of DGND (Figure 4-4). A safe value for DGND sink current is 1.2mA. If the sink current is expected to exceed this value, a buffer is recommended (see Figure 4-5). 36 DGND 23 V- 4.7 Temperature Compensation For most applications, VDISP (Pin 19) can be connected directly to DGND (Pin 36). For applications with a wide temperature range, some LCDs require that the drive levels vary with temperature to maintain good viewing angle and display contrast. Figure 4-6 shows two circuits that can be adjusted to give temperature compensation of about 10mV/°C between V+ (Pin 24) and VDISP. The diode between DGND and VDISP should have a low turn-on voltage because VDISP cannot exceed 0.3V below DGND. DS21459B-page 10 2002 Microchip Technology Inc. TC7129 FIGURE 4-6: TEMPERATURE COMPENSATING CIRCUITS V+ 1N4148 39kΩ TC7129 19 + 5kΩ 39kΩ 24 200kΩ – V+ 36 24 20kΩ 2N2222 19 VDISP 36 DGND 75kΩ VDISP DGND 18kΩ 23 23 V- V- 4.8 TC7129 RC Oscillator 4.9 Measuring Techniques For applications in which 3-1/2 digit (100µV) resolution is sufficient, an RC oscillator is adequate. A recommended value for the capacitor is 51pF. Other values can be used as long as they are sufficiently larger than the circuit parasitic capacitance. The resistor value is calculated as: Two important techniques are used in the TC7129: successive integration and digital auto-zeroing. Successive integration is a refinement to the traditional dual slope conversion technique. EQUATION 4-1: A dual slope conversion has two basic phases: integrate and de-integrate. During the integrate phase, the input signal is integrated for a fixed period of time; the integrated voltage level is thus proportional to the input voltage. During the de-integrate phase, the integrated voltage is ramped down at a fixed slope, and a counter counts the clock cycles until the integrator voltage crosses zero. The count is a measurement of the time to ramp the integrated voltage to zero, and is, therefore, proportional to the input voltage being measured. This count can then be scaled and displayed as a measurement of the input voltage. Figure 4-8 shows the phases of the dual slope conversion. R= 0.45 Freq * C For 120kHz frequency and C = 51pF, the calculated value of R is 75kΩ. The RC oscillator and the crystal oscillator circuits are shown in Figure 4-7. FIGURE 4-7: OSCILLATOR CIRCUITS 4.10 Dual Slope Conversion TC7129 1 5pF 40 120kHz 2 FIGURE 4-8: 270kΩ 10pF V+ Integrate DUAL SLOPE CONVERSION De-integrate V+ Zero Crossing TC7129 1 40 75kΩ 51pF 2002 Microchip Technology Inc. 2 Time The dual slope method has a fundamental limitation. The count can only stop on a clock cycle, so that measurement accuracy is limited to the clock frequency. In addition, a delay in the zero crossing comparator can add to the inaccuracy. Figure 4-9 shows these errors in an actual measurement. DS21459B-page 11 TC7129 FIGURE 4-9: ACCURACY ERRORS IN DUAL SLOPE CONVERSION Integrate De-integrate Over shoot due to zero crossing between clock pulses Time Integrator Residue Voltage Over shoot caused by comparator delay of 1 clock pulse Clock Pulses FIGURE 4-10: Zero Integrate and Latch INTEGRATION WAVEFORM INT1 Integrate DE1 De-integrate REST X10 DE2 REST X10 DE3 Zero Integrate TC7129 Integrator Residual Voltage Note: Shaded area greatly expanded in time and amplitude. DS21459B-page 12 2002 Microchip Technology Inc. TC7129 4.11 Successive Integration The successive integration technique picks up where dual slope conversion ends. The over shoot voltage shown in Figure 4-9, called the "integrator residue voltage," is measured to obtain a correction to the initial count. Figure 4-10 shows the cycles in a successive integration measurement. The waveform shown is for a negative input signal. The sequence of events during the measurement cycle is shown in Table 4-1. TABLE 4-1: MEASUREMENT CYCLE SEQUENCE Phase Description INT1 Input signal is integrated for fixed time (1000 clock cycles on 2V scale, 10,000 on 200 mV). DE1 Integrator voltage is ramped to zero. Counter counts up until zero crossing to produce reading accurate to 3-1/2 digits. Residue represents an over shoot of the actual input voltage. 4.12 Digital Auto-Zeroing To eliminate the effect of amplifier offset errors, the TC7129 uses a digital auto-zeroing technique. After the input voltage is measured as described above, the measurement is repeated with the inputs shorted internally. The reading with inputs shorted is a measurement of the internal errors and is subtracted from the previous reading to obtain a corrected measurement. Digital auto-zeroing eliminates the need for an external auto-zeroing capacitor used in other ADCs. 4.13 Inside the TC7129 Figure 4-11 shows a simplified block diagram of the TC7129. REST Rest; circuit settles. X10 Residue voltage is amplified 10 times and inverted. DE2 Integrator voltage is ramped to zero. Counter counts down until zero crossing to correct reading to 4-1/2 digits. Residue represents an under shoot of the actual input voltage. REST Rest; circuit settles. X10 Residue voltage is amplified 10 times and inverted. DE3 Integrator voltage is ramped to zero. Counter counts up until zero crossing to correct reading to 5-1/2 digits. Residue is discarded. 2002 Microchip Technology Inc. DS21459B-page 13 TC7129 FIGURE 4-11: TC7129 FUNCTIONAL BLOCK DIAGRAM Low Battery Continuity Backplane Drives Segment Drives TC7129 Annunciator Drive OSC1 VDISP Latch, Decode Display Multiplexer OSC2 Up/Down Results Counter OSC3 Sequence Counter/Decoder Control Logic DP1 DP2 UR/DP3 RANGE L/H CONT OR/DP4 V+ V- Analog Section REF HI REF LO DGND INT OUT INT IN COMMON FIGURE 4-12: BUFF IN IN HI LO INTEGRATOR BLOCK DIAGRAM CREF CINT RINT REF LO REF HI DE DE Integrator – INT1 – + IN HI DE- DE+ Buffer 10 pF + DE- DE+ INT INT1, INT2 To Digital Section + 100pF Common X10 Comparator 1 – Comparator 2 ZI, X10 REST IN LO – – Continuity DS21459B-page 14 + V 200mV + 500kΩ Continuity Comparator TC7129 To Display Driver 2002 Microchip Technology Inc. TC7129 4.14 Integrator Section FIGURE 4-13: CONTINUITY INDICATOR CIRCUIT The integrator section includes the integrator, comparator, input buffer amplifier, and analog switches (see Table 4-2), used to change the circuit configuration during the separate measurement phases described earlier. See Integrator Block Diagram (Figure 4-12). – + IN HI TABLE 4-2: Buffer SWITCH LEGENDS Label Description COM Label Meaning. DE Open during all de-integrate phases. DE– Closed during all de-integrate phases when input voltage is negative. DE+ Closed during all de-integrate phases when input voltage is positive. INT1 Closed during the first integrate phase (measurement of the input voltage). INT2 Closed during the second integrate phase (measurement of the amplifier offset). INT Open during both integrate phases. REST ZI Closed during the rest phase. IN LO – 200mV V + Closed during the X10 phase. X10 Open during the X10 phase. The buffer amplifier has a Common mode input voltage range from 1.5V above V- to 1V below V+. The integrator amplifier can swing to within 0.3V of the rails, although for best linearity, the swing is usually limited to within 1V. Both amplifiers can supply up to 80µA of output current, but should be limited to 20µA for good linearity. 500kΩ To Display Driver (Not Latched) CONT FIGURE 4-14: Closed during the zero integrate phase. X10 4.15 TC7129 INPUT/OUTPUT PIN SCHEMATIC TC7129 DP4/OR, Pin 20 DP3/UR, Pin 21 LATCH/HOLD Pin 22 CONTINUITY, Pin 27 500kΩ Continuity Indicator A comparator with a 200mV threshold is connected between IN HI (Pin 33) and IN LO (Pin 32). Whenever the voltage between inputs is less than 200mV, the CONTINUITY output (Pin 27) will be pulled HIGH, activating the continuity annunciator on the display. The continuity pin can also be used as an input to drive the continuity annunciator directly from an external source (see Figure 4-13). 4.16 Common and Digital Ground The common and digital ground (DGND) outputs are generated from internal zener diodes. The voltage between V+ and DGND is the internal supply voltage for the digital section of the TC7129. Common can source approximately 12µA; DGND has essentially no source capability (see Figure 4-15). A schematic of the input/output nature of this pin is also shown in Figure 4-14. 2002 Microchip Technology Inc. DS21459B-page 15 TC7129 FIGURE 4-15: DIGITAL GROUND (DGND) AND COMMON OUTPUTS 24 12µA V+ 3.2V 28 COM – 5V N + Logic Section 36 P TC7129 DGND N 23 4.17 V- Low Battery The low battery annunciator turns on when supply voltage between V- and V+ drops below 6.8V. The internal zener has a threshold of 6.3V. When the supply voltage drops below 6.8V, the transistor tied to V- turns OFF, pulling the "Low Battery" point HIGH. 4.18 Sequence and Results Counter A sequence counter and associated control logic provide signals that operate the analog switches in the integrator section. The comparator output from the integrator gates the results counter. The results counter is a six-section up/down decade counter, which holds the intermediate results from each successive integration. 4.19 Over Range and Under Range Outputs When the results counter holds a value greater than ±19,999, the DP4/OR output (Pin 20) is driven HIGH. When the results counter value is less than ±1000, the DP3/UR output (Pin 21) is driven HIGH. Both signals are valid on the falling edge of LATCH/HOLD (L/H) and do not change until the end of the next conversion cycle. The signals are updated at the end of each conversion, unless the L/H input (Pin 22) is held HIGH. Pins 20 and 21 can also be used as inputs for external control of decimal points 3 and 4. Figure 4-14 shows a schematic of the input/output nature of these pins. DS21459B-page 16 4.20 LATCH/Hold The L/H output goes LOW during the last 100 cycles of each conversion. This pulse latches the conversion data into the display driver section of the TC7129. This pin can also be used as an input. When driven HIGH, the display will not be updated; the previous reading is displayed. When driven LOW, the display reading is not latched; the sequence counter reading will be displayed. Since the counter is counting much faster than the backplanes are being updated, the reading shown in this mode is somewhat erratic. 4.21 Display Driver The TC7129 drives a triplexed LCD with three backplanes. The LCD can include decimal points, polarity sign, and annunciators for continuity and low battery. Figure 4-16 shows the assignment of the display segments to the backplanes and segment drive lines. The backplane drive frequency is obtained by dividing the oscillator frequency by 1200. This results in a backplane drive frequency of 100Hz for 60Hz operation (120kHz crystal) and 83.3Hz for 50Hz operation (100kHz crystal). Backplane waveforms are shown in Figure 4-17. These appear on outputs BP1, BP2, BP3 (Pins 16, 17, and 18). They remain the same, regardless of the segments being driven. Other display output lines (Pins 4 through 15) have waveforms that vary depending on the displayed values. Figure 4-18 shows a set of waveforms for the A, G, D outputs (Pins 5, 8, 11, and 14) for several combinations of "ON" segments. The ANNUNCIATOR DRIVE output (Pin 3) is a square wave, running at the backplane frequency (100Hz or 83.3Hz) with a peak-to-peak voltage equal to DGND voltage. Connecting an annunciator to Pin 3 turns it ON; connecting it to its backplane turns it OFF. 2002 Microchip Technology Inc. TC7129 FIGURE 4-16: DISPLAY SEGMENT ASSIGNMENTS Low Battery Continuity BP1 BP2 Backplane Connections BP3 Low Battery Continuity F4, E4, DP4 B1, C1, Continuity A4, G4, D4 A1, G1, D1 B4, C4, BC4 F1, E1, DP1 F3, E3, DP3 B2, C2, Low Battery A2, G2, D2 A3, G3, D3 B3, C3, MINUS FIGURE 4-17: F2, E2, DP2 BACKPLANE WAVEFORMS FIGURE 4-18: BP1 b Segment Line All Off BP2 a Segment On d, g Off BP3 a, g On d Off TYPICAL DISPLAY OUTPUT WAVEFORMS VDD VH VL VDISP VDD VH VL VDISP VDD VH VL VDISP VDD VH All On VL VDISP 2002 Microchip Technology Inc. DS21459B-page 17 TC7129 5.0 PACKAGING INFORMATION 5.1 Package Marking Information Package marking data not available a this time. 5.2 Taping Forms Component Taping Orientation for 44-Pin PLCC Devices User Direction of Feed PIN 1 W P Standard Reel Component Orientation for TR Suffix Device Carrier Tape, Number of Components Per Reel and Reel Size Package 44-Pin PLCC Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 32 mm 24 mm 500 13 in Note: Drawing does not represent total number of pins. Component Taping Orientation for 44-Pin PQFP Devices User Direction of Feed PIN 1 W P Standard Reel Component Orientation for TR Suffix Device Carrier Tape, Number of Components Per Reel and Reel Size Package 44-Pin PQFP Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 24 mm 16 mm 500 13 in Note: Drawing does not represent total number of pins. DS21459B-page 18 2002 Microchip Technology Inc. TC7129 5.3 Package Dimensions 40-Pin PDIP (Wide) PIN 1 .555 (14.10) .530 (13.46) 2.065 (52.45) 2.027 (51.49) .610 (15.49) .590 (14.99) .200 (5.08) .140 (3.56) .040 (1.02) .020 (0.51) .150 (3.81) .115 (2.92) .110 (2.79) .090 (2.29) .070 (1.78) .045 (1.14) .015 (0.38) .008 (0.20) 3° MIN. .700 (17.78) .610 (15.50) .022 (0.56) .015 (0.38) Dimensions: inches (mm) 44-Pin PLCC PIN 1 .021 (0.53) .013 (0.33) .050 (1.27) TYP. .695 (17.65) .685 (17.40) .630 (16.00) .591 (15.00) .656 (16.66) .650 (16.51) .032 (0.81) .026 (0.66) .020 (0.51) MIN. .656 (16.66) .650 (16.51) .120 (3.05) .090 (2.29) .695 (17.65) .685 (17.40) .180 (4.57) .165 (4.19) Dimensions: inches (mm) 2002 Microchip Technology Inc. DS21459B-page 19 TC7129 5.3 Package Dimensions (Continued) 44-Pin PQFP 7° MAX. .009 (0.23) .005 (0.13) PIN 1 .018 (0.45) .012 (0.30) .041 (1.03) .026 (0.65) .398 (10.10) .390 (9.90) .557 (14.15) .537 (13.65) .031 (0.80) TYP. .398 (10.10) .390 (9.90) .557 (14.15) .537 (13.65) .010 (0.25) TYP. .083 (2.10) .075 (1.90) .096 (2.45) MAX. Dimensions: inches (mm) DS21459B-page 20 2002 Microchip Technology Inc. TC7129 NOTES: 2002 Microchip Technology Inc. DS21459B-page 21 TC7129 SALES AND SUPPORT Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. DS21459B-page 22 2002 Microchip Technology Inc. TC7129 Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro ® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. 2002 Microchip Technology Inc. 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