SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002 D High-Drive Outputs (–32-mA IOH, 64-mA IOL) Ioff and Power-Up 3-State Support Hot Insertion 13 3 12 4 11 5 10 6 7 9 8 VCC 4OE 4A 4Y 3OE 3A 3Y 1A 1Y 2OE 2A 2Y 14 1A 1OE NC VCC 4OE 1 2 13 3 12 4 11 10 5 9 6 7 8 SN54ABT125 . . . FK PACKAGE (TOP VIEW) 1Y NC 2OE NC 2A 4OE 4A 4Y 3OE 3A 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3OE 2Y GND NC 3Y 3A 14 2 VCC 1 3Y 1OE 1A 1Y 2OE 2A 2Y GND Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) SN74ABT125 . . . RGY PACKAGE (TOP VIEW) SN54ABT125 . . . J OR W PACKAGE SN74ABT125 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) 1OE D D D Typical VOLP (Output Ground Bounce) <1 V at VCC = 5 V, TA = 25°C GND D NC – No internal connection description/ordering information The ’ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION –40°C to 85°C –55°C to 125°C ORDERABLE PART NUMBER PACKAGE† TA TOP-SIDE MARKING PDIP – N Tube SN74ABT125N SN74ABT125N QFN – RGY Tape and reel SN74ABT125RGYR AB125 Tube SN74ABT125D Tape and reel SN74ABT125DR SOP – NS Tape and reel SN74ABT125NSR ABT125 SSOP – DB Tape and reel SN74ABT125DBR AB125 TSSOP – PW Tape and reel SN74ABT125PWR AB125 CDIP – J Tube SNJ54ABT125J SNJ54ABT125J CFP – W Tube SNJ54ABT125W SNJ54ABT125W LCCC – FK Tube SNJ54ABT125FK SOIC – D ABT125 SNJ54ABT125FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002 FUNCTION TABLE (each buffer) INPUTS OE A OUTPUT Y L H H L L L H X Z logic diagram (positive logic) 1OE 1A 2OE 2A 1 2 3OE 3 1Y 4 5 3A 4OE 6 2Y 4A 10 9 8 3Y 13 12 11 4Y Pin numbers shown are for the D, DB, J, N, NS, PW, RGY, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W (see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W (see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W (see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-5. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002 recommended operating conditions (see Note 4) SN54ABT125 SN74ABT125 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC –24 Low-level output current 48 64 mA ∆t/∆v Input transition rise or fall rate 10 10 ns/V ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 High-level input voltage 2 2 0.8 Input voltage 0 V 0.8 0 VCC –32 –40 V V mA µs/V 200 125 V 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOL VCC = 4 4.5 5V Vhys II MIN TA = 25°C TYP† MAX SN54ABT125 MIN –1.2 MAX SN74ABT125 MIN –1.2 –1.2 2.5 2.5 2.5 IOH = –3 mA IOH = –24 mA 3 3 3 2 2 IOH = –32 mA IOL = 48 mA 2* UNIT V V 2 0.55 IOL = 64 mA 0.55 0.55* 0.55 100 V mV VCC = 0 to 5.5 V, VI = VCC or GND VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X ±1 ±1 ±1 µA ±50 ±50 ±50 µA VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE ≥ 2 V ±50 ±50 ±50 µA 10 10 10 µA VCC = 2.1 V to 5.5 V, VCC = 0, VO = 0.5 V, OE ≥ 2 V VI or VO ≤ 4.5 V –10 –10 –10 µA ±100 µA ICEX VCC = 5.5 V, VO = 5.5 V Outputs high 50 µA IO‡ VCC = 5.5 V, –200§ mA 250 µA IOZPU IOZPD IOZH IOZL Ioff VCC = 5.5 V, IO = 0, VI = VCC or GND ICC ∆ICC¶ Ci VO = 2.5 V Outputs high ±100 50 –50 –100 –200§ 1 250 50 –50 –200§ –50 250 Outputs low 24 30 30 30 mA Outputs disabled 0.5 250 250 250 µA Outputs enabled 1.5 1.5 1.5 Outputs disabled 0.05 0.05 0.05 1.5 1.5 1.5 Data inputs VCC = 5.5 V, One input at 3.4 V,, Other inputs at VCC or GND Control inputs VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V 3 Co 7 * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. § This limit may vary among suppliers. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. 4 MAX POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 mA pF pF SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER tPLH† tPHL† tPZH† tPZL† tPHZ tPLZ† FROM (INPUT) TO (OUTPUT) A Y OE Y OE Y VCC = 5 V, TA = 25°C SN54ABT125 SN74ABT125 MIN TYP MAX MIN MAX MIN MAX 1 3.2 4.6 1 6 1 4.9 1 2.5 4.6 1 6.2 1 4.9 1 3.6 5 1 6 1 5.9 1 2.5 6.2 1 7.5 1 6.8 1 3.8 5.4 1 6.3 1 6.2 1 3.3 5.3 1 6.5 1 6.2 UNIT ns ns ns † This limit may vary among suppliers. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V th 3V 1.5 V Input 1.5 V 0V Data Input 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V VOH 1.5 V Output 1.5 V VOL VOH 1.5 V 1.5 V VOL 1.5 V 1.5 V 0V tPZL tPLZ Output Waveform 1 S1 at 7 V (see Note B) tPLH tPHL Output 3V Output Control tPHL tPLH 1.5 V Output Waveform 2 S1 at Open (see Note B) 1.5 V 3.5 V VOL + 0.3 V VOL tPHZ tPZH 1.5 V VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 5962-9676801Q2A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC 5962-9676801QCA ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC 5962-9676801QDA ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC SN74ABT125D ACTIVE SOIC D 14 50 Pb-Free (RoHS) CU NIPDAU SN74ABT125DBLE OBSOLETE SSOP DB 14 None Call TI SN74ABT125DBR ACTIVE SSOP DB 14 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74ABT125DR ACTIVE SOIC D 14 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74ABT125N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74ABT125NSR ACTIVE SO NS 14 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74ABT125PW ACTIVE TSSOP PW 14 90 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74ABT125PWLE OBSOLETE TSSOP PW 14 None Call TI SN74ABT125PWR ACTIVE TSSOP PW 14 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74ABT125RGYR ACTIVE QFN RGY 14 1000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR SNJ54ABT125FK ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC SNJ54ABT125J ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC SNJ54ABT125W ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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