MICROCHIP MCP6543-E/SN

MCP6541/1R/1U/2/3/4
Push-Pull Output Sub-Microamp Comparators
Features
Description
•
•
•
•
•
•
•
•
•
•
•
The Microchip Technology Inc. MCP6541/2/3/4 family
of comparators is offered in single (MCP6541,
MCP6541R, MCP6541U), single with Chip Select (CS)
(MCP6543), dual (MCP6542) and quad (MCP6544)
configurations. The outputs are push-pull (CMOS/TTLcompatible) and are capable of driving heavy DC or
capacitive loads.
Low Quiescent Current: 600 nA/comparator (typ.)
Rail-to-Rail Input: VSS - 0.3V to VDD + 0.3V
CMOS/TTL-Compatible Output
Propagation Delay: 4 µs (typ., 100 mV Overdrive)
Wide Supply Voltage Range: 1.6V to 5.5V
Available in Single, Dual and Quad
Single available in SOT-23-5, SC-70-5 * packages
Chip Select (CS) with MCP6543
Low Switching Current
Internal Hysteresis: 3.3 mV (typ.)
Temperature Ranges:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Typical Applications
•
•
•
•
•
•
•
•
Laptop Computers
Mobile Phones
Metering Systems
Hand-held Electronics
RC Timers
Alarm and Monitoring Circuits
Windowed Comparators
Multi-vibrators
These comparators are optimized for low power, singlesupply operation with greater than rail-to-rail input
operation.
The
push-pull
output
of
the
MCP6541/1R/1U/2/3/4 family supports rail-to-rail output
swing and interfaces with TTL/CMOS logic. The internal
input hysteresis eliminates output switching due to internal input noise voltage, reducing current draw. The output limits supply current surges and dynamic power
consumption while switching. This product family operates with a single-supply voltage as low as 1.6V and
draws less than 1 µA/comparator of quiescent current.
The related MCP6546/7/8/9 family of comparators from
Microchip has an open-drain output. Used with a pull-up
resistor, these devices can be used as level-shifters for
any desired voltage up to 10V and in wired-OR logic.
* SC-70-5 E-Temp parts not available at this release of
the data sheet.
MCP6541U SOT-23-5 is E-Temp only.
Related Devices
• Open-Drain Output: MCP6546/7/8/9
Package Types
MCP6541
PDIP, SOIC, MSOP
NC
VDD
OUT
NC
OUT 1
VDD 2
VIN+ 3
MCP6541
SOT-23-5, SC-70-5
5 VDD
-
+
OUT 1
VSS 2
VIN+ 3
4 VIN–
OUTA
VINA–
V
INA+
4 VIN–
VSS
MCP6541U
SOT-23-5
VIN– 1
VSS 2
VIN+ 3
© 2006 Microchip Technology Inc.
MCP6542
PDIP, SOIC, MSOP
5 VSS
+
-
8
7
6
5
+
-
1
2
3
4
+
NC
VIN–
VIN+
VSS
MCP6541R
SOT-23-5
5 VDD
4 OUT
1
2
3
4
-+
8
7
+- 6
5
VDD
OUTA
OUTB VINA–
VINB– VINA+
VDD
VINB+
MCP6543
PDIP, SOIC, MSOP
NC
VIN–
VIN+
VSS
1
2
3
4
+
8
7
6
5
MCP6544
PDIP, SOIC, TSSOP
CS
VDD
1
2 -+ +3
4
14 OUTD
13 VIND–
12 VIND+
11 VSS
10 VINC+
VINB+ 5
VINB– 6 - + + - 9 VINC–
OUTB 7
8 OUTC
OUT
NC
DS21696E-page 1
MCP6541/1R/1U/2/3/4
1.0
ELECTRICAL
CHARACTERISTICS
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at those or any other conditions above those indicated
in the operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
Absolute Maximum Ratings †
VDD - VSS .........................................................................7.0V
Current at Analog Input Pin (VIN+, VIN-.........................±2 mA
†† See Section 4.1.2 “Input Voltage and Current
Limits”
Analog Input (VIN) †† ...................... VSS - 1.0V to VDD + 1.0V
All other Inputs and Outputs........... VSS - 0.3V to VDD + 0.3V
Difference Input voltage ....................................... |VDD - VSS|
Output Short-Circuit Current .................................continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
Storage temperature .....................................-65°C to +150°C
Maximum Junction Temperature (TJ) .......................... +150°C
ESD protection on all pins (HBM;MM) ...................4 kV; 400V
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C,VIN+ = VDD/2,
VIN– = VSS, and RL = 100 kΩ to VDD/2 (Refer to Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
VDD
1.6
—
5.5
V
IQ
0.3
0.6
1.0
µA
Conditions
Power Supply
Supply Voltage
Quiescent Current per comparator
IOUT = 0
Input
Input Voltage Range
VCMR
VSS−0.3
—
VDD+0.3
V
Common Mode Rejection Ratio
CMRR
55
70
—
dB
VDD = 5V, VCM = -0.3V to 5.3V
Common Mode Rejection Ratio
CMRR
50
65
—
dB
VDD = 5V, VCM = 2.5V to 5.3V
Common Mode Rejection Ratio
CMRR
55
70
—
dB
VDD = 5V, VCM = -0.3V to 2.5V
Power Supply Rejection Ratio
PSRR
63
80
—
dB
VCM = VSS
VOS
-7.0
±1.5
+7.0
mV
ΔVOS/ΔTA
—
±3
—
µV/°C
Input Offset Voltage
Drift with Temperature
Input Hysteresis Voltage
VCM = VSS (Note 1)
TA = -40°C to +125°C, VCM = VSS
VHYST
1.5
3.3
6.5
mV
Linear Temp. Co. (Note 2)
TC1
—
6.7
—
µV/°C
Quadratic Temp. Co. (Note 2)
TC2
—
-0.035
—
µV/°C2 TA = -40°C to +125°C, VCM = VSS
IB
—
1
—
At Temperature (I-Temp parts)
IB
—
25
100
pA
TA = +85°C, VCM = VSS (Note 3)
At Temperature (E-Temp parts)
IB
—
1200
5000
pA
TA = +125°C, VCM = VSS (Note 3)
VCM = VSS
Input Bias Current
pA
Input Offset Current
IOS
—
±1
—
pA
Common Mode Input Impedance
ZCM
—
1013||4
—
Ω||pF
Differential Input Impedance
ZDIFF
—
1013||2
—
Ω||pF
Note 1:
2:
3:
4:
VCM = VSS (Note 1)
TA = -40°C to +125°C, VCM = VSS
VCM = VSS
The input offset voltage is the center (average) of the input-referred trip points. The input hysteresis is the difference
between the input-referred trip points.
VHYST at different temperatures is estimated using VHYST (TA) = VHYST + (TA - 25°C) TC1 + (TA - 25°C)2 TC2.
Input bias current at temperature is not tested for SC-70-5 package.
Limit the output current to Absolute Maximum Rating of 30 mA.
DS21696E-page 2
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C,VIN+ = VDD/2,
VIN– = VSS, and RL = 100 kΩ to VDD/2 (Refer to Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
High-Level Output Voltage
VOH
VDD−0.2
—
—
V
Low-Level Output Voltage
VOL
—
—
VSS+0.2
V
ISC
—
-2.5, +1.5
—
mA
VDD = 1.6V (Note 4)
ISC
—
±30
—
mA
VDD = 5.5V (Note 4)
Push-Pull Output
Short-Circuit Current
Note 1:
2:
3:
4:
IOUT = -2 mA, VDD = 5V
IOUT = 2 mA, VDD = 5V
The input offset voltage is the center (average) of the input-referred trip points. The input hysteresis is the difference
between the input-referred trip points.
VHYST at different temperatures is estimated using VHYST (TA) = VHYST + (TA - 25°C) TC1 + (TA - 25°C)2 TC2.
Input bias current at temperature is not tested for SC-70-5 package.
Limit the output current to Absolute Maximum Rating of 30 mA.
AC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2,
Step = 200 mV, Overdrive = 100 mV, and CL = 36 pF (Refer to Figure 1-2 and Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
Rise Time
tR
—
0.85
—
µs
Fall Time
tF
—
0.85
—
µs
tPHL
—
4
8
µs
Propagation Delay (Low-to-High)
tPLH
—
4
8
µs
Propagation Delay Skew
tPDS
—
±0.2
—
µs
Maximum Toggle Frequency
fMAX
—
160
—
kHz
VDD = 1.6V
fMAX
—
120
—
kHz
VDD = 5.5V
Eni
—
200
—
µVP-P
Propagation Delay (High-to-Low)
Input Noise Voltage
Note 1:
Conditions
(Note 1)
10 Hz to 100 kHz
Propagation Delay Skew is defined as: tPDS = tPLH - tPHL.
MCP6543 CHIP SELECT (CS) CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = VSS,
and CL= 36 pF (Refer to Figures 1-1 and 1-3).
Parameters
Sym
Min
Typ
Max
CS Logic Threshold, Low
VIL
CS Input Current, Low
ICSL
CS Logic Threshold, High
CS Input Current, High
CS Input High, VDD Current
Units
Conditions
VSS
—
0.2 VDD
V
—
5.0
—
pA
VIH
0.8 VDD
—
VDD
V
ICSH
—
1
—
pA
CS = VDD
IDD
—
18
—
pA
CS = VDD
CS Input High, GND Current
ISS
—
–20
—
pA
CS = VDD
Comparator Output Leakage
IO(LEAK)
—
1
—
pA
VOUT = VDD, CS = VDD
CS Low to Comparator Output Low
Turn-on Time
tON
—
2
50
ms
CS = 0.2 VDD to VOUT = VDD/2,
VIN– = VDD
CS High to Comparator Output
High Z Turn-off Time
tOFF
—
10
—
µs
CS = 0.8 VDD to VOUT = VDD/2,
VIN– = VDD
VCS_HYST
—
0.6
—
V
VDD = 5V
CS Low Specifications
CS = VSS
CS High Specifications
CS Dynamic Specifications
CS Hysteresis
© 2006 Microchip Technology Inc.
DS21696E-page 3
MCP6541/1R/1U/2/3/4
CS
VIL
VIH
tON
VOUT
ISS
ICS
tOFF
1 pA (typ.)
VIN+ = VDD/2
-0.6 µA (typ.)
1 pA (typ.)
100 mV
tPLH
-20 pA (typ.)
FIGURE 1-1:
Timing Diagram for the CS
Pin on the MCP6543.
DS21696E-page 4
100 mV
Hi-Z
Hi-Z
-20 pA (typ.)
VIN–
VOUT
VOL
FIGURE 1-2:
Diagram.
tPHL
VOH
VOL
Propagation Delay Timing
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V and VSS = GND.
Parameters
Sym
Min
Specified Temperature Range
TA
-40
Operating Temperature Range
TA
-40
Storage Temperature Range
TA
-65
Typ
Max
Units
—
+85
°C
—
+125
°C
—
+150
°C
Conditions
Temperature Ranges
Note
Thermal Package Resistances
Thermal Resistance, 5L-SC-70
θJA
—
331
—
°C/W
Thermal Resistance, 5L-SOT-23
θJA
—
256
—
°C/W
Thermal Resistance, 8L-PDIP
θJA
—
85
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
163
—
°C/W
Thermal Resistance, 8L-MSOP
θJA
—
206
—
°C/W
Thermal Resistance, 14L-PDIP
θJA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
120
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Note:
1.1
The MCP6541/2/3/4 I-Temp parts operate over this extended temperature range, but with reduced performance. In any case, the Junction Temperature (TJ) must not exceed the Absolute Maximum specification
of +150°C.
Test Circuit Configuration
This test circuit configuration is used to determine the
AC and DC specifications.
VDD
200 kΩ
MCP654X
200 kΩ
200 kΩ
VIN = VSS
200 kΩ
VOUT
36 pF
VSS = 0V
FIGURE 1-3:
AC and DC Test Circuit for
the Push-Pull Output Comparators.
© 2006 Microchip Technology Inc.
DS21696E-page 5
MCP6541/1R/1U/2/3/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RL = 100 kΩ to VDD/2, and CL = 36 pF.
18%
1200 Samples
VCM = VSS
12%
Percentage of Occurrences
10%
8%
6%
4%
2%
0%
16%
14%
1200 Samples
VCM = VSS
12%
10%
8%
6%
4%
2%
0%
4
5
6
7
1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0
Input Offset Voltage (mV)
FIGURE 2-4:
VCM = VSS.
5%
1
VIN–
0
-1
0
1
2
3
4
5
6
7
Time (1 ms/div)
8
9
10
FIGURE 2-3:
The MCP6541/1R/1U/2/3/4
comparators show no phase reversal.
DS21696E-page 6
9.4
9.0
8.6
VDD = 1.6V
-0.016
2
-0.020
3
VDD = 5.5V
-0.024
4
596 Samples
VCM = VSS
TA = -40°C to +125°C
-0.056
VOUT
5
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
-0.060
VDD = 5.5V
6
FIGURE 2-5:
Input Hysteresis Voltage
Linear Temp. Co. (TC1) at VCM = VSS.
Percentage of Occurrences
Inverting Input, Output Voltage
(V)
7
8.2
4.6
14
12
8
10
6
4
2
0
-2
-4
-6
-8
-10
-12
Input Hysteresis Voltage –
Linear Temp. Co.; TC1 (µV/°C)
Input Offset Voltage Drift (µV/°C)
Input Offset Voltage Drift at
7.8
0%
0%
FIGURE 2-2:
VCM = VSS.
VDD = 1.6V
-0.028
2%
VDD = 5.5V
7.4
4%
10%
-0.032
6%
7.0
8%
15%
-0.036
10%
596 Samples
VCM = VSS
TA = -40°C to +125°C
20%
6.6
12%
25%
5.4
14%
Input Hysteresis Voltage at
-0.052
1200 Samples
VCM = VSS
TA= -40°C to +125°C
5.0
Input Offset Voltage at
Percentage of Occurrences
16%
-14
Percentage of Occurrences
FIGURE 2-1:
VCM = VSS.
Input Hysteresis Voltage (mV)
-0.040
3
6.2
2
-0.044
1
5.8
-7 -6 -5 -4 -3 -2 -1 0
-0.048
Percentage of Occurrences
14%
Input Hysteresis Voltage –
Quadratic Temp. Co.; TC2 (µV/°C2)
FIGURE 2-6:
Input Hysteresis Voltage
Quadratic Temp. Co. (TC2) at VCM = VSS.
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
VCM = VSS
VDD = 1.6V
VDD = 5.5V
125
3.5
3.0
2.5
TA = -40°C
2.0
Common Mode Input Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-9:
Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 5.5V.
© 2006 Microchip Technology Inc.
4.0
2.0
1.8
1.6
3.5
3.0
2.5
2.0
6.0
5.5
5.0
1.5
4.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-2.0
4.5
4.0
-1.5
5.0
3.5
-1.0
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
3.0
TA = +85°C
TA = +125°C
VDD = 5.5V
2.5
-0.5
5.5
0.0
0.0
6.0
-0.5
TA = -40°C
TA = +25°C
0.5
FIGURE 2-11:
Input Hysteresis Voltage vs.
Common Mode Input Voltage at VDD = 1.6V.
Input Hysteresis Voltage (mV)
Input Offset Voltage (mV)
VDD = 5.5V
1.0
1.4
Common Mode Input Voltage (V)
FIGURE 2-8:
Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 1.6V.
1.5
1.2
1.5
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-2.0
2.0
125
4.0
1.0
-1.5
4.5
2.0
-1.0
100
TA = +125°C
TA = +85°C
TA = +25°C
5.0
1.5
-0.5
VDD = 1.6V
1.0
TA = +125°C
5.5
0.8
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
6.0
0.6
1.0
0.0
0
25
50
75
Ambient Temperature (°C)
0.4
VDD = 1.6V
0.5
-25
0.2
Input Hysteresis Voltage (mV)
Input Offset Voltage (mV)
1.5
-50
FIGURE 2-10:
Input Hysteresis Voltage vs.
Ambient Temperature at VCM = VSS.
FIGURE 2-7:
Input Offset Voltage vs.
Ambient Temperature at VCM = VSS.
2.0
VDD = 5.5V
0.0
0
25
50
75
100
Ambient Temperature (°C)
VDD = 1.6V
-0.2
-25
VCM = VSS
0.5
-50
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
-0.4
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
Input Hysteresis Voltage (mV)
Input Offset Voltage (mV)
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = GND,
RL = 100 kΩ to VDD/2, and CL = 36 pF.
Common Mode Input Voltage (V)
FIGURE 2-12:
Input Hysteresis Voltage vs.
Common Mode Input Voltage at VDD = 5.5V.
DS21696E-page 7
MCP6541/1R/1U/2/3/4
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = GND,
RL = 100 kΩ to VDD/2, and CL = 36 pF.
10000
10n
Input Bias, Offset Currents (A)
90
Input Referred
CMRR, PSRR (dB)
85
80
75
PSRR, VIN+ = VSS, VDD = 1.6V to 5.5V
70
65
CMRR, VIN+ = -0.3 to 5.3V, VDD = 5.0V
60
55
-50
-25
0
25
50
75
Ambient Temperature (°C)
1000
125
CMRR,PSRR vs. Ambient
IB
| IOS |
1
10p
10
IOS, TA = +125°C
1p
1
FIGURE 2-16:
Input Bias Current, Input
Offset Current vs. Common Mode Input Voltage.
0.6
0.5
0.4
0.2
0.1
65
75
85
95
105
115
125
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Ambient Temperature (°C)
FIGURE 2-14:
Input Bias Current, Input
Offset Current vs. Ambient Temperature.
FIGURE 2-17:
Quiescent Current vs.
Power Supply Voltage.
0.7
VDD = 1.6V
Quiescent Current
per Comparator (µA)
Quiescent Current
per comparator (µA)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0.3
0.0
55
0.5
0.4
0.3
0.2
IOS, TA = +85°C
100f
0.1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.1
0.6
IB, TA = +85°C
0.7
10
0.7
VDD = 5.5V
Common Mode Input Voltage (V)
VDD = 5.5V
VCM = VDD
100
100p
100
Quiescent Current
per Comparator (µA)
Input Bias, Offset Currents
(pA)
FIGURE 2-13:
Temperature.
100
IB, TA = +125°C
1000
1n
Sweep VIN+, VIN– = VDD/2
0.1
Sweep VIN–, VIN+ = VDD/2
0.6
VDD = 5.5V
0.5
0.4
0.3
0.2
0.1
Sweep VIN+, VIN– = VDD/2
Sweep VIN–, VIN+ = VDD/2
0.0
0.0
0.0
0.2 0.4 0.6 0.8 1.0 1.2 1.4
Common Mode Input Voltage (V)
1.6
FIGURE 2-15:
Quiescent Current vs.
Common Mode Input Voltage at VDD = 1.6V.
DS21696E-page 8
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
FIGURE 2-18:
Quiescent Current vs.
Common Mode Input Voltage at VDD = 5.5V.
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
Supply Current (µA)
10
Output Short Circuit Current
Magnitude (mA)
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = GND,
RL = 100 kΩ to VDD/2, and CL = 36 pF.
100 mV Overdrive
VCM = VDD/2
RL = infinity
1
VDD = 5.5V
VDD = 1.6V
35
25
20
15
10
0.1
1
10
Toggle Frequency (kHz)
Supply Current vs. Toggle
0.8
0.7
0.6
0.5
0.4
VDD = 1.6V
VOL–VSS:
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
VDD–VOH:
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0.3
0.2
0.1
0.0
0.0
0.5
1.0
1.5
2.0
Output Current (mA)
2.5
35%
30%
25%
20%
VDD = 1.6V
10%
VOL – VSS:
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
VDD = 5.5V
5%
0%
VDD – VOH:
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
VDD = 5.5V
5
10
15
Output Current (mA)
20
25
FIGURE 2-23:
Output Voltage Headroom
vs. Output Current at VDD = 5.5V.
45%
600 Samples
100 mV Overdrive
VCM = VDD/2
15%
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
Percentage of Occurrences
40%
FIGURE 2-22:
Output Short Circuit Current
Magnitude vs. Power Supply Voltage.
3.0
FIGURE 2-20:
Output Voltage Headroom
vs. Output Current at VDD = 1.6V.
45%
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
100
Output Voltage Headroom (V)
FIGURE 2-19:
Frequency.
Output Voltage Headroom (V)
5
0
0.1
Percentage of Occurrences
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
30
600 Samples
100 mV Overdrive
VCM = VDD/2
40%
35%
30%
25%
20%
15%
VDD = 1.6V
10%
VDD = 5.5V
5%
0%
0
1
2
3
4
5
6
7
8
0
1
High-to-Low Propagation Delay (µs)
FIGURE 2-21:
Delay.
High-to-Low Propagation
© 2006 Microchip Technology Inc.
2
3
4
5
6
7
8
Low-to-High Propagation Delay (µs)
FIGURE 2-24:
Delay.
Low-to-High Propagation
DS21696E-page 9
MCP6541/1R/1U/2/3/4
45%
8
600 Samples
100 mV Overdrive
VCM = VDD/2
40%
35%
30%
25%
20%
VDD = 1.6V
VDD = 5.5V
15%
10%
5%
Propagation Delay (µs)
Percentage of Occurrences
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = GND,
RL = 100 kΩ to VDD/2, and CL = 36 pF.
0%
100 mV Overdrive
VCM = VDD/2
7
6
5
tPLH @ VDD = 5.5V
tPHL @ VDD = 5.5V
tPLH @ VDD = 1.6V
tPHL @ VDD = 1.6V
4
3
2
1
0
-2.0 -1.5 -1.0 -0.5
0.0
0.5
1.0
1.5
2.0
-50
-25
Propagation Delay Skew (µs)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Propagation Delay Skew.
100
VCM = VDD/2
tPLH @ 10 mV Overdrive
tPHL @ 10 mV Overdrive
tPLH @ 100 mV Overdrive
tPHL @ 100 mV Overdrive
2.0
2.5
3.0 3.5
4.0
4.5
Power Supply Voltage (V)
5.0
10
tPLH @ VDD = 5.5V
FIGURE 2-29:
Overdrive.
8
VDD = 1.6V
100 mV Overdrive
6
5
tPLH
4
3
tPHL
2
1
Propagation Delay (µs)
Propagation Delay (µs)
VCM = VDD/2
tPHL @ VDD = 5.5V
tPLH @ VDD = 1.6V
tPHL @ VDD = 1.6V
5.5
FIGURE 2-26:
Propagation Delay vs.
Power Supply Voltage.
7
125
1
1.5
8
100
FIGURE 2-28:
Propagation Delay vs.
Ambient Temperature.
Propagation Delay (µs)
Propagation Delay (µs)
FIGURE 2-25:
0
25
50
75
Ambient Temperature (°C)
1
0
7
10
100
Input Overdrive (mV)
1000
Propagation Delay vs. Input
VDD = 5.5V
100 mV Overdrive
6
5
4
3
tPHL
tPLH
2
1
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Common Mode Input Voltage (V)
1.6
FIGURE 2-27:
Propagation Delay vs.
Common Mode Input Voltage at VDD = 1.6V.
DS21696E-page 10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
FIGURE 2-30:
Propagation Delay vs.
Common Mode Input Voltage at VDD = 5.5V.
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
Chip Select, Output Voltage (V)
100 mV Overdrive
VCM = VDD/2
tPHL @ VDD = 1.6V
tPLH @ VDD = 1.6V
tPHL @ VDD = 5.5V
tPLH @ VDD = 5.5V
0
10
20
FIGURE 2-31:
Capacitance.
1.E-03
1m
Supply Current
per Comparator (A)
1.E-04
100µ
30 40 50 60 70
Load Capacitance (nF)
80
90
Propagation Delay vs. Load
Comparator
Shuts Off
VOUT
CS
0
1
2
CS Hysteresis
100n
1.E-07
CS
High-to-Low
CS
Low-to-High
VDD = 1.6V
10p
1.E-11
0.0 0.2 0.4
0.6
0.8
1.0
1.2
1.4
1.6
Comparator
Turns On
100µ
1.E-04
9
10
Comparator
Shuts Off
10µ
1.E-05
CS
Hysteresis
100n
1.E-07
10n
1.E-08
CS
Low-to-High
1n
1.E-09
CS
High-to-Low
VDD = 5.5V
10p
1.E-11
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
25
CS
Charging output
capacitance
0.0
-1.6
VDD = 1.6V
15
1.6
Start-up
IDD
0
-3.2
-4.9
-6.5
-8.1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Time (1 ms/div)
FIGURE 2-33:
Supply Current (charging
current) vs. Chip Select (CS) pulse at VDD = 1.6V
(MCP6543 only).
© 2006 Microchip Technology Inc.
FIGURE 2-35:
Supply Current (shoot
through current) vs. Chip Select (CS) Voltage at
VDD = 5.5V (MCP6543 only).
Supply Current
per Comparator (µA)
VOUT
Output Voltage,
Chip Select Voltage (V),
30
Supply Current (µA)
8
Chip Select (CS) Voltage (V)
FIGURE 2-32:
Supply Current (shoot
through current) vs. Chip Select (CS) Voltage at
VDD = 1.6V (MCP6543 only).
5
7
FIGURE 2-34:
Chip Select (CS) Step
Response (MCP6543 only).
Chip Select (CS) Voltage (V)
10
4
5
6
Time (ms)
100p
1.E-10
100p
1.E-10
20
3
1µ
1.E-06
1µ
1.E-06
1n
1.E-09
VDD = 5.5V
1.E-03
1m
Comparator
Turns On
10µ
1.E-05
10n
1.E-08
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
200
180
160
140
120
100
80
60
40
20
0
VOUT
6
3
0
-3
-6
-9
-12
-15
-18
-21
-24
CS
Start-up IDD
VDD = 5.5V
Charging output
capacitance
0.0
0.5
1.0 1.5 2.0 2.5 3.0
Time (0.5 ms/div)
Output Voltage,
Chip Select Voltage (V)
50
45
40
35
30
25
20
15
10
5
0
Supply Current
per Comparator (A)
Propagation Delay (µs)
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = GND,
RL = 100 kΩ to VDD/2, and CL = 36 pF.
3.5
FIGURE 2-36:
Supply Current (charging
current) vs. Chip Select (CS) pulse at VDD = 5.5V
(MCP6543 only).
DS21696E-page 11
MCP6541/1R/1U/2/3/4
Input Current Magnitude (A)
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2, VIN– = GND,
RL = 100 kΩ to VDD/2, and CL = 36 pF.
1.E-02
10m
1.E-03
1m
1.E-04
100µ
1.E-05
10µ
1µ
1.E-06
100n
1.E-07
10n
1.E-08
1n
1.E-09
100p
1.E-10
10p
1.E-11
1p
1.E-12
+125°C
+85°C
+25°C
-40°C
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-37:
Voltage
DS21696E-page 12
Input Bias Current vs. Input
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
1
1
4
1
6
1
2
4
4
1
2
2
2
VIN–, VINA– Inverting Input (comparator A)
3
3
3
3
3
3
3
VIN+, VINA+ Non-inverting Input (comparator A)
MCP6544
MCP6542
6
MCP6541
MCP6541
(PDIP,
(SOT-23-5,
SOIC,
SC-70-5)
MSOP)
MCP6543
MCP6541U
PIN FUNCTION TABLE
MCP6541R
TABLE 3-1:
Symbol
Description
OUT, OUTA Digital Output (comparator A)
7
5
2
5
8
7
4
VDD
—
—
—
—
5
—
5
VINB+
Non-inverting Input (comparator B)
—
—
—
—
6
—
6
VINB–
Inverting Input (comparator B)
—
—
—
—
7
—
7
OUTB
Digital Output (comparator B)
—
—
—
—
—
—
8
OUTC
Digital Output (comparator C)
—
—
—
—
—
—
9
VINC–
Inverting Input (comparator C)
—
—
—
—
—
—
10
VINC+
Non-inverting Input (comparator C)
4
2
5
2
4
4
11
VSS
—
—
—
—
—
—
12
VIND+
Non-inverting Input (comparator D)
—
—
—
—
—
—
13
VIND–
Inverting Input (comparator D)
—
—
—
—
—
—
14
OUTD
—
—
—
—
—
8
—
CS
Chip Select
1, 5, 8
—
—
—
—
1, 5
—
NC
No Internal Connection
3.1
Analog Inputs
The comparator non-inverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
3.2
CS Digital Input
This is a CMOS, Schmitt-triggered input that places the
part into a low power mode of operation.
3.3
Digital Outputs
The comparator outputs are CMOS, push-pull digital
outputs. They are designed to be compatible with
CMOS and TTL logic and are capable of driving heavy
DC or capacitive loads.
© 2006 Microchip Technology Inc.
3.4
Positive Power Supply
Negative Power Supply
Digital Output (comparator D)
Power Supply (VSS and VDD)
The positive power supply pin (VDD) is 1.6V to 5.5V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These can share a
bulk capacitor with nearby analog parts (within
100 mm), but it is not required.
DS21696E-page 13
MCP6541/1R/1U/2/3/4
4.0
APPLICATIONS INFORMATION
The MCP6541/2/3/4 family of push-pull output comparators are fabricated on Microchip’s state-of-the-art
CMOS process. They are suitable for a wide range of
applications requiring very low power consumption.
4.1
the resistors R1 and R2 limit the possible current drawn
out of the input pin. Diodes D1 and D2 prevent the input
pin (VIN+ and VIN–) from going too far above VDD.
When implemented as shown, resistors R1 and R2 also
limit the current through D1 and D2.
VDD
Comparator Inputs
4.1.1
PHASE REVERSAL
The MCP6541/1R/1U/2/3/4 comparator family uses
CMOS transistors at the input. They are designed to
prevent phase inversion when the input pins exceed
the supply voltages. Figure 2-3 shows an input voltage
exceeding both supplies with no resulting phase
inversion.
4.1.2
Bond
Pad
VIN+ Bond
Pad
Input
Stage
Bond
Pad
VIN–
FIGURE 4-1:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these amplifiers, the circuits they are in must limit the
currents (and voltages) at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-3
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
DS21696E-page 14
MCP6G0X
–
VOUT
D2
V2
R2
R3
R1 ≥
VSS – (minimum expected V1)
2 mA
R2 ≥
VSS – (minimum expected V2)
2 mA
FIGURE 4-2:
Protecting the Analog Inputs.
It is also possible to connect the diodes to the left of the
resistors R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistor then serves as in-rush current
limiter; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-37. Applications that are
high impedance may need to limit the useable voltage
range.
4.1.3
VSS Bond
Pad
+
R1
INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass ESD
events within the specified limits.
VDD
D1
V1
NORMAL OPERATION
The input stage of this family of devices uses two
differential input stages in parallel: one operates at low
input voltages and the other at high input voltages. With
this topology, the input voltage is 0.3V above VDD and
0.3V below VSS. Therefore, the input offset voltage is
measured at both VSS - 0.3V and VDD + 0.3V to ensure
proper operation.
The MCP6541/1R/1U/2/3/4 family has internally-set
hysteresis that is small enough to maintain input offset
accuracy (<7 mV) and large enough to eliminate output
chattering caused by the comparator’s own input noise
voltage (200 µVp-p). Figure 4-3 depicts this behavior.
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
VDD = 5.0V
VIN–
VOUT
Hysteresis
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
Input Voltage (10 mV/div)
Output Voltage (V)
4.4
8
7
6
5
4
3
2
1
0
-1
-2
-3
Time (100 ms/div)
FIGURE 4-3:
The MCP6541/2/3/4
comparators’ internal hysteresis eliminates
output chatter caused by input noise voltage.
4.2
Push-Pull Output
The push-pull output is designed to be compatible with
CMOS and TTL logic, while the output transistors are
configured to give rail-to-rail output performance. They
are driven with circuitry that minimizes any switching
current (shoot-through current from supply-to-supply)
when the output is transitioned from high-to-low, or from
low-to-high (see Figures 2-15, 2-18, 2-32 through 2-36
for more information).
4.3
MCP6543 Chip Select (CS)
The MCP6543 is a single comparator with Chip Select
(CS). When CS is pulled high, the total current
consumption drops to 20 pA (typ.); 1 pA (typ.) flows
through the CS pin, 1 pA (typ.) flows through the output pin and 18 pA (typ.) flows through the VDD pin, as
shown in Figure 1-1. When this happens, the
comparator output is put into a high-impedance state.
By pulling CS low, the comparator is enabled. If the CS
pin is left floating, the comparator will not operate
properly. Figure 1-1 shows the output voltage and
supply current response to a CS pulse.
The internal CS circuitry is designed to minimize
glitches when cycling the CS pin. This helps conserve
power, which is especially important in battery-powered
applications.
Externally Set Hysteresis
Greater flexibility in selecting hysteresis (or input trip
points) is achieved by using external resistors.
Input offset voltage (VOS) is the center (average) of the
(input-referred) low-high and high-low trip points. Input
hysteresis voltage (VHYST) is the difference between
the same trip points. Hysteresis reduces output
chattering when one input is slowly moving past the
other and thus reduces dynamic supply current. It also
helps in systems where it is best not to cycle between
states too frequently (e.g., air conditioner thermostatic
control).
4.4.1
NON-INVERTING CIRCUIT
Figure 4-4 shows a non-inverting circuit for singlesupply applications using just two resistors. The
resulting hysteresis diagram is shown in Figure 4-5.
VDD
-
VREF
VOUT
MCP654X
+
VIN
R1
RF
FIGURE 4-4:
Non-inverting circuit with
hysteresis for single-supply.
VOUT
VDD
VOH
High-to-Low
VOL
VSS
VSS
Low-to-High
VIN
VTHL VTLH
VDD
FIGURE 4-5:
Hysteresis Diagram for the
Non-Inverting Circuit.
The trip points for Figures 4-4 and 4-5 are:
EQUATION 4-1:
R ⎞
⎛
⎛R 1 ⎞
V TLH = V REF ⎜ 1 + ------1- ⎟ – V OL ⎜------- ⎟
RF ⎠
⎝
⎝R F ⎠
R ⎞
⎛
⎛R1 ⎞
V THL = V REF ⎜ 1 + ------1- ⎟ – V OH ⎜------- ⎟
RF ⎠
⎝
⎝R F ⎠
VTLH = trip voltage from low to high
VTHL = trip voltage from high to low
© 2006 Microchip Technology Inc.
DS21696E-page 15
MCP6541/1R/1U/2/3/4
4.4.2
INVERTING CIRCUIT
Where:
Figure 4-6 shows an inverting circuit for single-supply
using three resistors. The resulting hysteresis diagram
is shown in Figure 4-7.
R2 R3
R 23 = -----------------R2 + R3
R3
V 23 = ------------------ × V DD
R2 + R3
VDD
VIN
VDD
Using this simplified circuit, the trip voltage can be
calculated using the following equation:
VOUT
MCP654X
R2
EQUATION 4-2:
RF
⎛ R 23 ⎞
V THL = V OH ⎜ -----------------------⎟ + V 23 ⎛ ----------------------⎞
⎝
⎠
R
+
R
R
⎝ 23
23 + R F
F⎠
RF
R3
RF
⎛ R 23 ⎞
V TLH = V OL ⎜ -----------------------⎟ + V 23 ⎛ ----------------------⎞
⎝
⎠
R
+
R
R
⎝ 23
23 + R F
F⎠
FIGURE 4-6:
Hysteresis.
Inverting Circuit With
VTLH = trip voltage from low to high
VTHL = trip voltage from high to low
VOUT
Figure 2-20 and Figure 2-23 can be used to determine
typical values for VOH and VOL.
VDD
VOH
Low-to-High
High-to-Low
4.5
VIN
VOL
VSS
VSS
VTLH VTHL
FIGURE 4-7:
Inverting Circuit.
VDD
Hysteresis Diagram for the
In order to determine the trip voltages (VTHL and VTLH)
for the circuit shown in Figure 4-6, R2 and R3 can be
simplified to the Thevenin equivalent circuit with
respect to VDD, as shown in Figure 4-8.
VDD
MCP654X
+
VSS
VOUT
V23
R23
FIGURE 4-8:
DS21696E-page 16
With this family of comparators, the power supply pin
(VDD for single supply) should have a local bypass
capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good
edge rate performance.
4.6
Capacitive Loads
Reasonable capacitive loads (e.g., logic gates) have
little impact on propagation delay (see Figure 2-31).
The supply current increases with increasing toggle
frequency (Figure 2-19), especially with higher
capacitive loads.
4.7
-
Bypass Capacitors
Battery Life
In order to maximize battery life in portable
applications, use large resistors and small capacitive
loads. Avoid toggling the output more than necessary.
Do not use Chip Select (CS) frequently to conserve
start-up power. Capacitive loads will draw additional
power at start-up.
RF
Thevenin Equivalent Circuit.
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
4.8
PCB Surface Leakage
4.9
Unused Comparators
In applications where low input bias current is critical,
PCB (Printed Circuit Board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow. This is greater than the
MCP6541/1R/1U/2/3/4 family’s bias current at 25°C
(1 pA, typ.).
An unused amplifier in a quad package (MCP6544)
should be configured as shown in Figure 4-10. This
circuit prevents the output from toggling and causing
crosstalk. It uses the minimum number of components
and draws minimal current (see Figure 2-15 and
Figure 2-18).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-9.
VDD
VIN-
VIN+
¼ MCP6544
–
VSS
+
FIGURE 4-10:
Unused Comparators.
Guard Ring
FIGURE 4-9:
Example Guard Ring Layout
for Inverting Circuit.
1.
2.
Inverting Configuration (Figures 4-6 and 4-9):
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the
comparator (e.g., VDD/2 or ground).
b. Connect the inverting pin (VIN–) to the input
pad without touching the guard ring.
Non-inverting Configuration (Figure 4-4):
a. Connect the non-inverting pin (VIN+) to the
input pad without touching the guard ring.
b. Connect the guard ring to the inverting input
pin (VIN–).
© 2006 Microchip Technology Inc.
DS21696E-page 17
MCP6541/1R/1U/2/3/4
4.10
4.10.1
Typical Applications
4.10.3
PRECISE COMPARATOR
Some applications require higher DC precision. An
easy way to solve this problem is to use an amplifier
(such as the MCP6041) to gain-up the input signal
before it reaches the comparator. Figure 4-11 shows an
example of this approach.
BISTABLE MULTI-VIBRATOR
A simple bistable multi-vibrator design is shown in
Figure 4-13. VREF needs to be between the power
supplies (VSS = GND and VDD) to achieve oscillation.
The output duty cycle changes with VREF.
R1
R2
VREF
VDD
VDD
VREF
MCP6541
MCP6041
VOUT
VDD
VIN
R1
R2
MCP654X
VREF
FIGURE 4-11:
Comparator.
4.10.2
C1
VOUT
FIGURE 4-13:
R3
Bistable Multi-vibrator.
Precise Inverting
WINDOWED COMPARATOR
Figure 4-12 shows one approach to designing a windowed comparator. The AND gate produces a logic ‘1’
when the input voltage is between VRB and VRT (where
VRT > VRB).
VRT
VIN
VRB
FIGURE 4-12:
DS21696E-page 18
1/2
MCP6542
1/2
MCP6542
Windowed Comparator.
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
5.0
PACKAGING INFORMATION
5.1
Package Marking Information
5-Lead SC-70 (MCP6541)
XXNN Front)
YWW (Back)
Example:
Device
I-Temp
Code
E-Temp
Code
MCP6541U
ABNN
Note 2
Note 1:
2:
I-Temp parts prior to March
2005 are marked “ABN”
SC-70-5 E-Temp parts not
available at this release of
this data sheet.
Example:
5-Lead SOT-23 (MCP6541, MCP6541R, MCP6541U)
Device
XXNN
XXXXXXXX
XXXXXNNN
YYWW
ABNN
GTNN
AGNN
GUNN
—
ATNN
8-Lead MSOP
Applies to 5-Lead SOT-23
Example:
OR
MCP6541
e3
E/P^^256
0636
Example:
MCP6542
I/SN0636
256
OR
MCP6541E
SN^^0636
e3
256
Example:
XXXXXX
6543I
YWWNNN
636256
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
AB25
MCP6541
I/P256
0636
8-Lead SOIC (150 mil)
XXXXXXXX
XXXXYYWW
NNN
E-Temp
Code
MCP6541R
Note:
8-Lead PDIP (300 mil)
I-Temp
Code
MCP6541
MCP6541U
AB25 Front)
636 (Back)
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2006 Microchip Technology Inc.
DS21696E-page 19
MCP6541/1R/1U/2/3/4
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6544)
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
MCP6544-I/P
XXXXXXXXXXXXXX
0636256
OR
MCP6544E/P e3
0636256
MCP6544
I/P^^
e3
0636256
OR
14-Lead SOIC (150 mil) (MCP6544)
Example:
MCP6544ISL
XXXXXXXXXX
0636256
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
MCP6544
e3
E/SL^^
0636256
OR
14-Lead TSSOP (MCP6544)
XXXXXXXX
YYWW
NNN
DS21696E-page 20
Example:
MCP6544I
0636
256
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
5-Lead Plastic Small Outline Transistor (LT) (SC-70)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
D
p
B
n
1
Q1
A2
c
A1
L
Units
Dimension Limits
A
INCHES
MIN
NOM
MILLIMETERS*
MAX
MIN
NOM
MAX
Pitch
n
p
Overall Height
A
.031
.043
0.80
1.10
Molded Package Thickness
A2
.031
.039
0.80
1.00
Standoff
A1
.000
.004
0.00
0.10
Overall Width
E
.071
.094
1.80
2.40
Molded Package Width
E1
.045
.053
1.15
1.35
Overall Length
D
.071
.087
1.80
2.20
Foot Length
L
.004
.012
0.10
0.30
Q1
.004
.016
0.10
0.40
Lead Thickness
c
.004
.007
0.10
0.18
Lead Width
B
.006
.012
0.15
0.30
Number of Pins
Top of Molded Pkg to
Lead Shoulder
5
5
.026 (BSC)
0.65 (BSC)
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
JEITA (EIAJ) Standard: SC-70
Drawing No. C04-061
© 2006 Microchip Technology Inc.
Revised 07-19-05
DS21696E-page 21
MCP6541/1R/1U/2/3/4
5-Lead Plastic Small Outline Transistor (OT) (SOT23)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
B
p1
n
D
1
α
c
A
φ
L
β
A1
INCHES*
Units
Dimension Limits
A2
MIN
MILLIMETERS
NOM
MAX
MIN
NOM
Pitch
n
p
.038
0.95
Outside lead pitch (basic)
p1
.075
1.90
Number of Pins
Overall Height
5
MAX
5
A
.035
.046
.057
0.90
1.18
1.45
Molded Package Thickness
A2
.035
.043
.051
0.90
1.10
1.30
Standoff
A1
.000
.003
.006
0.00
0.08
0.15
Overall Width
E
.102
.110
.118
2.60
2.80
3.00
Molded Package Width
E1
.059
.064
.069
1.50
1.63
1.75
Overall Length
D
.110
.116
.122
2.80
2.95
3.10
Foot Length
.014
.018
.022
0.35
0.45
Foot Angle
L
f
Lead Thickness
c
.004
Lead Width
B
a
.014
Mold Draft Angle Top
Mold Draft Angle Bottom
b
0
5
.006
.017
10
0
0.55
5
.008
0.09
0.15
.020
0.35
0.43
10
0.20
0.50
0
5
10
0
5
10
0
5
10
0
5
10
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
EIAJ Equivalent: SC-74A
Revised 09-12-05
Drawing No. C04-091
DS21696E-page 22
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
p
eB
B
Units
Dimension Limits
n
p
INCHES*
NOM
8
.100
.155
.130
MAX
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MAX
Number of Pins
Pitch
Top to Seating Plane
A
.140
.170
4.32
Molded Package Thickness
A2
.115
.145
3.68
Base to Seating Plane
.015
A1
Shoulder to Shoulder Width
E
.300
.313
.325
8.26
Molded Package Width
E1
.240
.250
.260
6.60
Overall Length
D
.360
.373
.385
9.78
Tip to Seating Plane
L
.125
.130
.135
3.43
c
Lead Thickness
.008
.012
.015
0.38
Upper Lead Width
B1
.045
.058
.070
1.78
Lower Lead Width
B
.014
.018
.022
0.56
eB
Overall Row Spacing
§
.310
.370
.430
10.92
α
Mold Draft Angle Top
5
10
15
15
β
Mold Draft Angle Bottom
5
10
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
© 2006 Microchip Technology Inc.
MIN
MIN
DS21696E-page 23
MCP6541/1R/1U/2/3/4
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
INCHES*
NOM
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
.009
.017
12
12
MAX
MILLIMETERS
NOM
8
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
6.02
3.71
3.91
4.80
4.90
0.25
0.38
0.48
0.62
0
4
0.20
0.23
0.33
0.42
0
12
0
12
MAX
Number of Pins
Pitch
Overall Height
A
.053
.069
1.75
Molded Package Thickness
A2
.052
.061
1.55
Standoff
§
A1
.004
.010
0.25
Overall Width
E
.228
.244
6.20
Molded Package Width
E1
.146
.157
3.99
Overall Length
D
.189
.197
5.00
Chamfer Distance
h
.010
.020
0.51
Foot Length
L
.019
.030
0.76
φ
Foot Angle
0
8
8
c
Lead Thickness
.008
.010
0.25
Lead Width
B
.013
.020
0.51
α
Mold Draft Angle Top
0
15
15
β
Mold Draft Angle Bottom
0
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS21696E-page 24
MIN
A1
MIN
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
e
b
A2
A
ϕ
c
L1
A1
Number of Pins
Pitch
Overall Height
Molded Package
Standoff
Overall Width
Molded Package
Overall Length
Foot Length
Footprint
Foot Angle
Lead Thickness
Lead Width
Units
Dimension Limits
N
e
A
Thickness
A2
A1
E
Width
E1
D
L
L1
ϕ
c
b
MIN
—
0.75
0.00
0.40
0°
0.08
0.22
MILLIMETERS
NOM
8
0.65 BSC
—
0.85
—
4.90 BSC
3.00 BSC
3.00 BSC
0.60
0.95 REF
—
—
—
L
MAX
1.10
0.95
0.15
0.80
8°
0.23
0.40
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions
shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04–111, Sept. 8, 2006
© 2006 Microchip Technology Inc.
DS21696E-page 25
MCP6541/1R/1U/2/3/4
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
eB
B1
p
B
Units
Dimension Limits
n
p
INCHES*
NOM
14
.100
.155
.130
MAX
MILLIMETERS
NOM
14
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
18.80
19.05
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MAX
Number of Pins
Pitch
Top to Seating Plane
A
.140
.170
4.32
Molded Package Thickness
A2
.115
.145
3.68
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.313
.325
8.26
Molded Package Width
.240
.250
.260
6.60
E1
Overall Length
D
.740
.750
.760
19.30
Tip to Seating Plane
L
.125
.130
.135
3.43
c
Lead Thickness
.008
.012
.015
0.38
Upper Lead Width
B1
.045
.058
.070
1.78
Lower Lead Width
B
.014
.018
.022
0.56
eB
Overall Row Spacing
§
.310
.370
.430
10.92
α
Mold Draft Angle Top
5
10
15
15
β
Mold Draft Angle Bottom
5
10
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
DS21696E-page 26
MIN
MIN
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
L
β
Units
Dimension Limits
n
p
INCHES*
NOM
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
.009
.017
12
12
MAX
MILLIMETERS
NOM
14
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
5.99
3.81
3.90
8.56
8.69
0.25
0.38
0.41
0.84
0
4
0.20
0.23
0.36
0.42
0
12
0
12
MAX
Number of Pins
Pitch
Overall Height
A
.053
.069
1.75
Molded Package Thickness
A2
.052
.061
1.55
Standoff
§
A1
.004
.010
0.25
Overall Width
E
.228
.244
6.20
Molded Package Width
.150
.157
3.99
E1
Overall Length
D
.337
.347
8.81
Chamfer Distance
h
.010
.020
0.51
Foot Length
L
.016
.050
1.27
φ
Foot Angle
0
8
8
c
Lead Thickness
.008
.010
0.25
Lead Width
B
.014
.020
0.51
α
Mold Draft Angle Top
0
15
15
β
Mold Draft Angle Bottom
0
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
Revised 7-20-06
© 2006 Microchip Technology Inc.
MIN
A1
MIN
DS21696E-page 27
MCP6541/1R/1U/2/3/4
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
1
n
B
α
A
c
φ
β
L
Units
Dimension Limits
A1
A2
MILLIMETERS*
INCHES
MIN
NOM
MAX
MIN
NOM
MAX
Pitch
n
p
Overall Height
A
.039
.041
.043
1.00
1.05
Molded Package Thickness
A2
.033
.035
.037
0.85
0.90
0.95
Standoff
A1
.002
.004
.006
0.05
0.10
0.15
Overall Width
E
.246
.251
.256
6.25
6.38
6.50
Molded Package Width
E1
.169
.173
.177
4.30
4.40
4.50
Molded Package Length
D
.193
.197
.201
4.90
5.00
5.10
Foot Length
L
φ
.020
.024
.028
0.50
0.60
0.70
Foot Angle
Lead Thickness
c
.004
Lead Width
B
α
.007
Mold Draft Angle Top
Mold Draft Angle Bottom
β
Number of Pins
14
14
.026 BSC
0.65 BSC
4°
0°
8°
0°
.006
.008
0.09
.010
.012
0.19
4°
1.10
8°
0.15
0.20
0.25
0.30
12° REF
12° REF
12° REF
12° REF
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold fla sh or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tole rance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent: MO-153 AB-1
Drawing No. C04-087
DS21696E-page 28
Revised: 08-17-05
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
APPENDIX A:
REVISION HISTORY
Revision E (September 2006)
The following is the list of modifications:
1.
2.
3.
4.
Added MCP6541U pinout for the SOT-23-5
package.
Clarified Absolute Maximum Analog Input
Voltage and Current Specifications.
Added applications writeups on unused
comparators.
Added disclaimer to package outline drawings.
Revision D (May 2006)
The following is the list of modifications:
1.
2.
3.
4.
5.
6.
Added E-temp parts.
Changed VHYST temperature specification to
linear and quadratic temperature coefficients.
Changed specifications and plots for E-Temp.
Added Section 3.0 Pin Descriptions
Corrected package marking (See Section 5.1
“Package Marking Information”)
Added Appendix A: Revision History.
Revision C (September 2003)
Revision B (November 2002)
Revision A (March 2002)
• Original Release of this Document.
© 2006 Microchip Technology Inc.
DS21696E-page 29
MCP6541/1R/1U/2/3/4
NOTES:
DS21696E-page 30
© 2006 Microchip Technology Inc.
MCP6541/1R/1U/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
-X
/XX
Device
Temperature
Range
Package
Examples:
a)
b)
Device:
MCP6541:
MCP6541T:
MCP6541RT:
MCP6541UT:
MCP6542:
MCP6542T:
MCP6543:
MCP6543T:
MCP6544:
MCP6544T:
Temperature Range:
Single Comparator
Single Comparator (Tape and Reel)
(SC-70, SOT-23, SOIC, MSOP)
Single Comparator (Rotated - Tape and
Reel) (SOT-23 only)
Single Comparator (Tape and Reel)
(SOT-23-5 is E-Temp only)
Dual Comparator
Dual Comparator
(Tape and Reel for SOIC and MSOP)
Single Comparator with CS
Single Comparator with CS
(Tape and Reel for SOIC and MSOP)
Quad Comparator
Quad Comparator
(Tape and Reel for SOIC and TSSOP)
I
= -40°C to +85°C
E * = -40°C to +125°C
* SC-70-5 E-Temp parts not available at this release of the
data sheet.
Package:
LT
OT
MS
P
SN
SL
ST
=
=
=
=
=
=
=
Plastic Package (SC-70), 5-lead
Plastic Small Outline Transistor (SOT-23), 5-lead
Plastic MSOP, 8-lead
Plastic DIP (300 mil Body), 8-lead, 14-lead
Plastic SOIC (150 mil Body), 8-lead
Plastic SOIC (150 mil Body), 14-lead (MCP6544)
Plastic TSSOP (4.4mm Body), 14-lead (MCP6544)
c)
d)
e)
f)
a)
b)
c)
d)
a)
b)
c)
d)
a)
b)
c)
d)
© 2006 Microchip Technology Inc.
MCP6541T-I/LT:
Tape and Reel,
Industrial Temperature,
5LD SC-70.
MCP6541T-I/OT: Tape and Reel,
Industrial Temperature,
5LD SOT-23.
MCP6541-E/P:
Extended Temperature,
8LD PDIP.
MCP6541RT-I/OT: Tape and Reel,
Industrial Temperature,
5LD SOT23.
MCP6541-E/SN: Extended Temperature,
8LD SOIC.
MCP6541UT-E/OT:Tape and Reel,
Extended Temperature,
5LD SOT23.
MCP6542-I/MS:
Industrial Temperature,
8LD MSOP.
MCP6542T-I/MS: Tape and Reel,
Industrial Temperature,
8LD MSOP.
MCP6542-I/P:
Industrial Temperature,
8LD PDIP.
MCP6542-E/SN: Extended Temperature,
8LD SOIC.
MCP6543-I/SN:
Industrial Temperature,
8LD SOIC.
MCP6543T-I/SN: Tape and Reel,
Industrial Temperature,
8LD SOIC.
MCP6543-I/P:
Industrial Temperature,
8LD PDIP.
MCP6543-E/SN: Extended Temperature,
8LD SOIC.
MCP6544T-I/SL:
Tape and Reel,
Industrial Temperature,
14LD SOIC.
MCP6544T-E/SL: Tape and Reel,
Extended Temperature,
14LD SOIC.
MCP6544-I/P:
Industrial Temperature,
14LD PDIP.
MCP6544T-E/ST: Tape and Reel,
Extended Temperature,
14LD TSSOP.
DS21696E-page 31
MCP6541/1R/1U/2/3/4
NOTES:
DS21696E-page 32
© 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
© 2006 Microchip Technology Inc.
DS21696E-page 33
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Habour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-3910
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Alpharetta, GA
Tel: 770-640-0034
Fax: 770-640-0307
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Gumi
Tel: 82-54-473-4301
Fax: 82-54-473-4302
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Penang
Tel: 60-4-646-8870
Fax: 60-4-646-5086
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
08/29/06
DS21696E-page 34
© 2006 Microchip Technology Inc.