M MCP601/2/3/4 2.7V to 5.5V Single-Supply CMOS Op Amps Features Description • • • • • • • • The Microchip Technology Inc. MCP601/2/3/4 family of low-power operational amplifiers (op amps) are offered in single (MCP601), single with Chip Select (CS) (MCP603), dual (MCP602) and quad (MCP604) configurations. These op amps utilize an advanced CMOS technology that provides low bias current, highspeed operation, high open-loop gain and rail-to-rail output swing. This product offering operates with a single supply voltage that can be as low as 2.7V, while drawing 230 µA (typ.) of quiescent current per amplifier. In addition, the common mode input voltage range goes 0.3V below ground, making these amplifiers ideal for single-supply operation. Single-Supply: 2.7V to 5.5V Rail-to-Rail Output Input Range Includes Ground Gain Bandwidth Product: 2.8 MHz (typ.) Unity-Gain Stable Low Quiescent Current: 230 µA/amplifier (typ.) Chip Select (CS): MCP603 only Temperature Ranges: - Industrial: -40°C to +85°C - Extended: -40°C to +125°C • Available in Single, Dual and Quad These devices are appropriate for low-power, batteryoperated circuits due to the low quiescent current, for A/D convert driver amplifiers because of their wide bandwidth or for anti-aliasing filters by virtue of their low input bias current. Typical Applications • • • • • • • Portable Equipment A/D Converter Driver Photo Diode Pre-amp Analog Filters Data Acquisition Notebooks and PDAs Sensor Interface Available Tools The MCP601, MCP602 and MCP603 are available in standard 8-lead PDIP, SOIC and TSSOP packages. The MCP601 and MCP601R are also available in a standard 5-lead SOT-23 package, while the MCP603 is available in a standard 6-lead SOT-23 package. The MCP604 is offered in standard 14-lead PDIP, SOIC and TSSOP packages. • SPICE Macro Models at www.microchip.com • FilterLab® Software at www.microchip.com The MCP601/2/3/4 family is available in the Industrial and Extended temperature ranges and has a power supply range of 2.7V to 5.5V. Package Types MCP601 PDIP, SOIC, TSSOP MCP602 PDIP, SOIC, TSSOP MCP603 PDIP, SOIC, TSSOP MCP604 PDIP, SOIC, TSSOP NC 1 8 NC VOUTA 1 8 VDD NC 1 8 CS VOUTA 1 14 VOUTD VIN– 2 7 VDD VINA– 2 7 VOUTB VIN– 2 7 VDD 13 VIND– 6 VOUT VINA+ 3 VSS 4 6 VINB– VIN + 3 VSS 4 6 VOUT VINA– 2 VINA+ 3 VIN+ 3 VSS 4 5 NC MCP601 SOT23-5 VOUT 1 MCP601R SOT23-5 5 VDD VOUT 1 4 VIN– VIN+ 3 VSS 2 VIN+ 3 5 VINB+ 5 VSS VOUT 1 4 VIN– VIN + 3 VSS 2 VDD 4 VINB+ 5 MCP603 SOT23-6 VDD 2 2004 Microchip Technology Inc. 5 NC VINB– 6 6 VDD VOUTB 7 12 VIND+ 11 VSS 10 VINC+ 9 VINC– 8 VOUTC 5 CS 4 VIN– DS21314F-page 1 MCP601/2/3/4 1.0 ELECTRICAL CHARACTERISTICS PIN FUNCTION TABLE Name Function Absolute Maximum Ratings † VIN +, VINA+, VINB+, VINC+, VIND+ Non-inverting Inputs VIN –, VINA–, VINB–, VINC–, VIND– Inverting Inputs VDD - VSS .........................................................................7.0V All inputs and outputs...................... VSS - 0.3V to VDD + 0.3V Difference Input voltage ........................................ |VDD - VSS| Output Short Circuit Current...................................continuous Current at Input Pin .......................................................±2 mA Current at Output and Supply Pins .............................±30 mA Storage temperature .....................................-65°C to +150°C Junction temperature .................................................. +150°C ESD protection on all pins (HBM; MM) ................ ≥ 3 kV; 200V VDD Positive Power Supply VSS Negative Power Supply VOUT, VOUTA, VOUTB, VOUTC , VOUTD Outputs CS Chip Select NC No Internal Connection † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DC CHARACTERISTICS Electrical Specifications: Unless otherwise specified, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD /2 and RL = 100 kΩ to VDD /2. Parameters Input Offset Input Offset Voltage Industrial Temperature Extended Temperature Input Offset Temperature Drift Power Supply Rejection Input Current and Impedance Input Bias Current Industrial Temperature Extended Temperature Input Offset Current Common Mode Input Impedance Differential Input Impedance Common Mode Common Mode Input Range Common Mode Rejection Ratio Open-loop Gain DC Open-loop Gain (large signal) Output Maximum Output Voltage Swing Linear Output Voltage Swing Output Short Circuit Current Sym Min Typ Max Units VOS VOS VOS ∆VOS/∆TA PSRR -2 -3 -4.5 — 80 ±0.7 ±1 ±1 ±2.5 88 +2 +3 +4.5 — — mV mV mV µV/°C dB IB IB IB IOS ZCM — — — — — 1 20 450 ±1 1013||6 — 60 5000 — — pA pA TA = +85°C (Note 1) pA TA = +125°C (Note 1) pA Ω||pF ZDIFF — 1013||3 — Ω||pF VCMR CMRR VSS – 0.3 75 — 90 VDD – 1.2 — V dB A OL 100 115 — dB AOL 95 110 — dB — — — — ±22 ±12 VDD – 20 VDD – 60 V DD – 100 V DD – 100 — — mV mV mV mV mA mA VOL, VOH VSS + 15 VOL, VOH VSS + 45 VOUT VSS + 100 VOUT VSS + 100 ISC — ISC — Conditions TA = -40°C to +85°C (Note 1) TA = -40°C to +125°C (Note 1) TA = -40°C to +125°C VDD = 2.7V to 5.5V VDD = 5.0V, VCM = -0.3V to 3.8V RL = 25 kΩ to VDD/2, VOUT = 100 mV to VDD – 100 mV RL = 5 kΩ to VDD/2, VOUT = 100 mV to VDD – 100 mV RL = 25 kΩ to VDD /2, Output overdrive = 0.5V RL = 5 kΩ to VDD/2, Output overdrive = 0.5V RL = 25 kΩ to VDD/2, AOL ≥ 100 dB RL = 5 kΩ to VDD/2, AOL ≥ 95 dB VDD = 5.5V VDD = 2.7V Power Supply Supply Voltage VDD 2.7 — 5.5 V Quiescent Current per Amplifier IQ — 230 325 µA IO = 0 Note 1: These specifications are not tested in either the SOT-23 or TSSOP packages with date codes older than YYWW = 0408. In these cases, the minimum and maximum values are by design and characterization only. DS21314F-page 2 2004 Microchip Technology Inc. MCP601/2/3/4 AC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, V CM = VDD/2, VOUT ≈ VDD /2, RL = 100 kΩ to VDD/2 and CL = 50 pF. Parameters Sym Min Typ Max Units GBWP — PM — Conditions 2.8 — MHz 50 — ° G = +1 V/V G = +1 V/V Frequency Response Gain Bandwidth Product Phase Margin Step Response Slew Rate SR — 2.3 — V/µs tsettle — 4.5 — µs Input Noise Voltage Eni — 7 — Input Noise Voltage Density eni — 29 — nV/√Hz f = 1 kHz eni — 21 — nV/√Hz f = 10 kHz ini — 0.6 — fA/√Hz f = 1 kHz Settling Time (0.01%) G = +1 V/V, 3.8V step Noise Input Noise Current Density µVP-P f = 0.1 Hz to 10 Hz MCP603 CHIP SELECT CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, V CM = VDD/2, VOUT ≈ VDD /2, RL = 100 kΩ to VDD/2 and CL = 50 pF. Parameters Sym Min Typ Max Units Conditions DC Characteristics CS Logic Threshold, Low VIL VSS — 0.2 VDD V CS Input Current, Low ICSL -1.0 — — µA CS Logic Threshold, High VIH 0.8 VDD — VDD V CS = 0.2VDD CS Input Current, High ICSH — 0.7 2.0 µA CS = VDD Shutdown V SS current IQ_SHDN -2.0 -0.7 — µA CS = VDD Amplifier Output Leakage in Shutdown IO_SHDN — 1 — nA HYST — 0.3 — V Internal switch CS Low to Amplifier Output Turn-on Time tON — 3.1 10 µs CS ≤ 0.2VDD , G = +1 V/V CS High to Amplifier Output High-Z Time tOFF — 100 — ns CS ≥ 0.8VDD , G = +1 V/V, No load. CS Threshold Hysteresis Timing CS tON tOFF Hi-Z Output Active IDD 2 nA (typ.) 230 µA (typ.) ISS -700 nA (typ.) -230 µA (typ.) CS Current 700 nA (typ.) 2 nA (typ.) VOUT FIGURE 1-1: Timing Diagram. Hi-Z MCP603 Chip Select (CS) 2004 Microchip Technology Inc. DS21314F-page 3 MCP601/2/3/4 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V and VSS = GND. Parameters Sym Min Typ Max Units Conditions Specified Temperature Range TA -40 — +85 °C Industrial temperature parts TA -40 — +125 °C Extended temperature parts Operating Temperature Range TA -40 — +125 °C Note Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 5L-SOT23 θJA — 256 — °C/W Thermal Resistance, 6L-SOT23 θJA — 230 — °C/W Thermal Resistance, 8L-PDIP θJA — 85 — °C/W Thermal Resistance, 8L-SOIC θJA — 163 — °C/W Thermal Resistance, 8L-TSSOP θJA — 124 — °C/W Thermal Resistance, 14L-PDIP θJA — 70 — °C/W Thermal Resistance, 14L-SOIC θJA — 120 — °C/W Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W Temperature Ranges Thermal Package Resistances Note: The Industrial temperature parts operate over this extended range, but with reduced performance. The Extended temperature specs do not apply to Industrial temperature parts. In any case, the internal Junction temperature (TJ) must not exceed the absolute maximum specification of 150°C. DS21314F-page 4 2004 Microchip Technology Inc. MCP601/2/3/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0 100 -30 Gain 80 -60 Phase 60 300 -90 40 -120 20 -150 0 -180 -20 -210 -40 1.E-01 0.1 1.E+00 1.E+01 1 10 1.E+02 100 1.E+03 1.E+04 1k 1.E+05 1.E+06 1.E+07 10k 100k 1M 10M Quiescent Current per Amplifier (µA) 120 Open-Loop Phase (°) Open-Loop Gain (dB) Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, RL = 100 kΩ to VDD/2, V OUT ≈ VDD/2 and CL = 50 pF. IO = 0 -40°C 250 +25°C 200 +85°C 150 +125°C 100 50 0 -240 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Supply Voltage (V) Frequency (Hz) FIGURE 2-1: Frequency. Open-Loop Gain, Phase vs. 3.5 Quiescent Current per Amplifier (µA) Slew Rate (V/µs) Falling Edge 2.5 2.0 Rising Edge 1.5 1.0 0.5 IO = 0 250 VDD = 5.5V 200 150 VDD = 2.7V 100 50 0 0.0 -50 -25 0 25 50 75 100 -50 125 -25 Ambient Temperature (°C) Slew Rate vs. Temperature. GBWP PM, G = +1 -50 -25 0 25 50 75 110 100 90 80 70 60 50 40 30 20 10 0 100 125 FIGURE 2-5: Temperature. 50 75 100 125 Quiescent Current vs. 10,000 1µ 1,000 100n 100 10n 0.1 10 1.E-01 Ambient Temperature (°C) FIGURE 2-3: Gain Bandwidth Product, Phase Margin vs. Temperature. 2004 Microchip Technology Inc. 25 10µ Input Noise Voltage Density (V/√Hz) 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 Ambient Temperature (°C) Phase Margin, G = +1 (°) FIGURE 2-2: Gain Bandwidth Product (MHz) Quiescent Current vs. 300 VDD = 5.0V 3.0 FIGURE 2-4: Supply Voltage. 1.E+00 1 1.E+01 10 1.E+02 100 1.E+03 1k 1.E+04 10k 1.E+05 100k 1.E+06 1M Frequency (Hz) FIGURE 2-6: vs. Frequency. Input Noise Voltage Density DS21314F-page 5 MCP601/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, RL = 100 kΩ to VDD/2, V OUT ≈ VDD/2 and CL = 50 pF. 18% 1200 Samples 14% Percentage of Occurrences 12% 10% 8% 6% 4% 2% 0% 1200 Samples TA = -40 to +125°C 16% 14% 12% 10% 8% 6% 4% 2% 0% -2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 -10 -8 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -2 0 2 4 6 8 10 Input Offset Voltage Drift. 100 VDD = 5.5V VDD = 2.7V 95 90 PSRR 85 CMRR 80 75 125 -50 -25 0 Ambient Temperature (°C) FIGURE 2-11: Temperature. 75 100 125 VDD = 5.5V TA = -40°C TA = +25°C TA = +85°C TA = +125°C TA = +125°C 5.0 2.0 FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 2.7V. DS21314F-page 6 50 CMRR, PSRR vs. 0.5 1.5 Common Mode Input Voltage (V) 800 700 600 500 400 300 200 100 0 -100 -200 -0.5 800 700 VDD = 2.7V TA = -40°C 600 TA = +25°C 500 TA = +85°C 400 TA = +125°C 300 200 100 0 TA = +125°C -100 -200 -0.5 0.0 0.5 1.0 0.0 Input Offset Voltage vs. Input Offset Voltage (µV) FIGURE 2-8: Temperature. 25 Ambient Temperature (°C) 4.5 100 4.0 75 3.5 50 3.0 25 2.5 0 2.0 -25 1.5 -50 Input Offset Voltage (µV) -4 FIGURE 2-10: Input Offset Voltage. CMRR, PSRR (dB) Input Offset Voltage (mV) FIGURE 2-7: -6 Input Offset Voltage Drift (µV/°C) Input Offset Voltage (mV) 1.0 Percentage of Occurrences 16% Common Mode Input Voltage (V) FIGURE 2-12: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. 2004 Microchip Technology Inc. MCP601/2/3/4 150 100 No Load 130 120 110 100 90 1.E+04 1k 1.E+05 CMRR 60 50 40 30 10k 100k Frequency (Hz) 1.E+00 1M 1.E+01 FIGURE 2-16: Frequency. VDD = 5.5V VCM = 4.3V 100 IB IOS 10 VDD = 5.0V 10 100 Input Bias and Offset Currents (pA) Input Bias and Offset Currents (pA) 70 1.E+06 1 1.E+02 1.E+03 1.E+04 1.E+05 1k 10k Frequency (Hz) 1.E+06 100k CMRR, PSRR vs. 1000 IB, +125°C VDD = 5.5V max. VCMR ≥ 4.3V 100 IB, +85°C IOS, +125°C 10 IOS, +85°C 1 25 35 45 55 65 75 85 95 105 115 125 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (°C) Common Mode Input Voltage (V) FIGURE 2-14: Input Bias Current, Input Offset Current vs. Ambient Temperature. FIGURE 2-17: Input Bias Current, Input Offset Current vs. Common Mode Input Voltage. 120 120 DC Open-Loop Gain (dB) DC Open-Loop Gain (dB) 80 20 1.E+03 FIGURE 2-13: Channel-to-Channel Separation vs. Frequency. 1000 PSRR+ PSRR- 90 140 CMRR, PSRR (dB) Channel to Channel Separation (dB) Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, RL = 100 kΩ to VDD/2, V OUT ≈ VDD/2 and CL = 50 pF. VDD = 5.5V 110 100 VDD = 2.7V 90 RL = 25 kΩ 110 100 90 80 80 100 1.E+02 FIGURE 2-15: Load Resistance. 1.E+03 1.E+04 1k 10k Load Resistance (Ω) 1.E+05 100k DC Open-Loop Gain vs. 2004 Microchip Technology Inc. 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Supply Voltage (V) FIGURE 2-18: Supply Voltage. DC Open-Loop Gain vs. DS21314F-page 7 MCP601/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, RL = 100 kΩ to VDD/2, V OUT ≈ VDD/2 and CL = 50 pF. 100 3.0 130 90 GBWP 2.5 80 2.0 70 1.5 60 1.0 50 PM, G = +1 0.5 40 0.0 100 1.E+02 1.E+03 VDD = 5.5V, RL = 25 kΩ 120 110 100 1.E+05 1k 10k Load Resistance (Ω) -50 Output Headroom (mV); VDD - VOH and VOL - VSS Output Headroom (mV); VDD - VOH and VOL - VSS 1000 100 VDD-VOH VOL-VSS 10 50 75 100 125 DC Open-Loop Gain vs. VDD = 5.5V RL tied to VDD/2 VDD - VOH, RL = 5 kΩ VOL - VSS, RL = 5 kΩ 100 10 VDD - VOH, RL = 25 kΩ VOL - VSS, RL = 25 kΩ 10 1 1.E+05 1.E+06 1M -25 0 25 50 75 100 125 Ambient Temperature (°C) VDD = 5.0V 100k -50 FIGURE 2-23: vs. Temperature. Output Short Circuit Current Magnitude (mA) Maximum Output Voltage Swing (VP-P) 10 1.E+07 10M Frequency (Hz) FIGURE 2-21: Maximum Output Voltage Swing vs. Frequency. DS21314F-page 8 25 1 0.1 1 Output Current Magnitude (mA) FIGURE 2-20: Output Voltage Headroom vs. Output Current. 1.E+04 0 FIGURE 2-22: Temperature. 1,000 0.1 10k -25 Ambient Temperature (°C) FIGURE 2-19: Gain Bandwidth Product, Phase Margin vs. Load Resistance. 1 0.01 VDD = 5.5V, RL = 5 kΩ VDD = 2.7V, RL = 25 kΩ VDD = 2.7V, RL = 5 kΩ 90 80 30 100k 1.E+04 DC Open-Loop Gain (dB) VDD = 5.0V Phase Margin, G = +1 (°) Gain Bandwidth Product (MHz) 3.5 30 25 20 Output Voltage Headroom TA = -40°C TA = +25°C TA = +85°C TA = +125°C 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Supply Voltage (V) FIGURE 2-24: Output Short-Circuit Current vs. Supply Voltage. 2004 Microchip Technology Inc. MCP601/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, RL = 100 kΩ to VDD/2, V OUT ≈ VDD/2 and CL = 50 pF. 5.0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 VDD = 5.0V G = -1 4.5 Output Voltage (V) Output Voltage (V) 5.0 VDD = 5.0V G = +1 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 0.0 1.E-05 0.E+00 1.E-06 2.E-06 3.E-06 Time (1 µs/div) FIGURE 2-25: Pulse Response. Large Signal Non-Inverting FIGURE 2-28: Response. 2.55 2.53 2.51 2.49 2.47 2.45 6.E-06 7.E-06 8.E-06 9.E-06 1.E-05 Large Signal Inverting Pulse VDD = 5.0V G = -1 2.57 2.55 2.53 2.51 2.49 2.47 2.45 2.43 2.43 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 1.E-05 2.41 0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 Time (1 µs/div) FIGURE 2-26: Pulse Response. 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 1.E-05 Time (1 µs/div) Small Signal Non-Inverting FIGURE 2-29: Response. 0 CS -100 Quiescent Current through VSS (µA) Output Voltage, Chip Select Voltage (V) 5.E-06 2.59 VDD = 5.0V G = +1 2.57 Output Voltage (20 mV/div) Output Voltage (20 mV/div) 2.59 2.41 0.E+00 4.E-06 Time (1 µs/div) VDD = 5.0V G = +1 VIN = 2.5V RL = 100 kΩ to GND VOUT Active Small Signal Inverting Pulse VDD = 5.5V -200 -300 -400 -500 -600 -700 -800 VOUT High-Z 0.0E+00 5.0E-06 1.0E-05 1.5E-05 2.0E-05 2.5E-05 3.0E-05 3.5E-05 4.0E-05 Time (5 µs/div) FIGURE 2-27: (MCP603). Chip Select Timing 2004 Microchip Technology Inc. 4.5E-05 5.0E-05 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V) FIGURE 2-30: Quiescent Current Through VSS vs. Chip Select Voltage (MCP603). DS21314F-page 9 MCP601/2/3/4 0.8 VDD = 5.5V 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Internal Chip Select Switch Output Voltage (V) FIGURE 2-31: Chip Select Pin Input Current vs. Chip Select Voltage. 2.5 Amplifier On 6 VDD = +5.0V G = +2 5 4 3 2 VIN 1 VOUT 0 -1 0.0E+00 5.0E-06 1.0E-05 1.5E-05 2.0E-05 2.5E-05 Time (5 µs/div) Chip Select Voltage (V) 3.0 (Input and Output Voltages (V) Chip Select Pin Current (µA) Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, RL = 100 kΩ to VDD/2, V OUT ≈ VDD/2 and CL = 50 pF. FIGURE 2-33: The MCP601/2/3/4 family of op amps shows no phase reversal under input overdrive. VDD = 5.0V 2.0 1.5 CS Hi to Low CS Low to Hi 1.0 0.5 Amplifier Hi-Z 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Chip Select Voltage (V) FIGURE 2-32: Internal Switch. DS21314F-page 10 Hysteresis of Chip Select’s 2004 Microchip Technology Inc. MCP601/2/3/4 3.0 APPLICATIONS INFORMATION The MCP601/2/3/4 family of op amps are fabricated on Microchip’s state-of-the-art CMOS process. They are unity-gain stable and suitable for a wide range of general purpose applications. 3.1 Input The MCP601/2/3/4 amplifier family is designed to not exhibit phase reversal when the input pins exceed the supply rails. Figure 2-33 shows an input voltage that exceeds both supplies with no resulting phase inversion. The Common Mode Input Voltage Range (VCMR) includes ground in single-supply systems (VSS), but does not include VDD. This means that the amplifier input behaves linearly as long as the Common Mode Input Voltage (VCM) is kept within the specified VCMR limits (V SS – 0.3V to VDD – 1.2V at +25°C). Input voltages that exceed the input voltage range (VSS – 0.3V to VDD – 1.2V at +25°C) can cause excessive current to flow into or out of the input pins. Current beyond ±2 mA may cause reliability problems. Applications that exceed this rating must externally limit the input current with a resistor (R IN), as shown in Figure 3-1. RIN VIN + MCP60X – ( maximum expected V IN ) – V DD R IN ≥ ----------------------------------------------------------------------------2 mA The second specification that describes the output swing capability of these amplifiers is the Linear Output Voltage Swing. This specification defines the maximum output swing that can be achieved while the amplifier is still operating in its linear region. To verify linear operation in this range, the large signal (DC Open-Loop Gain (AOL)) is measured at points 100 mV inside the supply rails. The measurement must exceed the specified gains in the specification table. 3.3 MCP603 Chip Select (CS) The MCP603 is a single amplifier with Chip Select (CS). When CS is pulled high, the supply current drops to -0.7 µA (typ.), which is pulled through the CS pin to VSS. When this happens, the amplifier output is put into a high-impedance state. Pulling CS low enables the amplifier and, if the CS pin is left floating, the amplifier may not operate properly. Figure 1-1 is the Chip Select timing diagram and shows the output voltage, supply currents and CS current in response to a CS pulse. Figure 2-27 shows the measured output voltage response to a CS pulse. 3.4 Capacitive Loads Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response with overshoot and ringing in the step response. When driving large capacitive loads with these op amps (e.g., > 40 pF when G = +1), a small series resistor at the output (RISO in Figure 3-2) improves the feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. V SS – ( minimum expected V IN ) R IN ≥ -------------------------------------------------------------------------2 mA FIGURE 3-1: into an input pin. 3.2 + MCP60X – R IN limits the current flow Rail-to-Rail Output There are two specifications that describe the output swing capability of the MCP601/2/3/4 family of op amps. The first specification (Maximum Output Voltage Swing) defines the absolute maximum swing that can be achieved under the specified load conditions. For instance, the output voltage swings to within 15 mV of the negative rail with a 25 kΩ load to VDD/2. Figure 2-33 shows how the output voltage is limited when the input goes beyond the linear region of operation. 2004 Microchip Technology Inc. RG RISO VOUT CL RF FIGURE 3-2: Output resistor RISO stabilizes large capacitive loads. Figure 3-3 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN) in order to make it easier to interpret the plot for arbitrary gains. GN is the circuit’s noise gain. For non-inverting gains, GN and the gain are equal. For inverting gains, GN = 1 + |Gain| (e.g., -1 V/V gives G N = +2 V/V). DS21314F-page 11 MCP601/2/3/4 1. Connect the guard ring to the inverting input pin (VIN–) for non-inverting gain amplifiers, including unity-gain buffers. This biases the guard ring to the common mode input voltage. Connect the guard ring to the non-inverting input pin (VIN+) for inverting gain amplifiers and transimpedance amplifiers (converts current to voltage, such as photo detectors). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). 1k Recommended RISO (:) 1,000 2. 100 100 GN = +1 GN t +2 10 10p 10 10 100 1,000 10,000 100p 1n 10n Normalized Load Capacitance; CL / GN (F) FIGURE 3-3: Recommended RISO values for capacitive loads. Once you’ve selected RISO for your circuit, doublecheck the resulting frequency response peaking and step response overshoot in your circuit. Evaluation on the bench and simulations with the MCP601/2/3/4 SPICE macro model are very helpful. Modify R ISO’s value until the response is reasonable. 3.5 3.7.1 Typical Applications ANALOG FILTERS Figure 3-5 and Figure 3-6 show low-pass, secondorder, Butterworth filters with a cutoff frequency of 10 Hz. The filter in Figure 3-5 has a non-inverting gain of +1 V/V, and the filter in Figure 3-6 has an inverting gain of -1 V/V. PCB Surface Leakage In applications where low input bias current is critical, printed circuit board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012Ω. A 5V difference would cause 5 pA of current to flow. This is greater than the MCP601/2/3/4 family’s bias current at +25°C (1 pA, typ.). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 3-4. Guard Ring FIGURE 3-4: DS21314F-page 12 VIN– VIN+ Example Guard Ring layout. G = +1 V/V fP = 10 Hz C1 47 nF Supply Bypass With this family of op amps, the power supply pin (VDD for single-supply) should have a local bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-frequency performance. It also needs a bulk capacitor (i.e., 1 µF or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other parts. 3.6 3.7 R2 R1 641 kΩ 382 kΩ + VIN C2 22 nF FIGURE 3-5: Sallen-Key Filter. MCP60X VOUT – Second-Order, Low-Pass G = -1 V/V fP = 10 Hz R2 618 kΩ C1 8.2 nF R3 R1 618 kΩ 1.00 MΩ VIN VOUT C2 47 nF + MCP60X VDD/2 – FIGURE 3-6: Second-Order, Low-Pass Multiple-Feedback Filter. The MCP601/2/3/4 family of op amps have low input bias current, which allows the designer to select larger resistor values and smaller capacitor values for these filters. This helps produce a compact PCB layout. These filters, and others, can be designed using Microchip’s FilterLab® software. 2004 Microchip Technology Inc. MCP601/2/3/4 3.7.2 INSTRUMENTATION AMPLIFIER CIRCUITS Instrumentation amplifiers have a differential input that subtracts one input voltage from another and rejects common mode signals. These amplifiers also provide a single-ended output voltage. The three-op amp instrumentation amplifier is illustrated in Figure 3-7. One advantage of this approach is unitygain operation, while one disadvantage is that the common mode input range is reduced as R2/RG gets larger. V1 + R3 MCP60X R4 – – VOUT MCP60X RG R2 3.7.3 PHOTO DETECTION The MCP601/2/3/4 op amps can be used to easily convert the signal from a sensor that produces an output current (such as a photo diode) into a voltage (a transimpedance amplifier). This is implemented with a single resistor (R2) in the feedback loop of the amplifiers shown in Figure 3-9 and Figure 3-10. The optional capacitor (C2) sometimes provides stability for these circuits. A photodiode configured in the Photovoltaic mode has zero voltage potential placed across it (Figure 3-9). In this mode, the light sensitivity and linearity is maximized, making it best suited for precision applications. The key amplifier specifications for this application are: low input bias current, low noise, common mode input voltage range (including ground) and rail-to-rail output. + R2 R3 C2 R4 R2 – V2 ID1 VREF MCP60X + 2R 2 R V OU T = ( V 1 – V 2 ) 1 + --------- -----4- + V REF R G R 3 RG VREF V2 VOUT R2 MCP60X + FIGURE 3-9: The two-op amp instrumentation amplifier is shown in Figure 3-8. While its power consumption is lower than the three-op amp version, its main drawbacks are that the common mode range is reduced with higher gains and it must be configured in gains of two or higher. R2 Light – R1 - - MCP60X + MCP60X + Photovoltaic Mode Detector. In contrast, a photodiode that is configured in the Photoconductive mode has a reverse bias voltage across the photo-sensing element (Figure 3-10). This decreases the diode capacitance, which facilitates high-speed operation (e.g., high-speed digital communications). The design trade-off is increased diode leakage current and linearity errors. The op amp needs to have a wide Gain Bandwidth Product (GBWP). C2 R2 ID1 V1 R 1 2R 1 V O UT = ( V 1 – V 2 ) 1 + ------ + --------- + V REF R 2 RG FIGURE 3-8: Two-Op Amp Instrumentation Amplifier. Both instrumentation amplifiers should use a bulk bypass capacitor of at least 1 µF. The CMRR of these amplifiers will be set by both the op amp CMRR and resistor matching. 2004 Microchip Technology Inc. VOUT VOUT = ID1 R2 FIGURE 3-7: Three-Op Amp Instrumentation Amplifier. R1 D1 VDD D1 Light VBIAS – VDD VOUT MCP60X + VOUT = I D1 R2 VBIAS < 0V FIGURE 3-10: Detector. Photoconductive Mode DS21314F-page 13 MCP601/2/3/4 4.0 DESIGN TOOLS Microchip provides the basic design tools needed for the MCP601/2/3/4 family of op amps. 4.1 SPICE Macro Model The latest SPICE macro model of the MCP601/2/3/4 op amps is available on Microchip’s web site at www.microchip.com. This model is intended as an initial design tool that works well in the op amp’s linear region of operation at room temperature. See the SPICE model firmware for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specs and plots. 4.2 FilterLab® 2.0 FilterLab® 2.0 is an innovative software tool that simplifies analog active-filter (using op amps) design. Available at no cost from Microchip’s web site at www.microchip.com, the FilterLab active-filter software design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. DS21314F-page 14 2004 Microchip Technology Inc. MCP601/2/3/4 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 5-Lead SOT-23 (MCP601 and MCP601R Only) XXNN 04NN 6-Lead SOT-23A (MCP603 Only) XXNN Legend: Note: * XX...X YY WW NNN Example: Example: 04NN Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard OTP marking consists of Microchip part number, year code, week code, and traceability code. 2004 Microchip Technology Inc. DS21314F-page 15 MCP601/2/3/4 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW Example: MCP601 I/P256 0424 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Example: MCP601 I/SN0324 256 Example: 8-Lead TSSOP XXXX 601 XYWW I324 NNN 256 14-Lead PDIP (300 mil) (MCP604 Only) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) (MCP604 Only) Example: MCP604-I/P XXXXXXXXXXXXXX 0424256 Example: MCP604ISL XXXXXXXXXXX 0424256 XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 14-Lead TSSOP (4.4mm) (MCP604 Only) XXXXXXXX DS21314F-page 16 Example: 604I YYWW 0324 NNN 256 2004 Microchip Technology Inc. MCP601/2/3/4 5-Lead Plastic Small Outline Transistor (OT) (SOT-23) E E1 p B p1 n D 1 α c A Units Dimension Limits n Number of Pins p Pitch p1 Outside lead pitch (basic) Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic φ L β A A2 A1 E E1 D L φ c B α β MIN .035 .035 .000 .102 .059 .110 .014 0 .004 .014 0 0 A2 A1 INCHES* NOM 5 .038 .075 .046 .043 .003 .110 .064 .116 .018 5 .006 .017 5 5 MAX .057 .051 .006 .118 .069 .122 .022 10 .008 .020 10 10 MILLIMETERS NOM 5 0.95 1.90 0.90 1.18 0.90 1.10 0.00 0.08 2.60 2.80 1.50 1.63 2.80 2.95 0.35 0.45 0 5 0.09 0.15 0.35 0.43 0 5 0 5 MIN MAX 1.45 1.30 0.15 3.00 1.75 3.10 0.55 10 0.20 0.50 10 10 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-178 Drawing No. C04-091 2004 Microchip Technology Inc. DS21314F-page 17 MCP601/2/3/4 6-Lead Plastic Small Outline Transistor (CH) (SOT-23) E E1 B p1 n D 1 α c A A2 φ L β Units Dimension Limits n p MIN A1 INCHES* NOM MAX MILLIMETERS NOM 6 0.95 1.90 0.90 1.18 0.90 1.10 0.00 0.08 2.60 2.80 1.50 1.63 2.80 2.95 0.35 0.45 0 5 0.09 0.15 0.35 0.43 0 5 0 5 MIN Number of Pins 6 Pitch .038 p1 Outside lead pitch (basic) .075 Overall Height A .035 .046 .057 Molded Package Thickness .035 .043 .051 A2 Standoff .000 .003 .006 A1 Overall Width E .102 .110 .118 Molded Package Width .059 .064 .069 E1 Overall Length D .110 .116 .122 Foot Length L .014 .018 .022 φ Foot Angle 0 5 10 c Lead Thickness .004 .006 .008 Lead Width B .014 .017 .020 α Mold Draft Angle Top 0 5 10 β Mold Draft Angle Bottom 0 5 10 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. MAX 1.45 1.30 0.15 3.00 1.75 3.10 0.55 10 0.20 0.50 10 10 JEITA (formerly EIAJ) equivalent: SC-74A Drawing No. C04-120 DS21314F-page 18 2004 Microchip Technology Inc. MCP601/2/3/4 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L c § B1 B eB α β MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM MAX 8 .100 .155 .130 .170 .145 .313 .250 .373 .130 .012 .058 .018 .370 10 10 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 2004 Microchip Technology Inc. DS21314F-page 19 MCP601/2/3/4 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21314F-page 20 2004 Microchip Technology Inc. MCP601/2/3/4 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c φ β A1 A2 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L φ c B α β MIN INCHES NOM MAX 8 .026 .033 .002 .246 .169 .114 .020 0 .004 .007 0 0 .035 .004 .251 .173 .118 .024 4 .006 .010 5 5 .043 .037 .006 .256 .177 .122 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 8 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 2.90 3.00 3.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 MIN Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-086 2004 Microchip Technology Inc. DS21314F-page 21 MCP601/2/3/4 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β eB B1 p B Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing § eB .310 .370 .430 α Mold Draft Angle Top 5 10 15 β Mold Draft Angle Bottom 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 DS21314F-page 22 MAX 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15 2004 Microchip Technology Inc. MCP601/2/3/4 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A2 A φ A1 L β Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .150 .337 .010 .016 0 .008 .014 0 0 INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .347 .020 .050 8 .010 .020 15 15 MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 2004 Microchip Technology Inc. DS21314F-page 23 MCP601/2/3/4 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c φ β A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L φ c B α β MIN .033 .002 .246 .169 .193 .020 0 .004 .007 0 0 INCHES NOM 14 .026 .035 .004 .251 .173 .197 .024 4 .006 .010 5 5 A2 MAX .043 .037 .006 .256 .177 .201 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 14 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 MIN Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 DS21314F-page 24 2004 Microchip Technology Inc. MCP601/2/3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Range Package Device Single Op Amp Single Op Amp (Tape and Reel for SOT23, SOIC and TSSOP) MCP601RT Single Op Amp (Tape and Reel for SOT23-5) MCP602 Dual Op Amp MCP602T Dual Op Amp (Tape and Reel for SOIC and TSSOP) MCP603 Single Op Amp with Chip Select MCP603T Single Op Amp with Chip Select (Tape and Reel for SOT23, SOIC and TSSOP) MCP604 Quad Op Amp MCP604T Quad Op Amp (Tape and Reel for SOIC and TSSOP) I E Package OT CH P SN SL ST = -40°C to +85°C = -40°C to +125°C = = = = = = a) b) MCP601 MCP601T Temperature Range Examples: Plastic SOT23, 5-lead (MCP601 only) Plastic SOT23, 6-lead (MCP603 only) Plastic DIP (300 mil Body), 8, 14-lead Plastic SOIC (150 mil Body), 8-lead Plastic SOIC (150 mil Body), 14-lead Plastic TSSOP (4.4mm Body), 8, 14-lead c) d) e) MCP601-I/P: Single Op Amp, Industrial Temperature, 8LD PDIP package. MCP601-E/SN: Single Op Amp, Extended Temperature, 8LD SOIC package. MCP601T-I/OT: Tape and Reel, Industrial Temperature, Single Op Amp, 5-LD SOT23 package. MCP601T-E/ST: Tape and Reel, Extended Temperature, Single Op Amp, 8LD TSSOP package MCP601RT-E/OT: Tape and Reel, Extended Temperature, Single Op Amp, Rotated, 5-LD SOT23 package. a) MCP602-I/SN: b) MCP602-E/P: c) MCP602T-E/ST: a) MCP603-I/SN: b) MCP603-E/P: c) MCP603T-E/ST: d) MCP603T-I/SN: a) MCP604-I/P: b) MCP604-E/SL: c) MCP604T-I/ST: Dual Op Amp, Industrial Temperature, 8LD SOIC package. Dual Op Amp, Extended Temperature, 8LD PDIP package. Tape and Reel, Extended Temperature, Dual Op Amp, 8LD TSSOP package. Industrial Temperature, Single Op Amp with Chip Select,8LD SOIC package. Extended Temperature, Single Op Amp with Chip Select, 8LD PDIP package. Tape and Reel, Extended Temperature, Single Op Amp with Chip Select, 8LD TSSOP package. Tape and Reel, Industrial Temperature, Single Op Amp with Chip Select, 8LD SOIC package. Industrial Temperature, Quad Op Amp, 14LD PDIP package. Extended Temperature, Quad Op Amp, 14LD SOIC package. Tape and Reel, Industrial Temperature, Quad Op Amp, 14LD TSSOP package. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2004 Microchip Technology Inc. DS21314F-page 25 MCP601/2/3/4 NOTES: DS21314F-page 26 2004 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart and rfPIC are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartShunt and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, Select Mode, SmartSensor, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEEL OQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS21314F-page 27 2004 Microchip Technology Inc. M WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com China - Beijing Korea Unit 706B Wan Tai Bei Hai Bldg. No. 6 Chaoyangmen Bei Str. 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