CAT5172 256-Position SPI Compatible Digital Potentiometer The CAT5172 is a 256−position digitally programmable linear taper potentiometer ideally suited for replacing mechanical potentiometers and variable resistors. Like mechanical potentiometers, the CAT5172 has a resistive element, which can span VCC to Ground or float anywhere between the power supply rails. Wiper settings are controlled through an SPI−compatible digital interface. Upon power−up, the wiper assumes a mid−span position and may be repositioned anytime after the power is stable. The CAT5172 operates from 2.7 V to 5.5 V, while consuming less than 2 mA. This low operating current, combined with a small package footprint, make the CAT5172 ideal for battery−powered portable appliance. http://onsemi.com SOT23−8 TB SUFFIX CASE 527AK MARKING DIAGRAM Features • • • • • • • • • • 256−position End−to−End Resistance: 50 kW, 100 kW SPI Compatible Interface Power−on Preset to Midscale Single Supply 2.7 V to 5.5 V Low Temperature Coefficient 100 ppm/°C Low Power, IDD 2 mA max Wide Operating Temperature −40°C to +85°C RoHS−compliant SOT−23 8−Lead (2.9 mm x 3 mm) Package This is a Pb−Free Device ADYM AEYM 1 1 AD = 50 kW AE = 100 kW Y = Production Year Y = (Last Digit) M = Production Month M = (1 − 9, A, B, C) Typical Applications • Potentiometer Replacement • Transducer Adjustment of Pressure, Temperature, Position, Chemical, and Optical Sensors PIN CONNECTIONS W • RF Amplifier Biasing • Gain Control and Offset Adjustment A 1 VDD B GND CS CLK SDI (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2009 May, 2009 − Rev. 0 1 Publication Order Number: CAT5172/D CAT5172 VDD CS SDI CLK SPI INTERFACE A W B WIPER REGISTER GND Figure 1. Functional Block Diagram Table 1. ORDERING INFORMATION Part Number Resistance CAT5172TBI−50GT3 50 kW CAT5172TBI−00GT3 100 kW Temperature Range Package Shipping† −40°C to 85°C SOT−23−8 (Pb−Free) 3000/Tape & Reel 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Table 2. PIN FUNCTION DESCRIPTION Pin No. Pin Name 1 W Description 2 VDD Positive Power Supply. 3 GND Digital Ground. 4 CLK Serial Clock Input. Positive edge triggered. 5 SDI Serial Data Input. 6 CS 7 B Bottom Terminal of resistive element. 8 A Top Terminal of resistive element. Resistor’s Wiper Terminal. Chip Select Input, Active Low. When CS returns high, data will be loaded into the DAC register. Table 3. ABSOLUTE MAXIMUM RATINGS (Note 1) Rating VDD to GND Value Unit −0.3 to 6.5 V VA, VB, VW to GND VDD IMAX ±20 Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering, 10 sec) mA 0 to 6.5 V −40 to +85 °C 150 °C −65 to +150 °C 300 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. http://onsemi.com 2 CAT5172 Table 4. ELECTRICAL CHARACTERISTICS: 50 kW and 100 kW Versions VDD = 5 V ±10%, or 3 V ±10%; VA = VDD; VB = 0 V; –40°C < TA < +85°C; unless otherwise noted. Test Conditions Symbol Min Typ (Note 2) Max Unit Resistor Differential Nonlinearity (Note 3) RWB, VA = no connection R−DNL −1 ±0.1 +1 LSB Resistor Integral Nonlinearity (Note 3) RWB, VA = no connection R−INL −2 ±0.4 +2 LSB Nominal Resistor Tolerance (Note 4) TA = 25°C nRAB −20 +20 % Resistance Temperature Coefficient VAB = VDD, Wiper = no connection nRAB/nT 100 VDD = 5 V RW 50 120 100 250 Parameter DC CHARACTERISTICS — RHEOSTAT MODE Wiper Resistance VDD = 3 V ppm/°C W DC CHARACTERISTICS — POTENTIOMETER DIVIDER MODE Resolution N 8 Bits Differential Nonlinearity (Note 5) DNL −1 ±0.1 +1 LSB Integral Nonlinearity (Note 5) INL −1 ±0.4 +1 LSB Voltage Divider Temperature Coefficient Code = 0x80 nVW/nT 100 ppm/°C Full−Scale Error Code = 0xFF VWFSE −3 −1 0 LSB Zero−Scale Error Code = 0x00 VWZSE 0 1 3 LSB VA,B,W GND VDD V RESISTOR TERMINALS Voltage Range (Note 6) Capacitance (Note 7) A, B f = 1 MHz, measured to GND, Code = 0 x 80 CA,B 45 pF Capacitance (Note 7) W f = 1 MHz, measured to GND, Code = 0 x 80 CW 60 pF VA = VB = VDD/2 ICM 1 nA Input Logic High VDD = 5 V VIH Input Logic Low VDD = 5 V VIL Input Logic High VDD = 3 V VIH VDD = 3 V VIL 0.3VDD V VIN = 0 V or 5 V IIL ±1 mA Common−Mode Leakage (Note 7) DIGITAL INPUTS Input Logic Low Input Current Input Capacitance (Note 7) 0.7 x VDD V 0.3VDD 0.7 x VDD CIL V V 5 pF POWER SUPPLIES Power Supply Range Supply Current Power Dissipation (Note 8) Power Supply Sensitivity VDD RANGE 2.7 0.3 5.5 V 2 mA VIH = 5 V or VIL = 0 V IDD VIH = 5 V or VIL = 0 V, VDD = 5 V PDISS 0.2 mW nVDD = +5 V ±10%, Code = Midscale PSS ±0.05 %/% 2. Typical specifications represent average readings at +25°C and VDD = 5 V. 3. Resistor position nonlinearity error R−INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R−DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 4. VAB = VDD, Wiper (VW) = no connect. 5. INL and DNL are measured at VW with the DPP configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 6. Resistor terminals A, B, W have no limitations on polarity with respect to each other. 7. Guaranteed by design and not subject to production test. 8. PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 9. All dynamic characteristics use VDD = 5 V. http://onsemi.com 3 CAT5172 Table 4. ELECTRICAL CHARACTERISTICS: 50 kW and 100 kW Versions (continued) VDD = 5 V ±10%, or 3 V ±10%; VA = VDD; VB = 0 V; –40°C < TA < +85°C; unless otherwise noted. Parameter Min Typ (Note 2) Test Conditions Symbol Max Unit RAB = 50 kW / 100 kW, Code = 0x80 BW 100/40 kHz VA =1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kW THDW 0.05 % VA = 5 V, VB = 0 V, ±1 LSB error band tS 2 ms DYNAMIC CHARACTERISTICS (Notes 7 and 9) Bandwidth –3 dB Total Harmonic Distortion VW Settling Time (50 kW/100 kW) 2. Typical specifications represent average readings at +25°C and VDD = 5 V. 3. Resistor position nonlinearity error R−INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R−DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 4. VAB = VDD, Wiper (VW) = no connect. 5. INL and DNL are measured at VW with the DPP configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 6. Resistor terminals A, B, W have no limitations on polarity with respect to each other. 7. Guaranteed by design and not subject to production test. 8. PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 9. All dynamic characteristics use VDD = 5 V. Table 5. TIMING CHARACTERISTICS: 50 kW and 100 kW Versions VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +85°C; unless otherwise noted. Parameter Test Conditions Symbol Min Typ (Note 10) Max Unit 25 MHz SPI INTERFACE TIMING CHARACTERISTICS (Notes 11 and 12) (Specifications Apply to All Parts) Clock Frequency Input Clock Pulse width fCLK Clock level high or low tCH, tCL 20 ns Data Setup Time tDS 5 ns Data Hold Time tDH 5 ns CS Setup Time TCSS 15 ns CS High Pulse Width TCSW 40 ns CLK Fall to CS Fall Hold Time TCSH0 0 ns CLK Fall to CS Rise Hold Time TCSH1 0 ns CS Rise to Clock Rise Setup TCS1 10 ns 10. Typical specifications represent average readings at +25°C and VDD = 5 V. 11. Guaranteed by design and not subject to production test. 12. See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. http://onsemi.com 4 CAT5172 SPI Interface Table 6. CAT5172 SERIAL DATA−WORD FORMAT B7 B6 B5 B4 B3 B2 B1 B0 D7 MSB 27 D6 D5 D4 D3 D2 D1 D0 LSB 20 CS 1 2 3 4 5 6 7 8 CLK DATA IN D7 D6 D5 D4 D3 D2 D1 D0 SDI VOUT V1 V2 Figure 2. CAT5172 SPI Interface Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT) 1 SDI (DATA IN) 0 CLK tCSHO Dx tCH 1 0 1 CS Dx tCSS tDS tDH tCS1 tCSH1 tCL tCSW 0 tS VOUT VW ±1 LSB VW0 Figure 3. SPI Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT) http://onsemi.com 5 CAT5172 TYPICAL CHARACTERISTICS 0.03 0.1 0.02 0 DNL ERROR (LSB) ERROR (LSB) 0.01 0 −0.01 −0.02 −0.1 INL −0.2 −0.3 −0.03 −0.4 −0.04 −0.05 0 32 64 96 128 160 192 224 −0.5 256 0 32 64 96 128 160 192 TAP TAP Figure 4. Differential Non−Linearity, VCC = 5.6 V Figure 5. Integral Non−Linearity, VCC = 5.6 V 120 6 100 5 224 256 5.6 V VCC = 2.6 V 60 3.3 V 40 4.0 V 3 3.3 V 2 20 0 5.0 V 4 Vw (V) Rw (W) 80 5.6 V 4.0 V 0 50 100 VCC = 2.6 V 1 150 200 0 250 0 52 104 156 TAP TAP Figure 6. Wiper Resistance at Room Temperature Figure 7. Wiper Voltage 0.4 208 260 70 100 102.15 102.10 102.05 0.2 D (%) R (kW) 102.00 101.95 101.90 0 101.85 101.80 −0.2 −50 −20 10 40 70 101.75 −50 100 −20 10 40 TEMPERATURE (°C) TEMPERATURE (°C) Figure 8. Change in End−to−End Resistance Figure 9. End−to−End Resistance vs. Temperature http://onsemi.com 6 CAT5172 TYPICAL CHARACTERISTICS 400 CS 350 T = 90°C W ISB (nA) 300 T = −45°C 250 T = 25°C 200 150 100 2 3 4 5 6 VCC (V) Figure 10. Wiper’s Transition from Position 0xFF to Position 0x00 Relative to the CS Disable, VCC = 5 V Figure 11. Standby Current 0 30 −6 25 VCC = 5 V PSRR (dB) A (dB) −12 VCC = 3 V −18 −24 −30 −36 20 VCC = 5 V 15 VCC = 3 V 10 5 1 10 100 1000 0 1 10 100 f (KHz) f (KHz) Figure 12. Gain vs. Bandwidth (Tap 0x80) Figure 13. PSRR http://onsemi.com 7 1000 CAT5172 Basic Operation The CAT5172 is a 256−position digitally controlled potentiometer. When power is first applied the wiper assumes a mid−scale position and will remain there as long as CS remians high. Once the power supply is stable the wiper may be repositioned via the SPI compatible interface. The rising edge of the CS signal acts as the transfer command and each time CS transitions from LOW to HIGH the contents of the input register are loaded into the wiper register. In the power−up cycle, the input data register is cleared, setting all bits to 0 and the wiper register is loaded with 0x80 (128 Decimal) which moves the wiper to its midscale position. If CS is toggled CAT5172 transfers the contents of the input data register (0x00) to the wiper register moving the wiper to the bottom−most position (W = terminal B). This transfer is independent of whether new data has been input or not because CS acts as the transfer command. A RS RS Wiper Register and Decoder RS W RS B Figure 14. CAT5172 Equivalent DPP Circuit The equation for determining the digitally programmed output resistance between W and B is Programming: Variable Resistor R WB + D R AB ) R W 256 Rheostat Mode The resistance between terminals A and B, RAB, has a nominal value of 50 kW or 100 kW and has 256 contact points accessed by the wiper terminal, plus the B terminal contact. Data in the 8−bit Wiper register is decoded to select one of these 256 possible settings. The wiper’s first connection is at the B terminal, corresponding to control position 0x00. Ideally this would present a 0 W between the Wiper and B, but just as with a mechanical rheostat there is a small amount of contact resistance to be considered, there is a wiper resistance comprised of the RON of the FET switch connecting the wiper output with its respective contact point. In CAT5172 this ‘contact’ resistance is typically 50 W. Thus a connection setting of 0x00 yields a minimum resistance of 50 W between terminals W and B. For a 100 kW device, the second connection, or the first tap point, corresponds to 441 W (RWB = RAB/256 + RW = 390.6 + 50 W) for data 0x01. The third connection is the next tap point, is 831 W (2 x 390.6 + 50 W) for data 0x02, and so on. Figure 14 shows a simplified equivalent circuit where the last resistor string will not be accessed; therefore, there is 1 LSB less of the nominal resistance at full scale in addition to the wiper resistance. (eq. 1) where D is the decimal equivalent of the binary code loaded in the 8−bit Wiper register, RAB is the end−to−end resistance, and RW is the wiper resistance contributed by the on resistance of the internal switch. In summary, if RAB = 100 kW and the A terminal is open circuited, the following output resistance RWB will be set for the indicated Wiper register codes: Table 7. CODES AND CORRESPONDING RWB RESISTANCE FOR RAB = 100 kW, VDD = 5 V D (Dec.) RWB (W) Output State 255 99,559 Full Scale (RAB – 1 LSB + RW) 128 50,050 Midscale 1 441 1 LSB 0 50 Zero Scale (Wiper Contact Resistance) Be aware that in the zero−scale position, the wiper resistance of 50 W is still present. Current flow between W and B in this condition should be limited to a maximum pulsed current of no more than 20 mA. Failure to heed this restriction can cause degradation or possible destruction of the internal switch contact. Similar to the mechanical potentiometer, the resistance of the DPP (Digitally Programmed Potentiometer) between the wiper W and terminal A also produces a digitally controlled complementary resistance RWA. When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is R WA(D) + 256 * D R AB ) R W 256 http://onsemi.com 8 (eq. 2) CAT5172 Terminal Voltage Operating Range For RAB = 100 kW and the B terminal open circuited, the following output resistance RWA will be set for the indicated Wiper register codes. The CAT5172 VDD and GND power supply define the limits for proper 3−terminal digital potentiometer operation. Signals or potentials applied to terminals A, B or the wiper must remain inside the span of VDD and GND. Signals which attempt to go outside these boundaries will be clamped by the internal forward biased diodes. Table 8. CODES AND CORRESPONDING RWA RESISTANCE FOR RAB = 100 kW, VDD = 5 V D (Dec.) RWA (W) Output State 255 441 Full Scale 128 50,050 Midscale 1 99,659 1 LSB 0 100,050 Zero Scale VDD W, A, B Typical device to device resistance matching is lot dependent and may vary by up to ±20%. CAT5172 LOGIC SPI Compatible 3−Wire Serial Bus Control of CAT5172 is through a 3−wire SPI compatible digital interface (SDI, CS, and CLK). The CLK input is rising−edge sensitive and requires crisp transitions to avoid clocking incorrect data into the serial input register. When CS is low, the clock loads data into the serial register on each positive clock edge (Figure 1). Each 8−bit serial word must be loaded starting with the MSB. The format of the word is shown in Table 6. Data loaded into CAT5172’s 8−bit serial input register is transferred to the internal Wiper register when the CS line returns to logic high. Extra MSB bits are ignored. GND Figure 16. Power−up Sequence Because ESD protection diodes limit the voltage compliance at terminals A, B, and W (see Figure 15), it is recommended that VDD/GND be powered before applying any voltage to terminals A, B, and W. The ideal power−up sequence is: GND, VDD, digital inputs, and then VA/B/W. The order of powering VA, VB, VW, and the digital inputs is not important as long as they are powered after VDD/GND. ESD Protection Digital Input Power Supply Bypassing LOGIC Good design practice employs compact, minimum lead length layout design. Leads should be as direct as possible. It is also recommended to bypass the power supplies with quality low ESR Ceramic chip capacitors of 0.01 mF to 0.1 mF. Low ESR 1 mF to 10 mF tantalum or electrolytic capacitors can also be applied at the supplies to suppress transient disturbances and low frequency ripple. As a further precaution digital ground should be joined remotely to the analog ground at one point to minimize the ground bounce. GND Potentiometer VDD VDD C3 10 mF GND + C1 0.1 mF CAT5172 GND Figure 15. ESD Protection Networks Figure 17. Power Supply Bypassing http://onsemi.com 9 CAT5172 PACKAGE DIMENSIONS SOT−23, 8 Lead CASE 527AK−01 ISSUE A E1 e SYMBOL MIN A 0.90 A1 0.00 A2 0.90 A3 0.60 0.80 b 0.28 0.38 c 0.08 0.22 E b 1.45 0.15 1.30 1.10 2.90 BSC E 2.80 BSC E1 1.60 BSC 0.65 BSC L TOP VIEW MAX D e PIN #1 IDENTIFICATION NOM 0.45 0.30 L1 0.60 0.60 REF L2 0.25 REF θ 0° 8° D A2 A q A3 c L1 A1 SIDE VIEW L L2 END VIEW Notes: (1) All dimensions in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-178. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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