AD AD5260BRU200

a
FEATURES
256 Positions
AD5260 – 1-Channel
AD5262 – 2-Channel (Independently Programmable)
Potentiometer Replacement
20 k⍀, 50 k⍀, 200 k⍀
Low Temperature Coefficient 35 ppm/ⴗC
4-Wire SPI-Compatible Serial Data Input
5 V to 15 V Single-Supply; ⴞ5.5 V Dual-Supply Operation
Power ON Mid-Scale Preset
APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Stereo Channel Audio Level Control
Programmable Voltage to Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Low Resolution DAC Replacement
1-/2-Channel
15 V Digital Potentiometers
AD5260/AD5262
FUNCTIONAL BLOCK DIAGRAMS
A
W
B
SHDN
AD5260
VDD
RDAC
REGISTER
VSS
VL
CS
POWER-ON
RESET
LOGIC
PR
8
CLK
SDI
SDO
SERIAL INPUT REGISTER
GND
A1
W1 B1
A2
W2 B2
SHDN
The AD5260/AD5262 provide a single- or dual-channel, 256position, digitally controlled variable resistor (VR) device.* These
devices perform the same electronic adjustment function as a
potentiometer or variable resistor. Each channel of the AD5260/
AD5262 contains a fixed resistor with a wiper contact that taps the
fixed resistor value at a point determined by a digital code loaded
into the SPI-compatible serial-input register. The resistance between
the wiper and either end point of the fixed resistor varies linearly
with respect to the digital code transferred into the VR latch. The
variable resistor offers a completely programmable value of resistance,
between the A terminal and the wiper or the B terminal and the wiper.
The fixed A to B terminal resistance of 20 kW, 50 kW, or 200 kW has
a nominal temperature coefficient of 35 ppm/∞C. Unlike the majority
of the digital potentiometers in the market, these devices can operate
up to 15 V or ±5 V provided proper supply voltages are furnished.
Each VR has its own VR latch, which holds its programmed resistance
value. These VR latches are updated from an internal serial-to-parallel
shift register, which is loaded from a standard 3-wire serial-input
digital interface. The AD5260 contains an 8-bit serial register
while the AD5262 contains a 9-bit serial register. Each bit is clocked
into the register on the positive edge of the CLK. The AD5262
address bit determines the corresponding VR latch to be loaded
with the last 8 bits of the data word during the positive edging of
CS strobe. A serial data output pin at the opposite end of the serial
register enables simple daisy chaining in multiple VR applications
without additional external decoding logic. An optional reset pin
(PR) forces the wiper to the mid-scale position by loading 80H into
the VR latch.
VDD
RDAC1 REGISTER
VSS
RDAC2 REGISTER
VL
CS
POWER-ON
RESET
LOGIC
PR
8
CLK
SDI
SERIAL INPUT REGISTER
GND
AD5262
SDO
100
RWA
PERCENT OF NOMINAL
END-TO-END RESISTANCE – % RAB
GENERAL DESCRIPTION
RWB
75
50
25
0
0
64
128
192
256
CODE – Decimal
Figure 1. RWA and RWB vs. Code
REV. 0
The AD5260/AD5262 are available in thin surface-mount TSSOP-14
and TSSOP-16 packages. All parts are guaranteed to operate over
the extended industrial temperature range of –40∞C to +85∞C.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
*The terms digital potentiometers, VR, and RDAC are used interchangeably.
V, V = 0 V or, V = +5 V, V = –5 V, V = +5 V, V = +5 V,
AD5260/AD5262–SPECIFICATIONS (VV ==0 +15
V, – 40ⴗC < T < +85ⴗC unless otherwise noted.)
DD
SS
B
DD
SS
L
A
A
ELECTRICAL CHARACTERISTICS 20 kW, 50 kW, 200 kW VERSIONS
Parameter
Symbol
Conditions
DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs
Resistor Differential NL2
R-DNL
RWB, VA = NC
R-INL
RWB, VA = NC
Resistor Nonlinearity2
RAB
TA = 25∞C
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
RAB/T
Wiper = No Connect
IW = 1 V/RAB
Wiper Resistance
RW
Ch 1 and 2 RWB, DX = 80H
Channel Resistance Matching (AD5262 only) RWB/RWB
Resistance Drift
RAB
Min
Typ1
Max
Unit
–1
–1
–30
± 1/4
± 1/2
+1
+1
30
LSB
LSB
%
ppm/∞C
W
%
%
35
60
0.1
0.05
150
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs
Resolution
N
8
Differential Nonlinearity4
DNL
–1
Integral Nonlinearity4
INL
–1
Code = 80H
Voltage Divider Temperature Coefficient DVW/DT
Code = FFH
–2
Full-Scale Error
VWFSE
Zero-Scale Error
VWZSE
Code = 00H
0
± 1/4
± 1/2
5
–1
1
RESISTOR TERMINALS
Voltage Range5
Capacitance6 Ax, Bx
25
V
pF
55
pF
VA, B, W
CA,B
Capacitance6 Wx
CW
Common-Mode Leakage Current
Shut Down Current7
ICM
ISHDN
DIGITAL INPUTS and OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Output Logic High (SDO)
Output Logic Low (SDO)
Input Current8
Input Capacitance6
VIH
VIL
VIH
VIL
VOH
VOL
IIL
CIL
POWER SUPPLIES
Logic Supply
Power Single-Supply Range
Power Dual-Supply Range
Logic Supply Current
Positive Supply Current
Negative Supply Current
Power Dissipation9
VL
VDD RANGE
VDD/SS RANGE
IL
IDD
ISS
PDISS
Power Supply Sensitivity
PSS
VSS
f = 5 MHz,
measured to GND, Code = 80H
f = 1 MHz,
measured to GND, Code = 80H
VA =VB = VDD /2
+1
+1
+0
2
VDD
1
5
2.4
0.8
VL = 3 V, VSS = 0 V
VL = 3 V, VSS = 0 V
RPULL-UP = 2 kW to 5 V
IOL = 1.6 mA, VLOGIC = 5 V
VIN = 0 V or 5 V
2.1
0.6
4.9
5
VSS = 0 V
VL = 5 V
VIH = 5 V or VIL = 0 V
VSS = –5 V
VIH = 5 V or VIL = 0 V,
VDD = +5 V, VSS = –5 V
DVDD = +5 V, ±10%
2.7
4.5
± 4.5
0.003
0.4
±1
Bits
LSB
LSB
ppm/∞C
LSB
LSB
nA
mA
V
V
V
V
V
V
mA
pF
5.5
16.5
± 5.5
60
1
1
0.3
V
V
V
mA
mA
mA
mW
0.01
%/%
6, 10
DYNAMIC CHARACTERISTICS
Bandwidth –3 dB
Total Harmonic Distortion
BW
THDW
VW Settling Time
tS
Crosstalk11
CT
Analog Crosstalk
Resistor Noise Voltage
CTA
eN_WB
RAB = 20 kW/50 kW/200 kW
VA = 1 VRMS, VB = 0 V,
f = 1 kHz, RAB = 20 kW
VA = +5 V, VB = –5 V,
±1 LSB error band, RAB = 20 kW
VA = VDD, VB = 0 V,
Measure VW with Adjacent
RDAC Making Full-Scale
Code Change (AD5262 only)
VA1 = VDD, VB1 = 0V,
Measure VW1 with
VW2 = 5 V p-p @ f = 10 kHz,
RAB = 20 kW/200 kW (AD5262 only)
RWB = 20 kW
f = 1 kHz
–2–
310/130/30
0.014
kHz
%
5
ms
1
nV–s
–64
dB
13
nV/÷Hz
REV. 0
AD5260/AD5262
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
25
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
6, 12
INTERFACE TIMING CHARACTERISTICS apply to all parts
Clock Frequency
fCLK
Input Clock Pulsewidth
tCH, tCL
Clock level high or low
Data Setup Time
tDS
Data Hold Time
tDH
CLK to SDO Propagation Delay13
tPD
RL = 1 kΩ, CL < 20pF
CS Setup Time
tCSS
CS High Pulsewidth
tCSW
Reset Pulsewidth
tRS
CLK Fall to CS Rise Hold Time
tCSH
CS Rise to Clock Rise Setup
tCS1
20
10
10
1
5
20
50
0
10
160
NOTES
The AD5260/AD5262 contains 1,968 transistors. Die Size: 89 mil. × 105 mil. 9,345 sq. mil.
1
Typicals represent average readings at 25°C and VDD = +5 V, VSS = –5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W = VDD/R for both VDD = +5 V, VSS = –5 V.
3
VAB = VDD, Wiper (VW) = No connect.
4
INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = V DD and VB = 0V. DNL
specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the Ax terminals. All Ax terminals are open-circuit in shutdown mode.
8
Worst-case supply current consumed when input all logic-input levels set at 2.4 V, standard characteristic of CMOS logic.
9
PDISS is calculated from (IDD ⫻ VDD). CMOS logic level inputs result in minimum power dissipation.
10
All dynamic characteristics use V DD = +5 V, VSS = –5 V, VL = +5 V.
11
Measured at a V W pin where an adjacent V W pin is making a full-scale voltage change.
12
See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Switching characteristics are measured using V L = 5 V.
13
Propagation delay depends on value of V DD, RL, and CL.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25°C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +15 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, –7 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
AX – BX, AX – WX, BX – WX
Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Digital Inputs and Output Voltage to GND . . . . . . . 0 V, 7 V
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
REV. 0
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Thermal Resistance3 θ JA
TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the A, B, and W terminals at a given resistance setting.
3
Package Power Dissipation = (T J MAX – TA)/ θ JA
–3–
AD5260/AD5262
ORDERING GUIDE
Model
RAB (kW)
Temperature
Package
Description
Package
Option
No. of Parts
per Container
Branding
Information*
AD5260BRU20
AD5260BRU20-REEL7
AD5260BRU50
AD5260BRU50-REEL7
AD5260BRU200
AD5260BRU200-REEL7
AD5262BRU20
AD5262BRU20-REEL7
AD5262BRU50
AD5262BRU50-REEL7
AD5262BRU200
AD5262BRU200-REEL7
20
20
50
50
200
200
20
20
50
50
200
200
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
TSSOP-14
TSSOP-14
TSSOP-14
TSSOP-14
TSSOP-14
TSSOP-14
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
96
1000
96
1000
96
1000
96
1000
96
1000
96
1000
AD5260B20
AD5260B20
AD5260B50
AD5260B50
AD5260B200
AD5260B200
AD5262B20
AD5262B20
AD5262B50
AD5262B50
AD5262B200
AD5262B200
*Line 1 contains part number, line 2 contains differentiating detail by part type and ADI logo symbol, line 3 contains date code YWW.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5260/AD5262 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
AD5260/AD5262
Table I. AD5260 8-Bit Serial-Data Word Format
DATA
B7
SDI
CS
VOUT
ADDR
DATA
B6
B5
B4
B3
B2
B1
B0
B8
B7
B6
B5
B4
B3
B2
B1
B0
D7 D6
MSB
27
D5
D4
D3
D2
D1
D0
LSB
20
A0
D7 D6
MSB
27
D5
D4
D3
D2
D1
D0
LSB
20
28
1
0
CLK
Table II. AD5262 9-Bit Serial-Data Word Format
D7
D6
D5
D4
D3
D2
D1
SDI
(DATA IN)
D0
1
Ax OR Dx
Dx
0
1
0
1
SDO
(DATA OUT)
RDAC REGISTER LOAD
tDH
tDS
1
Aⴕx OR Dⴕx
Dⴕx
0
tPD_MAX
0
1
tCH
1
tCS1
CLK
0
0
Figure 2a. AD5260 Timing Diagram
CS
tCSS
1
tCSH
tCL
tCSW
0
tS
SDI
1
0
1
CLK
CS
0
1
A0
D7
D6
D5
D4
D3
D2
D1
VOUT
D0
ⴞ1 LSB
VDD
ⴞ1 LSB ERROR BAND
0V
Figure 2c. Detail Timing Diagram
RDAC REGISTER LOAD
0
1
VOUT
PR
0
1
0
tRS
tS
VOUT VDD
0V ⴞ1 LSB ERROR BAND
Figure 2b. AD5262 Timing Diagram
ⴞ1 LSB
Figure 2d. Preset Timing Diagram
REV. 0
–5–
AD5260/AD5262
AD5260 PIN CONFIGURATION
AD5262 PIN CONFIGURATION
A 1
14
SDO
SDO 1
16
A2
W 2
13
NC
A1 2
15
W2
12
VL
W1 3
11
VSS
B1 4
B 3
VDD 4
SHDN
CLK
AD5260
TOP VIEW 10 GND
(Not to Scale)
9 PR
6
8
SHDN
CS
AD5260 PIN FUNCTION DESCRIPTIONS
Pin
Number
Mnemonic
Description
1
2
3
4
A
W
B
VDD
5
SHDN
6
CLK
7
8
SDI
CS
A Terminal
Wiper Terminal
B Terminal
Positive power supply, specified
for operation at both 5 V or 15 V.
(Sum of |VDD| + |VSS| £ 15 V)
Active low input. Terminal A
open-circuit. Shutdown controls.
Variable Resistors of RDAC.
Serial Clock Input, positive edge
triggered.
Serial Data Input
Chip Select Input, Active Low.
When CS returns high, data will
be loaded into the RDAC register.
Active low preset to mid-scale; sets
RDAC registers to 80H.
Ground
Negative Power Supply, specified
for operation from 0 V to –5 V.
Logic Supply Voltage, needs to be
same voltage as the digital logic
controlling the AD5260.
No Connect (Users should not
connect anything other than dummy
pad on this pin)
Serial Data Output, Open Drain
transistor requires pull-up resistor.
9
PR
10
11
GND
VSS
12
VL
13
NC
14
SDO
14
B2
13
VL
TOP VIEW 12 V
SS
(Not to Scale)
11 GND
6
VDD 5
5
SDI 7
AD5262
CLK 7
10
PR
SDI 8
9
CS
AD5262 PIN FUNCTION DESCRIPTIONS
–6–
Pin
Number
Mnemonic
Description
1
SDO
2
3
4
5
A1
W1
B1
VDD
6
SHDN
7
CLK
8
9
SDI
CS
10
PR
11
12
GND
VSS
13
VL
14
15
16
B2
W2
A2
Serial Data Output, Open Drain
transistor requires pull-up resistor.
A Terminal RDAC #1
Wiper RDAC #1, address A0 = 02
B Terminal RDAC #1
Positive power supply, specified for
operation at both 5 V or 15 V.
(Sum of |VDD|+|VSS|£ 15 V)
Active low input. Terminal A
open-circuit. Shutdown controls
Variable Resistors #1 through #2.
Serial Clock Input, positive edge
triggered.
Serial Data Input.
Chip Select Input, Active Low.
When CS returns high, data in
the serial input register is decoded,
based on the address Bit A0, and
loaded into the target RDAC register.
Active low preset to mid-scale sets
RDAC registers to 80H.
Ground
Negative Power Supply, specified
for operation at both 0 V or –5 V
(Sum of |VDD| + |VSS| <15 V).
Logic Supply Voltage, needs to be
same voltage as the digital logic
controlling the AD5262.
B Terminal RDAC #2
Wiper RDAC #2, address A0 = 12
A Terminal RDAC #2
REV. 0
AD5260/AD5262
THEORY OF OPERATION
The AD5260/AD5262 provide a single- or dual-channel, 256-position
digitally controlled variable resistor (VR) device and operate up to
15 V maximum voltage. Changing the programmed VR settings
is accomplished by clocking an 8-/9-bit serial data word into the
SDI (Serial Data Input) pin. For the AD5262, the format of this
data word is one address bit. A0 represents the first bit B8, then
followed by eight data bits B7–B0 with MSB first. Tables I and II
provide the serial register data word format. See Table III for the
AD5262 address assignment to decode the location of the VR latch
receiving the serial register data in bits B7 through B0. VR outputs
can be changed one at a time in random sequence. The AD5260/
AD5262 presets to a mid-scale, simplifying fault condition recovery at power-up. Mid-scale can also be achieved at any time by
asserting the PR pin. Both parts have an internal power ON preset
that places the wiper in a mid-scale preset condition at power ON.
Operation of the power ON preset function depends only on the
state of the VL pin.
The AD5260/AD5262 contains a power shutdown SHDN pin,
which places the RDAC in an almost zero power consumption
state where terminals Ax are open circuited, and the wiper W is connected to B, resulting in only leakage currents being consumed in
the VR structure. In the shutdown mode, the VR latch settings are
maintained so that, returning to operational mode from power
shutdown, the VR settings return to their previous resistance values.
Table III. AD5262 Address Decode Table
A0
Latch Loaded
0
1
RDAC#1
RDAC#2
DIGITAL INTERFACING
The AD5260/AD5262 contains a 4-wire SPI-compatible
digital interface (SDI, SDO, CS, and CLK). For the AD5260,
the 8-bit serial word must be loaded with MSB first, and the
format of the word is shown in Table I. For the AD5262, the
9-bit serial word must be loaded with address bit A0 first, then
MSB of the data. The format of the word is shown in Table II.
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are used
for product evaluation, they should be debounced by a flip-flop or
other suitable means. Figure 3 shows more detail of the internal
digital circuitry. When CS is low, the clock loads data into the
serial register on each positive clock edge (see Table IV).
Table IV. Truth Table
CLK CS PR
SHDN
L
≠*
L
L
H
H
H
H
X
X
X
≠
H
X
H
H
L
H
H
H
X
X
H
H
≠
H
H
L
Register Activity
No SR effect, enables SDO pin
Shift one bit in from the SDI pin.
The eighth previously entered bit is
shifted out of the SDO pin.
Load SR data into RDAC latch
No Operation
Sets all RDAC latches to Mid-Scale,
wiper centered, and SDO latch
cleared.
Latches all RDAC latches to 80H.
Open circuits all resistor A–terminals,
connects W to B, turns off SDO
output transistor.
*≠ = positive edge, X = don’t care, SR = shift register
The data setup and data hold times in the specification table
determine the data valid time requirements. The AD5260 uses
an 8-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic high.
For the AD5262 the last 9 bits of the data word entered into the
serial register are held when CS returns high. Any extra bits are
ignored. At the same time CS goes high, it gates the address
decoder enabling AD5262 one of two positive edge-triggered
AD5262 RDAC latches (see Figure 4).
CS
AD5260/AD5262
RDAC 1
ADDR
DECODE
RDAC 2
CLK
VL
CS
RDAC
LATCH
#1
W1
B1
PR
EN
SDI
A0
D7
D6
D5
D4
D3
D2
D1
D0
The target RDAC latch is loaded with the last 8 bits of the serial data
word completing one RDAC update. For the AD5262, two separate
9-bit data words must be clocked in to change both VR settings.
During shutdown (SHDN) the SDO output pin is forced to the
off (logic high state) to disable power dissipation in the pull-up
resistor. See Figure 5 for equivalent SDO output circuit schematic.
ADDR
DEC
SER
REG
SDO
Figure 4. Equivalent Input Control Logic
A1
CLK
SERIAL
REGISTER
SDI
VDD
SHDN
A2
RDAC
LATCH
#2
W2
SDO
CS
B2
PR
SDI
SERIAL
REGISTER
D
CK
PR
POWERON
PRESET
RS
CLK
SHDN
PR
VSS
GND
Q
Figure 5. Detail SDO Output Schematic of the AD5260
Figure 3. AD5262 Block Diagram
REV. 0
–7–
AD5260/AD5262
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure as shown in Figure 6. This applies
to digital input pins CS, SDI, SDO, PR, SHDN, and CLK.
of this data sheet. An internal level shift circuit ensures that the
common-mode voltage range of the three terminals extends
from VSS to VDD regardless of the digital input level.
340⍀
POWER-UP SEQUENCE
LOGIC
Since there are diodes to limit the voltage compliance at terminals A, B, and W (see Figure 9), it is important to power VDD/VSS
first before applying any voltage to terminals A, B, and W. Otherwise, the diode will be forward biased such that VDD/VSS will be
powered unintentionally and may affect the rest of the user’s circuit.
The ideal power-up sequence is in the following order: GND,
VDD, VSS, VL, Digital Inputs, and VA/B/W . The order of powering
VA, VB, VW, and Digital Inputs is not important as long as they
are powered after VDD/VSS.
Figure 6. ESD Protection of Digital Pins
A, B, W
VSS
Daisy-Chain Operation
Figure 7. ESD Protection of Resistor Terminals
The serial-data output (SDO) pin contains an open drain
n-channel FET. This output requires a pull-up resistor to transfer data to the next package’s SDI pin. This allows for daisy
chaining several RDACs from a single processor serial data line.
The pull-up resistor termination voltage can be larger than the VDD
supply voltage. It is recommended to increase the Clock period
when using a pull-up resistor to the SDI pin of the following device
in series because capacitive loading at the daisy-chain node
SDO-SDI between devices may induce time delay to subsequent
devices. Users should be aware of this potential problem to achieve
data transfer successfully (see Figure 10). If two AD5260s are daisychained, this requires a total of 16 bits of data. The first 8 bits,
complying with the format shown in Table I, go to U2, and the
second 8 bits with the same format go to U1. The CS should be
kept low until all 16 bits are clocked into their respective serial
registers, and the CS is then pulled high to complete the operation.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum-lead length
layout design. The leads to the input should be as direct as possible with a minimum conductor length. Ground paths should
have low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01 mF–0.1 mF disc or chip ceramics capacitors. Low-ESR 1 mF to 10 mF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize any
transient disturbance (see Figure 8). Notice the digital ground
should also be joined remotely to the analog ground to minimize
the ground bounce.
VDD
ⴙ
C3
C4
VSS
C1
10␮F
0.1␮F
ⴙ
C2
10␮F
0.1␮F
VDD
VDD
AD5260
VSS
GND
U1
␮C
MOSI
SCLK SS
SDI
SDO
CS CLK
RP
2.2k⍀
AD5260
U2
SDI
SDO
CS CLK
Figure 8. Power Supply Bypassing
TERMINAL VOLTAGE OPERATING RANGE
Figure 10. Daisy-Chain Configuration
The AD5260/AD5262 positive VDD and negative VSS power
supply defines the boundary conditions for proper 3-terminal
digital potentiometer operation. Supply signals present on terminals A, B, and W that exceed VDD or VSS will be clamped by the
internal forward biased diodes (see Figure 9).
RDAC STRUCTURE
The RDAC contains a string of equal resistor segments, with an
array of analog switches, that act as the wiper connection. The
number of positions is the resolution of the device. The AD5260/
AD5262 have 256 connection points allowing it to provide better
than 0.4% set-ability resolution. Figure 11 shows an equivalent
structure of the connections between the three terminals that
make up one channel of the RDAC. The SWA and SWB will
always be ON, while one of the switches SW(0) to SW(2N – 1)
will be ON one at a time depending on the resistance position
decoded from the data bits. Since the switch is not ideal, there is
a 60 W wiper resistance, RW. Wiper resistance is a function of
supply voltage and temperature. The lower the supply voltage, the
higher the wiper resistance. Similarly, the higher the temperature,
the higher the wiper resistance. Users should be aware of the
contribution of the wiper resistance when accurate prediction of
the output resistance is needed.
VDD
A
W
B
VSS
Figure 9. Maximum Terminal Voltages Set by VDD and VSS
The ground pin of the AD5260/AD5262 device is primarily used
as a digital ground reference, which needs to be tied to the PCB’s
common ground. The digital input control signals to the AD5260/
AD5262 must be referenced to the device ground pin (GND),
and must satisfy the logic level defined in the specification table
–8–
REV. 0
AD5260/AD5262
Note that in the zero-scale condition a finite wiper resistance of
60 W is present. Care should be taken to limit the current flow
between W and B in this state to no more than 20 mA to avoid
degradation or possible destruction of the internal switches.
Ax
SHDN
RS
RS
D7
D6
D5
D4
D3
D2
D1
D0
Like the mechanical potentiometer the RDAC replaces, the
AD5260/AD5262 parts are totally symmetrical. The resistance
between the wiper W and terminal A also produces a digitally
controlled complementary resistance RWA. Figure 12 shows the
symmetrical programmability of the various terminal connections.
When RWA is used, the B–terminal can be let floating or tied to the
wiper. Setting the resistance value for RWA starts at a maximum
value of resistance and decreases as the data loaded in the latch
is increased in value. The general equation for this operation is:
RS
Wx
RDAC
LATCH
AND
DECODE
RS
DIGITAL CIRCUITRY
OMITTED FOR CLARITY
R WA ( D ) =
Bx
R S = R AB /2 N
(2)
For example, RAB = 20 kW, when VA = 0 V and B–terminal is open,
the following output resistance RWA will be set for the following
RDAC latch codes. The result will be the same if terminal B is
tied to W:
Figure 11. Simplified RDAC Architecture
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistances of the RDAC between terminals A and B
are available with values of 20 kW, 50 kW, and 200 kW. The final
three digits of the part number determine the nominal resistance
value, e.g., 20 kW = 20; 50 kW = 50; 200 kW = 200. The nominal
resistance (RAB) of the VR has 256 contact points accessed by the
wiper terminal, plus the B terminal contact. The 8-bit data in the
RDAC latch is decoded to select one of the 256 possible settings.
Assuming a 20 kW part is used, the wiper’s first connection starts
at the B terminal for data 00H. Since there is a 60 W wiper contact
resistance, such connection yields a minimum of 60 W resistance
between terminals W and B. The second connection is the first tap
point corresponds to 138 W (RWB = RAB/256 RW = 78 W 60 W)
for data 01H. The third connection is the next tap point representing 216 W (78 2 60) for data 02H and so on. Each LSB data
value increase moves the wiper up the resistor ladder until the last
tap point is reached at 19982 W [RAB 1 LSB RW]. The wiper
does not directly connect to the B terminal. See Figure 11 for a
simplified diagram of the equivalent RDAC circuit.
D
(DEC)
RWA
(W)
Output State
256
128
1
0
60
10060
19982
20060
Full-Scale
Mid-Scale
1 LSB
Zero-Scale
20
RWA
RWB
RWA(D), RWB(D) ⴚ k⍀
16
The general equation determining the digitally programmed
output resistance between W and B is:
D
R WB ( D ) =
¥ R AB + R W
256
256 - D
¥ R AB + R W
256
12
8
4
RAB = 20K⍀
(1)
0
0
64
128
192
256
D – CODE in decimal
where D is the decimal equivalent of the binary code which is
loaded in the 8-bit RDAC register, and RAB is the nominal endto-end resistance.
For example, RAB = 20 kW, when VB = 0 V and A–terminal is
open circuit, the following output resistance values RWB will be
set for the following RDAC latch codes. The result will be the
same if terminal A is tied to W:
D
(DEC)
RWB
(W)
Output State
256
128
1
0
19982
10060
138
60
Full-Scale (RAB – 1 LSB + RW)
Mid-Scale
1 LSB
Zero-Scale (wiper contact resistance)
REV. 0
Figure 12. AD5260/AD5262 Equivalent RDAC Circuit
The typical distribution of the nominal resistance RAB from
channel to channel matches within ±1%. Device-to-device matching is process lot dependent with the worst case of ±30% variation.
On the other hand, since the resistance element is processed in
thin film technology, the change in RAB with temperature has a
low 35 ppm/∞C temperature coefficient.
–9–
AD5260/AD5262—Typical Performance Characteristics
0.10
RHEOSTAT MODE DNL – LSB
0.6
0.5
0.4
0.3
ⴙ12V
0.2
ⴞ5V
0.1
0
–0.1
–0.2
ⴙ15V
0
32
64
96 128 160 192 224 256
CODE – Decimal
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.25
TPC 1. R-INL vs. Code vs.
Supply Voltages
64
TA = ⴚ40ⴗC
0.2
TA = ⴙ25ⴗC TA = ⴙ85ⴗC
0.1
0
–0.1
–0.2
–0.3
TA = ⴙ125ⴗC
–0.4
0
32
64
0
–0.2
ⴞ5V
ⴙ5V
0.1
ⴙ15V
0
–0.1
–0.2
–0.3
0
32
64
96 128 160 192 224 256
CODE – Decimal
RHEOSTAT MODE INL – LSB
AVG –3␴
0
–0.5
–0.8
5
10
VDD – VSS – V
15
20
TPC 7. INL vs. Supply Voltages
32
64
96 128 160 192 224 256
CODE – Decimal
0.4
0.3
0.2
ⴞ5V
ⴙ15V
0.1
0
–0.1
–0.2
–0.3
ⴙ5V
–0.4
–0.5
0
32
64
96 128 160 192 224 256
CODE – Decimal
RON @ VDD/V SS = ⴙ5V/0V
104
AVG +3␴
1.0
0.5
AVG
0
AVG –3␴
–0.5
–1.0
–2.0
0
124
84
RON @ V DD/V SS = ⴙ5V/ⴚ5V
64
44
RON @ VDD/VSS = ⴙ15V/0V
24
–1.5
0
TA = ⴙ25ⴗC
–0.6
TPC 6. DNL vs. Code vs.
Supply Voltages
1.5
AVG
TA = ⴚ40ⴗC
–0.4
TPC 3. INL vs. Code, V DD /V SS = ± 5 V
2.0
0.5
TA = ⴙ85ⴗC
0.2
TPC 5. INL vs. Code vs.
Supply Voltages
AVG +3␴
VDD = ⴙ5V
VSS = ⴚ5V
RAB = 20k⍀
0.5
0.2
–0.4
96 128 160 192 224 256
CODE – Decimal
1.0
–1.0
0.6
0.4
–1.0
96 128 160 192 224 256
CODE – Decimal
POTENTIOMETER MODE DNL – LSB
0.3
POTENTIOMETER MODE INL – LSB
POTENTIOMETER MODE DNL – LSB
32
TA = ⴙ125ⴗC
0.8
0.3
0.4
TPC 4. DNL vs. Code,
VDD/VSS = ± 5 V
POTENTIOMETER MODE INL – LSB
0
TPC 2. R-DNL vs. Code vs.
Supply Voltages
0.5
–0.5
ⴞ5V ⴙ15V
WIPER RESISTANCE – ⍀
RHEOSTAT MODE INL – LSB
ⴙ5V
1.0
ⴙ5V
ⴙ12V
POTENTIOMETER MODE INL – LSB
0.8
0.7
0
5
10
VDD – VSS – V
15
20
TPC 8. R-INL vs. Supply Voltages
–10–
4
ⴚ5
ⴚ1
3
7
VDD – V
11
15
TPC 9. Wiper ON Resistance vs.
Bias Voltage
REV. 0
AD5260/AD5262
0
2.5
2.0
VDD/V SS = +5V/0V
ZSE – LSB
VDD/V SS = +15V/0V
FSE – LSB
IDD/I SS SUPPLY CURRENT – ␮A
–0.5
1
–1.0
VDD/V SS = ⴞ5V
–1.5
1.5
VDD/V SS = ⴞ5V
1.0
VDD/V SS = +15V/0V
0.5
–2.0
VDD/V SS = +5V/0V
–20
0
20
40
60
TEMPERATURE – ⴗC
80
0
–40
100
TPC 10. Full-Scale Error
40
0
20
60
TEMPERATURE – ⴗC
–20
80
VDD/V SS = 5V/0V VLOGIC = 5V
ILOGIC – ␮A
ILOGIC – ␮A
27.0
VDD/V SS = ⴞ5V
100
25.5
25.0
59
26
92
TEMPERATURE – ⴗC
125
VDD/V SS = 5V/0V VLOGIC = 3V
0
1
2
3
4
6
100
0
50k⍀
–6
80
–12
60
20k⍀
20
0
–18
–24
–30
–36
–20
–42
200k⍀
–40
–60
60
50
50k⍀
30
20
10
0
–10
–20
5
20k⍀
40
200k⍀
0
32
64
TA = 25ⴗC
96 128 160 192 224 256
CODE – Decimal
TPC 15. Rheostat Mode Tempco
DRWB /DT vs. Code
TPC 14. ILOGIC vs. Digital Input
Voltage
120
40
CODE = FFH
80H
40H
20H
10H
08H
04H
02H
01H
–48
0
32
64
125
70
VIH – V
TPC 13. ILOGIC vs. Temperature
POTENTIOMETER MODE TEMPCO – ppm/ⴗC
10
GAIN – dB
–7
26
59
92
TEMPERATURE – ⴗC
TPC 12. Supply Current vs.
Temperature
VDD/V SS = +15V/0V
26.5
–7
80
27.5
–54
1k
96 128 160 192 224 256
CODE – Decimal
TPC 16. Potentiometer Mode
DVWB /DT vs. Code
REV. 0
VDD/V SS = ⴞ5V
1k
26.0
VDD/V SS = ⴙ15V/0V
0.01
TPC 11. Zero-Scale Error
28.0
24.5
–40
0.1
0.001
–40
100
RHEOSTAT MODE TEMPCO – ppm/ⴗC
–2.5
–40
VLOGIC = ⴙ5V
VIH = ⴙ5V
VIL = 0V
10k
100k
FREQUENCY – Hz
TPC 17. Gain vs. Frequency vs.
Code, RAB = 20 kW
–11–
1M
AD5260/AD5262
6
TA = 25ⴗC
CODE = FFH
80H
–6
–12
GAIN – dB
20H
–18
10H
–24
08H
–30
04H
–36
–18
–24
–30
–36
02H
–42
–42
01H
–48
–48
–54
1k
10k
100k
FREQUENCY – Hz
1M
–54
1k
TPC 18. Gain vs. Frequency vs. Code
RAB = 50 kW
CODE = FFH
80H
–12
20H
10H
08H
04H
–18
–30
–42
01H
10k
FREQUENCY – Hz
VIN = 50mV rms
–48 –3dB
VDD/V SS = ⴞ5V
BANDWIDTHS
–54
1k
10k
100k
1M
FREQUENCY – Hz
100k
TPC 20. –3 dB Bandwidth
600
500
500
CODE FFH
400
R = 50k⍀
f–3dB = 30kHz, R = 200k⍀
–24
–36
02H
R = 20k⍀
CODE = 80H, VA = VDD, VB = 0V
–PSRR @ VDD = ⴞ5V DC ⴞ 10% p-p AC
400
PSRR – dB
R = 200k⍀
f–3dB = 131kHz, R = 50k⍀
–6
40H
600
CODE = 80H
VDD/V SS = ⴞ5V
TA = 25ⴗC
f–3dB = 310kHz, R = 20k⍀
0
TPC 19. Gain vs. Frequency vs.
Code RAB = 200 kW
ILOGIC – ␮A
NORMALIZED GAIN FLATNESS – 0.1dB/DIV
0dB
6
TA = 25ⴗC
–6
40H
–12
GAIN – dB
0
GAIN – dB
6
0
300
VDD/V SS = ⴞ5V
200
300
200
VDD/V SS = +5V/0V
100
100
+PSRR @ VDD = ⴞ5V DC ⴞ 10% p-p AC
CODE 55H
100
1k
10k
FREQUENCY – Hz
TPC 21. Normalized Gain
Flatness vs. Frequency
100k
0
10k
100k
1M
FREQUENCY – Hz
10M
TPC 22. ILOGIC vs. Frequency
0
100
1k
1M
10k
100k
FREQUENCY – Hz
TPC 23. PSRR vs. Frequency
20mV/DIV
10mV/DIV
5V/DIV
5V/DIV
5V/DIV
1␮s/DIV
TPC 24. Mid-Scale Glitch
Energy, Code 80H to 7FH
20␮s/DIV
40ns/DIV
TPC 25. Large Signal Settling Time
TPC 26. Digital Feedthrough vs. Time
–12–
REV. 0
AD5260/AD5262
10
1
RAB = 20k⍀
RAB = 50k⍀
0.1
RAB = 200k⍀
0.01
0
32
64
CODE = 80H
VDD = VSS = ⴞ5V
0.05 SS = 135 UNITS
TPC 27. IMAX vs. Code
AVG –3␴
AVG
–0.05
CODE SET TO MID-SCALE
TA = 150ⴗC
3 LOTS
SAMPLE SIZE = 135
30
0
20
–0.10
AVG +3␴
10
–0.15
–0.20
0
96 128 160 192 224 256
CODE – Decimal
40
0.10
FREQUENCY
VA = VB = OPEN
TA = 25ⴗC
CHANGE IN TERMINAL RESISTANCE – %
THEORETICAL IWB_MAX – mA
100
0
–0.50 –0.40 –0.30 –0.20 –0.10 0 0.10 0.20
CHANNEL-TO-CHANNEL RAB MATCH – %
50 100 150 200 250 300 350 400 450 500
HOURS OF OPERATION AT 150ⴗC
TPC 28. Long-Term Resistance Drift
TPC 29. Channel-to-Channel
Resistance Matching (AD5262)
TEST CIRCUITS
Test Circuits 1 to 9 define the test conditions used in the product specification table.
VA
A
Vⴙ
V+ = VDD 10%
V+ = VDD
1LSB = V+/2N
DUT
VDD
W
PSRR (dB) = 20 LOG
A
V+
B
W
PSS (%/%) =
B
VMS
Test Circuit 1. Potentiometer Divider
Nonlinearity Error (INL, DNL)
Test Circuit 4. Power Supply Sensitivity (PSS, PSSR)
A
DUT
⌬VDD%
VMS
+13V
NC
A
⌬VMS%
⌬V
( ⌬VMS
)
DD
NC = NO CONNECT
W
VIN
IW
DUT
AD8610
OFFSET
GND
W
VOUT
B
–13V
B
VMS
Test Circuit 5. Gain vs. Frequency
Test Circuit 2. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
A
W
VW
I W = VDD /R NOMINAL
B
0.1V
ISW
B
VMS1
0.1V
ISW
CODE = 00H
W
DUT
VMS2
RSW =
DUT
VSS TO VDD
RW = [VMS1 – VMS2]/I W
A = NC
Test Circuit 6. Incremental ON Resistance
Test Circuit 3. Wiper Resistance
NC
VDD
DUT
VSS
A
GND
B
W
ICM
VCM
NC
Test Circuit 7. Common-Mode Leakage Current
REV. 0
–13–
AD5260/AD5262
TEST CIRCUITS (continued)
+5.0V
VDD
VLOGIC
␮C
I LOGIC
GND
CS
CS
SS
VDD
SCLK
CLK
MOSI
SDI
ⴞ5V p-p
ⴞ2.5V p-p
D = 80H
CLK
GND
VSS
SDI
–5.0V
DIGITAL INPUT
VOLTAGE
Figure 13. Bipolar Operation from Dual Supplies
Gain Control Compensation
Test Circuit 8. VLOGIC Current vs. Digital Input Voltage
Digital potentiometers are commonly used in gain control as in
the noninverting gain amplifier shown in Figure 14.
NC
VDD
DUT
VSS
A
GND
B
W
C2
4.7pF
ICM
R2
200k⍀
VCM
B
R1
47k⍀
NC
Test Circuit 9. Analog Crosstalk
C1
25pF
A
W
U1
VO
Vi
Figure 14. Typical Noninverting Gain Amplifier
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates output voltages at wiperto-B and wiper-to-A to be proportional to the input voltage at
A-to-B. Ignore the effect of the wiper resistance at the moment.
For example, connecting A-terminal to 5 V and B-terminal to
ground produces an output voltage at the wiper-to-B starting at
zero volts up to 1 LSB less than 5 V. Each LSB of voltage is equal
to the voltage applied across terminal AB divided by the 256 position of the potentiometer divider. Since the AD5260/AD5262
operates from dual supplies, the general equation defining the
output voltage at VW with respect to ground for any given input
voltage applied to terminals AB is:
D
(3)
VW ( D ) =
¥ VAB + VB
256
Operation of the digital potentiometer in the divider mode results
in more accurate operation over temperature. Unlike the rheostat
mode, the output voltage is dependent on the ratio of the internal
resistors RWA and RWB and not the absolute values; therefore, the
drift reduces to 5 ppm/∞C.
APPLICATIONS
Bipolar DC or AC Operation from Dual Supplies
The AD5260/AD5262 can be operated from dual supplies enabling
control of ground referenced AC signals or bipolar operation.
The AC signal, as high as VDD/VSS, can be applied directly across
terminals A–B with output taken from terminal W. See Figure 13
for a typical circuit connection.
Notice that when the RDAC B terminal parasitic capacitance is
connected to the op amp noninverting node, it introduces a zero
for the 1/bO term with +20 dB/dec, whereas a typical op amp GBP
has –20 dB/dec characteristics. A large R2 and finite C1 can cause
this Zero’s frequency to fall well below the crossover frequency.
Hence the rate of closure becomes 40 dB/dec and the system has
0∞ phase margin at the crossover frequency. The output may ring
or oscillate if the input is a rectangular pulse or step function.
Similarly, it is also likely to ring when switching between two
gain values because this is equivalent to a step change at the input.
Depending on the op amp GBP, reducing the feedback resistor
may extend the Zero’s frequency far enough to overcome the problem. A better approach, however, is to include a compensation
capacitor C2 to cancel the effect caused by C1. Optimum compensation occurs when R1 C1 = R2 C2. This is not an option
because of the variation of R2. As a result, one may use the relationship above and scale C2 as if R2 is at its maximum value. Doing so
may overcompensate and compromise the performance slightly
when R2 is set at low values. However, it will avoid the ringing or
oscillation at the worst case. For critical applications, C2 should
be found empirically to suit the need. In general, C2 in the range
of a few pF to no more than a few tenths of pF is usually adequate
for the compensation.
Similarly, there are W and A terminal capacitances connected to
the output (not shown). Fortunately their effect at this node is less
significant, and the compensation can be avoided in most cases.
Programmable Voltage Reference
For voltage divider mode operation, Figure 15, it is common
to buffer the output of the digital potentiometer unless the load is
much larger than RWB. Not only does the buffer serve the purpose of impedance conversion, but it also allows a heavier load
to be driven.
–14–
REV. 0
AD5260/AD5262
5V
1
VIN
Similar to the previous example, in the simpler (and much more
usual) case, where K = 1, a single digital pot AD5260, and U1
is replaced by a matched pair of resistors to apply Vi and – Vi at
the ends of the digital pot. The relationship becomes:
U1
AD5260
3
VOUT
A
GND
2
AD1582
5V
W
Ê
R 2 ˆ Ê 2 D2 ˆ
VO = Á1 +
- 1˜ ¥ Vi
R1 ˜¯ ÁË 256
Ë
¯
VO
AD8601
B
A1
If R2 is large, a few picofarad compensation capacitors may be
needed to avoid any gain peaking.
Figure 15. Programmable Voltage Reference
8-Bit Bipolar DAC
Figure 16 shows a low cost 8-bit bipolar DAC. It offers the same
number of adjustable steps but not the precision of conventional
DACs. The linearity and temperature coefficients, especially at low
values codes, are skewed by the effects of the digital potentiometer
wiper resistance. The output of this circuit is:
Ê 2D
ˆ
VO = Á
- 1˜ ¥ VREF
Ë 256
¯
Table VIII shows the result of adjusting D, with A2 configured as a
unity gain, a gain of 2, and a gain of 10. The result is a bipolar
amplifier with linearly programmable gain and 256-step resolution.
Table VIII. Result of Bipolar Gain Amplifier
(4)
+5V
AD5260
Vi
U2
U1
VO
OP2177
B
R
VOUT
+5VREF
TRIM
A2
A
ⴚ5VREF
+5V
R1 = •, R2 = 0
R1 = R2
R2 = 9R1
0
64
128
192
255
–1
–0.5
0
0.5
0.968
–2
–1
0
1
1.937
–10
–5
0
5
9.680
For applications that require high current adjustment such as a
laser diode driver or turnable laser, a boosted voltage source can
be considered (see Figure 18).
–5V
R
W1
D
Programmable Voltage Source with Boosted Output
W
VIN
(6)
Vi
GND
ADR425
VO
5V
OP2177
R1
10k⍀
P1
RBIAS
A
A1
–5V
W
U1
B
Figure 16. 8-Bit Bipolar DAC
CC
N1
A1
SIGNAL LO
IL
Bipolar Programmable Gain Amplifier
For applications that require bipolar gain, Figure 17 shows one
implementation. Digital potentiometer U1 sets the adjustment
range. The wiper voltage at W2 can therefore be programmed
between Vi and –KVi at a given U2 setting. Configuring A2 in
the noninverting mode allows linear gain and attenuation. The
transfer function is:
ˆ
VO Ê
R 2 ˆ Ê D2
= 1+
¥
¥ (1 + K ) - K ˜
Vi ÁË
R1 ˜¯ ÁË 256
¯
(5)
where K is the ratio of RWB1/RWA1 set by U1.
VDD
U2
OP2177
AD5262
VO
W2
A2
C1
A2
B2
R2
VSS
Vi
A1
B1
W1
VDD
–KVi
R1
U1
AD5262
OP2177
A1
VSS
Figure 17. Bipolar Programmable Gain Amplifier
REV. 0
U1= AD5260
A1= AD8601, AD8605, AD8541
P1= FDP360P, NDS9430
N1= FDV301N, 2N7002
Figure 18. Programmable Boosted Voltage Source
In this circuit, the inverting input of the op amp forces the VO to be
equal to the wiper voltage set by the digital potentiometer. The
load current is then delivered by the supply via the P-Ch FET P1.
The N-Ch FET N1 simplifies the op amp driving requirement.
A1 needs to be the rail-to-rail input type. Resistor R1 is needed to
prevent P1 from not turning off once it is on. The choice of R1 is a
balance between the power loss of this resistor and the output turnoff time. N1 can be any general-purpose signal FET; on the other
hand, P1 is driven in the saturation state, and therefore its power
handling must be adequate to dissipate (Vi – VO) IL power. This
circuit can source a maximum of 100 mA at 5 V supply. Higher
current can be achieved with P1 in a larger package. Note, a single
N-Ch FET can replace P1, N1, and R1 altogether. However, the output swing will be limited unless separate power supplies are used.
For precision application, a voltage reference such as ADR423,
ADR292, and AD1584 can be applied at the input of the digital
potentiometer.
Programmable 4-to-20 mA Current Source
A programmable 4-to-20 mA current source can be implemented
with the circuit shown in Figure 19. REF191 is a unique low
supply headroom and high current handling precision reference
–15–
AD5260/AD5262
that can deliver 20 mA at 2.048 V. The load current is simply the
voltage across terminals B-to-W of the digital pot divided by RS.
IL =
VREF ¥ D
RS
(7)
Programmable Low-Pass Filter
Digital potentiometer AD5262 can be used to construct a second
order Sallen Key Low-Pass Filter (see Figure 21). The design
equations are:
VO
=
Vi
ⴙ5V
2
U1
VIN
REF191
3
SLEEP
VOUT
C1
1␮F
GND
4
B W
AD5260
Q=
A
+5V
U2
–
(10)
1
1
+
R1C1 R2C 2
(11)
Users can first select some convenient values for the capacitors.
To achieve maximally flat bandwidth where Q = 0.707, let C1 be
twice the size of C2 and let R1 = R2. As a result, users can adjust
R1 and R2 to the same settings to achieve the desirable bandwidth.
RS
102⍀
OP1177
–2.048V TO VL
+
VL
RL
100⍀
–5V
(9)
1
R1R2C1C 2
wO =
0 TO (2.048 ⴙ VL)
6
2
wO
w
2
S 2 + O S + wO
Q
IL
C1
Figure 19. Programmable 4-to-20 mA Current Source
+2.5V
The circuit is simple, but be aware that dual-supply op amps are
ideal because the ground potential of REF191 can swing from
–2.048 V at zero scale to VL at full scale of the potentiometer
setting. Although the circuit works under single supply, the programmable resolution of the system will be reduced.
R1
A
Vi
R2
B
B
A
W
R
W
AD8601
C2
–2.5V
Programmable Bidirectional Current Source
For applications that require bidirectional current control or higher
voltage compliance, a Howland current pump can be a solution
(see Figure 20). If the resistors are matched, the load current is:
IL =
(R2 A + R2B) /R1 ¥ V
(8)
W
R2 B
R1
150k⍀
R2
15k⍀
C1
10pF
+15V
C2
10pF
+5V
A
W
B
–5V
R1
150k⍀
OP2177
A1
–15V
Figure 21. Sallen Key Low-Pass Filter
Programmable Oscillator
In a classic Wien-bridge oscillator, Figure 22, the Wien network
(R, R’, C, C’) provides positive feedback, while R1 and R2
provide negative feedback. At the resonant frequency, fo, the
overall phase shift is zero, and the positive feedback causes the
circuit to oscillate. With R = R’, C = C’, and R2 = R2A//(R2B+
RDIODE), the oscillation frequency is:
wO =
–15V
R2A
14.95k⍀
1
RC
or fO =
1
2pRC
(12)
where R is equal to RWA such that:
+15V
AD5260
ADJUSTED TO
SAME SETTINGS
A2
AD8016
VO
R
RL
50⍀
256 – D
R AB
(13)
256
At resonance, setting
R2
=2
(14)
R1
balances the bridge. In practice, R2/R1 should be set slightly larger
than 2 to ensure the oscillation can start. On the other hand, the
alternate turn-on of the diodes D1 and D2 ensures R2/R1 to be
smaller than 2 momentarily and therefore stabilizes the oscillation.
R=
VL
RL
500⍀
IL
Figure 20. Programmable Bidirectional Current Source
Once the frequency is set, the oscillation amplitude can be tuned
by R2B since:
2
V = I D R2B + VD
3 O
–16–
(15)
REV. 0
AD5260/AD5262
A
VO, ID, and VD are interdependent variables. With proper selection
of R2B, an equilibrium will be reached such that VO converges. R2B
can be in series with a discrete resistor to increase the amplitude,
but the total resistance cannot be too large to saturate the output.
R2
In both circuits in Figures 21 and 22, the frequency tuning requires
that both RDACs be adjusted to the same settings. Since the two
channels will be adjusted one at a time, an intermediate state will
occur that may not be acceptable for certain applications. As a
result, different devices can also be used in daisy-chained mode so
that parts can be programmed to the same setting simultaneously.
FREQUENCY
ADJUSTMENT
C
2.2nF
VP
C
2.2nF
+5V
B
R2 << R1
Figure 24. Lowering the Nominal Resistance
Figures 23 and 24 show that the digital potentiometers change steps
linearly. On the other hand, log taper adjustment is usually preferred in applications like audio control. Figure 25 shows another
way of resistance scaling. In this circuit, the smaller the R2 with
respect to RAB, the more the pseudo-log taper characteristic behaves.
R
10k⍀
A
B
R
10k⍀
A
W
R1
B
W
W
OP1177
Vi
U1
VO
AD5262
R1 = R1 = R2B = AD5262
D1 = D2 = 1N4148
VN
A
R1
B
–5V
R2B
10k⍀
B
W
R1
1k⍀
W
VO
R2
R2A
2.1k⍀ D1
D2
A
Figure 25. Resistor Scaling with Log Adjustment
Characteristics
AMPLITUDE
ADJUSTMENT
RDAC CIRCUIT SIMULATION MODEL
Figure 22. Programmable Oscillator with
Amplitude Control
Resistance Scaling
The AD5260/AD5262 offer 20 kW, 50 kW, and 200 kW nominal
resistance. For users who need lower resistance and still maintain the
numbers of step adjustment, they can parallel multiple devices. For
example, Figure 23 shows a simple scheme of paralleling both
channels of the AD5262. To adjust half of the resistance linearly
per step, users need to program both channels coherently with
the same settings.
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Configured
as a potentiometer divider, the –3 dB bandwidth of the AD5260
(20 kW resistor) measures 310 kHz at half scale. TPC 20 provides
the large signal BODE plot characteristics of the three available
resistor versions 20 kW, 50 kW, and 200 kW. A parasitic simulation
model is shown in Figure 26. Listing I provides a macro model
net list for the 20 kW RDAC.
RDAC
20k⍀
A
VDD
CW
CA
25pF
B
CB
25pF
55pF
A2
A1
W
B1
W1
W2
Figure 26. RDAC Circuit Simulation Model for RDAC = 20 kW
B2
LD
Figure 23. Reduce Resistance by Half with Linear
Adjustment Characteristics
In voltage divider mode, a much lower resistance can be achieved
by paralleling a discrete resistor as shown in Figure 24. The equivalent resistance becomes:
R WB _ eq =
D
(R1 §§ R2) + R W
256
Ê
D ˆ
R WA _ eq = Á1 ˜ ( R1 §§ R2) + R W
256
Ë
¯
REV. 0
(16)
(17)
Listing I. Macro Model Net List for RDAC
PARAM D=256, RDAC=20E3
*
SUBCKT DPOT (A,W,B)
*
CA
A
0
25E-12
RWA
A
W
{(1-D/256)*RDAC+60}
CW
W
0
55E-12
RWB
W
B
{D/256*RDAC+60}
CB
B
0
25E-12
*
.ENDS DPOT
–17–
AD5260/AD5262
DIGITAL POTENTIOMETER FAMILY SELECTION GUIDE1
Part
Number
Number
of VRs per
Package
Terminal
Voltage
Range (V)
Interface
Data
Control
Nominal
Resistance
(k⍀)
Resolution
Power Supply
(No. of Wiper Current
Positions)
(IDD) (␮A)
Packages
AD5201
1
± 3, 5.5
3-Wire
10, 50
33
40
mSOIC-10
Full AC Specs, Dual
Supply, Power-OnReset, Low Cost
AD5220
1
5.5
UP/DOWN
10, 50, 100
128
40
PDIP, SO-8,
mSOIC-8
No Rollover,
Power-On-Reset
AD7376
1
± 15, 28
3-Wire
10, 50, 100,
1000
128
100
PDIP-14,
SOL-16,
TSSOP-14
Single 28 V or Dual
± 15 V Supply Operation
AD5200
1
± 3, 5.5
3-Wire
10, 50
256
40
mSOIC-10
Full AC Specs, Dual
Supply, Power-On-Reset
AD8400
1
5.5
3-Wire
1, 10, 50, 100 256
5
SO-8
Full AC Specs
AD5260
1
± 5, 15
3-Wire
20, 50, 200
256
60
TSSOP-14
5 V to 15 V or ± 5 V
Operation,
TC < 50 ppm/∞C
AD5241
1
± 3, 5.5
2-Wire
10, 100,
1000
256
50
SO-14,
TSSOP-14
I2C Compatible,
TC < 50 ppm/∞C
AD5231
1
± 2.75, 5.5
3-Wire
10, 50, 100
1024
20
TSSOP-16
Nonvolatile Memory,
Direct Program, I/D,
± 6 dB settability
AD5222
2
± 3, 5.5
UP/DOWN
10, 50, 100,
1000
128
80
SO-14,
TSSOP-14
No Rollover, Stereo,
Power-On-Reset,
TC < 50 ppm/∞C
AD8402
2
5.5
3-Wire
1, 10, 50,
100
256
5
PDIP, SO-14,
TSSOP-14
Full AC Specs, nA
Shutdown Current
AD5207
2
± 3, 5.5
3-Wire
10, 50, 100
256
40
TSSOP-14
Full AC Specs, Dual
Supply, Power-OnReset, SDO
AD5232
2
± 2.75, 5.5
3-Wire
10, 50, 100
256
20
TSSOP-16
Nonvolatile Memory,
Direct Program, I/D,
± 6 dB Settability
AD52352
2
± 2.75, 5.5
3-Wire
25, 250
1024
20
TSSOP-16
Nonvolatile Memory,
Direct Program,
TC < 50 ppm/∞C
AD5242
2
± 3, 5.5
2-Wire
10, 100,
1000
256
50
SO-16,
TSSOP-16
I2C Compatible,
TC < 50 ppm/∞C
AD5262
2
± 5, 15
3-Wire
20, 50, 200
256
60
TSSOP-16
5 V to 15 V or ± 5 V
Operation,
TC < 50 ppm/∞C
AD5203
4
5.5
3-Wire
10, 100
64
5
PDIP, SOL-24, Full AC Specs, nA
TSSOP-24
Shutdown Current
AD5233
4
± 2.75, 5.5
3-Wire
10, 50, 100
64
20
TSSOP-24
AD5204
4
± 3, 5.5
3-Wire
10, 50, 100
256
60
PDIP, SOL-24, Full AC Specs, Dual
TSSOP-24
Supply, Power-On-Reset
AD8403
4
5.5
3-Wire
1, 10, 50, 100 256
5
PDIP, SOL-24, Full AC Specs, nA
TSSOP-24
Shutdown Current
AD5206
6
± 3, 5.5
3-Wire
10, 50, 100
60
PDIP, SOL-24, Full AC Specs, Dual
TSSOP-24
Supply, Power-On-Reset
1
2
256
Comments
Nonvolatile Memory,
Direct Program, I/D,
± 6 dB Settability
For the most current information on digital potentiometers, check the website at: www.analog.com/DigitalPotentiometers
Future product, consult factory for latest status.
–18–
REV. 0
AD5260/AD5262
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead TSSOP
(RU-14)
0.201 (5.10)
0.193 (4.90)
14
8
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
7
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.0433 (1.10)
MAX
0.0256
(0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
8ⴗ
0ⴗ
0.028 (0.70)
0.020 (0.50)
16-Lead TSSOP
(RU-16)
0.201 (5.10)
0.193 (4.90)
16
9
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
8
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
REV. 0
0.0433 (1.10)
MAX
8ⴗ
0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) 0ⴗ
BSC
0.0075 (0.19) 0.0035 (0.090)
–19–
0.028 (0.70)
0.020 (0.50)
–20–
PRINTED IN U.S.A.
C02695–0–3/02(0)