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SBVS045 − MARCH 2004
FEATURES
D Two-Input, One-Output Power Multiplexer
D
D
APPLICATIONS
D
D
D
D
D
D
D
With Low rDS(on) Switches:
− 84 mΩ Typ (TPS2113A)
− 120 mΩ Typ (TPS2112A)
Reverse and Cross-Conduction Blocking
Wide Operating Voltage Range . . . .2.8 V to
5.5 V
Low Standby Current . . . . 0.5-µA Typ
D
D Low Operating Current . . . . 55-µA Typ
D Adjustable Current Limit
D Controlled Output Voltage Transition Times,
PCs
PDAs
Digital Cameras
Modems
Cell Phones
Digital Radios
MP3 Players
PW PACKAGE
(TOP VIEW)
D
D
D
D
1
2
3
4
STAT
EN
VSNS
ILIM
Limits Inrush Current and Minimizes Output
Voltage Hold-Up Capacitance
CMOS- and TTL-Compatible Control Inputs
Auto-Switching Operating Mode
Thermal Shutdown
Available in a TSSOP-8 Package
8
7
6
5
IN1
OUT
IN2
GND
DESCRIPTION
The TPS211xA family of power multiplexers enables seamless transition between two power supplies, such as a battery
and a wall adapter, each operating at 2.8−5.5 V and delivering up to 1 A. The TPS211xA family includes extensive protection
circuitry, including user-programmable current limiting, thermal protection, inrush current control, seamless supply
transition, cross-conduction blocking, and reverse-conduction blocking. These features greatly simplify designing power
multiplexer applications.
TYPICAL APPLICATION
Switch
Status
IN1: 2.8 − 5.5 V
R1
TPS2113APW
1
STAT
2
EN
3
4
VSNS
ILIM
IN1 8
OUT
IN2
GND
0.1 µF
7
6
5
CL
RL
RILIM
IN2: 2.8 − 5.5 V
0.1 µF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
% % &'()(& * ))& * (' +,(& -. )(-*
(&'() ( *+'(&* +) / )* (' !* &*)&* *&-)- 0))&1.
)(-(& +)(**&2 -(* &( &**)1 &- *&2 (' +))*.
Copyright 2004, Texas Instruments Incorporated
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SBVS045 − MARCH 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
FEATURE
TPS2110A
TPS2111A
TPS2112A
TPS2113A
TPS2114A
TPS2115A
Current Limit Adjustment Range
0.31−0.75A
0.63−1.25A
0.31−0.75A
0.63−1.25A
0.31−0.75A
0.63−1.25A
Manual
Yes
Yes
No
No
Yes
Yes
Automatic
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
TSSOP-8
TSSOP-8
TSSOP-8
TSSOP-8
TSSOP-8
TSSOP-8
Switching Modes
Switch Status Output
Package
ORDERING INFORMATION
TA
PACKAGE
−40°C to 85°C
TSSOP-8 (PW)
ORDERING NUMBER(1)
MARKINGS
TPS2112APW
2112A
TPS2113APW
2113A
(1) The PW package is available taped and reeled. Add an R suffix to the device type (e.g., TPS2112APWR) to indicate tape and reel.
PACKAGE DISSIPATION RATINGS
PACKAGE
TSSOP-8 (PW)
DERATING FACTOR ABOVE
TA = 25°C
3.9 mW/°C
TA ≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
387 mW
213 mW
155 mW
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS2112A, TPS2113A
Input voltage range at pins IN1, IN2, EN, VSNS, ILIM(2)
Output voltage range, VO(OUT), VO(STAT)(2)
−0.3 V to 6 V
−0.3 V to 6 V
Output sink current, IO(STAT)
Continuous output current, IO
5 mA
TPS2112A
0.9 A
TPS2113A
1.5 A
Continuous total power dissipation
See Dissipation Rating Table
Operating virtual junction temperature range, TJ
−40°C to 125°C
Storage temperature range, Tstg
−65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds
260°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND.
RECOMMENDED OPERATING CONDITIONS
MIN
MAX UNIT
1.5
5.5
Input voltage at IN1, VI(IN1)
VI(IN2) ≥ 2.8 V
VI(IN2) < 2.8 V
2.8
5.5
VI(IN1) ≥ 2.8 V
VI(IN1) < 2.8 V
1.5
5.5
Input voltage at IN2, VI(IN2)
2.8
5.5
Input voltage, VI(EN), VI(VSNS)
Current limit adjustment range, IO(OUT)
0
5.5
TPS2112A
0.31
0.75
TPS2113A
0.63
1.25
−40
125
Operating virtual junction temperature, TJ
V
V
V
A
°C
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MIN
Human body model
CDM
2
MAX UNIT
2
kV
500
V
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SBVS045 − MARCH 2004
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted)
TPS2112A
PARAMETER
TEST CONDITIONS
MIN
TPS2113A
TYP
MAX
VI(IN1) = VI(IN2) = 5.0 V
VI(IN1) = VI(IN2) = 3.3 V
120
120
VI(IN1) = VI(IN2) = 2.8 V
VI(IN1) = VI(IN2) = 5.0 V
120
MIN
TYP
MAX
140
84
110
140
84
110
140
84
110
UNIT
POWER SWITCH
rDS(on)(1)
Drain-source
on-state resistance
(INx−OUT)
TJ = 25°C,
IL = 500 mA
TJ = 125°C,
IL = 500 mA
VI(IN1) = VI(IN2) = 3.3 V
VI(IN1) = VI(IN2) = 2.8 V
220
150
220
150
220
150
mΩ
mΩ
m
(1) The TPS211xA can switch a voltage as low as 1.5 V as long as there is a minimum of 2.8 V at one of the input power pins. In this specific case,
the lower supply voltage has no effect on the IN1 and IN2 switch on-resistances.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC INPUTS (EN)
VIH
VIL
High-level input voltage
2
V
Low-level input voltage
Input current
0.7
EN = High, sink current
1
EN = Low, source current
0.5
1.4
5
55
90
1
12
V
µA
SUPPLY AND LEAKAGE CURRENTS
VI(VSNS) = 1.5 V, EN = Low (IN1 active), VI(IN1) = 5.5 V,
VI(IN2) = 3.3 V, IO(OUT) = 0 A
Supply current from IN1
(operating)
Supply current from IN2
(operating)
Quiescent current from IN1
(STANDBY)
Quiescent current from IN2
(STANDBY)
Forward leakage current from IN1
(measured from OUT to GND)
VI(VSNS) = 1.5 V, EN = Low (IN1 active), VI(IN1) = 3.3 V,
VI(IN2) = 5.5 V, IO(OUT) = 0 A
VI(VSNS) = 0 V, EN = Low (IN2 active), VI(IN1) = 5.5 V,
VI(IN2) = 3.3 V, IO(OUT) = 0 A
VI(VSNS) = 0 V, EN = Low (IN2 active), VI(IN1) = 3.3 V,
VI(IN2) = 5.5 V, IO(OUT) = 0 A
VI(VSNS) = 1.5 V, EN = Low (IN1 active), VI(IN1) = 5.5 V,
VI(IN2) = 3.3 V, IO(OUT) = 0 A
VI(VSNS) = 1.5 V, EN =Low (IN1 active), VI(IN1) = 3.3 V,
VI(IN2) = 5.5 V, IO(OUT) = 0 A
VI(VSNS) = 0 V, EN = Low (IN2 active), VI(IN1) = 5.5 V,
VI(IN2)= 3.3 V, IO(OUT) = 0 A
VI(VSNS) = 0 V, EN = Low (IN2 active), VI(IN1) = 3.3 V,
VI(IN2) = 5.5 V, IO(OUT) = 0 A
EN = High (inactive), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V,
EN = High (inactive), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V,
EN = High (inactive), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V,
IO(OUT) = 0 A
IO(OUT) = 0 A
IO(OUT) = 0 A
EN = High (inactive), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V, IO(OUT) = 0 A
Forward leakage current from IN2
(measured from OUT to GND)
EN = High (inactive), VI(IN1) = 5.5 V, IN2 open,
VO(OUT) = 0 V (shorted), TJ = 25°C
EN = High (inactive), VI(IN2) = 5.5 V, IN1 open,
VO(OUT) = 0 V (shorted), TJ = 25°C
Reverse leakage current to INx
(measured from INx to GND)
EN = High (inactive), VI(INx) = 0 V, VO(OUT) = 5.5 V, TJ = 25°C
µA
75
1
1
75
µA
1
12
55
90
0.5
2
1
1
µA
µA
0.5
2
0.1
5
µA
0.1
5
µA
0.3
5
µA
0.01
1
µA
0.13
0.4
STAT OUTPUT
Leakage current
Saturation voltage
Deglitch time (falling edge only)
VO(STAT) = 5.5 V
II(STAT) = 2 mA, IN1 switch is on
150
V
µs
3
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SBVS045 − MARCH 2004
ELECTRICAL CHARACTERISTICS (Continued)
over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT LIMIT CIRCUIT
TPS2112A
RILIM = 400 Ω
RILIM = 700 Ω
0.51
0.63
0.80
0.30
0.36
0.50
TPS2113A
RILIM = 400 Ω
RILIM = 700 Ω
0.95
1.25
1.56
0.47
0.71
0.99
Current limit accuracy
td
Current limit settling time(1)
Time for short-circuit output current to
settle within 10% of its steady state value.
Input current at ILIM
VI(ILIM) = 0 V, IO(OUT) = 0 A
1
−15
A
ms
0
µA
(1) Not tested in production.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VSNS COMPARATOR
VI(VSNS) ↑
VI(VSNS) ↓
VSNS threshold voltage
0.78
0.8
0.82
0.735
0.755
0.775
150
220
µs
1
µA
VSNS comparator hysteresis(1)
30
Deglitch of VSNS comparator (both ↑↓)(1)
90
0 V ≤ VI(VSNS) ≤ 5.5 V
Input current
60
−1
V
mV
UVLO
Falling edge
IN1 and IN2 UVLO
1.15
Rising edge
IN1 and IN2 UVLO hysteresis(1)
Falling edge
Internal VDD UVLO (the higher of IN1 and IN2)
Internal VDD UVLO hysteresis(1)
UVLO deglitch for IN1, IN2(1)
1.25
1.30
1.35
30
57
65
2.4
2.53
Rising edge
30
Falling edge
2.58
2.8
50
75
V
mV
V
mV
µs
110
(1) Not tested in production.
MIN
TYP
MAX
UNIT
80
100
120
mV
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Thermal shutdown threshold(1)
TPS211xA is in current limit.
135
Recovery from thermal shutdown(1)
Hysteresis(1)
TPS211xA is in current limit.
125
PARAMETER
TEST CONDITIONS
REVERSE CONDUCTION BLOCKING
∆VO(I_block)
Minimum output-to-input voltage
difference to block switching
PARAMETER
EN = high, VI(IN1) = 3.3 V and VI(IN2) = VI(VSNS) =
0 V. Connect OUT to a 5 V supply through a series
1-kΩ resistor. Let EN = low. Slowly decrease the
supply voltage until OUT connects to IN1.
THERMAL SHUTDOWN
°C
C
10
IN2−IN1 COMPARATORS
Hysteresis of IN2−IN1 comparator
0.1
Deglitch of IN2−IN1 comparator (both ↑↓)(1)
(1) Not tested in production.
10
4
20
0.2
V
50
µs
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SBVS045 − MARCH 2004
SWITCHING CHARACTERISTICS
over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted)
TPS2112A
PARAMETER
TEST CONDITIONS
TPS2113A
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
POWER SWITCH
tr
Output rise time from
an enable(1)
VI(IN1) = VI(IN2) = 5 V,
VI(VSNS) = 1.5 V
TJ = 25°C, CL = 1 µF,
IL = 500 mA,
See Figure 1(a)
0.5
1.0
1.5
1
1.8
3
ms
tf
Output fall time from
a disable(1)
VI(IN1) = VI(IN2) = 5 V,
VI(VSNS) = 1.5 V
TJ = 25°C, CL = 1 µF,
IL = 500 mA,
See Figure 1(a)
0.35
0.5
0.7
0.5
1
2
ms
tt
Transition time(1)
IN1 to IN2 transition,
VI(IN1) = 3.3 V,
VI(IN2) = 5 V,
VI(EN) = 0 V
TJ = 125°C, CL = 10 µF,
IL = 500 mA
[Measure transition time
as 10−90% rise time or
from 3.4 V to 4.8 V on
VO(OUT)],
See Figure 1(b)
40
60
40
60
µs
tPLH1
Turn-on propagation
delay from enable(1)
TJ = 25°C, CL = 10 µF,
IL = 500 mA,
See Figure 1(a)
0.5
1
ms
tPHL1
Turn-off propagation
delay from a
disable(1)
TJ = 25°C, CL = 10 µF,
IL = 500 mA,
See Figure 1(a)
3
5
ms
TJ = 25°C, CL = 10 µF,
IL = 500 mA,
See Figure 1(c)
40
100
3
10
tPLH2
Switch-over rising
propagation delay(1)
tPHL2
Switch-over falling
propagation delay(1)
VI(IN1) = VI(IN2) = 5 V
Measured from enable to
10% of VO(OUT),
VI(VSNS) = 1.5 V
VI(IN1) = VI(IN2) = 5 V,
Measured from disable
to 90% of VO(OUT),
VI(VSNS) = 1.5 V
Logic 1 to Logic 0
transition on VSNS ,
VI(IN1) = 1.5 V,
VI(IN2) = 5 V,
VI(EN) = 0 V,
Measured from VSNS to
10% of VO(OUT)
Logic 0 to Logic 1
transition on VSNS
VI(IN1) = 1.5V,
VI(IN2) = 5V,
VI(EN) = 0 V,
Measured from VSNS to
90% of VO(OUT)
TJ = 25°C, CL = 10 µF,
IL = 500 mA,
See Figure 1(c)
2
2
40
100
µs
5
10
ms
(1) Not tested in production.
5
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SBVS045 − MARCH 2004
TRUTH TABLE
EN
VI(VSNS) > 0.8V
Yes
0
1
VI(IN2) > VI(IN1)
X
STAT
OUT(1)
0
IN1
IN1
No
No
0
No
Yes
Hi-Z
IN2
X
X
0
Hi-Z
X = Don’t care.
(1)The under-voltage lockout circuit causes the output OUT to go Hi-Z if the
selected power supply does not exceed the IN1/IN2 UVLO, or if neither of
the supplies exceeds the internal VDD UVLO.
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
EN
2
I
EN is a TTL- and CMOS-compatible input with a 1-µA pull-up. The truth table shown above illustrates the functionality
of EN.
GND
5
I
Ground
IN1
8
I
Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above the UVLO threshold and at
least one supply exceeds the internal VDD UVLO.
IN2
6
I
Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is above the UVLO threshold and
at least one supply exceeds the internal VDD UVLO.
ILIM
4
I
A resistor RILIM from ILIM to GND sets the current limit IL to 250/RILIM and 500/RILIM for the TPS2112A and TPS2113A,
respectively.
OUT
7
O
Power switch output
STAT
1
O
STAT is an open-drain output that is Hi-Z if the IN2 switch is ON. STAT pulls low if the IN1 switch is ON or if OUT is Hi-Z
(i.e., EN is equal to logic 0)
VSNS
3
I
An internal power FET connects OUT to IN1 if the VSNS voltage is greater than 0.8 V. Otherwise, the FET connects OUT
to the higher of IN1 and IN2. The truth table shown above illustrates the functionality of VSNS.
6
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SBVS045 − MARCH 2004
FUNCTIONAL BLOCK DIAGRAM
Internal VDD
1 µA
IN1
IN2
Vf = 0 V
Vf = 0 V
IO(OUT)
Q1
8
Q2
6
7
Charge
Pump
VDD
ULVO
IN2
ULVO
Cross-Conduction
Detector
IN1
ULVO
+
_
0.6 V
+
EN2
OUT
k* IO(OUT)
_
TPS2112A: k = 0.2%
TPS2113A: k = 0.1%
+
0.5 V
4
ILIM
+
_
EN1
Q1 is ON
Q2 is ON
UVLO (VDD)
VO(OUT) > VI(INx)
UVLO (IN2)
UVLO (IN1)
100 mV
+
+
_
EN1
EN
VSNS
GND
2
Control
Logic
3
5
0.8 V
+
_
VI(VSNS) >0.8 V
Thermal
Sense
VI(IN2) > VI(IN1)
IN2
+
_
IN1
1
STAT
Q2 is ON
7
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SBVS045 − MARCH 2004
PARAMETER MEASUREMENT INFORMATION
90%
90%
VO(OUT)
10%
10%
0V
tr
tf
tPLH1
tPHL1
EN
Switch Off
Switch Enabled
Switch Off
(a)
5V
4.8 V
VO(OUT)
3.4 V
3.3 V
tt
VSNS
Switch #2 Enabled
Switch #1 Enabled
(b)
5V
VO(OUT)
1.5 V
4.65 V
1.85 V
tPLH2
tPHL2
VSNS
Switch #1 Enabled
Switch #2 Enabled
Switch #1 Enabled
(c)
Figure 1. Propagation Delays and Transition Timing Waveforms
8
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SBVS045 − MARCH 2004
TYPICAL CHARACTERISTICS
OUTPUT SWITCHOVER RESPONSE
3.3 V
TPS2113APW
VI(VSNS)
NC
2
f = 28 Hz
22% Duty Cycle
2V/DIV
1
3
4
STAT
EN
VSNS
ILIM
400 Ω
0.1 µF
IN1
8
7
OUT
6
1 µF
IN2
GND
50 Ω
5
5V
VO(OUT)
0.1 µF
2V/DIV
Output Switchover Response Test Circuit
t − Time − 1 ms/div
Figure 2
OUTPUT TURN-ON RESPONSE
VI(EN)
2V/Div
5V
TPS2113APW
f = 28 Hz
78% Duty Cycle
NC
1
2
3
4
400 Ω
STAT
EN
VSNS
ILIM
IN1
0.1 µF
8
7
OUT
IN2
GND
6
1 µF
50 Ω
5
VO(OUT)
2V/Div
Output Turn-On Response Test Circuit
t − Time − 2 ms/div
Figure 3
9
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SBVS045 − MARCH 2004
TYPICAL CHARACTERISTICS
OUTPUT SWITCHOVER VOLTAGE DROOP
VI(VSNS)
2V/Div
CL = 1 µF
VO(OUT)
2V/Div
CL = 0 µF
t − Time − 40 µs/div
5V
SW1
1 kΩ
TPS2113APW
NC
f = 580 Hz
90% Duty Cycle
1
2
STAT
EN
3
VSNS
4
ILIM
IN1
0.1 µF
8
7
OUT
IN2
GND
6
5
CL
50 Ω
400 Ω
0.1 µF
Output Switchover Voltage Droop Test Circuit
Figure 4
NOTE: To initialize the TPS2113A for this test, set input VSNS equal to 0 V, turn on the 5 V supply, and then turn on switch SW1.
10
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SBVS045 − MARCH 2004
TYPICAL CHARACTERISTICS
OUTPUT SWITCHOVER VOLTAGE DROOP
vs
LOAD CAPACITANCE
5
VI = 5 V
∆ VO(OUT) − Output Voltage Droop − V
4.5
4
3.5
RL = 10 Ω
3
2.5
2
1.5
RL = 50 Ω
1
0.5
0
0.1
VI
1
10
CL − Load Capacitance − µF
SW1
TPS2113APW
f = 28 Hz
50% Duty Cycle
1
STAT
2
EN
3
VSNS
4
ILIM
400 Ω
NC
0.1 µF
100
1 kΩ
IN1 8
7
OUT
6
IN2
5
GND
50 Ω
0.1 µF
0.1 µF
1 µF
10 µF
47 µF
10 Ω
100 µF
Output Switchover Voltage Droop Test Circuit
Figure 5
NOTE: To initialize the TPS2113A for this test, set input VSNS equal to 0 V, turn on the supply Vi, and then turn on switch SW1.
11
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SBVS045 − MARCH 2004
TYPICAL CHARACTERISTICS
AUTO SWITCHOVER VOLTAGE DROOP
VI(IN1)
2V/Div
5V
TPS2113A
1kΩ
1
STAT
2
f = 220 Hz
20% Duty Cycle
EN
3
4
400Ω
VO(OUT)
2V/Div
VSNS
ILIM
8
IN1
7
OUT
6
IN2
5
GND
0.1 µF
VOUT
3.3V 10 µF
0.1 µF
75% less output voltage
droop compared to TPS2113
Auto Switchover Voltage Droop Test Circuit
t − Time − 250 µs/div
12
Figure 6
50 Ω
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SBVS045 − MARCH 2004
TYPICAL CHARACTERISTICS
INRUSH CURRENT
vs
LOAD CAPACITANCE
300
− Inrush Current − mA
250
200
VI = 5 V
150
VI = 3.3 V
I
I
100
50
0
0
VI
f = 28 Hz
90% Duty Cycle
20
40
60
80
CL − Load Capacitance − µF
100
TPS2113APW
1
NC
2
3
4
400 Ω
STAT
EN
VSNS
ILIM
IN1
OUT
IN2
GND
8
0.1 µF
To Oscilloscope
7
6
5
50 Ω
0.1 µF
1 µF
10 µF
47 µF
100 µF
Output Capacitor Inrush Current Test Circuit
Figure 7
13
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TYPICAL CHARACTERISTICS
SWITCH ON-RESISTANCE
vs
SUPPLY VOLTAGE
SWITCH ON-RESISTANCE
vs
JUNCTION TEMPERATURE
120
rDS(on) − Switch On-Resistance − m Ω
rDS(on) − Switch On-Resistance − m Ω
180
160
TPS2112A
140
120
TPS2113A
100
80
60
−50
TPS2112A
115
110
105
100
95
90
TPS2113A
85
80
0
50
100
TJ − Junction Temperature − °C
2
150
3
4
5
VI(INx) − Supply Voltage − V
Figure 8
Figure 9
IN1 SUPPLY CURRENT
vs
SUPPLY VOLTAGE
IN1 SUPPLY CURRENT
vs
SUPPLY VOLTAGE
0.96
60
Device Disabled
VI(IN2) = 0 V
IO(OUT) = 0 A
IN1 Switch is ON
VI(IN2) = 0 ,
IO(OUT) = 0 A
58
I(IN1) − IN1 Supply Current − µ A
0.94
0.92
0.90
0.88
0.86
I
I I(IN1) − IN1 Supply Current − µ A
6
56
54
52
50
48
46
44
0.84
42
40
0.82
2
3
4
5
VI(IN1)− IN1 Supply Voltage − V
Figure 10
14
6
2
3
4
5
VI(IN1) − Supply Voltage − V
Figure 11
6
www.ti.com
SBVS045 − MARCH 2004
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
1.2
70
I I(INx) − Supply Current − µ A
I I(INx) − Supply Current − µ A
1
80
Device Disabled
VI(IN1) = 5.5 V
VI(IN2) = 3.3 V
IO(OUT) = 0 A
II(IN1) = 5.5 V
0.8
0.6
0.4
60
IN1 Switch is ON
VI(IN1) = 5.5 V
VI(IN2) = 3.3 V
IO(OUT) = 0 A
II(IN1)
50
40
30
20
0.2
10
II(IN2) = 3.3 V
0
−50
0
50
100
TJ − Junction Temperature − °C
Figure 12
150
0
−50
II(IN2)
0
50
100
TJ − Junction Temperature − °C
150
Figure 13
15
www.ti.com
SBVS045 − MARCH 2004
APPLICATION INFORMATION
Some applications have two energy sources, one of which should be used in preference to another. Figure 14
shows a circuit that will connect IN1 to OUT until the voltage at IN1 falls below a user-specified value. Once
the voltage on IN1 falls below this value, the TPS2112A/3A will select the higher of the two supplies. This usually
means that the TPS2112A/3A will swap to IN2.
Switch Status
IN1: 2.8 − 5.5 V
R3
TPS2113APW
1
R1
2
3
4
R2
IN1
STAT
OUT
EN
VSNS
IN2
ILIM
GND
8
0.1 µF
7
6
RL
CL
5
RILIM
IN2: 2.8 − 5.5 V
0.1 µF
Figure 14. Auto-Selecting for a Dual Power Supply Application
In Figure 15, the multiplexer selects between two power supplies based upon the EN logic signal. OUT
connects to IN1 if EN is logic 1; otherwise, OUT connects to IN2. The logic thresholds for the EN terminal are
compatible with both TTL and CMOS logic.
Switch Status
IN1: 2.8 − 5.5 V
TPS2113APW
1
2
3
4
STAT
EN
VSNS
ILIM
IN1
OUT
IN2
GND
0.1 µF
8
7
6
5
CL
RILIM
IN2: 2.8 − 5.5 V
0.1 µF
Figure 15. Manually Switching Power Sources
16
R1
RL
www.ti.com
SBVS045 − MARCH 2004
DETAILED DESCRIPTION
AUTO-SWITCHING MODE
The TPS2112A/3A only supports the auto-switching mode. In this mode, OUT connects to IN1 if VI(VSNS) is
greater than 0.8 V, otherwise OUT connects to the higher of IN1 and IN2.
The VSNS terminal includes hysteresis equal to 3.75–7.5% of the threshold selected for transition from the
primary supply to the higher of the two supplies. This hysteresis helps avoid repeated switching from one supply
to the other due to resistive drops.
N-CHANNEL MOSFETs
Two internal high-side power MOSFETs implement a single-pole double-throw (SPDT) switch. Digital logic
selects the IN1 switch, IN2 switch, or no switch (Hi-Z state). The MOSFETs have no parallel diodes so
output-to-input current cannot flow when the FET is off. An integrated comparator prevents turn-on of a FET
switch if the output voltage is greater than the input voltage.
CROSS-CONDUCTION BLOCKING
The switching circuitry ensures that both power switches will never conduct at the same time. A comparator
monitors the gate-to-source voltage of each power FET and allows a FET to turn on only if the gate-to-source
voltage of the other FET is below the turn-on threshold voltage.
REVERSE-CONDUCTION BLOCKING
When the TPS211xA switches from a higher-voltage supply to a lower-voltage supply, current can potentially
flow back from the load capacitor into the lower-voltage supply. To minimize such reverse conduction, the
TPS211xA will not connect a supply to the output until the output voltage has fallen to within 100 mV of the supply
voltage. Once a supply has been connected to the output, it will remain connected regardless of output voltage.
CHARGE PUMP
The higher of supplies IN1 and IN2 powers the internal charge pump. The charge pump provides power to the
current limit amplifier and allows the output FET gate voltage to be higher than the IN1 and IN2 supply voltages.
A gate voltage that is higher than the source voltage is necessary to turn on the N-channel FET.
CURRENT LIMITING
A resistor RILIM from ILIM to GND sets the current limit to 250/RILIM and 500/RILIM for the TPS2112A and
TPS2113A, respectively. Setting resistor RILIM equal to zero is not recommended as that disables current
limiting.
OUTPUT VOLTAGE SLEW-RATE CONTROL
The TPS2112A/3A slews the output voltage at a slow rate when OUT switches to IN1 or IN2 from the Hi-Z state
(see Truth Table). A slow slew rate limits the inrush current into the load capacitor. High inrush currents can
glitch the voltage bus and cause a system to hang up or reset. It can also cause reliability issues—like pit the
connector power contacts, when hot-plugging a load such as a PCI card. The TPS2112A/3A slews the output
voltage at a much faster rate when OUT switches between IN1 and IN2. The fast rate minimizes the output
voltage droop and reduces the output voltage hold-up capacitance requirement.
17
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
TPS2112APW
ACTIVE
TSSOP
PW
8
150
None
CU NIPDAU
Level-1-220C-UNLIM
TPS2112APWR
ACTIVE
TSSOP
PW
8
2000
None
CU NIPDAU
Level-1-220C-UNLIM
TPS2113APW
ACTIVE
TSSOP
PW
8
150
None
CU NIPDAU
Level-1-220C-UNLIM
TPS2113APWR
ACTIVE
TSSOP
PW
8
2000
None
CU NIPDAU
Level-1-220C-UNLIM
TPS2113APWRG4
PREVIEW
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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