PCS5P23Z05B/09B May 2007 rev 0.2 Timing-Safe™ Peak EMI reduction IC General Features • eight-pin version and accepts one reference input and drives out five low-skew clocks. • Clock distribution with Timing-Safe™ Peak EMI Reduction Input frequency range: 20MHz - 50MHz • Zero input - output propagation delay the CLKIN pin. The PLL feedback is on-chip and is • Low-skew outputs obtained from the CLKOUT pad, internal to the device. All parts have on-chip PLLs that lock to an input clock on • Output-output skew less than 250pS • Device-device skew less than 700pS Multiple PCS5P23Z05B/09B devices can accept the same • Less than 200pS cycle-to-cycle jitter input clock and distribute it. In this case, the skew between • Available in 16pin, 150mil SOIC, 4.4mm TSSOP the outputs of the two devices is guaranteed to be less than (PCS5P23Z09B), and in 8pin, 150 mil SOIC, 700pS. 4.4mm TSSOP Packages (PCS5P23Z05B) • 3.3V Operation All outputs have less than 200pS of cycle-to-cycle jitter. • Industrial temperature range The input and output propagation delay is guaranteed to be • • Advanced CMOS technology The First True Drop-in Solution guaranteed to be less than 250pS. less than ±350pS, and the output-to-output skew is Refer “Spread Spectrum Control and Input-Output Skew Functional Description Table” PCS5P23Z05B/09B is a versatile, 3.3V zero-delay buffer designed to distribute high-speed Timing-Safe™ clocks with Peak EMI Reduction. PCS5P23Z09B accepts one reference input and drives out nine low-skew clocks. It is available in a 16pin Package. The PCS5P23Z05B is the for deviations and Input-Output Skew for PCS5P23Z05B and PCS5P23Z09B devices The PCS5P23Z05B and PCS5P23Z09B are available in two different packages, as shown in the ordering information table. Block Diagram CLKIN PLL PLL CLKOUT MUX CLKIN CLKOUT CLKA1 CLK1 CLKA2 CLK2 CLKA3 CLK3 PCS5P23Z05B CLK4 CLKA4 S2 S1 Select Input Decoding CLKB1 CLKB2 CLKB3 PCS5P23Z09B PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. CLKB4 PCS5P23Z05B/09B May 2007 rev 0.2 Spread Spectrum Frequency Generation The clocks in digital systems are typically square waves PCBs etc. These methods are expensive. Spread with a 50% duty cycle and as frequencies increase the spectrum clocking reduces the peak energy by reducing edge rates also get faster. Analysis shows that a square the Q factor of the clock. This is done by slowly wave is composed of fundamental frequency and modulating the clock frequency. The PCS5P23Z05B/09B harmonics. The fundamental frequency and harmonics uses the center modulation spread spectrum technique in generate the energy peaks that become the source of which the modulated output frequency varies above and EMI. Regulatory agencies test electronic equipment by below measuring the amount of peak energy radiated from the modulation rate. With center modulation, the average equipment. In fact, the peak level allowed decreases as frequency is the same as the unmodulated frequency and the frequency increases. The standard methods of there is no performance degradation the reference frequency with a specified reducing EMI are to use shielding, filtering, multi-layer Timing-Safe™ technology Timing-Safe™ technology is the ability to modulate a clock source with Spread Spectrum technology and maintain synchronization with any associated data path. Pin Configuration ( 8 Pin Device ) CLKIN 1 8 CLKOUT 7 CLK4 CLK2 3 6 VDD GND 4 5 CLK3 CLKIN 1 16 CLKOUT CLKA1 2 15 CLKA4 CLKA2 3 14 CLKA3 VDD 4 13 VDD GND 5 12 GND CLKB1 6 11 CLKB4 CLKB2 7 10 CLKB3 S2 9 S1 CLK1 2 PCS5P23Z05B Pin Configuration ( 16 Pin Device ) 8 PCS5P23Z09B Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 2 of 14 PCS5P23Z05B/09B May 2007 rev 0.2 Pin Description for PCS5P23Z05B Pin # Pin Name 1 CLKIN 2 1 Buffered clock output 1 Buffered clock output CLK2 4 GND CLK3 6 VDD 8 Ground 1 5 7 Input reference frequency, 5V-tolerant input CLK1 3 Description Buffered clock output 3.3V supply 1 CLK4 CLKOUT Buffered clock output 1,2 Buffered clock output, internal feedback on this pin Notes: 1. Weak pull-down on these outputs. 2. This output is driven and has an internal feedback for the PLL. 3. All Buffered clock outputs are Timing-Safe™. Pin Description for PCS5P23Z09B Pin # Pin Name Description 1 CLKIN Input reference frequency, 5V tolerant input 2 CLKA11 Buffered clock output 3 1 CLKA2 Buffered clock output 4 VDD 5 GND 6 7 8 9 10 3.3V supply Ground 1 Buffered clock output 1 Buffered clock output CLKB1 CLKB2 2 S2 Select Input, bit 2 2 S1 Select Input, bit 1 1 Buffered clock output 1 Buffered clock output CLKB3 11 CLKB4 12 GND 13 VDD 14 15 16 Ground 3.3V supply 1 Buffered clock output 1 Buffered clock output 1,3 Buffered output, Internal feedback on this pin CLKA3 CLKA4 CLKOUT Notes: 1. Weak pull-down on all outputs. 2. Weak pull-up on these Inputs. 3. This output is driven and has an internal feedback for the PLL. 4. All Buffered clock outputs are Timing-Safe™. Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 3 of 14 PCS5P23Z05B/09B May 2007 rev 0.2 Spread Spectrum Control and Input-Output Skew Table (Note: The values given in the table are for an input frequency of 32MHz) Device Deviation Input-Output Skew(±TSKEW) PCS5P23Z05B ±0.25 % 0.125 PCS5P23Z09B ±0.25 % 0.125 Note: TSKEW is measured in units of the Clock Period Absolute Maximum Ratings Symbol Rating Unit VDD Voltage on any pin with respect to Ground Parameter -0.5 to +4.6 V TSTG Storage temperature -65 to +125 °C Ts Max. Soldering Temperature (10 sec) 260 °C TJ Junction Temperature 150 °C TDV Static Discharge Voltage (As per JEDEC STD22- A114-B) 2 KV Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Operating Conditions for PCS5P23Z05B and PCS5P23Z09B Devices Parameter Description Min Max Unit VDD Supply Voltage 3.0 3.6 V TA Operating Temperature (Ambient Temperature) -40 +85 °C CL Load Capacitance 30 pF CIN Input Capacitance 7 pF Electrical Characteristics for PCS5P23Z05B and PCS5P23Z09B Parameter VIL Description 1 Input HIGH Voltage IIL Input LOW Current IIH Min Typ Input LOW Voltage VIH VOL Test Conditions 1 Max Unit 0.8 V 2.0 V VIN = 0V 50 µA Input HIGH Current VIN = VDD 100 µA Output LOW Voltage2 IOL = 8mA 0.4 V 2 VOH Output HIGH Voltage IOH = -8mA IDD Supply Current Unloaded outputs Zo Output Impedance 2.4 V 15 mA 23 Ω Note: 1. CLKIN input has a threshold voltage of VDD/2 2. Parameter is guaranteed by design and characterization. Not 100% tested in production Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 4 of 14 PCS5P23Z05B/09B May 2007 rev 0.2 Switching Characteristics for PCS5P23Z05B and PCS5P23Z09B Parameter 1/t1 Description Test Conditions Output Frequency 2 Min 30pF load 20 40 Typ Unit 50 MHz Duty Cycle = (t2 / t1) * 100 Measured at VDD/2 60 % t3 Output Rise Time1, 2 Measured between 0.8V and 2.0V 2.5 nS t4 Output Fall Time1, 2 Measured between 2.0V and 0.8V 2.5 nS All outputs equally loaded 250 pS Measured at VDD /2 ±350 pS 700 pS 200 pS 1.0 mS t5 t6 Output-to-output skew 2 Delay, CLKIN Rising Edge to CLKOUT Rising Edge 2 t7 Device-to-Device Skew 2 tJ Cycle-to-cycle jitter 2 tLOCK PLL Lock Time 2 Measured at VDD/2 on the CLKOUT pins of the device Loaded outputs Stable power supply, valid clock presented on CLKIN pin 50 Max Note: 1. The parameters are specified with loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 5 of 14 PCS5P23Z05B/09B May 2007 rev 0.2 Switching Waveforms Duty Cycle Timing t t 1 2 1.4 V 1.4 V 1.4 V All Outputs Rise/Fall Time 2.0V 0.8V OUTPUT 2.0 V 0.8 V 3.3 V 0V t4 t3 Output - Output Skew 1.4 V OUTPUT 1.4 V OUTPUT t 5 Input - Output Propagation Delay V INPUT /2 DD V OUTPUT t /2 DD 6 Device - Device Skew CLKOUT, Device 1 VDD/2 V CLKOUT, Device 2 t /2 DD 7 Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 6 of 14 PCS5P23Z05B/09B May 2007 rev 0.2 Input-Output Skew Test Circuit Input Timing-Safe™ Output TEST CIRCUIT +3.3V VDD TSKEW - TSKEW+ +3.3V CLKOUT 0.1uF OUTPUTS LOAD VDD One clock cycle N=1 0.1uF TSKEW represents input-output skew GND GND when spread spectrum is ON For example, TSKEW = ± 0.125 for an Input clock 32MHz, translates in to (1/32MHz) * 0.125=3.90nS A Typical example of Timing-Safe™ waveform Input Input CLKOUT with SSOFF Timing-Safe™ CLKOUT Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 7 of 14 PCS5P23Z05B/09B May 2007 rev 0.2 Package Information 8-lead (150-mil) SOIC Package H E D A2 A C A1 D θ e L B Dimensions Symbol Inches Min Max Millimeters Min Max A1 0.004 0.010 0.10 0.25 A 0.053 0.069 1.35 1.75 A2 0.049 0.059 1.25 1.50 B 0.012 0.020 0.31 0.51 C 0.007 0.010 0.18 0.25 D 0.193 BSC 4.90 BSC E 0.154 BSC 3.91 BSC e 0.050 BSC 1.27 BSC H 0.236 BSC 6.00 BSC L 0.016 0.050 0.41 1.27 θ 0° 8° 0° 8° Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 8 of 14 PCS5P23Z05B/09B May 2007 rev 0.2 8-lead TSSOP (4.40-MM Body) H E D A2 A C θ e A1 L B Dimensions Symbol Inches Min Millimeters Max A Min Max 0.043 1.10 A1 0.002 0.006 0.05 0.15 A2 0.033 0.037 0.85 0.95 B 0.008 0.012 0.19 0.30 c 0.004 0.008 0.09 0.20 D 0.114 0.122 2.90 3.10 E 0.169 0.177 4.30 4.50 e 0.026 BSC 0.65 BSC H 0.252 BSC 6.40 BSC L 0.020 0.028 0.50 0.70 θ 0° 8° 0° 8° Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 9 of 14 PCS5P23Z05B/09B May 2007 rev 0.2 16-lead (150 Mil) Molded SOIC Package PIN 1 ID 1 8 H E 9 16 D h Seating Plane A2 D A e C θ 0.004 L A1 B Dimensions Symbol Inches Millimeters Min Max Min Max A 0.053 0.069 1.35 1.75 A1 0.004 0.010 0.10 0.25 A2 0.049 0.059 1.25 1.50 B 0.013 0.022 0.33 0.53 C 0.008 0.012 0.19 0.27 D 0.386 0.394 9.80 10.01 E 0.150 0.157 3.80 4.00 e 0.050 BSC 1.27 BSC H 0.228 0.244 5.80 6.20 h 0.010 0.016 0.25 0.41 L 0.016 0.035 0.40 0.89 θ 0° 8° 0° 8° Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 10 of 14 PCS5P23Z05B/09B May 2007 rev 0.2 16-lead TSSOP (4.40-MM Body) 1 8 PIN 1 ID E 16 A A2 e B A1 Seating Plane C θ D 9 H L D Dimensions Symbol Inches Min Millimeters Max A Min Max 0.043 1.20 A1 0.002 0.006 0.05 0.15 A2 0.031 0.041 0.80 1.05 B 0.007 0.012 0.19 0.30 C 0.004 0.008 0.09 0.20 D 0.193 0.201 4.90 5.10 E 0.169 0.177 4.30 4.50 e 0.026 BSC 0.65 BSC H 0.252 BSC 6.40 BSC L 0.020 0.030 0.50 0.75 θ 0° 8° 0° 8° Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 11 of 14 PCS5P23Z05B/09B May 2007 rev 0.2 Ordering Codes Ordering Code Marking Package Type Temperature PCS5P23Z09BF-16-ST 5P23Z09BF 16-pin 150-mil SOIC-TUBE, Pb Free Commercial PCS5I23Z09BF-16-ST 5I23Z09BF 16-pin 150-mil SOIC-TUBE, Pb Free Industrial PCS5P23Z09BF-16-SR 5P23Z09BF 16-pin 150-mil SOIC-TAPE & REEL, Pb Free Commercial PCS5I23Z09BF-16-SR 5I23Z09BF 16-pin 150-mil SOIC-TAPE & REEL, Pb Free Industrial PCS5P23Z09BF-16-TT 5P23Z09BF 16-pin 4.4-mm TSSOP - TUBE, Pb Free Commercial PCS5I23Z09BF-16-TT 5I23Z09BF 16-pin 4.4-mm TSSOP - TUBE, Pb Free Industrial PCS5P23Z09BF-16-TR 5P23Z09BF 16-pin 4.4-mm TSSOP - TAPE & REEL, Pb Free Commercial PCS5I23Z09BF-16-TR 5I23Z09BF 16-pin 4.4-mm TSSOP - TAPE & REEL, Pb Free Industrial PCS5P23Z05BF-08-ST 5P23Z05BF 8-pin 150-mil SOIC-TUBE, Pb Free Commercial PCS5I23Z05BF-08-ST 5I23Z05BF 8-pin 150-mil SOIC-TUBE, Pb Free Industrial PCS5P23Z05BF-08-SR 5P23Z05BF 8-pin 150-mil SOIC-TAPE & REEL, Pb Free Commercial PCS5I23Z05BF-08-SR 5I23Z05BF 8-pin 150-mil SOIC-TAPE & REEL, Pb Free Industrial PCS5P23Z05BF-08-TT 5P23Z05BF 8-pin 4.4-mm TSSOP - TUBE, Pb Free Commercial PCS5I23Z05BF-08-TT 5I23Z05BF 8-pin 4.4-mm TSSOP - TUBE, Pb Free Industrial PCS5P23Z05BF-08-TR 5P23Z05BF 8-pin 4.4-mm TSSOP - TAPE & REEL, Pb Free Commercial PCS5I23Z05BF-08-TR 5I23Z05BF 8-pin 4.4-mm TSSOP - TAPE & REEL, Pb Free Industrial PCS5P23Z09BG-16-ST 5P23Z09BG 16-pin 150-mil SOIC-TUBE, Green Commercial PCS5I23Z09BG-16-ST 5I23Z09BG 16-pin 150-mil SOIC-TUBE, Green Industrial PCS5P23Z09BG-16-SR 5P23Z09BG 16-pin 150-mil SOIC-TAPE & REEL, Green Commercial PCS5I23Z09BG-16-SR 5I23Z09BG 16-pin 150-mil SOIC-TAPE & REEL, Green Industrial PCS5P23Z09BG-16-TT 5P23Z09BG 16-pin 4.4-mm TSSOP - TUBE, Green Commercial PCS5I23Z09BG-16-TT 5I23Z09BG 16-pin 4.4-mm TSSOP - TUBE, Green Industrial PCS5P23Z09BG-16-TR 5P23Z09BG 16-pin 4.4-mm TSSOP - TAPE & REEL, Green Commercial PCS5I23Z09BG-16-TR 5I23Z09BG 16-pin 4.4-mm TSSOP - TAPE & REEL, Green Industrial PCS5P23Z05BG-08-ST 5P23Z05BG 8-pin 150-mil SOIC-TUBE, Green Commercial PCS5I23Z05BG-08-ST 5I23Z05BG 8-pin 150-mil SOIC-TUBE, Green Industrial PCS5P23Z05BG-08-SR 5P23Z05BG 8-pin 150-mil SOIC-TAPE & REEL, Green Commercial PCS5I23Z05BG-08-SR 5I23Z05BG 8-pin 150-mil SOIC-TAPE & REEL, Green Industrial PCS5P23Z05BG-08-TT 5P23Z05BG 8-pin 4.4-mm TSSOP - TUBE, Green Commercial PCS5I23Z05BG-08-TT I23Z05BG 8-pin 4.4-mm TSSOP - TUBE, Green Industrial PCS5P23Z05BG-08-TR 5P23Z05BG 8-pin 4.4-mm TSSOP - TAPE & REEL, Green Commercial PCS5I23Z05BG-08-TR 5I23Z05BG 8-pin 4.4-mm TSSOP - TAPE & REEL, Green Industrial Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 12 of 14 PCS5P23Z05B/09B May 2007 rev 0.2 Device Ordering Information P C S 5 P 2 3 Z 0 5 B F - 0 8 - T R Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 13 of 14 PCS5P23Z05B/09B May 2007 rev 0.2 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS5P23Z05B/09B Document Version: 0.2 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 Timing-Safe™ US Patent Pending. © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. Timing-Safe™ Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 14 of 14