TI TL16C550BFN

TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
D
D
D
D
D
D
D
D
Capable of Running With All Existing
TL16C450 Software
After Reset, All Registers Are Identical to
the TL16C450 Register Set
In the FIFO Mode, Transmitter and Receiver
Are Each Buffered With 16-Byte FIFOs to
Reduce the Number of Interrupts to the
CPU
In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data
Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (216 – 1) and Generates an Internal 16×
Clock
Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added to or
Deleted From the Serial Data Stream
Independent Receiver Clock Input
Transmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled
D
D
D
D
D
D
D
D
D
Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (DC to 562 Kbit/s)
False-Start Bit Detection
Complete Status Reporting Capabilities
3-State Outputs Provide TTL Drive
Capabilities for Bidirectional Data Bus and
Control Bus
Line Break Generation and Detection
Internal Diagnostic Capabilities:
– Loopback Controls for Communications
Link Fault Isolation
– Break, Parity, Overrun, Framing Error
Simulation
Fully Prioritized Interrupt System Controls
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
Faster Plug-In Replacement for National
Semiconductor NS16550A
description
The TL16C550B and the TL16C550BI are functional upgrades of the TL16C450 asynchronous
communications element (ACE). Functionally identical to the TL16C450 on power up (character mode†), the
TL16C550B and TL16C550BI can be placed in an alternate mode (FIFO) to relieve the CPU of excessive
software overhead.
In this alternate FIFO mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte
in the receiver FIFO) to be stored in both receive and transmit modes. To minimize system overhead and
maximize system efficiency, all logic is on the chip. Two of the TL16C450 terminal functions (RXRDY and
TXRDY) have been changed to allow signalling of DMA transfers.
The TL16C550B and the TL16C550BI perform serial-to-parallel conversions on data received from a peripheral
device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read and report
on the status of the ACE at any point in the ACE operation. Reported status information includes: the type of
transfer operation in progress, the status of the operation, and any error conditions encountered.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† The TL16C550B and the TL16C550BI can also be reset to the TL16C450 mode under software control.
Copyright  1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
description (continued)
The TL16C550B and the TL16C550BI ACE include programmable, on-board, baud rate generators. These
generators are capable of dividing a reference clock input by divisors from 1 to (216 – 1) and producing a 16 ×
clock for driving the internal transmitter logic. Provisions are included to use this 16× clock to drive the receiver
logic. Also included in the ACE is a complete modem control capability and a processor interrupt system that
may be software tailored to user requirements to minimize the computing required to handle the
communications link.
The TL16C550B is available in a 40-pin DIP (N) package, 44-pin PLCC (FN) package, and 48-pin TQFP (PT)
package. The TL16C550BI is available in a 44-pin PLCC (FN) package.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
VCC
RI
DCD
DSR
CTS
MR
OUT1
DTR
RTS
OUT2
INTRPT
RXRDY
A0
A1
A2
ADS
TXRDY
DDIS
RD2
RD1
6 5 4
D5
D6
D7
RCLK
SIN
NC
SOUT
CS0
CS1
CS2
BAUDOUT
7
3
2 1 44 43 42 41 40
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
29
17
18 19 20 21 22 23 24 25 26 27 28
MR
OUT1
DTR
RTS
OUT2
NC
INTRPT
RXRDY
A0
A1
A2
TXRDY
ADS
40
2
WR1
WR2
VSS
NC
RD1
RD2
DDIS
1
XIN
XOUT
D0
D1
D2
D3
D4
D5
D6
D7
RCLK
SIN
SOUT
CS0
CS1
CS2
BAUDOUT
XIN
XOUT
WR1
WR2
VSS
FN PACKAGE
(TOP VIEW)
D4
D3
D2
D1
D0
NC
VCC
RI
DCD
DSR
CTS
N PACKAGE
(TOP VIEW)
NC
D4
D3
D2
D1
D0
VCC
RI
DCD
DSR
CTS
NC
PT PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
NC
D5
D6
D7
RCLK
NC
SIN
SOUT
CS0
CS1
CS2
BAUDOUT
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
NC
MR
OUT1
DTR
RTS
OUT2
INTRPT
RXRDY
A0
A1
A2
NC
NC
XIN
XOUT
WR1
WR2
VSS
RD1
RD2
NC
DDIS
TXRDY
ADS
13 14 15 16 17 18 19 20 21 22 23 24
NC – No internal connection
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3
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
functional block diagram
Internal
Data Bus
8 –1
D7 – D0
8
S
e
l
e
c
t
Receiver
FIFO
Receiver
Buffer
Register
Data
Bus
Buffer
Line
Control
Register
A0
A1
A2
CS0
CS1
CS2
ADS
MR
RD1
RD2
WR1
WR2
DDIS
TXRDY
XIN
XOUT
RXRDY
Receiver
Shift
Register
10
Receiver
Timing and
Control
9
RCLK
28
27
26
Divisor
Latch (LS)
12
Divisor
Latch (MS)
Baud
Generator
15
BAUDOUT
13
14
25
35
21
22
18
19
Line
Control
Register
Line
Status
Register
Select
and
Control
Logic
Transmitter
FIFO
Transmitter
Holding
Register
S
e
l
e
c
t
Line
Control
Register
23
24
16
32
Modem
Control
Register
36
33
17
29
11
Modem
Control
Logic
Modem
Status
Register
37
38
39
34
31
Interrupt
Enable
Register
Interrupt
Control
Logic
Interrupt
I/O
Register
FIFO
Control
Register
Terminal numbers shown are for the N package.
4
SIN
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• DALLAS, TEXAS 75265
30
SOUT
RTS
CTS
DTR
DSR
DCD
RI
OUT1
OUT2
INTRPT
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
Terminal Functions
TERMINAL
NO.
N
NO.
FN
NO.
PT
I/O
DESCRIPTION
A0
A1
A2
28
27
26
31
30
29
28
27
26
I
Register select. A0 – A2 are used during read and write operations to select the ACE register to read
from or write to. Refer to Table 1 for register addresses, and refer to the address strobe (ADS) signal
description.
ADS
25
28
24
I
Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select
signals (CS0, CS1, CS2) drive the internal select logic directly; when high, the register select and chip
select signals are held in the state they are in when the low-to-high transition of ADS occurs.
BAUDOUT
15
17
12
O
Baud out. BAUDOUT is a 16 × clock signal for the transmitter section of the ACE. The clock rate is
established by the reference oscillator frequency divided by a divisor specified by the baud generator
divisor latches. BAUDOUT can also be used for the receiver section by tying this output to RCLK.
CS0
CS1
CS2
12
13
14
14
15
16
9
10
11
I
Chip select. When CS0 = high, CS1 = high, and CS2 = low, these three inputs select the ACE. When
any of these inputs are inactive, the ACE remains inactive. Refer to the ADS signal description.
CTS
36
40
38
I
Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of
the modem status register. Bit 0 (∆ CTS) of the modem status register indicates that this signal has
changed states since the last read from the modem status register. If the modem status interrupt is
enabled when CTS changes state, an interrupt is generated.
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
43
44
45
46
47
2
3
4
I/O
Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
information between the ACE and the CPU.
DCD
38
42
40
I
Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD)
of the modem status register. Bit 3 (∆ DCD) of the modem status register indicates that this signal has
changed states since the last read from the modem status register. If the modem status interrupt is
enabled when DCD changes state, an interrupt is generated.
DDIS
23
26
22
O
Driver disable. This output is active (high) when the CPU is not reading data. When active, this output
can disable an external transceiver.
DSR
37
41
39
I
Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of
the modem status register. Bit 1 (∆ DSR) of the modem status register indicates this signal has changed
states since the last read from the modem status register. If the modem status interrupt is enabled when
DSR changes state, an interrupt is generated.
DTR
33
37
33
O
Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to
establish communication. DTR is placed in the active state by setting the DTR bit of the modem control
register to a high level. DTR is placed in the inactive state either as a result of a master reset, during
loop mode operation, or clearing the DTR bit.
INTRPT
30
33
30
O
Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced.
Four conditions that cause an interrupt to be issued are: a receiver error, received data is available or
timed out (FIFO mode only), the transmitter holding register is empty, or an enabled modem status
interrupt. The INTRPT output is reset (deactivated) either when the interrupt is serviced or as a result
of a master reset.
MR
35
39
35
I
Master reset. When active (high), MR clears most ACE registers and sets the state of various output
signals. Refer to Table 2.
OUT1
OUT2
34
31
38
35
34
31
O
Outputs 1 and 2. User-designated outputs that are set to their active low states by setting their
respective modem control register bits (OUT1 and OUT2) high. OUT1 and OUT2 are set to their inactive
(high) states as a result of master reset, during loop mode operations, or by clearing bit 2 (OUT1) or
bit 3 (OUT2) of the modem control register.
RCLK
9
10
5
I
Receiver clock. RCLK is the 16 × baud rate clock for the receiver section of the ACE.
NAME
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5
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
Terminal Functions (Continued)
TERMINAL
NO.
N
NO.
FN
NO.
PT
I/O
DESCRIPTION
RD1
RD2
21
22
24
25
19
20
I
Read inputs. When either input is active (low or high respectively) while the ACE is selected, the CPU
is allowed to read status information or data from a selected ACE register. Only one of these inputs is
required for the transfer of data during a read operation; the other input should be tied in its inactive state
(i.e., RD2 tied low or RD1 tied high).
RI
39
43
41
I
Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the
modem status register. Bit 2 (TERI) of the modem status register indicates that the RI input has
transitioned from a low to a high state since the last read from the modem status register. If the modem
status interrupt is enabled when this transition occurs, an interrupt is generated.
RTS
32
36
32
O
Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive
data. RTS is set to its active state by setting the RTS modem control register bit and is set to its inactive
(high) state either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS)
of the MCR.
RXRDY
29
32
29
O
Receiver ready output. Receiver direct memory access (DMA) signalling is available with this terminal.
When operating in the FIFO mode, one of two types of DMA signalling can be selected using the FIFO
control register bit 3 (FCR3). When operating in the TL16C450 mode, only DMA mode 0 is allowed.
Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1
supports multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO
has been emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), when there is at least one
character in the receiver FIFO or receiver holding register, RXRDY is active low. When RXRDY has
been active but there are no characters in the FIFO or holding register, RXRDY goes inactive (high).
In DMA mode 1 (FCR0 = 1, FCR3 = 1), when the trigger level or the timeout has been reached, RXRDY
goes active (low); when it has been active but there are no more characters in the FIFO or holding
register, it goes inactive (high).
SIN
10
11
7
I
Serial data input. Input from a connected communications device
SOUT
11
13
8
O
Composite serial data output. Output to a connected communication device. SOUT is set to the marking
(set) state as a result of master reset.
TXRDY
24
27
23
O
Transmitter ready output. Transmitter DMA signalling is available with this terminal. When operating in
the FIFO mode, one of two types of DMA signalling can be selected using FCR3. When operating in
the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a
transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple
transfers are made continuously until the transmit FIFO has been filled.
VCC
VSS
40
44
42
20
22
18
WR1
WR2
18
19
20
21
16
17
I
XIN
XOUT
16
17
18
19
14
15
I/O
NAME
6
5-V supply voltage
Supply common
Write inputs. When either input is active (high or low respectively) and while the ACE is selected, the
CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs is
required to transfer data during a write operation; the other input should be tied in its inactive state (i.e.,
WR2 tied low or WR1 tied high).
External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).
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TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range at any input, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Continuous total power dissipation at (or below) 70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 mW
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Operating free-air temperature range, TA: TL16C550B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TL16C550BI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Case temperature for 10 seconds, TC: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N or PT package . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS (ground).
recommended operating conditions
Supply voltage, VCC
NOM
4.75
5
MAX
UNIT
5.25
V
V
– 0.5
VCC
0.8
TL16C550B
0
70
°C
TL16C550BI
–40
85
°C
High-level input voltage, VIH
2
Low-level input voltage, VIL
Operating
O
erating free-air tem
temperature
erature, TA
MIN
V
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH‡
VOL‡
High-level output voltage
Il
Input current
VCC = 5.25 V,,
VI = 0 to 5.25 V,
IOZ
High-impedance-state
g
output current
VCC = 5.25 V,
VSS = 0,
VO = 0 to 5.25 V,
Chip selected in write mode or chip deselect
ICC
Supply
Su
ly current
25 V
TA = 25
25°C
VCC = 5
5.25
V,
C,
SIN,
V,
SIN DSR,
DSR DCD,
DCD CTS,
CTS and RI at 2 V
8V
All other inputs at 0
0.8
V, XTAL1 at 4 MHz
MHz,
No
Baud
kbit/s
N lload
d on outputs,
t t
B
d rate
t = 50 kbit/
Ci(CLK)
Clock input capacitance
Co(CLK)
Clock output capacitance
Ci
Input capacitance
Low-level output voltage
IOH = – 1 mA
IOL = 1.6 mA
TYP†
MAX
2.4
Co
Output capacitance
† All typical values are at VCC = 5 V, TA = 25°C.
‡ These parameters apply for all outputs except XOUT.
• DALLAS, TEXAS 75265
UNIT
V
0.4
V
10
µA
± 20
µA
µ
10
mA
15
20
pF
20
30
pF
6
10
pF
10
20
pF
VSS = 0,,
All other terminals floating
VCC = 0,
VSS = 0,
f = 1 MHz
MHz,
TA = 25°C,
25°C
All other terminals grounded
POST OFFICE BOX 655303
MIN
7
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
ALT. SYMBOL
FIGURE
TEST CONDITIONS
tcR
tcW
Cycle time, read (tw7 + td8 + td9)
RC
Cycle time, write (tw6 + td5 + td6)
WC
tw1
tw2
Pulse duration, clock high
tXH
tXL
1
f = 9 MHz maximum
1
f = 9 MHz maximum
tw5
tw6
Pulse duration, address strobe low
tADS
tWR
tw7
tw8
Pulse duration, read strobe
tRD
Pulse duration, master reset
tsu1
tsu2
Setup time, address valid before ADS↑
tMR
tAS
tsu3
th1
Setup time, data valid before WR1↓ or WR2↑
th2
th3
Hold time, chip select valid after ADS↑
th4
th5
Hold time, address valid after WR1↑ or WR2↓
th6
th7
td4†
Hold time, chip select valid after RD1↑ or RD2↓
td5†
td6†
td7†
Delay time, address valid before WR1↓ or WR2↑
td8†
td9
Delay time, address valid to RD1↓ or RD2↑
Pulse duration, clock low
Pulse duration, write strobe
Setup time, chip select valid before ADS↑
Hold time, address low after ADS↑
Hold time, chip select valid after WR1↑ or WR2↓
Hold time, data valid after WR1↑ or WR2↓
Hold time, address valid after RD1↑ or RD2↓
Delay time, chip select valid before WR1↓ or WR2↑
Delay time, write cycle, WR1↑ or WR2↓ to ADS↓
Delay time, chip select valid to RD1↓ or RD2↑
Delay time, read cycle, RD1↑ or RD2↓ to ADS↓
td10
Delay time, RD1↓ or RD2↑ to data valid
td11
Delay time, RD1↑ or RD2↓ to floating data
† Only applies when ADS is low
MIN
MAX
UNIT
87
ns
87
ns
40
ns
40
ns
2,3
9
ns
2
40
ns
3
40
ns
1
µs
8
ns
2,3
tCS
tDS
2,3
8
ns
2
15
ns
tAH
tCH
2,3
0
ns
2,3
0
ns
tWCS
tWA
2
10
ns
2
10
ns
tDH
2
5
ns
tRCS
tRA
3
10
ns
3
20
ns
tCSW
tAW
2
7
ns
2
7
ns
tWC
tCSR
2
40
ns
3
7
ns
tAR
tRC
3
7
ns
3
40
ns
tRVD
tHZ
3
CL = 75 pF
45
ns
3
CL = 75 pF
20
ns
system switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 2)
PARAMETER
ALT. SYMBOL
FIGURE
tdis(R) Disable time, RD1↑↓ or RD2↓↑ to DDIS↑↓
tRDD
3
NOTE 2: Charge and discharge time is determined by VOL, VOH, and external loading.
TEST CONDITIONS
CL = 75 pF
MIN
MAX
20
UNIT
ns
baud generator switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, CL = 75 pF
PARAMETER
tw3
tw4
Pulse duration, BAUDOUT low
td1
td2
Delay time, XIN↑ to BAUDOUT↑
8
Pulse duration, BAUDOUT high
Delay time, XIN↑↓ to BAUDOUT↓
ALT. SYMBOL
FIGURE
tLW
tHW
1
f = 9 MHz, CLK ÷ 2
80
1
f = 9 MHz, CLK ÷ 2
80
tBLD
tBHD
1
75
ns
1
65
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TEST CONDITIONS
MIN
MAX
UNIT
ns
ns
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 3)
ALT. SYMBOL
FIGURE
td12
Delay time, RCLK to sample
PARAMETER
tSCD
4
TEST CONDITIONS
MIN
MAX
10
UNIT
ns
td13
Delay time, stop to set interrupt or read
RBR to LSI interrupt or stop to RXRDY↓
tSINT
4,5,6,7,8
1
RCLK
cycle
td14 Delay time, read RBR/LSR to reset interrupt low
tRINT
4,5,6,7,8
CL = 75 pF
40
ns
NOTE 3: In the FIFO mode, the read cycle (RC) = 425 ns (minimum) between reads of the receiver FIFO and the status registers (interrupt
identification register or line status register).
transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER
ALT. SYMBOL
FIGURE
TEST CONDITIONS
MIN
MAX
UNIT
td15
Delay time, initial write (INTRPT low) to transmit
start (SOUT low)
tIRS
9
8
24
baudout
cycles
td16
Delay time, stop (SOUT low) to interrupt (INTRPT
high)
tSTI
9
8
9
baudout
cycles
td17
Delay time, WR THR high to reset interrupt
(INTRPT low)
tHR
9
50
ns
td18
Delay time, initial WR THR low to THRE interrupt
(INTRPT high)
tSI
9
32
baudout
cycles
td19
Delay time, RD IIR low to reset THRE interrupt
(INTRPT low)
tIR
9
CL = 75 pF
35
ns
td20
Delay time, WR THR high to TXRDY high
(inactive)
tWXI
10,11
CL = 75 pF
35
ns
td21
Delay time, start (SOUT low) to TXRDY low
(active)
tSXA
10,11
CL = 75 pF
8
baudout
cycles
CL = 75 pF
16
modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, CL = 75 pF
PARAMETER
ALT. SYMBOL
FIGURE
MIN
MAX
UNIT
td22
Delay time, WR MCR low to output (RTS, DTR, OUT1, OUT2) low or high
tMDO
12
50
ns
td23
Delay time, modem interrupt (CTS, DSR, DCD) low to set interrupt
(INTRPT) high
tSIM
12
35
ns
td24
Delay time, RD MSR low to reset interrupt (INTRPT) low
tRIM
12
40
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
N
tw2
tw1
XIN
td2
td1
BAUDOUT
(1/1)
td1
td2
BAUDOUT
(1/2)
tw3
tw4
BAUDOUT
(1/3)
BAUDOUT
(1/N)
(N > 3)
2 XIN Cycles
(N – 2) XIN Cycles
Figure 1. Baud Generator Timing Waveforms
10
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TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
tw5
50%
ADS
50%
50%
tsu1
th1
A0 – A2
50%
50% Valid†
Valid
50%
tsu2
th2
CS0, CS1, CS2
50%
50%
th3
tw6
td4
td5
WR1, WR2
Valid†
Valid
th4†
td6
50%
Active
50%
tsu3
th5
Valid Data
D7 – D0
† Applicable only when ADS is low.
Figure 2. Write Cycle Timing Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
tw5
50%
ADS
50%
50%
tsu1
th1
A0 – A2
Valid
50%
50% Valid† 50%
tsu2
th2
CS0, CS1, CS2
50%
Valid
td7†
td8†
50%
RD1, RD2
50% Valid†
th6
tw7
50%
th7†
td9
Active
50%
tdis(R)
DDIS
tdis(R)
50%
50%
td10
D7 – D0
td11
Valid Data
† Applicable only when ADS is low.
Figure 3. Read Cycle Timing Waveforms
12
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TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
RCLK
td12
8 CLKs
Sample Clock
TL16C450 Mode:
SIN
Start
Data Bits 5 – 8
Parity
Stop
Sample Clock
INTRPT
(data ready)
50%
td13
INTRPT
(RCV error)
50%
td14
50%
50%
RD1, RD2
(read RBR)
50%
Active
td14
RD1, RD2
(read LSR)
50%
Active
Figure 4. Receiver Timing Waveforms
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TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
SIN
Data Bits 5 – 8
Stop
Sample Clock
Trigger-Level
Interrupt
(FCR6, 7 = 0, 0)
50%
(FIFO at or above
trigger level)
50%
(FIFO below
trigger level)
td13
(see Note A)
td14
INTRPT
Line Status
Interrupt (LSI)
50%
50%
td14
RD1
(RD LSR)
Active
50%
Active
RD1
(RD RBR)
50%
NOTE A: For a timeout interrupt, td13 = 8 RCLKs.
Figure 5. Receiver FIFO First Byte (Sets DR Bit) Waveforms
SIN
Stop
Sample Clock
Timeout or
Trigger-Level
Interrupt
50%
50%
(FIFO below
trigger level)
td13
(see Note A)
td14
50%
Line Status
Interrupt (LSI)
50%
Top Byte of FIFO
td13
td14
RD1, RD2
(RDLSR)
RD1, RD2
(RDRBR)
(FIFO at or above
trigger level)
50%
Active
50%
50%
Active
Previous Byte
Read From FIFO
NOTE A: For a timeout interrupt, td13 = 8 RCLKs.
Figure 6. Receiver FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms
14
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• DALLAS, TEXAS 75265
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
RD
(RD RBR)
50%
Active
See Note A
SIN
(first byte)
Stop
Sample Clock
td13
(see Note B)
td14
50%
50%
RXRDY
NOTES: A. This is the reading of the last byte in the FIFO.
B. For a timeout interrupt, td13 = 8 RCLKs.
Figure 7. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
RD
(RD RBR)
50%
Active
See Note A
SIN
(first byte that reaches
the trigger level)
Sample Clock
td13
(see Note B)
RXRDY
td14
50%
50%
NOTES: A. This is the reading of the last byte in the FIFO.
B. For a timeout interrupt, td13 = 8 RCLKs.
Figure 8. Receiver Ready (RXRDY) Waveforms, FCR = 1 or FCR3 = 1 (Mode 1)
POST OFFICE BOX 655303
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TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
Start
50%
SOUT
Data Bits
Parity
td15
INTRPT
(THRE)
50%
Start
50%
Stop
50%
td16
50%
50%
50%
50%
td18
td17
td17
WR THR 50%
50%
50%
td19
RD IIR
50%
Figure 9. Transmitter Timing Waveforms
WR
(WR THR)
SOUT
Byte #1
50%
Data
Parity
Stop
Start
50%
td21
td20
TXRDY
50%
50%
Figure 10. Transmitter Ready (TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
Byte #16
WR
(WR THR)
SOUT
50%
Data
Parity
Stop
td21
td20
TXRDY
Start
50%
50%
FIFO Full
50%
Figure 11. Transmitter Ready (TXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
WR
(WR MCR)
50%
50%
td22
td22
RTS, DTR,
OUT1, OUT2
50%
50%
50%
CTS, DSR, DCD
td23
INTRPT
(modem)
50%
50%
50%
td24
td23
RD2
(RD MSR)
50%
RI
50%
Figure 12. Modem Control Timing Waveforms
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17
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
APPLICATION INFORMATION
SOUT
D7 – D0
D7 – D0
MEMR or I/OR
MEMW or I/ON
INTR
C
P
U
B
u
s
RESET
A0
RD1
RTS
WR1
DTR
INTRPT
DSR
MR
DCD
A0
A1
A1
A2
SIN
EIA232-D Drivers
and Receivers
CTS
TL16C550B
(ACE)
RI
A2
ADS
XIN
WR2
L
3.072 MHz
RD2
CS
H
CS2
XOUT
CS1
BAUDOUT
CS0
RCLK
Figure 13. Basic TL16C550B Configuration
Receiver Disable
WR
WR1
TL16C550B
(ACE)
Microcomputer
System
Data Bus
Data Bus
8-Bit
Bus Transceiver
D7 – D0
DDIS
Driver Disable
Figure 14. Typical Interface for a High-Capacity Data Bus
18
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• DALLAS, TEXAS 75265
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
APPLICATION INFORMATION
TL16C550B
XIN
A16 – A23
A16 – A23
XOUT
16
Alternate
Crystal Control
17
15
12
BAUDOUT
CS0
Address
Decoder
CPU
13
14
RCLK
CS1
CS2
DTR
25
ADS
RTS
33
32
20
1
34
ADS
OUT1
35
RSI/ABT
9
OUT2
MR
31
A0 – A7
Buffer
AD0 – AD15
D0 – D7
39
RI
38
PHI1
DCD
PHI2
8
37
6
DSR
CTS
PHI1
ADS
PHI2
RSTO
RD
21
TCU
18
WR
RD1
36
5
11
SOUT
2
WR1
10
SIN
INTRPT
3
30
24
AD0 – AD15
TXRDY
22
19
RD2
DDIS
WR2
GND
(VSS)
RXRDY
20
23
29
40
7
1
EIA-232-D
Connector
5V
(VCC)
Terminal numbers shown are for the N package.
Figure 15. Typical TL16C550B Connection to a CPU
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TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
Table 1. Register Selection
DLAB†
A2
A1
A0
0
L
L
L
Receiver buffer (read), transmitter holding (write)
0
L
L
H
Interrupt enable register
X
L
H
L
Interrupt identification register (read only)
X
L
H
L
FIFO control register (write)
X
L
H
H
Line control register
X
H
L
L
Modem control register
X
H
L
H
Line status register
X
H
H
L
Modem status register
X
H
H
H
Scratch register
1
L
L
L
Divisor latch (LSB)
REGISTER
1
L
L
H
Divisor latch (MSB)
† The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal
is controlled by writing to this bit location (see Table 3).
Table 2. ACE Reset Functions
REGISTER/SIGNAL
RESET
CONTROL
RESET STATE
Interrupt Enable Register
Master Reset
All bits cleared (bits 0 – 3 forced and bits 4 – 7 permanent)
Interrupt Identification Register
Master Reset
Bit 0 is set, bits 1 – 3 are cleared, and bits 4 – 7 are permanently
cleared
FIFO Control Register
Master Reset
All bits cleared
Line Control Register
Master Reset
All bits cleared
Modem Control Register
Master Reset
All bits cleared (5 – 7 permanent)
Line Status Register
Master Reset
Bits 5 and 6 are set, all other bits are cleared
Modem Status Register
Master Reset
Bits 0 – 3 are cleared, bits 4 – 7 are input signals
SOUT
Master Reset
High
INTRPT (receiver error flag)
Read LSR/MR
Low
INTRPT (received data available)
Read RBR/MR
Low
Read IR/Write THR/MR
Low
Read MSR/MR
Low
OUT2
Master Reset
High
RTS
Master Reset
High
DTR
Master Reset
High
OUT1
Master Reset
High
Scratch Register
Master Reset
No effect
Divisor Latch (LSB and MSB) Registers
Master Reset
No effect
Receiver Buffer Registers
Master Reset
No effect
Transmitter Holding Registers
Master Reset
No effect
INTRPT (transmitter holding register empty)
INTRPT (modem status changes)
RCVR FIFO
MR/FCR1 – FCR0/
∆FCR0
All bits low
XMIT FIFO
MR/FCR2 – FCR0/
∆FCR0
All bits low
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 3. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.
Table 3. Summary of Accessible Registers
REGISTER ADDRESS
Bit
No.
0
1
2
3
0 DLAB = 0
0 DLAB = 0
Receiver
Buffer
Register
(Read
Only)
Transmitter
Holding
Register
(Write
Only)
RBR
Data Bit 0†
Data Bit 1
Data Bit 2
Data Bit 3
1 DLAB = 0
2
2
3
4
5
6
7
0 DLAB = 1
1 DLAB = 1
Interrupt
Enable
Register
Interrupt
Ident.
Register
(Read
Only)
FIFO
Control
Register
(Write
Only)
Line
Control
Register
Modem
Control
Register
Line
Status
Register
Modem
Status
Register
Scratch
Register
Divisor
Latch
(LSB)
Latch
(MSB)
THR
IER
IIR
FCR
LCR
MCR
LSR
MSR
SCR
DLL
DLM
Data Bit 0
Enable
Received
Data
Available
Interrupt
(ERBI)
0 if
interrupt
Pending
FIFO
Enable
Word
Length
Select
Bit 0
(WLS0)
Data
Terminal
Ready
(DTR)
Data
Ready
(DR)
Delta
Clear
to Send
Bit 0
Bit 0
Bit 8
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBEI)
Interrupt
ID
Bit (1)
Receiver
FIFO
Reset
Word
Length
Select
Bit 1
(WLS1)
Request
to Send
(RTS)
Overrun
Error
(OE)
Bit 1
Bit 1
Bit 9
Data Bit 2
Enable
Receiver
Line Status
Interrupt
(ELSI)
Interrupt
ID
Bit (2)
Transmitter
FIFO
Reset
Number
of
Stop Bits
(STB)
OUT1
Parity
Error
(PE)
Trailing
Edge Ring
Indicator
(TERI)
Bit 2
Bit 2
Bit 10
Data Bit 3
Enable
Modem
Status
Interrupt
(EDSSI)
Interrupt
ID
Bit (2)
(see
Note 4)
DMA
Mode
Select
Parity
Enable
(PEN)
OUT2
Framing
Error
(FE)
Delta
Data
Carrier
Detect
Bit 3
Bit 3
Bit 11
Loop
Break
Interrupt
(BI)
Clear
to
Send
(CTS)
Bit 4
Bit 4
Bit 12
Data Bit 1
(∆CTS)
Delta
Data
Set
Ready
(∆DSR)
(∆DCD)
4
Data Bit 4
Data Bit 4
0
0
Reserved
Even
Parity
Select
(EPS)
5
Data Bit 5
Data Bit 5
0
0
Reserved
Stick
Parity
0
Transmitter
Holding
Register
(THRE)
Data
Set
Ready
(DSR)
Bit 5
Bit 5
Bit 13
6
Data Bit 6
Data Bit 6
0
FIFOs
Enabled
(see
Note 4)
Receiver
Trigger
(LSB)
Break
Control
0
Transmitter
Empty
(TEMT)
Ring
Indicator
(RI)
Bit 6
Bit 6
Bit 14
7
Data Bit 7
Data Bit 7
0
FIFOs
Enabled
(see
Note 4)
Receiver
Trigger
(MSB)
Divisor
Latch
Access
Bit
(DLAB)
0
Error in
RCVR
FIFO
(see
Note 4)
Data
Carrier
Detect
(DCD)
Bit 7
Bit 7
Bit 15
† Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
NOTE 4: These bits are always 0 in the TL16C450 mode.
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TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
FIFO control register (FCR)
The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables
the FIFOs, clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling.
Bit 0: FCR0, when set, enables the transmit and receive FIFOs. This bit must be set when other FCR bits are
written to or they are not programmed. Changing this bit clears the FIFOs.
D
D
D
D
D
Bit 1: FCR1, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not
cleared. The one that is written to this bit position is self clearing.
Bit 2: FCR2, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not
cleared. The one that is written to this bit position is self clearing.
Bit 3: When FCR0 is set, setting FCR3 causes the RXRDY and TXRDY to change from mode 0 to
mode 1.
Bits 4 and 5: FCR4 and FCR5 are reserved for future use.
Bits 6 and 7: FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt (see Table 4).
Table 4. Receiver FIFO Trigger Level
RECEIVER FIFO
TRIGGER LEVEL (BYTES)
BIT 7
BIT 6
0
0
01
0
1
04
1
0
08
1
1
14
FIFO interrupt mode operation
When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1) receiver interrupt occur as
follows:
1. The receive data available interrupt is issued to the microprocessor when the FIFO has reached its
programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level.
2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the
interrupt, it is cleared when the FIFO drops below the trigger level.
3. The receiver line status interrupt (IIR = 0110) has higher priority than the received data available
interrupt (IIR = 0100).
4. The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver
FIFO. It is cleared when the FIFO is empty.
22
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TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
When the receiver FIFO and receiver interrupts are enabled, receiver FIFO timeout interrupt occurs as follows:
1. FIFO timeout interrupt occurs when the following conditions exist:
a. At least one character is in the FIFO.
b. The most recent serial character received is longer than four continuous character times ago (when
two stop bits are programmed, the second one is included in this time delay).
c.
The most recent microprocessor read of the FIFO is longer than four continuous character times
ago. This causes a maximum character received to interrupt an issued delay of 160 ms at
300 baud with a 12-bit character.
2. Character times are calculated by using the RCLK input for a clock signal (makes the delay proportional
to the baud rate).
3. When a timeout interrupt has occurred, it is cleared and the timer is reset when the microprocessor
reads one character from the receiver FIFO.
4. When a timeout interrupt has not occurred, the timeout timer is reset after a new character is received or
after the microprocessor reads the receiver FIFO.
When the transmit FIFO and transmitter interrupts are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur
as follows:
1. The transmitter holding register interrupt (02) occurs when the transmit FIFO is empty. It is cleared as
soon as the THR is written to (1 to 16 characters may be written to the transmit FIFO while servicing this
interrupt) or the IIR is read.
2. The transmit FIFO empty indications are delayed one character time minus the last stop bit time when
the following occurs: THRE = 1 and there have not been at least two bytes at the same time in the
transmit FIFO since the last THRE = 1. The first transmitter interrupt after changing FCR0 is immediate
when it is enabled.
Character timeout and receiver FIFO trigger level interrupts have the same priority as the current received data
available interrupt; transmit FIFO empty has the same priority as the current THRE interrupt.
FIFO polled mode operation
When FCR0 is set, clearing IER0, IER1, IER2, IER3, or all four puts the ACE in the FIFO polled mode of
operation. Since the receiver and transmitter are controlled separately, either one or both can be in the polled
mode of operation.
In this mode, the user program checks receiver and transmitter status via the LSR. As stated previously:
•
•
•
•
•
LSR0 is set as long as there is one byte in the receiver FIFO.
LSR1 – LSR4 specify which error(s) have occurred. Character error status is handled the same way as
when in the interrupt mode; the IIR is not affected since IER2 = 0.
LSR5 indicates when the transmit FIFO is empty.
LSR6 indicates that both the transmit FIFO and shift registers are empty.
LSR7 indicates whether there are any errors in the receiver FIFO.
There is no trigger level reached or timeout condition indicated in the FIFO polled mode. However, the receiver
and transmit FIFOs are still fully capable of holding characters.
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TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
interrupt enable register (IER)
The IER enables each of the five types of interrupts (refer to Table 5) and the INTRPT output signal in response
to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The
contents of this register are summarized in Table3 and are described in the following bulleted list.
D
D
D
D
D
Bit 0: This bit when set enables the received data available interrupt.
Bit 1: This bit when set enables the THRE interrupt.
Bit 2: This bit when set enables the receiver line status interrupt.
Bit 3: This bit when set enables the modem status interrupt.
Bits 4 – 7: These bits in the IER are not used and are always cleared.
interrupt identification register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
most popular microprocessors. The ACE provides four prioritized levels of interrupts which are:
D
D
D
D
Priority 1 – Receiver line status (highest priority)
Priority 2 – Receiver data ready or receiver character timeout
Priority 3 – Transmitter holding register empty
Priority 4 – Modem status (lowest priority)
When an interrupt is generated, the IIR indicates that an interrupt is pending and the type of that interrupt in its
three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and described
in Table 4. Detail on each bit are as follows:
D
D
D
D
D
24
Bit 0: This bit can be used either in a hardwire prioritized or polled interrupt system. When this bit is cleared,
an interrupt is pending. When bit 0 is set, no interrupt is pending.
Bits 1 and 2: These two bits identify the highest priority interrupt pending, as indicated in Table 5.
Bit 3. This bit is always cleared in the TL16C450 mode. In FIFO mode, this bit is set with bit 2 to indicate
that a timeout interrupt is pending.
Bits 4 – 5: These two bits are not used and are always cleared.
Bits 6 and 7: These two bits are always cleared in the TL16C450 mode. They are set when bit 0 of the FIFO
control register is set.
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PRINCIPLES OF OPERATION
interrupt identification register (IIR) (continued)
Table 5. Interrupt Control Functions
INTERRUPT
IDENTIFICATION
REGISTER
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
1
PRIORITY
LEVEL
INTERRUPT TYPE
None
None
INTERRUPT SOURCE
INTERRUPT RESET
METHOD
None
None
0
1
1
0
1
Receiver line status
Overrun error, parity error,
framing error or break interrupt
0
1
0
0
2
Received data available
Receiver data available in the
TL16C450 mode or trigger level
reached in the FIFO mode.
Reading the receiver buffer
register
Reading the receiver buffer
register
Reading the line status register
1
1
0
0
2
Character timeout
indication
No characters have been
removed from or input to the
receiver FIFO during the last
four character times, and there
is at least one character in it
during this time
0
0
1
0
3
Transmitter holding
register empty
Transmitter holding register–
empty
Reading the interrupt
identification register (if source
of interrupt) or writing into the
transmitter holding register
0
0
0
0
4
Modem status
Clear to send, data set ready,
ring indicator, or data carrier
detect
Reading the modem status
register
line control register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 3 and are described in the following bulleted list.
D
Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.
These bits are encoded in Table 6.
Table 6. Serial Character Word Length
D
BIT 1
BIT 0
WORD LENGTH
0
0
5 bits
0
1
6 bits
1
0
7 bits
1
1
8 bits
Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When
bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated
is dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit,
regardless of the number of stop bits selected. The number of stop bits generated, in relation to word length
and bit 2, is shown in Table 7.
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TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
line control register (LCR) (continued)
Table 7. Number of Stop Bits Generated
D
D
D
D
D
BIT 2
WORD LENGTH SELECTED
BY BITS 1 AND 2
NUMBER OF STOP
BITS GENERATED
0
Any word length
1
1
5 bits
1 1/2
1
6 bits
2
1
7 bits
2
1
8 bits
2
Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between
the last data word bit and the first stop bit. In received data, when bit 3 is set, parity is checked. When
bit 3 is cleared, no parity is generated or checked.
Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity
(an even number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is
cleared, odd parity (an odd number of logic 1s) is selected.
Bit 5: This is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as
cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set. When
bit 5 is cleared, stick parity is disabled.
Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where SOUT
is forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled and has no
affect on the transmitter logic; it only effects the serial output.
Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the
baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver
buffer, the THR, or the IER.
line status register (LSR)†
The LSR provides information to the CPU concerning the status of data transfers. The contents of this register
are summarized in Table 3 and are described in the following bulleted list.
D
D
Bit 0: This bit is the data ready (DR) indicator for the receiver. Bit 0 is set whenever a complete incoming
character has been received and transferred into the RBR or the FIFO. Bit 0 is cleared by reading all of the
data in the RBR or the FIFO.
Bit 1‡: This bit is the overrun error (OE) indicator. When bit 1 is set, it indicates that before the character
in the RBR is read, it is overwritten by the next character transferred into the register. The OE indicator is
cleared every time the CPU reads the contents of the LSR. If the FIFO mode data continues to fill the FIFO
beyond the trigger level, an overrun error occurs only after the FIFO is full and the next character has been
completely received in the shift register. An OE is indicated to the CPU as soon as it happens. The character
in the shift register is overwritten, but it is not transferred to the FIFO.
† The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.
‡ Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.
26
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PRINCIPLES OF OPERATION
line status register (LSR) (continued)†
D
Bit 2‡: This bit is the parity error (PE) indicator. When bit 2 is set, it indicates that the parity of the received
data character does not match the parity selected in the LCR (bit 4). The PE bit is cleared every time the
CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character
in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top
of the FIFO.
D
Bit 3‡: This bit is the framing error (FE) indicator. When bit 3 is set, it indicates that the received character
did not have a valid (set) stop bit. The FE bit is cleared every time the CPU reads the contents of the LSR.
In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This
error is revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to
resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to the
next start bit. The ACE samples this start bit twice and then accepts the input data.
D
Bit 4‡: This bit is the break interrupt (BI) indicator. When bit 4 is set, it indicates that the received data input
was held cleared for longer than a full-word transmission time. A full-word transmission time is defined as
the total time of the start, data, parity, and stop bits. The BI bit is cleared every time the CPU reads the
contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to
which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO.
When a break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled
after SIN goes to the marking state and receives the next valid start bit.
D
D
D
Bit 5: This bit is the THRE indicator. Bit 5 is set when the THR is empty, indicating that the ACE is ready
to accept a new character. If the THRE interrupt is enabled when the THRE bit is set, an interrupt is
generated. THRE is set when the contents of the THR are transferred to the transmitted shift register. This
bit is cleared concurrent with the loading of the THR by the CPU. In the FIFO mode, this bit is set when the
transmit FIFO is empty; it is cleared when at least one byte is written to the transmit FIFO.
Bit 6: This bit is the transmitter empty (TEMT) indicator. Bit 6 is set when the THR and the TSR are both
empty. When either the THR or the TSR contains a data character, the TEMT bit is cleared. In the FIFO
mode, this bit is set when the transmitter FIFO and shift register are both empty.
Bit 7: In the TL16C550B and the TL16C550BI mode, this bit is always cleared. In the TL16C450 mode, this
bit is always cleared. In the FIFO mode, LSR7 is set when there is at least one parity, framing, or break error
in the FIFO. It is cleared when the microprocessor reads the LSR and there are no subsequent errors in
the FIFO.
modem control register (MCR)
The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is
emulating a modem. The contents of this register are summarized in Table 3 and are described in the following
bulleted list.
D
D
D
Bit 0: This bit (DTR) controls the data terminal ready (DTR) output. Setting bit 0 forces the DTR output to
its low state. When bit 0 is cleared, DTR goes high.
Bit 1: This bit (RTS) controls the request to send (RTS) output in a manner identical to bit 0’s control over
the DTR output.
Bit 2: This bit (OUT1) controls the output 1 (OUT1) signal, a user-designated output signal, in a manner
identical to bit 0’s control over the DTR output.
† The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.
‡ Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.
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PRINCIPLES OF OPERATION
modem control register (MCR) (continued)
D
D
Bit 3: This bit (OUT2) controls the output 2 (OUT2) signal, a user-designated output signal, in a manner
identical to bit 0’s control over the DTR output.
Bit 4: This bit provides a local loop back feature for diagnostic testing of the ACE. When this bit is set, the
following occurs:
–
The SOUT is set high.
–
The SIN is disconnected.
–
The output of the TSR is looped back into the receiver shift register input.
–
The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected.
–
The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four
modem control inputs.
–
The four modem control outputs are forced to their inactive (high) states.
In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify
the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational.
The modem control interrupts are also operational, but the modem control interrupt’s sources are now the
lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the
IER.
D
Bits 5 – 7: These bits are permanently cleared.
modem status register (MSR)
The MSR is an 8-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change
information; when a control input from the modem changes state, the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are
described in the following bulleted list.
D
D
D
D
D
D
28
Bit 0: This bit is the change in clear-to-send (∆ CTS) indicator. Bit 0 indicates that the CTS input has
changed states since the last time it was read by the CPU . When this bit is set and the modem status
interrupt is enabled, a modem status interrupt is generated.
Bit 1: This bit is the change in data set ready (∆ DSR) indicator. Bit 1 indicates that the DSR input has
changed states since the last time it was read by the CPU. When this bit is set and the modem status
interrupt is enabled, a modem status interrupt is generated.
Bit 2: This bit is the trailing edge of the ring indicator (TERI) detector. Bit 2 indicates that the RI input to the
chip has changed from a low to a high state. When this bit is set and the modem status interrupt is enabled,
a modem status interrupt is generated.
Bit 3: This bit is the change in data carrier detect (∆ DCD) indicator. Bit 3 indicates that the DCD input to
the chip has changed states since the last time it was read by the CPU. When this bit is set and the modem
status interrupt is enabled, a modem status interrupt is generated.
Bit 4: This bit is the complement of the clear-to-send (CTS) input. When bit 4 (loop) of the MCR is set,
bit 4 is equivalent to the MCR bit 1 (RTS).
Bit 5: This bit is the complement of the data set ready (DSR) input. When bit 4 (loop) of the MCR is set,
bit 5 is equivalent to the MCR bit 1 (DTR).
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ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
modem status register (MSR) (continued)
D
D
Bit 6: This bit is the complement of the ring indicator (RI) input. When bit 4 (loop) of the MCR is set, bit 6
is equivalent to the MCRs bit 2 (OUT1).
Bit 7: This bit is the complement of the data carrier detect (DCD) input. When bit 4 (loop) of the MCR is set,
bit 7 is equivalent to the MCRs bit 3 (OUT2).
programmable baud generator
The ACE contains a programmable baud generator that takes a clock input in the range between dc and 8 MHz
and divides it by a divisor in the range between 1 and (216 –1). The output frequency of the baud generator is
16 × the baud rate. The formula for the divisor is:
divisor # = XIN frequency input ÷ (desired baud rate × 16)
Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either
of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Tables 8 and 9 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072 MHz
respectively. For baud rates of 38.4 kbit/s and below, the error obtained is very small. The accuracy of the
selected baud rate is dependent on the selected crystal frequency. Refer to Figure 16 for examples of typical
clock circuits.
Table 8. Baud Rates Using a 1.8432-MHz Crystal
DESIRED
BAUD RATE
DIVISOR USED
TO GENERATE
16 × CLOCK
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
50
2304
75
1536
110
1047
0.026
134.5
857
0.058
150
768
300
384
600
192
1200
96
1800
64
2000
58
2400
48
3600
32
4800
24
7200
16
9600
12
19200
6
38400
3
56000
2
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TL16C550B, TL16C550BI
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SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
programmable baud generator (continued)
Table 9. Baud Rates Using a 3.072-MHz Crystal
DESIRED
BAUD RATE
DIVISOR USED
TO GENERATE
16 × CLOCK
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
50
3840
75
2560
110
1745
0.026
134.5
1428
0.034
150
1280
300
640
600
320
1200
160
1800
107
2000
96
2400
80
3600
53
4800
40
7200
27
9600
20
19200
10
38400
5
0.312
0.628
1.23
VCC
VCC
Driver
XIN
XIN
External
Clock
C1
Crystal
RP
Optional
Driver
Optional
Clock
Output
RX2
Oscillator Clock
to Baud Generator
Logic
XOUT
Oscillator Clock
to Baud Generator
Logic
XOUT
C2
TYPICAL CRYSTAL OSCILLATOR NETWORK
CRYSTAL
RP
1 MΩ
RX2
C1
C2
3.1 MHz
1.5 kΩ
10-30 pF
40-60 pF
1.8 MHz
1 MΩ
1.5 kΩ
10-30 pF
40-60 pF
Figure 16. Typical Clock Circuits
30
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ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
PRINCIPLES OF OPERATION
receiver buffer register (RBR)
The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte
FIFO. Timing is supplied by the 16 × receiver clock (RCLK). Receiver section control is a function of the ACE
line control register.
The ACE RSR receives serial data from the SIN terminal. The RSR then deserializes the data and moves it into
the RBR FIFO. In the TL16C450 mode, when a character is placed in the receiver buffer register and the
received data available interrupt is enabled, an interrupt is generated. This interrupt is cleared when the data
is read out of the RBR. In the FIFO mode, the interrupts are generated based on the control setup in the FIFO
control register.
scratch register
The scratch register is an 8-bit register that is intended for programmer use as a scratchpad in the sense that
it temporarily holds the programmer’s data without affecting any other ACE operation.
transmitter holding register (THR)
The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a
16-byte FIFO. Timing is supplied by the baud out (BAUDOUT) clock signal. Transmitter section control is a
function of the ACE’s line control register.
The ACE THR receives data off the internal data bus and when the shift register is idle, moves it into the TSR.
The TSR serializes the data and outputs it at the SOUT. In the TL16C450 mode, when the THR is empty and
the transmitter holding register empty (THRE) interrupt is enabled, an interrupt is generated. This interrupt is
cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated based on
the control setup in the FIFO control register.
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TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
MECHANICAL DATA
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
E
18
D2 / E2
E1
D2 / E2
14
8
0.021 (0,53)
0.013 (0,33)
0.007 (0,18) M
0.050 (1,27)
9
13
0.008 (0,20) NOM
D/E
D2 / E2
D1 / E1
NO. OF
PINS
**
MIN
MAX
MIN
MAX
MIN
MAX
20
0.385 (9,78)
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.169 (4,29)
28
0.485 (12,32)
0.495 (12,57)
0.450 (11,43)
0.456 (11,58)
0.191 (4,85)
0.219 (5,56)
44
0.685 (17,40)
0.695 (17,65)
0.650 (16,51)
0.656 (16,66)
0.291 (7,39)
0.319 (8,10)
52
0.785 (19,94)
0.795 (20,19)
0.750 (19,05)
0.756 (19,20)
0.341 (8,66)
0.369 (9,37)
68
0.985 (25,02)
0.995 (25,27)
0.950 (24,13)
0.958 (24,33)
0.441 (11,20)
0.469 (11,91)
84
1.185 (30,10)
1.195 (30,35)
1.150 (29,21)
1.158 (29,41)
0.541 (13,74)
0.569 (14,45)
4040005 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
32
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MECHANICAL DATA
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PIN SHOWN
A
24
13
0.560 (14,22)
0.520 (13,21)
1
12
0.060 (1,52) TYP
0.200 (5,08) MAX
0.610 (15,49)
0.590 (14,99)
0.020 (0,51) MIN
Seating Plane
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.125 (3,18) MIN
0.010 (0,25) M
PINS **
0°– 15°
0.010 (0,25) NOM
24
28
32
40
48
52
A MAX
1.270
(32,26)
1.450
(36,83)
1.650
(41,91)
2.090
(53,09)
2.450
(62,23)
2.650
(67,31)
A MIN
1.230
(31,24)
1.410
(35,81)
1.610
(40,89)
2.040
(51,82)
2.390
(60,71)
2.590
(65,79)
DIM
4040053 / B 04/95
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Falls within JEDEC MS-011
Falls within JEDEC MS-015 (32 pin only)
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TL16C550B, TL16C550BI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136B – JANUARY 1994 – REVISED AUGUST 1996
MECHANICAL DATA
PT (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
1,45
1,35
Seating Plane
1,60 MAX
0°– 7°
0,75
0,45
0,10
4040052 / B 03/95
NOTES: A.
B.
C.
D.
34
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MO-136
This may also be a thermally-enhanced plastic package with leads connected to the die pads.
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