Ordering number : ENA0599 Monolithic Linear IC LA6560 For CD Five-Channel Driver (BTL : Four-Channel, H Bridge : One-Channel) Overview The LA6560 is a 5-channel driver (BTL : 4-channel, H bridge : 1-channel) for CD players. Functions • Power amplifier 5-channel built-in. (Bridge-connection (BTL) : 4-channel, H bridge : 1-channel) • IO max 1A • Level shift circuit built-in (except H bridge). • Mute circuit (output ON/OFF) built-in. (Operable with BTL AMP and not operable for the H bridge of 5VREG) • 5V regulator built-in (external PNP transistor). • With VREF changeover function (H : external, L : internal (2.5V) selected) • Overheat protection circuit (thermal shutdown) built-in. Specifications Maximum Ratings at Ta = 25°C Parameter Supply voltage Symbol Conditions Ratings VCC max Allowable power dissipation Pd max Maximum output current IO max Maximum input voltage VINB MUTE pin voltage Unit 14 V Independent IC 2.0 W Mounted on specified board. * 0.8 W Each output for H bridge, channel 1 to 4. A 13 V 13 V Operating temperature Topr -30 to +85 °C Storage temperature Tstg -55 to +150 °C * Specified board size : VMUTE 1 76.1×114.3×1.6mm3, glass epoxy. Recommended Operating Conditions at Ta = 25°C Parameter Supply voltage Symbol VCC Conditions Ratings Unit 5.6 to 13 V Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. D0606 MS PC B8-6307 No.A0599-1/9 LA6560 Electrical Characteristics at Ta = 25°C, VCC1 = VCC2 = 8V, VREF = 2.5V, unless especially specified. Parameter Symbol Ratings Conditions min typ Unit max ALL Blocks No-load current drain ON ICC-ON BTL-AMP output ON, 30 50 mA 10 15 mA 175 200 °C 10 mV LOADING block OFF *1 No-load current drain OFF ICC-OFF Thermal shutdown temperature TSD All outputs OFF *1 Design guarantee value 150 VREF AMP VREF-AMP offset voltage -10 VREF-OFFSET VREF Input voltage range VREF-IN VREF-OUT output current I-VREF-OUT 1 CH1 input reference voltage 2 VCC-1.5 5 V 6.6 mA 50 mV VCC-1.5 mA BTL AMP Block (CH1 to CH4) Output offset voltage VOFF Voltage difference between outputs for BTL -50 AMP, each channel. *2 Input voltage range VIN Input voltage range for input for OP-AMP. 0 Output voltage VO Each voltage between V0+ and V0- when 5.7 6.2 3.6 4 V RL = 8Ω. *3 Closed-circuit voltage gain VG Input and output gain. 4.4 Times Input OP-AMP:BUFFER Slew rate SR AMP Independent 0.5 V/μs Multiply 2 between outputs. MUTE ON voltage VMUTE-ON Output ON voltage, each MUTE *4 MUTE OFF voltage VMUTE-OFF Output OFF voltage, each MUTE *4 2 V 0.5 V Input AMP Block (CH1 to 4) Input voltage range Output current (SINK) Output current (SOURCE) VIN-OP 0 SINK-OP 2 SOURCE-OP *5 VOFF-OP CH1 input changeover voltage 1 VSW-OP1 CH1 input AMP(B), external REF select *6 VSW-OP2 CH1 input AMP(A), internal VREF select *6 V mA μA 500 -10 Output offset voltage CH1 input changeover voltage 2 300 VCC-1.5 10 mV 0.5 V 2 V Loading Block (CH5, H bridge) Output voltage VO-LOAD At forward and reverse rotation, 5.7 6.5 V RL = 8Ω, VCONT=VCC *3 Break output saturation voltage VCE-BREAK Input low level Output voltage at braking *7 VIN-L VIN-H Input high level 0.3 V 1 V 2 V Power Supply Block (PNP transistor : 2SB632K-use) 5V supply voltage REG-IN SINK current VOUT REG-IN-SINK IO = 200mA 4.8 Base current of external PNP *8 5 5.0 5.2 V 10 mA Line regulation ΔVOLN 6V ≤ VCC ≤ 12V, IO = 200mA 10 100 mV Load regulation ΔVOLD 5mA ≤ IO ≤ 200mA 10 100 mV Note *1 : Current dissipation that is a sum of VCC1 and VCC2 at no load. *2 : Input AMP is a BUFFER AMP. *3 : Voltage difference between both ends of load (8Ω). Output saturated. *4 : Output ON with MUTE : [H] and OFF with MUTE : [L] (HI impedance). *5 : The source of input OP-AMP is a constant current. As the 11kΩ resistance to the next stage is a load, pay due attention when setting the input OP-AMP gain. *6 : With VIN1-SW : [L], the input AMP selects AMP-A while VREF selects internal VREF (≈ 2.5V). With VIN1-SW : [H], the input AMP selects AMP-B while VREF selects external VREF (≈ VREF-IN). *7 : Short (GND) brake used. SINK side output ON. *8 : 5VREG incorporates a drooping protection circuit and operated when the base current is 10mA (TYP). No.A0599-2/9 LA6560 Package Dimensions unit : mm (typ) 3251 17.8 (6.2) 19 0.65 (4.9) 7.9 10.5 36 18 0.3 0.25 2.7 2.45max 2.0 (2.25) 0.8 0.1 1 SANYO : HSOP36R(375mil) Pd max -- Ta 2.5 Allowable power dissipation, Pd max – W (0.5) 2 Specified board : 76.1×114.3×1.6mm3 glass epoxy When mounted on a board 1.5 1 0.8 1.04 Independent IC 0.5 0 --30 --20 0.42 0 20 40 60 80 100 Ambient temperature, Ta – °C No.A0599-3/9 LA6560 Block Diagram VCC2 3 VLO- 4 VLO+ 5 VO4+ 6 VO4- 7 VO3+ 8 VO3- 9 (LOAD output voltage setting) BTL-AMP Output ON/OFF Output control 2 MUTE 22kΩ 11kΩ Level shift REV Signal system GND Thermal shutdown Level shift 1 Input FWD VIN1/VREF-SW 36 S-GND 35 VCONT 34 MUTE 33 VIN4 32 VIN4- 31 VIN4+ 30 VREF-IN 29 VIN1(VREF)-SW 28 VREF-OUT(CH1) Power system GND Power system GND FR FR FR FR Level shift 5VREG (Extemal PNP) VO2+ 10 VO2- 11 Level shift VO1+ 12 VO1- 13 22kΩ 11kΩ VCC1 14 27 REG-OUT 26 REG-IN 25 VIN3+ 24 VIN3- 23 VIN3 22 VIN2+ 21 VIN2- 20 VIN2 19 VIN1+B 22kΩ 11kΩ 22kΩ VIN1 15 11kΩ VIN1-A 16 AMP-A [L] [H] VIN1 (VREF)-SW [L]:Internal VREF (2.5V fixed) [H]:Internal VREF VIN1+A 17 VIN1-B 18 AMP-B VIN1 (VREF)-SW [L]:AMP-A [H]:AMP-B No.A0599-4/9 LA6560 Pin Functions Pin No. Symbol 1 FWD Output change pin (FWD) for 5CH (VLO), logic input for loading block. Pin descriptions 2 REV Output change pin (REV) for 5CH (VLO), logic input for loading block. 3 VCC2 Power supply for CH3, 4, and 5. 4 VLO- Loading output (-) 5 VLO+ Loading output (+) 6 VO4+ Output pin (+) for channel 4 7 VO4- Output pin (-) for channel 4 8 VO3+ Output pin (+) for channel 3 Output pin (-) for channel 3 9 VO3- 10 VO2+ Output pin (+) for channel 2 11 VO2- Output pin (-) for channel 2 12 VO1+ Output pin (+) for channel 1 13 VO1- Output pin (-) for channel 1 14 VCC1 Power supply for CH1, 2 (BTL). 15 VIN1 Input pin for channel 1 16 VIN1-A 17 VIN1+A OP-AMP input AMP-A input pin (-) OP-AMP input AMP-A input pin (+) 18 VIN1-B Input AMP-B input pin (-) for channel 1 19 VIN1+B 20 VIN2 Input pin for channel 2, input AMP output 21 VIN2- Input pin (-) for channel 2 22 VIN2+ Input pin (+) for channel 2 23 VIN3 Input pin for channel 3, input AMP output 24 VIN3- Input pin (-) for channel 3 25 VIN3+ Input pin (+) for channel 3 26 REG-IN 27 REG-OUT Input AMP-B input pin (+) for channel 1 PNP transistor base connected 5V power output to which the PNP transistor collector connected. 28 VREF-OUT 29 VIN1 (VREF) -SW CH1 reference voltage output. Outputs internal VREF (2.5V : TYP) or external VREF. 30 VREF-IN 31 VIN4+ 32 VIN4- Input pin (-) for channel 4 33 VIN4 Input pin for channel 4, input AMP output 34 MUTE All BTL AMP output ON/OFF 35 VCONT LOADING output voltage setting 36 S-GND Signal system GND Pin for changeover between input AMP-A/internal VREF (TYP2.5V) and input AMP-B/ external VREF. Reference voltage applied pin Input pin (+) for channel 4 Note : Center frame (FR) becomes GND for the power system (P-GND). Set this to the minimum potential together with S-GND. No.A0599-5/9 LA6560 Pin Description Pin No. 17 19 16 18 15 22 21 20 25 24 23 32 Symbol VIN1+A VIN1+B Pin function Input Description Input pin (CH1 to 4) (CH1 to 4) VIN1-A VIN1-B VIN*- VCC VIN1 VIN2+ VIN* VIN*+ VIN2VIN2 VIN3+ VIN3- S-GND VIN3 VIN4- 33 VIN4+ VIN4 1 FWD Input Logic input pin. 2 REV (H bridge) By combining H and L 31 Equivalent circuit of this pin, any one of four modes (forward/ reversed/brake/idling) can be selected. FWD REV 50kΩ 50kΩ 50kΩ 50kΩ S-GND 12 13 10 11 VO1+ VO1- Output Output for channel (BTL-AMP) 1 to 4. VCC* VO2+ VO2VO3+ VO3- VO* VO4+ VO4- RF* 7 4 VLO- Output H bridge (LOADING) 5 VLO+ (H bridge) output and LOADING 8 9 6 35 VCONT output setting pin VLO+ VLO- VCC P-GND 20kΩ 1kΩ 34 MUTE MUTE BTL AMP output, which turns ON/OFF the 1kΩ 20kΩ VCONT VCC1 output, MUTE : H Output OFF MUTE : L Output OFF MUTE 100kΩ 100kΩ S-GND No.A0599-6/9 LA6560 Truth Table (loading (H bridge) section) FWD L H *1 *2 REV VLO+ VLO- Loading output L OFF OFF OFF *1 H H L Forward L L H Reversed H L L (Short) brake *2 The output has a high impedance. At brake, the SINK side transistor is ON (short brake). VLO+ and VLO- are approximately on the GND level. Relation of MUTE and Power (VCC*) CH1(BTL) VCC1 CH2(BTL) MUTE CH3(BTL) CH4(BTL) VCC2 CH5 (H bridge) VIN1 (VREF)-SW (CH1 input AMP selection and internal/external VREF selection function) (Relation between input AMP (CH1 only) and VREF) VIN1_SW Input AMP (CH1) state VREF state H VIN1-A (AMP-A) Internal VREF (2.5V : TYP) L VIN1-B (AMP-B) External VREF Internal reference voltage (2.5V (TYP)) External reference voltage VIN1-A VIN1-B VREF (VIN1)-SW 0.5V 2V On MUTE MUTE BTLAMP output VREF-OUT L OFF H ON VREF-OUT operates in an interlock with MUTE. No.A0599-7/9 LA6560 Sample Application Circuit SW MUTE 1 FWD S-GND 36 2 REV VCONT 35 3 VCC2 4 VLO- VIN4 33 5 VLO+ VIN4- 32 6 VO4+ VIN4+ 31 7 VO4- VREF-IN 30 8 VO3+ VIN1(VREF)-SW 29 9 VO3- VREF-OUT(CH1) 28 LOADING ELEVETOR 0.1μF LOADING MOTOR MUTE 34 M 2.2Ω 0.1μF TRACKING COIL 2.2Ω 0.1μF FOCUS COIL 2.2Ω FR FR 0.1μF SPINDLE MOTOR 0.1μF REG-OUT 27 11 VO2- REG-IN 26 12 VO1+ VIN3+ 25 13 VO1- VIN3- 24 14 VCC1 VIN3 23 15 VIN1 VIN2+ 22 16 VIN1-A VIN2- 21 17 VIN1+A VIN2 20 18 VIN1-B VIN1+B 19 5VREG VCC M 2.2Ω VCC 10 VO2+ M 2.2Ω SLED MOTOR FR FR TRACKING FOCUS SPINDLE SLED VREF No.A0599-8/9 LA6560 Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 2006. Specifications and information herein are subject to change without notice. PS No.A0599-9/9