Ordering number : ENA1153 CMOS IC LV5124T 2-Cell Lithium-Ion Secondary Battery Protection IC Overview The LV5124T is a protection IC for 2-cell lithium-ion secondary batteries. Features • Monitoring function for each cell: Detects overcharge and over-discharge conditions and controls the charging and discharging operation of each cell. • High detection voltage accuracy: Over-charge detection accuracy ±25mV Over-discharge detection accuracy ±100mV • Hysteresis cancel function: The hysteresis of over-discharge detection voltage is made small by sensing the connection of a load after overcharging has been detected. • Discharge current monitoring function: Detects over-currents and load shorting, and an excessive discharge current is controlled. • Latch function after detecting over-current (Release is made by connecting the charger) • Low current consumption: Normal operation mode typ. 6.0µA Stand by mode max. 0.2µA • 0V cell charging function: Charging is enabled even when the cell voltage is 0V by giving a potential difference between the VDD pin and V- pin. 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To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 52808 MS 20080312-S00003 No.A1153-1/8 LV5124T Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Power supply voltage Input voltage Charger minus voltage Output voltage Cout pin voltage Dout pin voltage Allowable power dissipation Symbol Conditions Ratings VDD Unit -0.3 to +12 V V- VDD-28 to VDD+0.3 V Vcout VDD-28 to VDD+0.3 V Vdout Pd max VSS-0.3 to VDD+0.3 Independent IC 170 V mW Operating ambient temperature Topr -30 to +85 °C Storage temperature Tstg -40 to +125 °C Electrical Characteristics at Ta = 25°C, unless especially specified. Parameter Symbol Conditions Operation input voltage Vcell Between VDD and VSS 0V cell charging minimum operation Vmin Between VDD-VSS =0 and VDD-V- Ratings min typ Unit max 1.5 10 V 1.5 V voltage Over-charge detection voltage Vd1 Over-charge release voltage Vr1 4.325 4.350 4.375 V V- ≤ Vd3 4.100 4.150 4.200 V V- > Vd3 4.250 4.360 V Over-charge detection delay time td1 VDD-Vc=3.5V→4.5V, Vc-VSS=3.5V 0.5 1.0 1.5 s Over-charge release delay time tr1 VDD-Vc=4.5V→3.5V, Vc-VSS=3.5V 20.0 40.0 60.0 ms Over-discharge detection voltage Vd2 2.20 2.30 2.40 V Over-discharge release Vh2 10.0 20.0 40.0 mV hysteresis voltage Over-discharge detection delay time td2 VDD-Vc=3.5V→2.2V, Vc-VSS=3.5V 50 100 150 ms Over-discharge release delay time tr2 VDD-Vc=2.2V→3.5V, Vc-VSS=3.5V 0.5 1.0 1.5 ms Over-current detection voltage Vd3 VDD-Vc=3.5V, Vc-VSS=3.5V 0.18 0.20 0.22 V Over-current release Vh3 VDD-Vc=3.5V, Vc-VSS=3.5V 5.0 10.0 20.0 mV hysteresis voltage Over-current detection delay time td3 VDD-Vc=3.5V, Vc-VSS=3.5V 2.5 5.0 7.5 ms Over-current release delay time tr3 VDD-Vc=3.5V, Vc-VSS=3.5V 0.5 1.0 1.5 ms Vd4 VDD-Vc=3.5V, Vc-VSS=3.5V 1.0 1.3 1.6 V ms Short circuit detection voltage Short circuit detection delay time td4 VDD-Vc=3.5V, Vc-VSS=3.5V 0.2 0.5 0.8 Standby release voltage Vstb VDD-Vc=2.0V, Vc-VSS=2.0V (V-)-VSS VDD×0.4 VDD×0.5 VDD×0.6 Internal resistance (connect to VDD) RDD 100 200 400 kΩ Internal resistance (connect to VSS) RSS 0.5 1.0 1.5 MΩ Cout Nch ON voltage VOL1 IOL=50µA, VDD-Vc=4.4V, Vc-VSS=4.4V Cout Pch ON voltage VOH1 IOL=50µA, VDD-Vc=3.9V, Vc-VSS=3.9V Dout Nch ON voltage VOL2 IOL=50µA, VDD-Vc=Vd2(min), 0.5 VDD-0.5 V V V 0.5 V Vc-VSS=Vd2(min) Dout Pch ON voltage VOH2 IOL=50µA, VDD-Vc=3.9V, Vc-VSS=3.9V VDD-0.5 V Vc input current Ivc VDD-Vc=3.5V, Vc-VSS=3.5V 0.0 1.0 µA Current consumption IDD VDD-Vc=3.5V, Vc-VSS=3.5V 6.0 13.0 µA Standby current Istb VDD-Vc=2.2V, Vc-VSS=3.5V 0.2 µA Vtest VDD-Vc=3.5V, Vc-VSS=3.5V VDD×0.6 V T-terminal input ON voltage VDD×0.4 VDD×0.5 No.A1153-2/8 LV5124T Package Dimensions unit : mm (typ) 3245B Pd max -- Ta Allowable power dissipation, Pd max -- mW 200 3.0 0.5 3.0 4.9 8 1 (0.53) 2 0.65 0.125 1.1MAX (0.85) 0.25 Independent IC 170 150 100 68 50 0 -30 -20 0 20 40 60 80 100 0.08 Ambient temperature, Ta -- °C SANYO : MSOP8(150mil) Pin Assignment Dout T 8 7 1 2 VDD Cout Vc Sense 6 5 3 V- 4 Top view VSS Pin Functions Pin No. 1 Symbol VDD Description VDD pin 2 Cout Overcharge detection output pin 3 V- Charger minus voltage input pin 4 VSS VSS pin 5 Sense Sense pin 6 Vc Intermediate voltage input pin 7 T Pin to shorten detection time(“H”: Shortening mode, “L”: Normal mode) 8 Dout Overdischarge detection output pin No.A1153-3/8 LV5124T Block Diagram Sence 5 VDD 1 + + - Vc 6 2 Cout td1,tr1 Delay conrol logic + - td2,tr2 8 Dout + + - td3,tr3 + - 4 VSS 3 V- td4 7 T No.A1153-4/8 LV5124T Functional Description Over-charge detection If either of the cell voltage is equal to or more than the over-charge detection voltage, stop further charging by turning “L” the Cout pin and turning off external Nch MOS FET after the over-charge detection delay time. This delay time is set by the internal counter. The over-charge detection comparator has the hysteresis function. Note that this hysteresis can be cancelled by connecting the load after detection of over-charge detection. and it becomes small to hysteresis peculiar to a comparator. Once over-charge detection is made, over-current detection is not made to prevent incorrect operations. Note that short-circuit can be detected. Over-charge release If both cell voltages become equal to or less than the over-charge release voltage (VM ≤ Vd3) when charger is connected, or if it become equal to or less than the over-charge release voltage (VM > Vd3) when load is connected, the Cout pin returns to “H” after the over-charge release delay time set by the internal counter. When load is connected and either cell or both cell voltages are equal to or more than the over-charge release voltage (VM > Vd3), the Cout pin does not return to “H”. But the load current flows through the parasitic diode of external Nch MOS FET on Cout, consequently each cell voltage becomes equal to or less than over-charge release voltage (VM > Vd3), the Cout pin returns to “H” after the over-charge release delay time. Over-discharge detection When either cell voltage is equal to or less than over-discharge voltage, the IC stops further discharging by turning the Dout pin “L” and turning off external Nch MOS FET after the over-charge detection delay time. The IC goes into stand-by mode after detecting over-discharge and its consumption current is kept at about 0A. After over-discharge detection, the V- pin will be connected to VDD pin via internal resistor (typ 200kΩ). Over-discharge release Release from over-discharge is made by only connecting charger. If the V- pin voltage becomes equal to or lower than the stand-by release voltage by connecting charger after detecting over-discharge, The IC is released from the stand-by state to start cell voltage monitoring. If both cell voltages become equal to or more than the over-discharge detection voltage by charging, the Dout pin returns to “H” after the over-discharge release delay time set by the internal counter. Over-current detection When excessive current flows through the battery, the V- pin voltage rises by the ON resister of external MOS FET and becomes equal to or more than the over-current detection voltage, the Dout pin turns to “L” after the over-current detection delay time and the external Nch MOS FET is turned off to prevent excessive current in the circuit. The detection delay time is set by the internal counter. After detection, the V- pin will be connected to VSS via internal resistor (typ 1MΩ). It will not go into stand-by mode after detecting over-current. Short circuit detection If greater discharging current flows through the battery and the V- pin voltage becomes equal to or more than the short-circuit detection voltage, it will go into short-circuit detection state after the short circuit delay time shorter than the over-current detection delay time. When short-circuit is detected, just like the time of over-current detection, the Dout pin turns to “L” and external Nch MOS FET is turned off to prevent high current in the circuit. The V- pin will be connected to VSS after detection via internal resistor (typ 1MΩ). It will not go into stand-by mode after detecting short circuit. Over-current/short-detection release After detecting over-current or short circuit, the internal resistor (typ.1MΩ) between V- pin and VSS pin becomes effective. In this case, the V-pin voltage will be more than over-current detection voltage because of the relation between internal resister and the internal impedance of V- pin. Therefore, if the load resister is removed after detecting over-current or short circuit, the detection state will be kept. Release from over-current or short circuit is only made by connecting a charger to make the V- pins lower than over-current detection voltage and the Dout pin returns to “H after over-current release delay time set by the internal counter. No.A1153-5/8 LV5124T 0V cell charging operation If voltage between VDD and V becomes equal to or more than the 0V cell charging lowest operation voltage when the cell voltage is 0V, the Cout pin turns to “H” and charging is enabled. Shorten the test time By turning T pin to the VDD , the delay times set by the internal counter can be cut. If T pin is open, the delay times are normal. Delay time not set by the counter just like as short circuit detection delay cannot be controlled by this pin And we recommend that T pin is connected to Vss to prevent malfunction when excessive current flows in short circuit operation. Operation in case of detection overlap Operation in case of detection overlap Overlap state State after detection During over-charge Over-discharge Over-charge detection is prioritized. If over- When over-charge state is made first, V- is detection, detection is made, discharge state continues even after over- released. When over-discharge is detected charge detection, over-discharge detection is after over-charge state is made, the IC does not resumed. go into the stand-by mode. Note that V- is connected to VDD via 200kΩ. Over-current (*1) Both detections can be made in parallel. (*2) When over-current state is made first, V- is detection is made, Over-charge detection continues even when the connected to VSS via 1MΩ. When over-charge over-current state is made first. If the over- state is made first, V- is released. charge state is made first, over-current detection is interrupted. During over-discharge Over-charge detection Over-discharge detection is interrupted and The IC does not go into the stand-by mode detection, is made, over-charge detection is prioritized. When over- when over-discharge state is made after over- discharge state continues even after over- charge detection. Note that V- is connected to charge state is made, over-discharge detection VDD via 200kΩ. is resumed. Over-current (*3) Both detections can be made in parallel. (*4) If over-current state is made first, V- will be detection is made, Over-discharge detection continues even when connected to VSS via 1MΩ. If over-discharge the over-current state is made first. But over- detection is made next, V- also will be current detection is interrupted when the over- connected to VDD via 200kΩ to get into stand- discharge state is made first, by mode. If over-discharge state is made first, Vwill be connected to VDD via 200kΩ to get into During over-current detection, Over-charge detection is made, Over-discharge detection is made, (*1) stand-by mode. (*2) (*3) (*4) (Note) Short-circuit detection can be made independently. No.A1153-6/8 LV5124T Timing Chart [Cout Output System] Hysteresis cancellation by load connection Charger connection Load connection Charger connection Load connection Charger connection Vd1 Vr1 VDD Vd2 VDD Discharging via FETparasite Di Vd4 V- Vd3 VSS Vd5 VDD td1 Cout tr1 td1 tr1 VOver-charge detection state Over-charge detection state [Dout Output System] Load connection Charger connection Load connection Charger Load connection connection Over-current occurrence Charger connection Load connection Load short-circuit occurrence Vd1 Vr1 VDD Vd2 To standby To standby VDD Vd4 V- Vd3 VSS Vd5 Charging via FETparasite Di Charging via FETparasite Di VDD Dout td2 tr2 td3 tr3 td4 tr3 td2 VSS Over-discharge detection state Over-current detection state Short-circuit detection state Charge return Charge return VDD Cout V- No.A1153-7/8 LV5124T Application Circuit Example + R4 R1 C1 VDD Sense C3 T R2 Vc C2 VSS LV5124T V- VSS Dout Cout R3 − Components Recommended value max unit R1, R2 100 1k Ω R3 2k 4k Ω R4 100 10k Ω C1, C2, C3 0.1µ 1µ F * These numbers don't mean to guarantee the characteristic of the IC. * In addition to the components in the upper diagram, it is necessary to insert a capacitor with enough capacity between VDD and VSS of the IC as near as possible to stabilize the power supply voltage to the IC. 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of May, 2008. Specifications and information herein are subject to change without notice. PS No.A1153-8/8