STMICROELECTRONICS M48T59

M48T59
M48T59Y, M48T59V
5.0 or 3.3 V, 64 Kbit (8 Kbit x 8) TIMEKEEPER® SRAM
Not For New Design
Features
■
Integrated ultra low power SRAM, real-time
clock, power-fail control circuit, and battery
■
Frequency test output for real-time clock
software calibration
■
Automatic power-fail chip deselect and WRITE
protection
■
WRITE protect voltages
(VPFD = Power-fail deselect voltage):
– M48T59: VCC = 4.75 to 5.5 V
4.5 V ≤ VPFD ≤ 4.75 V
– M48T59Y: VCC = 4.5 to 5.5 V
4.2 V ≤ VPFD ≤ 4.5 V
– M48T59V(a): VCC = 3.0 to 3.6 V
2.7 V ≤ VPFD ≤ 3.0 V
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PCDIP28 (PC)
battery/crystal
CAPHAT
■
Self-contained battery and crystal in the
CAPHAT™ DIP package
■
Packaging includes a 28-lead SOIC and
SNAPHAT® top (to be ordered separately)
■
SOIC package provides direct connection for a
SNAPHAT top which contains the battery and
crystal
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SNAPHAT (SH)
battery/crystal
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Microprocessor power-on reset (valid even
during battery back-up mode)
■
Programmable alarm output active in the
battery back-up mode
■
Battery low flag
■
RoHS compliant
– Lead-free second level interconnect
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SOH28 (MH)
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a. Contact local ST sales office for availability of 3.3 V
version.
April 2008
Rev 7
This is information on a product still in production but not recommended for new designs.
1/32
www.st.com
1
Contents
M48T59, M48T59Y, M48T59V
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
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2.2
Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4
Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5
Setting the alarm clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8
Programmable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9
Battery low flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10
Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11
Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.12
VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 19
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Maximum ratings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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olePackage mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5
8
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
6
2.1
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
M48T59, M48T59Y, M48T59V
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Alarm repeat mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PCDIP28 – 28-pin plastic DIP, battery CAPHAT, package mechanical data . . . . . . . . . . . 25
SOH28 – 28-lead plastic small outline, battery SNAPHAT, pack. mech. data . . . . . . . . . . 26
SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package mech. data. . . . . . . 27
SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package mech. data. . . . . . 28
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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List of figures
M48T59, M48T59Y, M48T59V
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
28-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PCDIP28 CAPHAT connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Read mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write enable controlled, write mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip enable controlled, write mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Back-up mode alarm waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PCDIP28 – 28-pin plastic DIP, battery CAPHAT, package outline . . . . . . . . . . . . . . . . . . . 25
SOH28 – 28-lead plastic small outline, battery SNAPHAT, package outline . . . . . . . . . . . 26
SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline . . . . . . . . . . 27
SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline . . . . . . . . . 28
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M48T59, M48T59Y, M48T59V
1
Description
Description
The M48T59/Y/V TIMEKEEPER® RAM is an 8 Kb x 8 non-volatile static RAM and real-time
clock. The monolithic chip is available in two special packages to provide a highly integrated
battery backed-up memory and real-time clock solution.
The M48T59/Y/V is a non-volatile pin and function equivalent to any JEDEC standard 8 Kb
x8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the
non-volatility of PROMs without any requirement for special write timing or limitations on the
number of writes that can be performed.
The 28-pin, 600 mil DIP CAPHAT™ houses the M48T59/Y/V silicon with a quartz crystal
and a long life lithium button cell in a single package.
The 28-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct
connection to a separate SNAPHAT® housing containing the battery and crystal. The
unique design allows the SNAPHAT battery package to be mounted on top of the SOIC
package after the completion of the surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery and crystal damage due to the high
temperatures required for device surface-mounting. The SNAPHAT housing is keyed to
prevent reverse insertion.
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The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or
in Tape & Reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT)
part number is “M4T28-BR12SH1” or “M4T32-BR12SHx” (see Table 19 on page 30).
Caution:
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Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the
lithium button-cell battery.
Figure 1.
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Logic diagram
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VCC
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8
A0-A12
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DQ0-DQ7
M48T59
M48T59Y
M48T59V
IRQ/FT
RST
G
VSS
AI01380E
5/32
Description
M48T59, M48T59Y, M48T59V
Table 1.
Signal names
A0-A12
Address inputs
DQ0-DQ7
Data inputs / outputs
IRQ/FT
Interrupt / frequency test output (open drain)
RST
Reset output (open drain)
E
Chip enable
G
Output enable
W
Write enable
VCC
Supply voltage
VSS
Ground
Figure 2.
28-pin SOIC connections
RST
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
Figure 3.
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AI01382E
RST
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7
M48T59 22
8 M48T59Y 21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
W
IRQ/FT
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
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AI01381D
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VCC
W
IRQ/FT
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
PCDIP28 CAPHAT connections
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1
2
27
3
26
4
25
5
24
6
23
7 M48T59Y 22
8 M48T59V 21
9
20
10
19
11
18
12
17
13
16
14
15
M48T59, M48T59Y, M48T59V
Figure 4.
Description
Block diagram
IRQ/FT
OSCILLATOR AND
CLOCK CHAIN
16 x 8 BiPORT
SRAM ARRAY
32,768 Hz
CRYSTAL
A0-A12
POWER
DQ0-DQ7
8176 x 8
SRAM ARRAY
LITHIUM
CELL
E
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
W
VPFD
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AI01383D
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Operation modes
2
M48T59, M48T59Y, M48T59V
Operation modes
As Figure 4 on page 7 shows, the static memory array and the quartz-controlled clock
oscillator of the M48T59/Y/V are integrated on one silicon chip.
The two circuits are interconnected at the upper eight memory locations to provide user
accessible BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh. The
clock locations contain the century, year, month, date, day, hour, minute, and second in 24
hour BCD format (except for the century). Corrections for 28, 29 (leap year - valid until
2100), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control
register. This byte controls user access to the clock information and also stores the clock
calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory
locations consisting of BiPORT™ READ/WRITE memory cells. The M48T59/Y/V includes a
clock control circuit which updates the clock bytes with current information once per second.
The information can be accessed by the user in the same manner as any other location in
the static memory array.
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The M48T59/Y/V also has its own Power-fail Detect circuit. The control circuitry constantly
monitors the single 5V/3.3 V supply for an out of tolerance condition. When VCC is out of
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low VCC. As VCC falls below the
Battery Back-up Switchover Voltage (VSO), the control circuitry connects the battery which
maintains data and clock operation until valid power returns.
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Table 2.
Operating modes
Mode
Deselect
WRITE
READ
4.75 to 5.5 V
or
4.5 to 5.5 V
or
3.0 to 3.6 V
VIH
VSO to VPFD (min)(1)(1)
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Deselect
E
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READ
Deselect
VCC
≤ VSO(1)
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W
DQ7-DQ0
Power
X
X
High Z
Standby
-O
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
X
X
X
High Z
CMOS standby
X
X
X
High Z
Battery back-up
mode
VIL
1. See Table 13 on page 24 for details.
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X = VIH or VIL; VSO = Battery back-up switchover voltage.
Read mode
The M48T59/Y/V is in the READ Mode whenever W (WRITE Enable) is high and E (Chip
Enable) is low. The unique address specified by the 13 address inputs defines which one of
the 8,192 bytes of data is to be accessed. Valid data will be available at the Data I/O pins
within Address Access time (tAVQV) after the last address input signal is stable, providing
that the E and G access times are also satisfied. If the E and G access times are not met,
valid data will be available after the latter of the Chip Enable Access time (tELQV) or Output
Enable Access time (tGLQV).
M48T59, M48T59Y, M48T59V
Operation modes
The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are
activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If
the Address Inputs are changed while E and G remain active, output data will remain valid
for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
Figure 5.
Read mode AC waveforms
tAVAV
A0-A12
VALID
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
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tGLQX
DQ0-DQ7
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VALID
AI01385
Note:
WRITE enable (W) = High.
Table 3.
Read mode AC characteristics
Parameter(1)
Symbol
tAVAV
READ cycle time
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M48T59/Y/V
–70
Min
Unit
Max
70
ns
tAVQV(2)
Address valid to output valid
70
ns
tELQV(2)
Chip enable low to output valid
70
ns
tGLQV(2)
Output enable low to output valid
35
ns
tELQX(3)
tGLQX(3)
tEHQZ(3)
tGHQZ(3)
tAXQX(2)
Chip enable low to output transition
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Output enable low to output transition
5
ns
5
ns
Chip enable high to output Hi-Z
25
ns
Output enable high to output Hi-Z
25
ns
Address transition to output transition
10
ns
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V, 4.75 to 5.5 V, or 3.0 to 3.6 V (except where
noted).
2. CL = 100pF (see Figure 13 on page 22).
3. CL = 5pF (see Figure 13 on page 22).
9/32
Operation modes
2.2
M48T59, M48T59Y, M48T59V
Write mode
The M48T59/Y/V is in the WRITE Mode whenever W and E are low. The start of a WRITE is
referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable
prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to
the end of WRITE and remain valid for tWHDX afterward. G should be kept high during
WRITE cycles to avoid bus contention; however, if the output bus has been activated by a
low on E and G a low on W will disable the outputs tWLQZ after W falls.
Figure 6.
Write enable controlled, write mode AC waveforms
tAVAV
A0-A12
VALID
tAVWH
tWHAX
tAVEL
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tWLWH
tAVWL
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W
tWLQZ
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tWHDX
DATA INPUT
DQ0-DQ7
Figure 7.
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tDVWH
AI01386
Chip enable controlled, write mode AC waveforms
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A0-A12
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tWHQX
tAVAV
VALID
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01387B
10/32
M48T59, M48T59Y, M48T59V
Table 4.
Operation modes
Write mode AC characteristics
M48T59/Y/V
Symbol
Parameter(1)
–70
Min
Unit
Max
tAVAV
WRITE cycle time
70
ns
tAVWL
Address valid to WRITE enable low
0
ns
tAVEL
Address valid to chip enable low
0
ns
tWLWH
WRITE enable pulse width
50
ns
tELEH
Chip enable low to chip enable high
55
ns
tWHAX
WRITE enable high to address transition
0
ns
tEHAX
Chip enable high to address transition
0
ns
tDVWH
Input valid to WRITE enable high
30
ns
tDVEH
Input valid to chip enable high
30
ns
tWHDX
WRITE enable high to input transition
5
tEHDX
Chip enable high to input transition
5
tWLQZ(2)(3)
25
Address valid to WRITE enable high
60
tAVEH
Address valid to chip enable high
60
tWHQX(2)(3)
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WRITE enable low to output Hi-Z
tAVWH
WRITE enable high to output transition
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ns
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5
ns
ns
ns
ns
ns
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V, 4.75 to 5.5 V, or 3.0 to 3.6 V
(except where noted).
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2. CL = 5pF (see Figure 13 on page 22).
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
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Data retention mode )
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With valid VCC applied, the M48T59/Y/V operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs
become high impedance, and all inputs are treated as “don't care.”
Note:
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A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
user can be assured the memory will be in a write protected state, provided the VCC fall time
is not less than tF. The M48T59/Y/V may respond to transient noise spikes on VCC that
reach into the deselect window during the time the device is sampling VCC. Therefore,
decoupling of the power supply lines is recommended.
When VCC drops below VSO, the control circuit switches power to the internal battery which
preserves data and powers the clock. The internal button cell will maintain data in the
M48T59/Y/V for an accumulated period of at least 7 years when VCC is less than VSO. As
system power returns and VCC rises above VSO, the battery is disconnected and the power
supply is switched to external VCC. Deselect continues for trec after VCC reaches VPFD
(max).
For more information on Battery Storage Life refer to the Application Note AN1012.
11/32
Clock operations
M48T59, M48T59Y, M48T59V
3
Clock operations
3.1
Reading the clock
Updates to the TIMEKEEPER® registers should be halted before clock data is read to
prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are
only data registers and not the actual clock counters, so updating the registers can be halted
without disturbing the clock itself.
Updating is halted when a '1' is written to the READ Bit, D6 in the Control register (1FF8h).
As long as a '1' remains in that position, updating is halted. After a halt is issued, the
registers reflect the count; that is, the day, date, and the time that were current at the
moment the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an
update in progress. Updating is within a second after the bit is reset to a '0.'
3.2
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Setting the clock
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Bit D7 of the Control register (1FF8h) is the WRITE Bit. Setting the WRITE Bit to a '1,' like
the READ Bit, halts updates to the TIMEKEEPER registers. The user can then load them
with the correct day, date, and time data in 24 hour BCD format (see Table 5 on page 13).
Resetting the WRITE Bit to a '0' then transfers the values of all time registers (1FF9h1FFFh) to the actual TIMEKEEPER counters and allows normal operation to resume. After
the WRITE Bit is reset, the next clock update will occur within approximately one second.
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See the Application Note AN923, “TIMEKEEPER Rolling Into the 21st Century” for
information on Century Rollover.
Note:
Upon power-up following a power failure, both the WRITE Bit and the READ Bit will be reset
to '0.'
3.3
Stopping and starting the oscillator
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The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The STOP Bit is the MSB of the seconds register. Setting it to a '1' stops the
oscillator. The M48T59/Y/V in the DIP package is shipped from STMicroelectronics with the
STOP Bit set to a '1.' When reset to a '0,' the M48T59/Y/V oscillator starts within one
second.
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Note:
12/32
It is not necessary to set the WRITE Bit when setting or resetting the FREQUENCY TEST
Bit (FT), the STOP Bit (ST) or the CENTURY ENABLE Bit (CEB).
M48T59, M48T59Y, M48T59V
Table 5.
Clock operations
Register map
Data
Function/range
BCD format
Address
D7
D6
1FFFh
D5
D4
D3
D2
10 Years
10 M
D1
D0
Year
Year
00-99
Month
Month
01-12
Date
Date
01-31
Century/day
00-01/01-07
Hours
Hours
00-23
Minutes
Minutes
00-59
Seconds
Seconds
00-59
1FFEh
0
0
0
1FFDh
0
0
10 date
1FFCh
0
FT
1FFBh
0
0
1FFAh
0
1FF9h
ST
1FF8h
W
1FF7h
WDS
1FF6h
AFE
Y
ABE
1FF5h
RPT4
Y
Al. 10 date
Alarm date
Alarm date
1FF4h
RPT3
Y
Al. 10 hours
Alarm hours
Alarm hours
CEB
CB
0
Day
10 hours
10 minutes
10 seconds
R
S
Calibration
Control
BMB BMB BMB BMB BMB
RB1 RB0
4
3
2
1
0
Y
Y
Y
Y
Y
Watchdog
Interrupts
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1FF3h
RPT2
Alarm 10 minutes
Alarm minutes
Alarm minutes
1FF2h
RPT1
Alarm 10 seconds
Alarm seconds
Alarm seconds
1FF1h
Y
Y
Y
Y
Y
Y
Y
Y
Unused
1FF0h
WDF
AF
Z
BL
Z
Z
Z
Z
Flags
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Keys:
S = Sign bit
FT = Frequency test bit
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00-23
00-59
00-59
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R = Read bit
W = Write bit
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ST = Stop bit
0 = Must be set to '0'
Y = '1' or '0'
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Z = '0' and are read only
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AF = Alarm flag (read only)
BL = Battery low (read only)
WDS = Watchdog steering bit
BMB0-BMB4 = Watchdog multiplier bits
RB0-RB1 = Watchdog resolution bits
AFE = Alarm flag enable
ABE = Alarm in battery back-up mode enable
RPT1-RPT4 = Alarm repeat mode bits
WDF = Watchdog flag (read only)
CEB = Century enable bit
CB = Century bit
13/32
Clock operations
3.4
M48T59, M48T59Y, M48T59V
Calibrating the clock
The M48T59/Y/V is driven by a quartz-controlled oscillator with a nominal frequency of
32,768 Hz. The devices are tested not to exceed 35 PPM (parts per million) oscillator
frequency error at 25°C, which equates to about ±1.53 minutes per month. With the
calibration bits properly set, the accuracy of each M48T59/Y/V improves to better than +1/–
2 PPM at 25°C.
The oscillation rate of any crystal changes with temperature (see Figure 8 on page 15).
Most clock chips compensate for crystal frequency and temperature shift error with
cumbersome “trim” capacitors. The M48T59/Y/V design, however, employs periodic counter
correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 9 on page 15. The number of times pulses
are blanked (subtracted, negative calibration) or split (added, positive calibration) depends
upon the value loaded into the five-bit Calibration byte found in the Control Register. Adding
counts speeds the clock up, subtracting counts slows the clock down.
The Calibration Byte occupies the five lower order bits (D4-D0) in the Control register
(1FF8h). These bits can be set to represent any value between 0 and 31 in binary form. Bit
D5 is the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration.
Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per
minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a
binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be
modified; if a binary 6 is loaded, the first 12 will be affected, and so on.
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Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles; for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 PPM of
adjustment per calibration step in the calibration register. Assuming that the oscillator is in
fact running at exactly 32,768 Hz, each of the 31 increments in the Calibration Byte would
represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or
–2.75 minutes per month.
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Two methods are available for ascertaining how much calibration a given M48T59/Y/V may
require. The first involves simply setting the clock, letting it run for a month and comparing it
to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows
the designer to give the end user the ability to calibrate his clock as his environment may
require, even after the final product is packaged in a non-user serviceable enclosure. All the
designer has to do is provide a simple utility that accesses the Calibration Byte.
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The second approach is better suited to a manufacturing environment, and involves the use
of the IRQ/FT pin. The pin will toggle at 512 Hz when the Stop Bit (D7 of 1FF9h) is '0,' the
FT Bit (D6 of 1FFCh) is '1,' the AFE Bit (D7 of 1FF6h) is '0,' and the Watchdog Steering Bit
(D7 of 1FF7h) is '1' or the Watchdog Register is reset (1FF7h = 0).
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Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at
the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 PPM
oscillator frequency error, requiring a –10 (WR001010) to be loaded into the Calibration
Byte for correction. Note that setting or changing the Calibration Byte does not affect the
Frequency Test output frequency.
The IRQ/FT pin is an open drain output which requires a pull-up resistor for proper
operation. A 500 - 10 kΩ resistor is recommended in order to control the rise time. The FT
Bit is cleared on power-down.
For more information on calibration, see Application Note AN934, “TIMEKEEPER
Calibration.”
14/32
M48T59, M48T59Y, M48T59V
Figure 8.
Clock operations
Crystal accuracy across temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
–100
F
2
= -0.038 ppm
(T - T0) ± 10%
C2
T0 = 25 °C
–120
–140
)
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–160
–40
–30
–20
–10
0
10
20
30
40
50
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60
Temperature °C
70
80
AI00999
Figure 9.
Clock calibration
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NORMAL
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POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
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Pthe alarm clock
Setting
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3.5
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Note:
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AI00594B
Registers 1FF5h-1FF2h contain the alarm settings. The alarm can be configured to go off at
a prescribed time on a specific day of the month or repeat every month, day, hour, minute, or
second. It can also be programmed to go off while the M48T59/Y/V is in the battery back-up
mode of operation to serve as a system wake-up call.
Bits RPT1-RPT4 put the alarm in the repeat mode of operation. Table 6 on page 16 shows
the possible configurations. Codes not listed in the table default to the once per second
mode to quickly alert the user of an incorrect alarm setting.
User must transition address (or toggle chip enable) to see Flag Bit change.
When the clock information matches the alarm clock settings based on the match criteria
defined by RPT1-RPT4, AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set, the
15/32
Clock operations
M48T59, M48T59Y, M48T59V
alarm condition activates the IRQ/FT pin. To disable the alarm, write '0' to the Alarm Date
Register and RPT1-4. The Alarm Flag and the IRQ/FT output are cleared by a READ to the
Flags Register as shown in Figure 10 on page 16. A subsequent READ of the Flags
Register is necessary to see that the value of the Alarm Flag has been reset to '0.'
The IRQ/FT pin can also be activated in the battery back-up mode. The IRQ/FT will go low if
an alarm occurs and both the ABE (Alarm in Battery Back-up Mode Enable) and the AFE
are set. The ABE and AFE bits are reset during power-up, therefore an alarm generated
during power-up will only set AF. The user can read the Flag Register at system boot-up to
determine if an alarm was generated while the M48T59/Y/V was in the deselect mode
during power-down. Figure 11 on page 17 illustrates the back-up mode alarm timing.
Figure 10. Alarm interrupt reset waveform
15ns Min
A0-A12
ADDRESS 1FF0h
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ACTIVE FLAG BIT
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IRQ/FT
HIGH-Z
Table 6.
Alarm repeat mode
RPT4
RPT3
RPT2
1
1
1
1
1
1
1
1
1
0
0
0
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16/32
0
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RPT1
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AI01388B
Alarm activated
1
Once per second
0
Once per minute
0
Once per hour
0
0
Once per day
0
0
Once per month
M48T59, M48T59Y, M48T59V
Clock operations
Figure 11. Back-up mode alarm waveforms
trec
VCC
VPFD (max)
VPFD (min)
VSO
ABE, AFE bit in Interrupt Register
AF bit in Flags Register
IRQ/FT
HIGH-Z
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HIGH-Z
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AI03254B
3.6
Watchdog timer
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The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of time-out into the eight-bit
Watchdog Register (Address 1FF7h). The five bits (BMB4-BMB0) that store a binary
multiplier and the two lower order bits (RB1-RB0) select the resolution, where 00 = 1/16
second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is
then determined to be the multiplication of the five-bit multiplier value with the resolution.
(For example: writing 00001110 in the Watchdog Register = 3 x 1 or 3 seconds).
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Note:
Accuracy of timer is within ± the selected resolution.
If the processor does not reset the timer within the specified period, the M48T59/Y/V sets
the WDF (Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset.
WDF is reset by reading the Flags Register (Address 1FF0h).
Note:
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User must transition address (or toggle chip enable) to see Flag Bit change.
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The most significant bit of the Watchdog Register is the Watchdog Steering Bit. When set to
a '0,' the watchdog will activate the IRQ/FT pin when timed-out. When WDS is set to a '1,'
the watchdog will output a negative pulse on the RST pin for a duration of trec. The
Watchdog Register, the FT Bit, and the AFE and ABE Bits will reset to a '0' at the end of a
watchdog time-out when the WDS bit is set to a '1.'
The watchdog timer resets when the microprocessor performs a re-write of the Watchdog
Register. The time-out period then starts over. The watchdog timer is disabled by writing a
value of 00000000 to the eight bits in the Watchdog Register.
The watchdog function is automatically disabled upon power-down and the Watchdog
Register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the
frequency test function is activated, the watchdog or alarm function prevails and the
frequency test function is denied.
17/32
Clock operations
3.7
M48T59, M48T59Y, M48T59V
Power-on reset
The M48T59/Y/V continuously monitors VCC. When VCC falls to the power fail detect trip
point, the RST pulls low (open drain) and remains low on power-up for trec after VCC passes
VPFD (max). RST is valid for all VCC conditions. The RST pin is an open drain output and an
appropriate resistor to VCC should be chosen to control rise time.
3.8
Programmable interrupts
The M48T59/Y/V provides two programmable interrupts; an alarm and a watchdog. When
an interrupt condition occurs, the M48T59/Y/V sets the appropriate flag bit in the Flag
Register 1FF0h. The interrupt enable bits in (AFE and ABE) in 1FF6h and the Watchdog
Steering (WDS) Bit in 1FF7h allow the interrupt to activate the IRQ/FT pin.
The Alarm flag and the IRQ/FT output are cleared by a READ to the Flags Register. An
interrupt condition reset will not occur unless the addresses are stable at the flag location for
at least 15ns while the device is in the READ Mode as shown in Figure 10 on page 16.
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The IRQ/FT pin is an open drain output and requires a pull-up resistor (10 kΩ
recommended) to VCC. The pin remains in the high impedance state unless an interrupt
occurs or the Frequency Test Mode is enabled.
3.9
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Battery low flag
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The M48T59/Y/V automatically performs periodic battery voltage monitoring upon power-up
and at factory-programmed time intervals of 24 hours (at day rollover) as long as the device
is powered and the oscillator is running. The Battery Low Flag (BL), Bit D4 of the Flags
Register 1FF0h, will be asserted high if the internal or SNAPHAT® battery is found to be
less than approximately 2.5 V. The BL Flag will remain active until completion of battery
replacement and subsequent battery low monitoring tests, either during the next power-up
sequence or the next scheduled 24-hour interval.
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If a battery low is generated during a power-up sequence, this indicates that the battery
voltage is below 2.5 V (approximately), which may be insufficient to maintain data integrity.
Data should be considered suspect and verified as correct. A fresh battery should be
installed.
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Note:
Note:
18/32
If a battery low indication is generated during the 24-hour interval check, this indicates the
battery is near end of life. However, data has not been compromised due to the fact that a
nominal VCC is supplied. In order to insure data integrity during subsequent periods of
battery back-up mode, it is recommended that the battery be replaced. The SNAPHAT top
may be replaced while VCC is applied to the device.
This will cause the clock to lose time during the interval the battery/crystal is removed.
Battery monitoring is a useful technique only when performed periodically. The M48T59/Y/V
only monitors the battery when a nominal VCC is applied to the device. Thus applications
which require extensive durations in the battery back-up mode should be powered-up
periodically (at least once every few months) in order for this technique to be beneficial.
Additionally, if a battery low is indicated, data integrity should be verified upon power-up via
a checksum or other technique.
M48T59, M48T59Y, M48T59V
3.10
Clock operations
Century bit
Bit D5 and D4 of Clock Register 1FFCh contain the CENTURY ENABLE Bit (CEB) and the
CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or
from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle.
Note:
The WRITE Bit must be set in order to write to the CENTURY Bit.
3.11
Initial power-on defaults
Upon application of power to the device, the following register bits are set to a '0' state:
WDS; BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; FT (see Table 7).
Table 7.
Default values
Condition
W
R
FT
AFE
ABE
Initial power-up
(Battery attach for SNAPHAT)(2)
0
0
0
0
0
Subsequent power-up / RESET(3)
0
0
0
0
0
0
0
1
Power-down
(4)
1. WDS, BMB0-BMB4, RBO, RB1.
2. State of other control bits undefined.
3. State of other control bits remains unchanged.
Watchdog
register(1)
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1
0
0
0
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3.12
V noise and negative goingbtransients
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4. Assuming these bits set to '1' prior to power-down.
CC
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
Figure 12 on page 20) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, it is recommended to connect a
schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and MBRS120T3 is recommended for surface
mount.
19/32
Clock operations
M48T59, M48T59Y, M48T59V
Figure 12. Supply voltage protection
VCC
VCC
0.1μF
DEVICE
VSS
AI02169
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20/32
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M48T59, M48T59Y, M48T59V
4
Maximum ratings
Maximum ratings
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 8.
Absolute maximum ratings
Symbol
TA
TSTG
TSLD(1)(2)(3)
Parameter
Ambient operating temperature
Storage temperature (VCC off, oscillator off)
Lead solder temperature for 10 seconds
VIO
Input or output voltages
VCC
Supply voltage
IO
Output current
PD
Power dissipation
Value
Unit
0 to 70
°C
–40 to 85
°C
260
°C
–0.3 to 7
V
M48T59/M48T59Y
–0.3 to 7
M48T59V
–0.3 to 4.6
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20
1
V
mA
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1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to
exceed 150°C for longer than 30 seconds).
2. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget
not to exceed 180°C for between 90 to 150 seconds).
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3. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal
budget not to exceed 245°C for greater than 30 seconds).
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Caution:
Negative undershoots below –0.3 V are not allowed on any pin while in the Battery Back-up
mode.
Caution:
Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
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21/32
DC and AC parameters
5
M48T59, M48T59Y, M48T59V
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC Characteristic
tables are derived from tests performed under the Measurement Conditions listed in Table 9.
Designers should check that the operating conditions in their projects match the
measurement conditions when using the quoted parameters.
Table 9.
Operating and AC measurement conditions
Parameter
M48T59
M48T59Y
M48T59V
Unit
4.75 to 5.5
4.5 to 5.5
3.0 to 3.6
V
0 to 70
0 to 70
0 to 70
°C
Load capacitance (CL)
100
100
50
pF
Input rise and fall times
≤5
≤5
≤5
ns
0 to 3
0 to 3
0 to 3
V
1.5
1.5
1.5
Supply voltage (VCC)
Ambient operating temperature (TA)
Input pulse voltages
Input and output timing ref. voltages
Note:
Figure 13. AC measurement load circuit
l
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)
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t
c
u
d
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eP
645Ω
t
e
ol
P
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et
(1)
CL = 100pF
CL includes JIG capacitance
V
c
u
d
o
r
Output Hi-Z is defined as the point where data is no longer driven.
DEVICE
UNDER
TEST
)
s
t(
1.75V
AI02325
1. 50pF for M48T59V.
bs
Note:
O
Excluding open-drain output pins
Table 10.
Capacitance
Parameters(1)(2)
Symbol
CIN
CIO(3)
Min
Max
Unit
Input capacitance
10
pF
Input / output capacitance
10
pF
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.
2. At 25°C, f = 1 MHz.
3. Outputs deselected.
22/32
M48T59, M48T59Y, M48T59V
Table 11.
DC and AC parameters
DC characteristics
Symbol
M48T59/Y
Test condition(1)
Parameter
Unit
Min
ILO(2)
Output leakage current
ICC
Supply current
ICC1
Supply current (standby) TTL
ICC2
Supply current (standby) CMOS
VIL
Input low voltage
VIH
Input high voltage
Max
Min
Max
0V ≤ VIN ≤ VCC
±1
±1
µA
0V ≤ VOUT ≤ VCC
±1
±1
µA
Outputs open
50
30
mA
E = VIH
3
2
mA
E = VCC – 0.2 V
3
1
mA
Input leakage current
ILI
M48T59V
–0.3
0.8
–0.3
0.8
V
2.2
VCC + 0.3
2
VCC + 0.3
V
Output low voltage
IOL = 2.1 mA
0.4
0.4
V
VOL
Output low voltage (IRQ/FT and
RST)(3)
IOL = 10 mA
0.4
0.4
V
VOH
Output high voltage
IOH = –1 mA
2.4
2.4
V
)
s
t(
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V, 4.75 to 5.5 V, or 3.0 to 3.6 V (except where
noted).
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r
2. Outputs deselected.
3. The IRQ/FT and RST pins are open drain.
Figure 14. Power down/up mode AC waveforms
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VCC
VPFD (max)
VPFD (min)
O
)
VSO
tF
s
(
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c
u
d
tPD
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eP
RST
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ol
INPUTS
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bs
tFB
OUTPUTS
RECOGNIZED
P
e
et
tR
tRB
tDR
trec
DON'T CARE
RECOGNIZED
HIGH-Z
VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI03258
23/32
DC and AC parameters
Table 12.
M48T59, M48T59Y, M48T59V
Power down/up AC characteristics
Parameter(1)
Symbol
Min
tPD
E or W at VIH before power down
tF(2)
VPFD (max) to VPFD (min) VCC fall time
tFB(3)
Max
Unit
0
µs
300
µs
VPFD (min) to VSS VCC fall time
10
µs
tR
VPFD (min) to VPFD (max) VCC rise time
10
µs
tRB
VSS to VPFD (min) VCC rise time
1
trec
VPFD (max) to RST high
40
µs
200
ms
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V, 4.75 to 5.5 V, or 3.0 to 3.6 V
(except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring
until 200µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 13.
Power down/up trip points DC characteristics
Parameter(1)(2)
Symbol
Min
Typ
Max
M48T59
4.5
4.6
4.75
Power-fail deselect voltage
M48T59Y
4.2
4.35
4.5
M48T59V
2.7
2.9
3.0
VSO
Battery back-up switchover
voltage
M48T59/Y
tDR(3)
Expected data retention time
VPFD
VPFD –100mV
P
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et
7
)
s
t(
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3.0
M48T59V
Unit
V
V
V
V
V
YEARS
1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V, 4.75 to 5.5 V, or 3.0 to 3.6 V
(except where noted).
l
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2. All voltages referenced to VSS.
3. At 25°C, VCC = 0 V.
O
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24/32
M48T59, M48T59Y, M48T59V
6
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 15. PCDIP28 – 28-pin plastic DIP, battery CAPHAT, package outline
A2
A1
B1
B
A
L
C
e1
)
s
t(
eA
e3
c
u
d
o
r
D
N
E
1
Note:
l
o
bs
Drawing is not to scale.
Table 14.
P
e
et
PCDIP
O
)
PCDIP28 – 28-pin plastic DIP, battery CAPHAT, package mechanical data
t(s
mm
Symb
c
u
d
Typ
A
Typ
Min
Max
8.89
9.65
0.350
0.380
0.76
0.015
0.030
A2
8.38
8.89
0.330
0.350
B
0.38
0.53
0.015
0.021
B1
1.14
1.78
0.045
0.070
C
0.20
0.31
0.008
0.012
D
39.37
39.88
1.550
1.570
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eP
Ob
Max
0.38
A1
t
e
l
o
s
Min
inches
E
17.83
18.34
0.702
0.722
e1
2.29
2.79
0.090
0.110
e3
29.72
36.32
1.170
1.430
eA
15.24
16.00
0.600
0.630
L
3.05
3.81
0.120
0.150
N
28
28
25/32
Package mechanical data
M48T59, M48T59Y, M48T59V
Figure 16. SOH28 – 28-lead plastic small outline, battery SNAPHAT, package outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note:
)
s
t(
Drawing is not to scale.
Table 15.
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u
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r
SOH28 – 28-lead plastic small outline, battery SNAPHAT, pack. mech. data
mm
inches
Symb
Typ
Min
Max
A
3.05
0.05
0.36
A2
2.34
B
0.36
C
0.15
o
s
b
D
17.71
Max
0.120
0.002
0.014
0.092
0.106
0.51
0.014
0.020
0.32
0.006
0.012
18.49
0.697
0.728
8.89
0.324
0.350
–
–
2.69
-O
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
a
0°
8°
0°
8°
N
28
eB
o
r
eP
26/32
Min
)
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du
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Ob
eP
let
A1
E
t
e
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o
s
Typ
CP
8.23
1.27
–
–
0.050
3.20
3.61
0.126
0.142
28
0.10
0.004
M48T59, M48T59Y, M48T59V
Package mechanical data
Figure 17. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package
outline
A1
A2
A3
A
eA
B
L
eB
D
E
SHTK-A
Note:
)
s
t(
Drawing is not to scale.
Table 16.
c
u
d
o
r
SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package mech.
data
mm
Symb
Typ
Min
A
l
o
bs
9.78
A1
6.73
A2
6.48
A3
)
s
t(
c
du
B
7.24
-O
6.99
P
e
et
Typ
Min
Max
0.385
0.265
0.285
0.255
0.275
0.38
0.015
0.46
0.56
0.018
0.022
21.21
21.84
0.835
0.860
14.22
14.99
0.560
0.590
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
D
E
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eP
eA
t
e
ol
Max
inches
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b
O
27/32
Package mechanical data
M48T59, M48T59Y, M48T59V
Figure 18. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package
outline
A1
A2
A3
A
eA
B
L
eB
D
E
SHTK-A
Note:
)
s
t(
Drawing is not to scale.
Table 17.
c
u
d
o
r
SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package mech.
data
mm
Symb
Typ
Min
A
8.00
A2
7.24
B
E
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28/32
L
8.00
P
e
et
Typ
Min
Max
0.415
0.315
0.335
0.285
0.315
0.38
0.015
0.46
0.56
0.018
0.022
21.21
21.84
0.835
0.860
17.27
18.03
0.680
0.710
15.55
15.95
0.612
0.628
3.20
3.61
0.126
0.142
2.03
2.29
0.080
0.090
s
(
t
c
u
d
D
8.51
O
)
A3
eB
l
o
bs
10.54
A1
eA
Max
inches
M48T59, M48T59Y, M48T59V
7
Part numbering
Part numbering
Table 18.
Ordering information scheme
Example:
M48T
59Y
–70
MH
1
E
Device type
M48T
Supply voltage and write protect voltage
59(1) = VCC = 4.75 to 5.5 V; VPFD = 4.5 to 4.75 V
59Y = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V
59V(2) = VCC = 3.0 to 3.6 V; VPFD = 2.7 to 3.0 V
Speed
–70 = 70 ns
)
s
t(
Package
c
u
d
o
r
PC = PCDIP28
MH(3) = SOH28
Temperature range
1 = 0 to 70°C
l
o
bs
Shipping method
P
e
et
O
)
For SOH28:
E = Lead-free package (ECOPACK®), tubes
F = Lead-free package (ECOPACK®), tape & reel
s
(
t
c
u
d
For PCDIP28:
blank = tubes
o
r
eP
1. The M48T59 part is offered with the PCDIP28 (e.g., CAPHAT™) package only.
2. Contact local ST sales office for availability of 3.3 V version.
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ol
Caution:
3. The SOIC package (SOH28) requires the SNAPHAT® battery/crystal package which is ordered
separately under the part number “M4TXX-BR12SH” in plastic tube or “M4TXX-BR12SHTR” in
tape & reel form (see Table 19).
Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will
drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
29/32
Part numbering
M48T59, M48T59Y, M48T59V
Table 19.
SNAPHAT battery table
Part number
M4T28-BR12SH1
M4T32-BR12SHx
Description
Package
Lithium battery (48mAh) SNAPHAT
Lithium battery (120mAh) SNAPHAT
SH
SH
)
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30/32
P
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et
M48T59, M48T59Y, M48T59V
8
Revision history
Revision history
Table 20.
Document revision history
Date
Revision
Changes
Oct-1999
1.0
First Issue
22-Mar-2000
1.1
Century Bit Paragraph added; tFB value changed (Table 12)
13-Jul-2000
2.0
From Preliminary Data to Data Sheet
14-May-2001
3.0
Reformatted, Ind. Temp. added (Table 9), SNAPHAT table added
(Table 19), temp/voltage info. added to tables (Table 10, 11, 3, 4, 12,
13)
31-Jul-2001
3.1
Formatting changes from recent document review findings
06-Aug-2001
3.2
Fix text for Setting the Alarm Clock (Figure 10)
20-May-2002
3.3
Modify reflow time and temperature footnotes (Table 8)
07-Aug-2002
3.4
Add marketing status note (Table 18)
01-Apr-2003
4.0
v2.2 template applied; test condition updated (Table 13)
02-Apr-2004
5.0
Reformatted; update Lead-free package information (Table 8, 18)
25-Nov-2004
6.0
Remove all Industrial temperature references (Table 3, 4, 8, 9, 11, 12,
13, 18)
01-Apr-2008
7.0
Product status is “Not for New Design”; reformatted document; added
lead-free second level interconnect information to cover page and
Section 6: Package mechanical data; updated Table 11, 19.
)
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31/32
M48T59, M48T59Y, M48T59V
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)
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P
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eP
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
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32/32