STMICROELECTRONICS M48T129V

M48T129Y
M48T129V
5.0 or 3.3 V, 1 Mbit (128 Kbit x 8) TIMEKEEPER® SRAM
Features
■
Integrated, ultra low power SRAM, real-time
clock, power-fail control circuit, battery, and
crystal
■
BCD coded century, year, month, day, date,
hours, minutes, and seconds
■
Battery low warning flag
■
Automatic power-fail chip deselect and WRITE
protection
■
Two WRITE protect voltages:
(VPFD = power-fail deselect voltage)
– M48T129Y: VCC = 4.5 to 5.5 V
4.2 V ≤ VPFD ≤ 4.5 V
– M48T129V: VCC = 3.0 to 3.6 V
2.7 V ≤ VPFD ≤ 3.0 V
■
Conventional SRAM operation; unlimited
WRITE cycles
■
Software controlled clock calibration for high
accuracy applications
■
10 years of data retention and clock operation
in the absence of power
■
Self-contained battery and crystal in DIP
package
■
Microprocessor power-on reset
(valid even during battery backup mode)
■
Programmable alarm output active in battery
backup mode
■
RoHS compliant
– Lead-free second level interconnect
June 2010
32
1
Doc ID 5710 Rev 4
PMDIP32 module (PM)
1/28
www.st.com
1
Contents
M48T129V, M48T129Y
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
2.1
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
TIMEKEEPER® registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4
Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5
Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6
Setting the alarm clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9
Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10
Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11
VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 19
4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7
Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/28
Doc ID 5710 Rev 4
M48T129V, M48T129Y
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
TIMEKEEPER® register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Alarm repeat mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PMDIP32 – 32-pin plastic DIP module, package mechanical data. . . . . . . . . . . . . . . . . . . 24
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Doc ID 5710 Rev 4
3/28
List of figures
M48T129V, M48T129Y
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
4/28
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
32-pin module connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8
Address controlled, READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Backup mode alarm waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PMDIP32 – 32-pin plastic DIP module, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Doc ID 5710 Rev 4
M48T129V, M48T129Y
1
Description
Description
The M48T129Y/V TIMEKEEPER® RAM is a 128 Kb x 8 non-volatile static RAM and realtime clock with programmable alarms and a watchdog timer. The special DIP package
provides a fully integrated battery-backed memory and real-time clock solution. The
M48T129Y/V directly replaces industry standard 128 Kb x 8 SRAM. It also provides the nonvolatility of Flash without any requirement for special WRITE timing or limitations on the
number of WRITEs that can be performed.
The 32-pin, 600 mil DIP hybrid houses a controller chip, SRAM, quartz crystal, and a longlife lithium button cell in a single package.
Figure 1.
Logic diagram
VCC
17
8
A0-A16
W
DQ0-DQ7
M48T129Y
M48T129V
E
RST
IRQ/FT
G
VSS
Table 1.
AI02260
Signal names
A0-A16
DQ0-DQ7
Address inputs
Data Inputs / outputs
E
Chip enable input
G
Output enable input
W
WRITE enable input
RST
IRQ/FT
Reset output (open drain)
Interrupt / frequency test output (open drain)
VCC
Supply voltage
VSS
Ground
Doc ID 5710 Rev 4
5/28
Description
M48T129V, M48T129Y
Figure 2.
32-pin module connections
RST
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
Figure 3.
1
32
2
31
30
3
29
4
28
5
27
6
26
7
8 M48T129Y 25
9 M48T129V 24
23
10
22
11
21
12
20
13
19
14
18
15
17
16
VCC
A15
IRQ/FT
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI02261
Block diagram
16 x 8
TIMEKEEPER
REGISTERS
OSCILLATOR AND
CLOCK CHAIN
32,768 Hz
CRYSTAL
RST
IRQ/FT
POWER
A0-A16
131,056 x 8
SRAM ARRAY
LITHIUM
CELL
DQ0-DQ7
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
VCC
6/28
E
VPFD
Doc ID 5710 Rev 4
W
G
VSS
AI02583
M48T129V, M48T129Y
2
Operating modes
Operating modes
Figure 3 on page 6 illustrates the static memory array and the quartz controlled clock
oscillator. The clock locations contain the century, year, month, date, day, hour, minute, and
second in 24-hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and
31 day months are made automatically. The nine clock bytes (1FFFFh-1FFF9h and 1FFF1h)
are not the actual clock counters, they are memory locations consisting of BiPORT™
READ/WRITE memory cells within the static RAM array.
The M48T129Y/V includes a clock control circuit which updates the clock bytes with current
information once per second. The information can be accessed by the user in the same
manner as any other location in the static memory array. Byte 1FFF8h is the clock control
register. This byte controls user access to the clock information and also stores the clock
calibration setting.
Byte 1FFF7h contains the watchdog timer setting. The watchdog timer can generate either a
reset or an interrupt, depending on the state of the watchdog steering bit (WDS). Bytes
1FFF6h-1FFF2h include bits that, when programmed, provide for clock alarm functionality.
Alarms are activated when the register content matches the month, date, hours, minutes,
and seconds of the clock registers. Byte 1FFF1h contains century information. Byte 1FFF0h
contains additional flag information pertaining to the watchdog timer, the alarm condition
and the battery status. The M48T129Y/V also has its own power-fail detect circuit. This
control circuitry constantly monitors the supply voltage for an out of tolerance condition.
When VCC is out of tolerance, the circuit write protects the TIMEKEEPER® register data and
external SRAM, providing data security in the midst of unpredictable system operation. As
VCC falls below battery backup switchover voltage (VSO), the control circuitry automatically
switches to the battery, maintaining data and clock operation until valid power is restored.
Table 2.
Operating modes
Mode
VCC
Deselect
WRITE
READ
4.5 to 5.5V
or
3.0 to 3.6V
READ
Deselect
Deselect
VSO to VPFD
≤
(min)(1)
VSO(1)
E
G
W
DQ0DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
X
X
X
High Z
CMOS standby
X
X
X
High Z
Battery backup mode
1. See Table 12 on page 23 for details.
Note:
X = VIH or VIL; VSO = battery backup switchover voltage.
Doc ID 5710 Rev 4
7/28
Operating modes
2.1
M48T129V, M48T129Y
READ mode
The M48T129Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The unique address specified by the 17 address inputs defines which one of
the 131,072 bytes of data is to be accessed. Valid data will be available at the data I/O pins
within tAVQV (address access time) after the last address input signal is stable, providing the
E and G access times are also satisfied. If the E and G access times are not met, valid data
will be available after the latter of the chip enable access times (tELQV) or output enable
access time (tGLQV).
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are
activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If
the address inputs are changed while E and G remain active, output data will remain valid
for tAXQX (output data hold time) but will go indeterminate until the next address access.
Figure 4.
Chip enable or output enable controlled, READ mode AC waveforms
tAVAV
VALID
A0-A16
tAXQX
tAVQV
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DATA OUT
DQ0-DQ7
AI01197
Figure 5.
Address controlled, READ mode AC waveforms
tAVAV
VALID
A0-A16
tAVQV
tAXQX
DQ0-DQ7
DATA VALID
DATA VALID
AI02324
8/28
Doc ID 5710 Rev 4
M48T129V, M48T129Y
Operating modes
Table 3.
READ mode AC characteristics
M48T129Y
M48T129V
–70
–85
Parameter(1)
Symbol
Min
Max
70
Min
Unit
Max
tAVAV
READ cycle time
85
ns
tAVQV
Address valid to output valid
70
85
ns
tELQV
Chip enable low to output valid
70
85
ns
tGLQV
Output enable low to output valid
40
55
ns
tELQX(2)
Chip enable low to output transition
5
5
ns
tGLQX(2)
Output enable low to output
transition
5
5
ns
tEHQZ(2)
Chip enable high to output Hi-Z
25
30
ns
Output enable high to output Hi-Z
25
30
ns
tGHQZ
(2)
tAXQX
Address transition to output
transition
5
5
ns
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
2. CL = 5 pF.
Doc ID 5710 Rev 4
9/28
Operating modes
2.2
M48T129V, M48T129Y
WRITE mode
The M48T129Y/V is in the WRITE mode whenever W (WRITE enable) and E (chip enable)
are low state after the address inputs are stable.
The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE
is terminated by the earlier rising edge of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for a minimum of tEHAX from chip enable or
tWHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in
must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G
should be kept high during WRITE cycles to avoid bus contention; although, if the output bus
has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W
falls.
Figure 6.
WRITE enable controlled, WRITE AC waveforms
tAVAV
VALID
A0-A16
tAVWH
tAVEL
tWHAX
E
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI02382
Figure 7.
Chip enable controlled, WRITE AC waveforms
tAVAV
A0-A16
VALID
tAVEL
tELEH
tEHAX
E
tAVWL
W
tWHDX
DATA INPUT
DQ0-DQ7
tDVWH
AI02582
10/28
Doc ID 5710 Rev 4
M48T129V, M48T129Y
Table 4.
Symbol
Operating modes
WRITE mode AC characteristics
M48T129Y
M48T129V
–70
–85
Parameter(1)
Min
Max
Min
Unit
Max
tAVAV
WRITE cycle time
70
85
ns
tAVWL
Address valid to WRITE enable low
0
0
ns
tAVEL
Address valid to chip enable low
0
0
ns
tWLWH
WRITE enable pulse width
50
60
ns
tELEH
Chip enable low to chip enable high
55
65
ns
tWHAX
WRITE enable high to address transition
5
5
ns
tEHAX
Chip enable high to address transition
10
15
ns
tDVWH
Input valid to WRITE enable high
30
35
ns
tDVEH
Input valid to chip enable high
30
35
ns
tWHDX
WRITE enable high to input transition
5
5
ns
tEHDX
Chip enable high to input transition
10
tWLQZ(2)(3)
WRITE enable low to output Hi-Z
15
25
ns
30
ns
tAVWH
Address valid to WRITE enable high
60
70
ns
tAVEH
Address valid to chip enable high
60
70
ns
WRITE enable high to output transition
5
5
ns
tWHQX(2)(3)
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
2. CL = 5 pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid VCC applied, the M48T129Y/V operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically deselect, write protecting
itself when VCC falls between VPFD (max), VPFD (min) window. All outputs become high
impedance and all inputs are treated as “Don't care.”
Note:
A power failure during a WRITE cycle may corrupt data at the current addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
memory will be in a write protected state, provided the VCC fall time is not less than tF. The
M48T129Y/V may respond to transient noise spikes on VCC that cross into the deselect
window during the time the device is sampling VCC. Therefore, decoupling of the power
supply lines is recommended.
When VCC drops below VSO, the control circuit switches power to the internal battery,
preserving data and powering the clock. The internal energy source will maintain data in the
M48T129Y/V for an accumulated period of at least 10 years at room temperature. As
system power rises above VSO, the battery is disconnected, and the power supply is
switched to external VCC. Deselect continues for tREC after VCC reaches VPFD (max). For a
further more detailed review of lifetime calculations, please see application note AN1012.
Doc ID 5710 Rev 4
11/28
Clock operations
M48T129V, M48T129Y
3
Clock operations
3.1
TIMEKEEPER® registers
The M48T129Y/V offers 16 internal registers which contain TIMEKEEPER®, alarm,
watchdog, interrupt, flag, and control data. These registers are memory locations which
contain external (user accessible) and internal copies of the data (usually referred to as
BiPORT™ TIMEKEEPER cells). The external copies are independent of internal functions
except that they are updated periodically by the simultaneous transfer of the incremented
internal copy. TIMEKEEPER® and alarm registers store data in BCD.
3.2
Reading the clock
Updates to the TIMEKEEPER® registers should be halted before clock data is read to
prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are
only data registers and not the actual clock counters, so updating the registers can be halted
without disturbing the clock itself.
Updating is halted when a '1' is written to the READ bit, D6 in the control register (1FFF8h).
As long as a '1' remains in that position, updating is halted. After a halt is issued, the
registers reflect the count; that is, the day, date, and time that were current at the moment
the halt command was issued. All of the TIMEKEEPER® registers are updated
simultaneously. A halt will not interrupt an update in progress. Updating occurs 1 second
after the READ bit is reset to a '0.'
3.3
Setting the clock
Bit D7 of the control register (1FFF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like
the READ bit, halts updates to the TIMEKEEPER® registers. The user can then load them
with the correct day, date, and time data in 24-hour BCD format (see Table 5 on page 13).
Resetting the WRITE bit to a '0' then transfers the values of all time registers (1FFFFh1FFF9h, 1FFF1h) to the actual TIMEKEEPER® counters and allows normal operation to
resume. After the WRITE bit is reset, the next clock update will occur approximately one
second later.
Note:
Upon power-up following a power failure, both the WRITE bit and the READ bit will be reset
to '0.'
3.4
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The STOP bit is located at bit D7 within 1FFF9h. Setting it to a '1' stops the
oscillator. When reset to a '0', the M48T129Y/V oscillator starts within one second.
Note:
12/28
It is not necessary to set the WRITE bit when setting or resetting the FREQUENCY TEST
bit (FT) or the STOP bit (ST).
Doc ID 5710 Rev 4
M48T129V, M48T129Y
Table 5.
Clock operations
TIMEKEEPER® register map
Data
Function/range
Address
D7
D6
1FFFEh
0
0
1FFFDh
0
0
1FFFCh
0
FT
1FFFBh
0
0
1FFFAh
0
1FFF9h
ST
1FFF8h
W
1FFF7h
WDS
1FFF6h
AFE
0
1FFF5h
RPT4
RPT5
1FFF4h
RPT3
0
1FFF3h
RPT2
1FFF2h
RPT1
1FFFFh
D4
D3
D2
10 Years
D0
BCD format
Year
Year
00-99
Month
01-12
Date
Date
01-31
Day of week
Day
01-07
Hours (24-hour format)
Hours
00-23
10 minutes
Minutes
Minutes
00-59
10 seconds
Seconds
Seconds
00-59
10 M
10 date
0
0
0
10 hours
S
Calibration
BMB4 BMB3
ABE
BMB2
BMB1 BMB0
Al 10M
Control
RB1
RB0
Watchdog
Alarm month
A month
01-12
Al 10 date
Alarm date
Al date
01-31
Al 10 hours
Alarm hours
A hours
00-23
Al 10 minutes
Alarm minutes
A min
00-59
Al 10 seconds
Alarm seconds
A sec
00-59
100 year
Century
00-99
1000 year
WDF
D1
Month
0
R
1FFF1h
1FFF0h
D5
AF
0
BL
Y
Y
Y
Y
Flag
Keys:
S = SIGN bit
FT = FREQUENCY TEST bit
R = READ bit
W = WRITE bit
ST = STOP bit
0 = Must be set to '0'
Y = '1' or '0‘
BL = Battery low (read only)
AF = Alarm flag (read only)
WDS = Watchdog steering bit
BMB0-BMB4 = Watchdog multiplier bits
RB0-RB1 = Watchdog resolution bits
AFE = Alarm flag enable
ABE = Alarm in battery backup mode enable
RPT1-RPT5 = Alarm repeat mode bits
WDF = Watchdog flag (read only)
Doc ID 5710 Rev 4
13/28
Clock operations
3.5
M48T129V, M48T129Y
Calibrating the clock
The M48T129Y/V is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The devices are factory calibrated at 25 °C and tested for accuracy. Clock
accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25 °C, which
equates to about ±1.53 minutes per month (see Figure 8 on page 15). When the calibration
circuit is properly employed, accuracy improves to better than +1/–2 ppm at
25 °C. The oscillation rate of crystals changes with temperature. The M48T129Y/V design
employs periodic counter correction. The calibration circuit adds or subtracts counts from
the oscillator divider circuit at the divide by 256 stage, as shown in Figure 9 on page 15.
The number of times pulses are blanked (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five calibration bits found in the
control register. Adding counts speeds the clock up, subtracting counts slows the clock
down. The calibration bits occupy the five lower order bits (D4-D0) in the control register
1FFF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit
D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration
occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened by 256 oscillator cycles.
If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be
modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each
calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every
125, 829, 120 actual oscillator cycles, that is +4.068 or –2.034 ppm of adjustment per
calibration step in the calibration register. Assuming that the oscillator is running at exactly
32,768Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35
seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month.
Figure 9 on page 15 illustrates a TIMEKEEPER® calibration waveform.
Two methods are available for ascertaining how much calibration a given M48T129Y/V may
require. The first involves setting the clock, letting it run for a month and comparing it to a
known accurate reference and recording deviation over a fixed period of time.
Calibration values, including the number of seconds lost or gained in a given period, can be
found in the application note “AN934, Timekeeper calibration.”
This allows the designer to give the end user the ability to calibrate the clock as the
environment requires, even if the final product is packaged in a non-user serviceable
enclosure. The designer could provide a simple utility that accesses the calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use
of the IRQ/FT pin. The pin will toggle at 512 Hz, when the stop bit (ST, D7 of 1FFF9h) is '0,'
the frequency test bit (FT, D6 of 1FFFCh) is '1,' the alarm flag enable bit (AFE, D7 of
1FFF6h) is '0,' and the watchdog steering bit (WDS, D7 of 1FFF7h) is '1' or the watchdog
register (1FFF7h = 0) is reset.
Note:
A 4 second settling time must be allowed before reading the 512 Hz output.
Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at
the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10 (WR001010) to be loaded into the calibration byte
for correction. Note that setting or changing the calibration byte does not affect the
frequency test output frequency.
The IRQ/FT pin is an open drain output which requires a pull-up resistor for proper
operation. A 500-10 kΩ resistor is recommended in order to control the rise time. The FT bit
is cleared on power-up.
14/28
Doc ID 5710 Rev 4
M48T129V, M48T129Y
Clock operations
Figure 8.
Crystal accuracy across temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
–100
ΔF = -0.038 ppm (T - T )2 ± 10%
0
F
C2
–120
T0 = 25 °C
–140
–160
–40
–30
–20
–10
0
10
20
30
Temperature °C
Figure 9.
40
50
60
70
80
AI00999
Calibration waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
Doc ID 5710 Rev 4
15/28
Clock operations
3.6
M48T129V, M48T129Y
Setting the alarm clock
Registers 1FFF6h-1FFF2h contain the alarm settings. The alarm can be configured to go off
at a prescribed time on a specific month, date, hour, minute, or second or repeat every
month, day, hour, minute, or second. It can also be programmed to go off while the
M48T129Y/V is in the battery back-up to serve as a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 6 on page 16 shows
the possible configurations. Codes not listed in the table default to the once per second
mode to quickly alert the user of an incorrect alarm setting.
Note:
User must transition address (or toggle chip enable) to see flag bit change.
When the clock information matches the alarm clock settings based on the match criteria
defined by RPT5-RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set, the
alarm condition activates the IRQ/FT pin. To disable alarm, write ’0’ to the alarm date
register and RPT1-5. The IRQ/FT output is cleared by a READ to the flags register as
shown in Figure 10 A subsequent READ of the flags register is necessary to see that the
value of the alarm flag has been reset to '0.'
The IRQ/FT pin can also be activated in the battery back-up mode. The IRQ/FT will go low if
an alarm occurs and both ABE (alarm in battery backup mode enable) and AFE are set. The
ABE and AFE bits are reset during power-up, therefore an alarm generated during power-up
will only set AF. The user can read the flag register at system boot-up to determine if an
alarm was generated while the M48T129Y/V was in the deselect mode during power-up.
Figure 11 on page 17 illustrates the backup mode alarm timing.
Figure 10. Alarm interrupt reset waveform
15ns Min
ADDRESS 1FF0h
AD0-AD7
ACTIVE FLAG BIT
IRQ/FT
HIGH-Z
AI02581
Table 6.
16/28
Alarm repeat mode
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm activated
1
1
1
1
1
Once per second
1
1
1
1
0
Once per minute
1
1
1
0
0
Once per hour
1
1
0
0
0
Once per day
1
0
0
0
0
Once per month
0
0
0
0
0
Once per year
Doc ID 5710 Rev 4
M48T129V, M48T129Y
Clock operations
Figure 11. Backup mode alarm waveforms
tREC
VCC
VPFD (max)
VPFD (min)
VSO
AFE bit in Interrupt Register
AF bit in Flags Register
IRQ/FT
HIGH-Z
HIGH-Z
AI01678C
3.7
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of time-out into the watchdog
register, address 1FFF7h. Bits BMB4-BMB0 store a binary multiplier and the two lower
order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1
second, and 11 = 4 seconds. The amount of time-out is then determined to be the
multiplication of the five-bit multiplier value with the resolution. (For example: writing
00001110 in the watchdog register = 3*1 or 3 seconds).
Note:
Accuracy of timer is a function of the selected resolution.
If the processor does not reset the timer within the specified period, the M48T129Y/V sets
the WDF (watchdog flag) and generates a watchdog interrupt or a microprocessor reset.
WDF is reset by reading the flags register (address 1FFF0h). The most significant bit of the
watchdog register is the watchdog steering bit (WDS). When set to a '0,' the watchdog will
activate the IRQ/FT pin when timed-out. When WDS is set to a '1,' the watchdog will output
a negative pulse on the RST pin for 40 to 200 ms. The watchdog register and the FT bit will
reset to a '0' at the end of a watchdog time-out when the WDS bit is set to a '1.'
The watchdog timer can be reset by two methods:
1.
a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (WDI);
or
2.
the microprocessor can perform a WRITE of the watchdog register.
The time-out period then starts over. The WDI pin should be tied to VSS if not used. The
watchdog will be reset on each transition (edge) seen by the WDI pin. In the order to
perform a software reset of the watchdog timer, the original time-out period can be written
into the watchdog register, effectively restarting the count-down cycle.
Doc ID 5710 Rev 4
17/28
Clock operations
M48T129V, M48T129Y
Should the watchdog timer time-out, and the WDS bit is programmed to output an interrupt,
a value of “00h” needs to be written to the watchdog register in order to clear the IRQ/FT
pin. This will also disable the watchdog function until it is again programmed correctly. A
READ of the flags register will reset the watchdog flag (bit D7; register 1FFF0h).
The watchdog function is automatically disabled upon power-down and the watchdog
register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the
frequency test function is activated, the watchdog or alarm function prevails and the
frequency test function is denied.
3.8
Power-on reset
The M48T129Y/V continuously monitors VCC. When VCC falls to the power fail detect trip
point, the RST pulls low (open drain) and remains low on power-up for tREC after VCC
passes VPFD (max). The RST pin is an open drain output and an appropriate pull-up resistor
to VCC should be chosen to control the rise time.
3.9
Battery low warning
The M48T129Y/V automatically performs battery voltage monitoring upon power-up and at
factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit
D4 of flags register 1FFF0h, will be asserted if the battery voltage is found to be less than
approximately 2.5 V.
If a battery low is generated during a power-up sequence, this indicates that the battery is
below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM.
Data should be considered suspect and verified as correct.
If a battery low indication is generated during the 24-hour interval check, this indicates that
the battery is near end of life. However, data is not compromised due to the fact that a
nominal VCC is supplied.
The M48T129Y/V only monitors the battery when a nominal VCC is applied to the device.
Thus applications which require extensive durations in the battery back-up mode should be
powered-up periodically (at least once every few months) in order for this technique to be
beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon
power-up via a checksum or other technique.
3.10
Initial power-on defaults
Upon application of power to the device, the following register bits are set to a '0' state:
WDS, BMB0-BMB4, RB0,RB1, AFE, ABE, W, R and FT.
18/28
Doc ID 5710 Rev 4
M48T129V, M48T129Y
3.11
Clock operations
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (see
Figure 12) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, ST recommends connecting a schottky
diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817
is recommended for through hole and MBRS120T3 is recommended for surface-mount).
Figure 12. Supply voltage protection
VCC
VCC
0.1µF
DEVICE
VSS
AI02169
Doc ID 5710 Rev 4
19/28
Maximum ratings
4
M48T129V, M48T129Y
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 7.
Absolute maximum ratings
Symbol
TA
TSTG
TSLD(1)(2)
Parameter
Ambient operating temperature
Storage temperature (VCC off, oscillator off)
Value
Unit
0 to 70
°C
–40 to 85
°C
260
°C
–0.3 to VCC +0.3
V
M48T129Y
–0.3 to 7.0
V
M48T129V
–0.3 to 4.6
V
Lead solder temperature for 10 seconds
VIO
Input or output voltages
VCC
Supply voltage
IO
Output current
20
mA
PD
Power dissipation
1
W
1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. In order to protect the lithium
battery, preheat temperatures must be limited such that the battery temperature does not exceed +85 °C.
Furthermore, the devices shall not be exposed to IR reflow.
2. For DIP packaged devices, ultrasonic vibrations should not be used for post-solder cleaning to avoid
damaging the crystal.
Caution:
20/28
Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
Doc ID 5710 Rev 4
M48T129V, M48T129Y
5
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 8.
Operating and AC measurement conditions
Parameter
Supply voltage (VCC)
Ambient operating temperature (TA)
M48T129Y
M48T129V
Unit
4.5 to 5.5
3.0 to 3.6
V
0 to 70
0 to 70
°C
Load capacitance (CL)
100
50
pF
Input rise and fall times
≤5
≤5
ns
0 to 3
0 to 3
V
1.5
1.5
V
Input pulse voltages
Input and output timing ref. voltages
Note:
Output Hi-Z is defined as the point where data is no longer driven.
Figure 13. AC testing load circuit
650Ω
DEVICE
UNDER
TEST
CL = 100pF
or 50pF
1.75V
CL includes JIG capacitance
Note:
AI01803C
Excluding open drain output pins; 50 pF for M48T129V.
Table 9.
Capacitance
Parameter(1)(2)
Symbol
CIN
CIO(3)
Min
Max
Unit
Input capacitance
-
20
pF
Input / output capacitance
-
20
pF
1. Effective capacitance measured with power supply at 5 V (M48T129Y) or 3.3 V (M48T129V); sampled
only, not 100% tested.
2. At 25 °C, f = 1 MHz.
3. Outputs deselected.
Doc ID 5710 Rev 4
21/28
DC and AC parameters
Table 10.
M48T129V, M48T129Y
DC characteristics
Sym.
Parameter
M48T129Y
M48T129V
–70
–85
Test condition(1)
Min
ILI(2)
ILO
(2)
Input leakage current
Output leakage current
Max
Min
Unit
Max
0 V ≤ VIN ≤ VCC
±2
±2
µA
0 V ≤ VOUT ≤ VCC
±2
±2
µA
Outputs open
95
50
mA
E = VIH
8
4
mA
E = VCC – 0.2 V
4
3
mA
ICC
Supply current
ICC1
Supply current (standby) TTL
ICC2
Supply current (standby) CMOS
VIL
Input low voltage
–0.3
0.8
–0.3
0.4
V
VIH
Input high voltage
2.2
VCC + 0.3
2.2
VCC + 0.3
V
VOL
Output low voltage
IOL = 2.1 mA
0.4
V
VOH
Output high voltage
IOH = –1 mA
0.4
2.4
2.2
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
2. Outputs deselected.
22/28
Doc ID 5710 Rev 4
V
M48T129V, M48T129Y
DC and AC parameters
Figure 14. Power down/up mode AC waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tFB
INPUTS
tRB
tREC
DON'T CARE
RECOGNIZED
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
VALID
RST
AI01805
Table 11.
Power down/up AC characteristics
Parameter(1)
Symbol
tF(2)
VPFD (max) to VPFD (min) VCC fall time
tFB(3)
VPFD (min) to VSS VCC fall time
Min
Max
Unit
300
µs
M48T129Y
10
µs
M48T129V
150
µs
tR
VPFD (min) to VPFD (max) VCC rise time
0
µs
tRB
VSS to VPFD (min) VCC rise time
1
µs
tREC
VPFD (max) to RST high
40
200
ms
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 12.
Power down/up trip points DC characteristics
Parameter(1)(2)
Symbol
VPFD
Power-fail deselect voltage
VSO
Battery backup switchover voltage
tDR
(3)
Min
Typ
M48T129Y
4.2
4.35
4.5
V
M48T129V
2.7
2.9
3.0
V
M48T129Y
3.0
M48T129V
VPFD –100mV
Expected data retention time
Max
10
Unit
V
YEARS
1. All voltages referenced to VSS.
2. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
3. At 25 °C; VCC = 0 V.
Doc ID 5710 Rev 4
23/28
Package mechanical data
6
M48T129V, M48T129Y
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 15. PMDIP32 – 32-pin plastic DIP module, package outline
A
A1
B
S
L
C
eA
e1
e3
D
N
E
1
PMDIP
Note:
Drawing is not to scale.
Table 13.
PMDIP32 – 32-pin plastic DIP module, package mechanical data
mm
inches
Symbol
Typ
A
Max
9.27
Typ
Min
Max
9.52
0.365
0.375
A1
0.38
–
0.015
–
B
0.43
0.59
0.017
0.023
C
0.20
0.33
0.008
0.013
D
42.42
43.18
1.670
1.700
E
18.03
18.80
0.710
0.740
e1
2.29
2.79
0.090
0.110
e3
24/28
Min
38.1
1.5
eA
14.99
16.00
0.590
0.630
L
3.05
3.81
0.120
0.150
S
1.91
2.79
0.075
0.110
N
32
Doc ID 5710 Rev 4
32
M48T129V, M48T129Y
7
Environmental information
Environmental information
Figure 16. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
Please refer to the following web site address for additional information regarding
compliance statements and waste recycling.
Go to www.st.com/nvram, then select "Lithium Battery Recycling" from "Related Topics".
Doc ID 5710 Rev 4
25/28
Part numbering
8
M48T129V, M48T129Y
Part numbering
Table 14.
Ordering information scheme
Example:
M48T
129Y
–70
PM
1
Device type
M48T
Supply voltage and write protect voltage
129Y = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V
129V = VCC = 3.0 to 3.6 V; VPFD = 2.7 to 3.0 V
Speed
–70 = 70 ns (for M48T129Y)
–85 = 85 ns (for M48T129V)
Package
PM = PMDIP32
Temperature range
1 = 0 to 70 °C
Shipping method
Blank = ECOPACK® package, tubes
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
26/28
Doc ID 5710 Rev 4
M48T129V, M48T129Y
9
Revision history
Revision history
Table 15.
Document revision history
Date
Revision
Apr-2000
1
Chipset data sheet - First Issue
22-Jun-2001
2
Reformatted; added temperature information (Table 9, 10, 3, 4, 11,
<Blue>12)
01-Aug-2001
2.1
Added value to AC Testing Load Circuit (Figure 13)
06-Aug-2001
2.2
Fix text and table for “Setting the Alarm Clock” (Table 6)
13-Aug-2001
2.3
Fix error in “Setting the Alarm Clock” text
07-Nov-2001
2.4
Remove chipset option from ordering information (Table 14)
26-Mar-2002
2.5
Replace “chipset” term with “solution,” as well as related changes
throughout the document
20-May-2002
2.6
Modify reflow time and temperature footnotes (Table 7)
18-Nov-2002
2.7
Modified SMT text (Figure 2, 4)
24-Oct-2003
2.8
Remove references to M68Zxxx (obsolete) parts (Figure 4); corrected
footnote (Table 11)
22-Feb-2005
3
Reformatted; IR reflow, SO package updates (Table 7)
4
Removed SOH44 package, SNAPHAT housing and all references
throughout datasheet; updated Features, Section 4, Section 6,
Table 13, 14; added Section 7: Environmental information; reformatted
document.
09-Jun-2010
Changes
Doc ID 5710 Rev 4
27/28
M48T129V, M48T129Y
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Doc ID 5710 Rev 4