TIBPAL16L8-25C, TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C TIBPAL16L8-30M, TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000 D D D DEVICE I INPUTS 3-STATE O OUTPUTS REGISTERED Q OUTPUTS I/O PORTS PAL16L8 10 2 0 6 4 PAL16R4 8 0 4 (3-state buffers) PAL16R6 8 0 6 (3-state buffers) 2 8 (3-state buffers) 0 PAL16R8 8 0 TIBPAL16L8’ C SUFFIX . . . J OR N PACKAGE M SUFFIX . . . J OR W PACKAGE (TOP VIEW) I I I I I I I I I GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC O I/O I/O I/O I/O I/O I/O O I TIBPAL16L8’ C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE (TOP VIEW) I I I I I 4 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 I/O I/O I/O I/O I/O I GND I O I/O description 3 2 O D High-Performance Operation: Propagation Delay C Suffix . . . 25 ns Max M Suffix . . . 30 ns Max Functionally Equivalent, but Faster Than PAL16L8A, PAL16R4A, PAL16R6A, and PAL16R8A Power-Up Clear on Registered Devices (All Register Outputs Are Set High, but Voltage Levels at the Output Pins Go Low) Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability I I I VCC D These programmable array logic devices feature high speed and functional equivalency when compared with currently available devices. These IMPACT circuits combine the latest Advanced Low-Power Schottky technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically results in a more compact circuit board. In addition, chip carriers are available for further reduction in board space. The TIBPAL16’ C series is characterized from 0°C to 75°C. The TIBPAL16’ M series is characterized for operation over the full military temperature range of –55°C to 125°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. These devices are covered by U.S. Patent 4,410,987. IMPACT is a trademark of Texas Instruments. PAL is a registered trademark of Advanced Micro Devices Inc. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS059 FEBRUARY 1984 – REVISED APRIL 2000 15 7 14 8 13 9 12 10 11 TIBPAL16R6’ C SUFFIX . . . J OR N PACKAGE M SUFFIX . . . J OR W PACKAGE (TOP VIEW) CLK I I I I I I I I GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC I/O Q Q Q Q Q Q I/O OE TIBPAL16R8’ C SUFFIX . . . J OR N PACKAGE M SUFFIX . . . J OR W PACKAGE (TOP VIEW) CLK I I I I I I I I GND 2 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC Q Q Q Q Q Q Q Q OE POST OFFICE BOX 655303 I/O 6 5 17 6 16 7 15 8 14 9 10 11 12 13 I/O Q Q Q Q TIBPAL16R6’ C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE (TOP VIEW) I I I I I 3 2 I/O 16 1 20 19 18 4 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 Q Q Q Q Q TIBPAL16R8’ C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE (TOP VIEW) I I I I I 3 2 Q 5 3 2 OE I/O I/O 17 4 OE I/O Q 4 I I I I I 4 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 • DALLAS, TEXAS 75265 OE Q Q 18 I I CLK VCC 3 VCC I/O I/O Q Q Q Q I/O I/O OE I GND 19 I I CLK VCC 20 2 I GND 1 I I CLK VCC CLK I I I I I I I I GND TIBPAL16R4’ C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE (TOP VIEW) I GND TIBPAL16R4’ C SUFFIX . . . J OR N PACKAGE M SUFFIX . . . J OR W PACKAGE (TOP VIEW) Q Q Q Q Q TIBPAL16L8-25C, TIBPAL16R4-25C TIBPAL16L8-30M, TIBPAL16R4-30M LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000 functional block diagrams (positive logic) TIBPAL16L8’ & 32 × 64 16 × 10 I 16 6 16 EN ≥ 1 7 O 7 O 7 I/O 7 I/O 7 I/O 7 I/O 7 I/O 7 I/O 6 TIBPAL16R4’ OE CLK EN 2 C1 & 32 × 64 I 16 × 8 ≥1 8 I=1 2 Q 1D 8 Q 8 Q 8 Q 16 4 4 16 EN ≥ 1 7 I/O 7 I/O 7 I/O 7 I/O 4 4 denotes fused inputs POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TIBPAL16R6-25C, TIBPAL16R8-25C TIBPAL16R6-30M, TIBPAL16R8-30M LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000 functional block diagrams (positive logic) TIBPAL16R6’ OE CLK EN 2 C1 & 32 × 64 I 16 × 8 ≥1 8 I=1 2 Q 1D 8 Q 8 Q 8 Q 8 Q 8 Q 16 6 2 16 EN ≥ 1 7 I/O I/O 7 2 6 TIBPAL16R8’ OE CLK EN 2 C1 & 32 × 64 16 × I 8 8 ≥1 I=1 2 8 Q 8 Q 8 Q 8 Q 8 Q 8 Q 8 Q 16 8 16 8 denotes fused inputs 4 Q 1D POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TIBPAL16L8-25C TIBPAL16L8-30M LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000 logic diagram (positive logic) I 1 First Fuse Numbers I I I I I I I I 2 3 4 5 6 7 8 9 Increment 0 4 8 12 16 20 24 28 0 32 64 96 128 160 192 224 31 19 256 288 320 352 384 416 448 480 18 512 544 576 608 640 672 704 736 17 768 800 832 864 896 928 960 992 16 1024 1056 1088 1120 1152 1184 1216 1248 15 1280 1312 1344 1376 1408 1440 1472 1504 14 1536 1568 1600 1632 1664 1696 1728 1760 13 1792 1824 1856 1888 1920 1952 1984 2016 12 11 O I/O I/O I/O I/O I/O I/O O I Fuse number = First fuse number + Increment POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TIBPAL16R4-25C TIBPAL16R4-30M LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000 logic diagram (positive logic) CLK 1 First Fuse Numbers I I I I I I I I 2 3 4 5 6 7 8 9 Increment 0 4 8 12 16 20 24 31 19 256 288 320 352 384 416 448 480 18 512 544 576 608 640 672 704 736 I=1 1D 768 800 832 864 896 928 960 992 I=1 1D 1024 1056 1088 1120 1152 1184 1216 1248 I=1 1D 1280 1312 1344 1376 1408 1440 1472 1504 I=1 1D 17 I/O I/O Q C1 16 Q C1 15 Q C1 14 Q C1 1536 1568 1600 1632 1664 1696 1728 1760 13 1792 1824 1856 1888 1920 1952 1984 2016 12 11 Fuse number = First fuse number + Increment 6 28 0 32 64 96 128 160 192 224 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 I/O I/O OE TIBPAL16R6-25C TIBPAL16R6-30M LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000 logic diagram (positive logic) CLK 1 First Fuse Numbers I I I I I I I I 2 3 4 5 6 7 8 9 Increment 0 4 8 12 16 20 24 28 31 0 32 64 96 128 160 192 224 19 256 288 320 352 384 416 448 480 I=1 1D 512 544 576 608 640 672 704 736 I=1 1D 768 800 832 864 896 928 960 992 I=1 1D 1024 1056 1088 1120 1152 1184 1216 1248 I=1 1D 1280 1312 1344 1376 1408 1440 1472 1504 I=1 1D 1536 1568 1600 1632 1664 1696 1728 1760 I=1 1D 18 I/O Q C1 17 Q C1 16 Q C1 15 Q C1 14 Q C1 13 Q C1 1792 1824 1856 1888 1920 1952 1984 2016 12 11 I/O OE Fuse number = First fuse number + Increment POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TIBPAL16R8-25C TIBPAL16R8-30M LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000 logic diagram (positive logic) CLK 1 First Fuse Numbers I I I I I I I I 2 3 4 5 6 7 8 9 Increment 0 4 8 12 16 20 24 28 31 0 32 64 96 128 160 192 224 I=1 1D 256 288 320 352 384 416 448 480 I=1 1D 512 544 576 608 640 672 704 736 I=1 1D 768 800 832 864 896 928 960 992 I=1 1D 1024 1056 1088 1120 1152 1184 1216 1248 I=1 1D 1280 1312 1344 1376 1408 1440 1472 1504 I=1 1D 1536 1568 1600 1632 1664 1696 1728 1760 I=1 1D 1792 1824 1856 1888 1920 1952 1984 2016 I=1 1D 19 Q C1 18 Q C1 17 Q C1 16 Q C1 15 Q C1 14 Q C1 13 Q C1 12 Q C1 11 OE Fuse number = First fuse number + Increment 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TIBPAL16L8-25C, TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C NOTE 1: These ratings apply, except for programming pins, during a programming cycle. recommended operating conditions MIN NOM MAX UNIT 4.75 5 5.25 V 5.5 V 0.8 V VCC VIH Supply voltage VIL IOH Low-level input voltage High-level output current –3.2 mA IOL fclock Low-level output current 24 mA 30 MHz High-level input voltage 2 Clock frequency 0 tw Pulse duration, duration clock (see Note 2) tsu th Setup time, input or feedback before clock↑ Hold time, input or feedback after clock↑ High 10 Low 15 ns 20 ns 0 ns TA Operating free-air temperature 0 25 75 °C NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified are for clock high or low only, but not for both simultaneously. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TIBPAL16L8-25C, TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000 electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDITIONS VIK VOH VCC = 4.75 V, VCC = 4.75 V, II = –18 mA IOH = –3.2 mA VOL VCC = 4.75 V, IOL = 24 mA VCC = 5 5.25 25 V V, VO = 2.7 27V VCC = 5 5.25 25 V V, VO = 0.4 04V II IIH VCC = 5.25 V, VCC = 5.25 V, VI = 5.5 V VI = 2.7 V IIL IO‡ VCC = 5.25 V, VCC = 5.25 V, VI = 0.4 V VO = 2.25 V IOZH IOZL Outputs I/O ports Outputs I/O ports MIN 2.4 TYP† MAX UNIT –1.5 V 3.3 0.35 V 0.5 20 100 –20 –250 –30 V µA µA 0.1 mA 20 µA –0.25 mA –125 mA ICC VCC = 5.25 V, VI = 0, Outputs open 75 100 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one-half of the short-circuit output current, IOS. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) FROM (INPUT) TO (OUTPUT) I, I/O O, I/O tpd ten CLK↑ Q OE↓ Q tdis ten OE↑ Q I, I/O tdis I, I/O PARAMETER fmax tpd TYP† MAX 15 25 ns 10 15 ns 15 20 ns 10 20 ns O, I/O 14 25 ns O, I/O 13 25 ns TEST CONDITIONS 30 R1 = 500 Ω, R2 = 500 Ω, S Fi See Figure 3 † All typical values are at VCC = 5 V, TA = 25°C. 10 MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MHz TIBPAL16L8-30M, TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C NOTE 1: These ratings apply, except for programming pins, during a programming cycle. recommended operating conditions MIN NOM MAX UNIT 4.5 5 5.5 V 5.5 V VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 V High-level output current –2 mA IOL fclock Low-level output current 12 mA 25 MHz High-level input voltage 2 Clock frequency 0 tw Pulse duration, duration clock (see Note 2) tsu th Setup time, input or feedback before clock↑ Hold time, input or feedback after clock↑ High 15 Low 20 ns 25 ns 0 ns TA Operating free-air temperature –55 25 125 °C NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified are for clock high or low only, but not for both simultaneously. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TIBPAL16L8-30M, TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000 electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDITIONS VIK VOH VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –2 mA VOL VCC = 4.5 V, IOL = 12 mA VCC = 5 5.5 5V VO = 2.7 27V VCC = 5 5.5 5V V, VO = 0.4 04V VCC = 5 5.5 5V V, VI = 5 5.5 5V VCC = 5.5 V, VI = 2.7 V IOZH IOZL Outputs I/O ports Outputs I/O ports Pin 1, 11 II All others MIN 2.4 TYP† I/O ports I/O ports All others IOS‡ ICC V V 0.4 20 100 –20 –250 0.2 0.1 V µA µA mA 50 100 All others IIL UNIT –1.5 3.2 0.25 Pin 1, 11 IIH MAX µA 20 VCC = 5 5.5 5V V, VI = 0 0.4 4V VCC = 5.5 V, VCC = 5.5 V, VO = 0.5 V VI = 0, –0.25 –0.2 –30 Outputs open 75 mA –250 mA 105 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to avoid test-equipment degradation. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) FROM (INPUT) TO (OUTPUT) I, I/O tpd ten tdis ten PARAMETER fmax tpd TYP† MAX O, I/O 15 30 ns CLK↑ Q 10 20 ns OE↓ Q 15 25 ns OE↑ Q 10 25 ns I, I/O O, I/O 14 30 ns O, I/O 13 30 ns MIN 25 tdis I, I/O † All typical values are at VCC = 5 V, TA = 25°C. 12 TEST CONDITIONS POST OFFICE BOX 655303 R1 = 390 Ω, R2 = 750 Ω, S Fi See Figure 4 • DALLAS, TEXAS 75265 UNIT MHz TIBPAL16L8-25C, TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C TIBPAL16L8-30M, TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000 programming information Texas Instruments programmable logic devices can be programmed using widely available software and inexpensive device programmers. Complete programming specifications, algorithms, and the latest information on hardware, software, and firmware are available upon request. Information on programmers capable of programming Texas Instruments programmable logic also is available, upon request, from the nearest TI field sales office or local authorized TI distributor, by calling Texas Instruments at +1 (972) 644–5580, or by visiting the TI Semiconductor Home Page at www.ti.com/sc. preload procedure for registered outputs (see Figure 1 and Note 3) The output registers can be preloaded to any desired state during device testing. This permits any state to be tested without having to step through the entire state-machine sequence. Each register is preloaded individually by following the steps given below. Step 1. Step 2. Step 3. Step 4. With VCC at 5 V and Pin 1 at VIL, raise Pin 11 to VIHH. Apply either VIL or VIH to the output corresponding to the register to be preloaded. Pulse Pin 1, clocking in preload data. Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing the voltage level at the output pin. VIHH Pin 11 td VIL td tsu tw VIH Pin 1 VIL VIH Registered I/O Input VOH Output VIL VOL NOTE 3: td = tsu = th = 100 ns to 1000 ns VIHH = 10.25 V to 10.75 V Figure 1. Preload Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TIBPAL16L8-25C, TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C TIBPAL16L8-30M, TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000 power-up reset (see Figure 2) Following power up, all registers are set high. This feature provides extra flexibility to the system designer and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and feedback setup times are met. VCC 5V 4V tpd† (600 ns TYP, 1000 ns MAX) VOH Active-Low Registered Output 1.5 V VOL tsu‡ VIH CLK 1.5 V 1.5 V VIL tw † This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data. ‡ This is the setup time for input or feedback. Figure 2. Power-Up Reset Waveforms 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TIBPAL16L8-25C, TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000 PARAMETER MEASUREMENT INFORMATION 7V S1 R1 From Output Under Test Test Point CL (see Note A) R2 LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V Timing Input 0.3 V 1.3 V 3.5 V 1.3 V 0.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 3.5 V 1.3 V 1.3 V tdis 0.3 V tpd VOH In-Phase Output 1.3 V 1.3 V Out-of-Phase Output (see Note D) Waveform 1 S1 Closed (see Note B) 1.3 V tpd 1.3 V tdis ten VOH 1.3 V VOL Waveform 2 S1 Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ≈3.5 V VOL + 0.3 V VOL VOL tpd 1.3 V 0.3 V ten 1.3 V tpd 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.3 V tw th tsu Data Input 3.5 V High-Level Pulse 1.3 V VOH 1.3 V VOH – 0.3 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf ≤ 2 ns, duty cycle = 50% D. When measuring propagation delay times of 3-state outputs from low to high, switch S1 is closed. When measuring propagation delay times of 3-state outputs from high to low, switch S1 is open. E. Equivalent loads may be used for testing. Figure 3. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TIBPAL16L8-25C, TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000 PARAMETER MEASUREMENT INFORMATION 5V S1 R1 From Output Under Test Test Point CL (see Note A) R2 LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V Timing Input 0 1.5 V 3V 1.5 V 0 3V Low-Level Pulse 1.5 V 0 1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS 3V Output Control (low-level enabling) 3V 1.5 V 1.5 V tdis 0 tpd VOH In-Phase Output 1.5 V 1.5 V Out-of-Phase Output (see Note D) Waveform 1 S1 Closed (see Note B) 1.5 V tpd 1.5 V tdis ten VOH 1.5 V VOL Waveform 2 S1 Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ≈3.3 V VOL + 0.5 V VOL VOL tpd 1.5 V 0 ten 1.5 V tpd 1.5 V 0 VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.5 V tw th tsu Data Input 3V High-Level Pulse 1.5 V VOH 1.5 V VOH – 0.5 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses have the following characteristics: PRR ≤ 10 MHz, tr = tf ≤ 2 ns, duty cycle = 50% D. When measuring propagation delay times of 3-state outputs, switch S1 is closed. E. Equivalent loads may be used for testing. Figure 4. Load Circuit and Voltage Waveforms 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2005 PACKAGING INFORMATION (1) Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 5962-85155052A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC 5962-8515505RA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC 5962-8515505SA ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC 5962-85155062A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC 5962-8515506RA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC 5962-8515506SA ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC 5962-85155072A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC 5962-8515507RA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC 5962-8515507SA ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC 5962-85155082A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC 5962-8515508RA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC 5962-8515508SA ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC JM38510/50605BRA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC JM38510/50606BRA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC JM38510/50607BRA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC JM38510/50608BRA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC TIBPAL16L8-25CFN ACTIVE PLCC FN 20 46 None Call TI Level-1-220-UNLIM TIBPAL16L8-25CN ACTIVE PDIP N 20 20 None Call TI Level-NC-NC-NC TIBPAL16L8-30MFKB ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC TIBPAL16L8-30MJ ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC TIBPAL16L8-30MJB ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC TIBPAL16L8-30MWB ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC TIBPAL16R4-25CFN ACTIVE PLCC FN 20 46 None Call TI Level-1-220-UNLIM TIBPAL16R4-25CN ACTIVE PDIP N 20 20 None Call TI Level-NC-NC-NC TIBPAL16R4-30MFKB ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC TIBPAL16R4-30MJ ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC TIBPAL16R4-30MJB ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC TIBPAL16R4-30MWB ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC TIBPAL16R6-25CFN ACTIVE PLCC FN 20 46 None Call TI Level-1-220-UNLIM TIBPAL16R6-25CN ACTIVE PDIP N 20 20 None Call TI Level-NC-NC-NC TIBPAL16R6-30MFKB ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC TIBPAL16R6-30MJ ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC TIBPAL16R6-30MJB ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC TIBPAL16R6-30MWB ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC TIBPAL16R8-25CFN ACTIVE PLCC FN 20 46 None Call TI Level-1-220-UNLIM TIBPAL16R8-25CN ACTIVE PDIP N 20 20 None Call TI Level-NC-NC-NC TIBPAL16R8-30MFKB ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC TIBPAL16R8-30MJ ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC TIBPAL16R8-30MJB ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC TIBPAL16R8-30MWB ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC The marketing status values are defined as follows: Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2005 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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